1 | /*****************************************************************************\ |
2 | Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. |
3 | This file is licensed under the Snes9x License. |
4 | For further information, consult the LICENSE file in the root directory. |
5 | \*****************************************************************************/ |
6 | |
7 | #include "snes9x.h" |
8 | #include "fxinst.h" |
9 | #include "fxemu.h" |
10 | |
11 | // Set this define if you wish the plot instruction to check for y-pos limits (I don't think it's nessecary) |
12 | #define CHECK_LIMITS |
13 | |
14 | |
15 | /* |
16 | Codes used: |
17 | rn = a GSU register (r0 - r15) |
18 | #n = 4 bit immediate value |
19 | #pp = 8 bit immediate value |
20 | (yy) = 8 bit word address (0x0000 - 0x01fe) |
21 | #xx = 16 bit immediate value |
22 | (xx) = 16 bit address (0x0000 - 0xffff) |
23 | */ |
24 | |
25 | // 00 - stop - stop GSU execution (and maybe generate an IRQ) |
26 | static void fx_stop (void) |
27 | { |
28 | CF(G); |
29 | GSU.vCounter = 0; |
30 | GSU.vInstCount = GSU.vCounter; |
31 | |
32 | // Check if we need to generate an IRQ |
33 | if (!(GSU.pvRegisters[GSU_CFGR] & 0x80)) |
34 | SF(IRQ); |
35 | |
36 | GSU.vPlotOptionReg = 0; |
37 | GSU.vPipe = 1; |
38 | CLRFLAGS; |
39 | R15++; |
40 | } |
41 | |
42 | // 01 - nop - no operation |
43 | static void fx_nop (void) |
44 | { |
45 | CLRFLAGS; |
46 | R15++; |
47 | } |
48 | |
49 | // 02 - cache - reintialize GSU cache |
50 | static void fx_cache (void) |
51 | { |
52 | uint32 c = R15 & 0xfff0; |
53 | |
54 | if (GSU.vCacheBaseReg != c || !GSU.bCacheActive) |
55 | { |
56 | fx_flushCache(); |
57 | GSU.vCacheBaseReg = c; |
58 | GSU.bCacheActive = TRUE; |
59 | |
60 | #if 0 |
61 | if (c < (0x10000 - 512)) |
62 | { |
63 | const uint8 *t = &ROM(c); |
64 | memcpy(GSU.pvCache, t, 512); |
65 | } |
66 | else |
67 | { |
68 | const uint8 *t1, t2; |
69 | uint32 i = 0x10000 - c; |
70 | t1 = &ROM(c); |
71 | t2 = &ROM(0); |
72 | memcpy(GSU.pvCache, t1, i); |
73 | memcpy(&GSU.pvCache[i], t2, 512 - i); |
74 | } |
75 | #endif |
76 | } |
77 | |
78 | CLRFLAGS; |
79 | R15++; |
80 | } |
81 | |
82 | // 03 - lsr - logic shift right |
83 | static void fx_lsr (void) |
84 | { |
85 | uint32 v; |
86 | GSU.vCarry = SREG & 1; |
87 | v = USEX16(SREG) >> 1; |
88 | R15++; |
89 | DREG = v; |
90 | GSU.vSign = v; |
91 | GSU.vZero = v; |
92 | TESTR14; |
93 | CLRFLAGS; |
94 | } |
95 | |
96 | // 04 - rol - rotate left |
97 | static void fx_rol (void) |
98 | { |
99 | uint32 v = USEX16((SREG << 1) + GSU.vCarry); |
100 | GSU.vCarry = (SREG >> 15) & 1; |
101 | R15++; |
102 | DREG = v; |
103 | GSU.vSign = v; |
104 | GSU.vZero = v; |
105 | TESTR14; |
106 | CLRFLAGS; |
107 | } |
108 | |
109 | // 05 - bra - branch always |
110 | static void fx_bra (void) |
111 | { |
112 | uint8 v = PIPE; |
113 | R15++; |
114 | FETCHPIPE; |
115 | R15 += SEX8(v); |
116 | } |
117 | |
118 | // Branch on condition |
119 | #define BRA_COND(cond) \ |
120 | uint8 v = PIPE; \ |
121 | R15++; \ |
122 | FETCHPIPE; \ |
123 | if (cond) \ |
124 | R15 += SEX8(v); \ |
125 | else \ |
126 | R15++ |
127 | |
128 | #define TEST_S (GSU.vSign & 0x8000) |
129 | #define TEST_Z (USEX16(GSU.vZero) == 0) |
130 | #define TEST_OV (GSU.vOverflow >= 0x8000 || GSU.vOverflow < -0x8000) |
131 | #define TEST_CY (GSU.vCarry & 1) |
132 | |
133 | // 06 - blt - branch on less than |
134 | static void fx_blt (void) |
135 | { |
136 | BRA_COND((TEST_S != 0) != (TEST_OV != 0)); |
137 | } |
138 | |
139 | // 07 - bge - branch on greater or equals |
140 | static void fx_bge (void) |
141 | { |
142 | BRA_COND((TEST_S != 0) == (TEST_OV != 0)); |
143 | } |
144 | |
145 | // 08 - bne - branch on not equal |
146 | static void fx_bne (void) |
147 | { |
148 | BRA_COND(!TEST_Z); |
149 | } |
150 | |
151 | // 09 - beq - branch on equal |
152 | static void fx_beq (void) |
153 | { |
154 | BRA_COND(TEST_Z); |
155 | } |
156 | |
157 | // 0a - bpl - branch on plus |
158 | static void fx_bpl (void) |
159 | { |
160 | BRA_COND(!TEST_S); |
161 | } |
162 | |
163 | // 0b - bmi - branch on minus |
164 | static void fx_bmi (void) |
165 | { |
166 | BRA_COND(TEST_S); |
167 | } |
168 | |
169 | // 0c - bcc - branch on carry clear |
170 | static void fx_bcc (void) |
171 | { |
172 | BRA_COND(!TEST_CY); |
173 | } |
174 | |
175 | // 0d - bcs - branch on carry set |
176 | static void fx_bcs (void) |
177 | { |
178 | BRA_COND(TEST_CY); |
179 | } |
180 | |
181 | // 0e - bvc - branch on overflow clear |
182 | static void fx_bvc (void) |
183 | { |
184 | BRA_COND(!TEST_OV); |
185 | } |
186 | |
187 | // 0f - bvs - branch on overflow set |
188 | static void fx_bvs (void) |
189 | { |
190 | BRA_COND(TEST_OV); |
191 | } |
192 | |
193 | // 10-1f - to rn - set register n as destination register |
194 | // 10-1f (B) - move rn - move one register to another (if B flag is set) |
195 | #define FX_TO(reg) \ |
196 | if (TF(B)) \ |
197 | { \ |
198 | GSU.avReg[(reg)] = SREG; \ |
199 | CLRFLAGS; \ |
200 | } \ |
201 | else \ |
202 | GSU.pvDreg = &GSU.avReg[reg]; \ |
203 | R15++ |
204 | |
205 | #define FX_TO_R14(reg) \ |
206 | if (TF(B)) \ |
207 | { \ |
208 | GSU.avReg[(reg)] = SREG; \ |
209 | CLRFLAGS; \ |
210 | READR14; \ |
211 | } \ |
212 | else \ |
213 | GSU.pvDreg = &GSU.avReg[reg]; \ |
214 | R15++ |
215 | |
216 | #define FX_TO_R15(reg) \ |
217 | if (TF(B)) \ |
218 | { \ |
219 | GSU.avReg[(reg)] = SREG; \ |
220 | CLRFLAGS; \ |
221 | } \ |
222 | else \ |
223 | { \ |
224 | GSU.pvDreg = &GSU.avReg[reg]; \ |
225 | R15++; \ |
226 | } |
227 | |
228 | static void fx_to_r0 (void) |
229 | { |
230 | FX_TO(0); |
231 | } |
232 | |
233 | static void fx_to_r1 (void) |
234 | { |
235 | FX_TO(1); |
236 | } |
237 | |
238 | static void fx_to_r2 (void) |
239 | { |
240 | FX_TO(2); |
241 | } |
242 | |
243 | static void fx_to_r3 (void) |
244 | { |
245 | FX_TO(3); |
246 | } |
247 | |
248 | static void fx_to_r4 (void) |
249 | { |
250 | FX_TO(4); |
251 | } |
252 | |
253 | static void fx_to_r5 (void) |
254 | { |
255 | FX_TO(5); |
256 | } |
257 | |
258 | static void fx_to_r6 (void) |
259 | { |
260 | FX_TO(6); |
261 | } |
262 | |
263 | static void fx_to_r7 (void) |
264 | { |
265 | FX_TO(7); |
266 | } |
267 | |
268 | static void fx_to_r8 (void) |
269 | { |
270 | FX_TO(8); |
271 | } |
272 | |
273 | static void fx_to_r9 (void) |
274 | { |
275 | FX_TO(9); |
276 | } |
277 | |
278 | static void fx_to_r10 (void) |
279 | { |
280 | FX_TO(10); |
281 | } |
282 | |
283 | static void fx_to_r11 (void) |
284 | { |
285 | FX_TO(11); |
286 | } |
287 | |
288 | static void fx_to_r12 (void) |
289 | { |
290 | FX_TO(12); |
291 | } |
292 | |
293 | static void fx_to_r13 (void) |
294 | { |
295 | FX_TO(13); |
296 | } |
297 | |
298 | static void fx_to_r14 (void) |
299 | { |
300 | FX_TO_R14(14); |
301 | } |
302 | |
303 | static void fx_to_r15 (void) |
304 | { |
305 | FX_TO_R15(15); |
306 | } |
307 | |
308 | // 20-2f - to rn - set register n as source and destination register |
309 | #define FX_WITH(reg) \ |
310 | SF(B); \ |
311 | GSU.pvSreg = GSU.pvDreg = &GSU.avReg[reg]; \ |
312 | R15++ |
313 | |
314 | static void fx_with_r0 (void) |
315 | { |
316 | FX_WITH(0); |
317 | } |
318 | |
319 | static void fx_with_r1 (void) |
320 | { |
321 | FX_WITH(1); |
322 | } |
323 | |
324 | static void fx_with_r2 (void) |
325 | { |
326 | FX_WITH(2); |
327 | } |
328 | |
329 | static void fx_with_r3 (void) |
330 | { |
331 | FX_WITH(3); |
332 | } |
333 | |
334 | static void fx_with_r4 (void) |
335 | { |
336 | FX_WITH(4); |
337 | } |
338 | |
339 | static void fx_with_r5 (void) |
340 | { |
341 | FX_WITH(5); |
342 | } |
343 | |
344 | static void fx_with_r6 (void) |
345 | { |
346 | FX_WITH(6); |
347 | } |
348 | |
349 | static void fx_with_r7 (void) |
350 | { |
351 | FX_WITH(7); |
352 | } |
353 | |
354 | static void fx_with_r8 (void) |
355 | { |
356 | FX_WITH(8); |
357 | } |
358 | |
359 | static void fx_with_r9 (void) |
360 | { |
361 | FX_WITH(9); |
362 | } |
363 | |
364 | static void fx_with_r10 (void) |
365 | { |
366 | FX_WITH(10); |
367 | } |
368 | |
369 | static void fx_with_r11 (void) |
370 | { |
371 | FX_WITH(11); |
372 | } |
373 | |
374 | static void fx_with_r12 (void) |
375 | { |
376 | FX_WITH(12); |
377 | } |
378 | |
379 | static void fx_with_r13 (void) |
380 | { |
381 | FX_WITH(13); |
382 | } |
383 | |
384 | static void fx_with_r14 (void) |
385 | { |
386 | FX_WITH(14); |
387 | } |
388 | |
389 | static void fx_with_r15 (void) |
390 | { |
391 | FX_WITH(15); |
392 | } |
393 | |
394 | // 30-3b - stw (rn) - store word |
395 | #define FX_STW(reg) \ |
396 | GSU.vLastRamAdr = GSU.avReg[reg]; \ |
397 | RAM(GSU.avReg[reg]) = (uint8) SREG; \ |
398 | RAM(GSU.avReg[reg] ^ 1) = (uint8) (SREG >> 8); \ |
399 | CLRFLAGS; \ |
400 | R15++ |
401 | |
402 | static void fx_stw_r0 (void) |
403 | { |
404 | FX_STW(0); |
405 | } |
406 | |
407 | static void fx_stw_r1 (void) |
408 | { |
409 | FX_STW(1); |
410 | } |
411 | |
412 | static void fx_stw_r2 (void) |
413 | { |
414 | FX_STW(2); |
415 | } |
416 | |
417 | static void fx_stw_r3 (void) |
418 | { |
419 | FX_STW(3); |
420 | } |
421 | |
422 | static void fx_stw_r4 (void) |
423 | { |
424 | FX_STW(4); |
425 | } |
426 | |
427 | static void fx_stw_r5 (void) |
428 | { |
429 | FX_STW(5); |
430 | } |
431 | |
432 | static void fx_stw_r6 (void) |
433 | { |
434 | FX_STW(6); |
435 | } |
436 | |
437 | static void fx_stw_r7 (void) |
438 | { |
439 | FX_STW(7); |
440 | } |
441 | |
442 | static void fx_stw_r8 (void) |
443 | { |
444 | FX_STW(8); |
445 | } |
446 | |
447 | static void fx_stw_r9 (void) |
448 | { |
449 | FX_STW(9); |
450 | } |
451 | |
452 | static void fx_stw_r10 (void) |
453 | { |
454 | FX_STW(10); |
455 | } |
456 | |
457 | static void fx_stw_r11 (void) |
458 | { |
459 | FX_STW(11); |
460 | } |
461 | |
462 | // 30-3b (ALT1) - stb (rn) - store byte |
463 | #define FX_STB(reg) \ |
464 | GSU.vLastRamAdr = GSU.avReg[reg]; \ |
465 | RAM(GSU.avReg[reg]) = (uint8) SREG; \ |
466 | CLRFLAGS; \ |
467 | R15++ |
468 | |
469 | static void fx_stb_r0 (void) |
470 | { |
471 | FX_STB(0); |
472 | } |
473 | |
474 | static void fx_stb_r1 (void) |
475 | { |
476 | FX_STB(1); |
477 | } |
478 | |
479 | static void fx_stb_r2 (void) |
480 | { |
481 | FX_STB(2); |
482 | } |
483 | |
484 | static void fx_stb_r3 (void) |
485 | { |
486 | FX_STB(3); |
487 | } |
488 | |
489 | static void fx_stb_r4 (void) |
490 | { |
491 | FX_STB(4); |
492 | } |
493 | |
494 | static void fx_stb_r5 (void) |
495 | { |
496 | FX_STB(5); |
497 | } |
498 | |
499 | static void fx_stb_r6 (void) |
500 | { |
501 | FX_STB(6); |
502 | } |
503 | |
504 | static void fx_stb_r7 (void) |
505 | { |
506 | FX_STB(7); |
507 | } |
508 | |
509 | static void fx_stb_r8 (void) |
510 | { |
511 | FX_STB(8); |
512 | } |
513 | |
514 | static void fx_stb_r9 (void) |
515 | { |
516 | FX_STB(9); |
517 | } |
518 | |
519 | static void fx_stb_r10 (void) |
520 | { |
521 | FX_STB(10); |
522 | } |
523 | |
524 | static void fx_stb_r11 (void) |
525 | { |
526 | FX_STB(11); |
527 | } |
528 | |
529 | // 3c - loop - decrement loop counter, and branch on not zero |
530 | static void fx_loop (void) |
531 | { |
532 | GSU.vSign = GSU.vZero = --R12; |
533 | if ((uint16) R12 != 0) |
534 | R15 = R13; |
535 | else |
536 | R15++; |
537 | CLRFLAGS; |
538 | } |
539 | |
540 | // 3d - alt1 - set alt1 mode |
541 | static void fx_alt1 (void) |
542 | { |
543 | SF(ALT1); |
544 | CF(B); |
545 | R15++; |
546 | } |
547 | |
548 | // 3e - alt2 - set alt2 mode |
549 | static void fx_alt2 (void) |
550 | { |
551 | SF(ALT2); |
552 | CF(B); |
553 | R15++; |
554 | } |
555 | |
556 | // 3f - alt3 - set alt3 mode |
557 | static void fx_alt3 (void) |
558 | { |
559 | SF(ALT1); |
560 | SF(ALT2); |
561 | CF(B); |
562 | R15++; |
563 | } |
564 | |
565 | // 40-4b - ldw (rn) - load word from RAM |
566 | #define FX_LDW(reg) \ |
567 | uint32 v; \ |
568 | GSU.vLastRamAdr = GSU.avReg[reg]; \ |
569 | v = (uint32) RAM(GSU.avReg[reg]); \ |
570 | v |= ((uint32) RAM(GSU.avReg[reg] ^ 1)) << 8; \ |
571 | R15++; \ |
572 | DREG = v; \ |
573 | TESTR14; \ |
574 | CLRFLAGS |
575 | |
576 | static void fx_ldw_r0 (void) |
577 | { |
578 | FX_LDW(0); |
579 | } |
580 | |
581 | static void fx_ldw_r1 (void) |
582 | { |
583 | FX_LDW(1); |
584 | } |
585 | |
586 | static void fx_ldw_r2 (void) |
587 | { |
588 | FX_LDW(2); |
589 | } |
590 | |
591 | static void fx_ldw_r3 (void) |
592 | { |
593 | FX_LDW(3); |
594 | } |
595 | |
596 | static void fx_ldw_r4 (void) |
597 | { |
598 | FX_LDW(4); |
599 | } |
600 | |
601 | static void fx_ldw_r5 (void) |
602 | { |
603 | FX_LDW(5); |
604 | } |
605 | |
606 | static void fx_ldw_r6 (void) |
607 | { |
608 | FX_LDW(6); |
609 | } |
610 | |
611 | static void fx_ldw_r7 (void) |
612 | { |
613 | FX_LDW(7); |
614 | } |
615 | |
616 | static void fx_ldw_r8 (void) |
617 | { |
618 | FX_LDW(8); |
619 | } |
620 | |
621 | static void fx_ldw_r9 (void) |
622 | { |
623 | FX_LDW(9); |
624 | } |
625 | |
626 | static void fx_ldw_r10 (void) |
627 | { |
628 | FX_LDW(10); |
629 | } |
630 | |
631 | static void fx_ldw_r11 (void) |
632 | { |
633 | FX_LDW(11); |
634 | } |
635 | |
636 | // 40-4b (ALT1) - ldb (rn) - load byte |
637 | #define FX_LDB(reg) \ |
638 | uint32 v; \ |
639 | GSU.vLastRamAdr = GSU.avReg[reg]; \ |
640 | v = (uint32) RAM(GSU.avReg[reg]); \ |
641 | R15++; \ |
642 | DREG = v; \ |
643 | TESTR14; \ |
644 | CLRFLAGS |
645 | |
646 | static void fx_ldb_r0 (void) |
647 | { |
648 | FX_LDB(0); |
649 | } |
650 | |
651 | static void fx_ldb_r1 (void) |
652 | { |
653 | FX_LDB(1); |
654 | } |
655 | |
656 | static void fx_ldb_r2 (void) |
657 | { |
658 | FX_LDB(2); |
659 | } |
660 | |
661 | static void fx_ldb_r3 (void) |
662 | { |
663 | FX_LDB(3); |
664 | } |
665 | |
666 | static void fx_ldb_r4 (void) |
667 | { |
668 | FX_LDB(4); |
669 | } |
670 | |
671 | static void fx_ldb_r5 (void) |
672 | { |
673 | FX_LDB(5); |
674 | } |
675 | |
676 | static void fx_ldb_r6 (void) |
677 | { |
678 | FX_LDB(6); |
679 | } |
680 | |
681 | static void fx_ldb_r7 (void) |
682 | { |
683 | FX_LDB(7); |
684 | } |
685 | |
686 | static void fx_ldb_r8 (void) |
687 | { |
688 | FX_LDB(8); |
689 | } |
690 | |
691 | static void fx_ldb_r9 (void) |
692 | { |
693 | FX_LDB(9); |
694 | } |
695 | |
696 | static void fx_ldb_r10 (void) |
697 | { |
698 | FX_LDB(10); |
699 | } |
700 | |
701 | static void fx_ldb_r11 (void) |
702 | { |
703 | FX_LDB(11); |
704 | } |
705 | |
706 | // 4c - plot - plot pixel with R1, R2 as x, y and the color register as the color |
707 | static void fx_plot_2bit (void) |
708 | { |
709 | uint32 x = USEX8(R1); |
710 | uint32 y = USEX8(R2); |
711 | uint8 *a; |
712 | uint8 v, c; |
713 | |
714 | R15++; |
715 | CLRFLAGS; |
716 | R1++; |
717 | |
718 | #ifdef CHECK_LIMITS |
719 | if (y >= GSU.vScreenHeight) |
720 | return; |
721 | #endif |
722 | |
723 | if (!(GSU.vPlotOptionReg & 0x01) && !(COLR & 0xf)) |
724 | return; |
725 | |
726 | if (GSU.vPlotOptionReg & 0x02) |
727 | c = ((x ^ y) & 1) ? (uint8) (GSU.vColorReg >> 4) : (uint8) GSU.vColorReg; |
728 | else |
729 | c = (uint8) GSU.vColorReg; |
730 | |
731 | a = GSU.apvScreen[y >> 3] + GSU.x[x >> 3] + ((y & 7) << 1); |
732 | v = 128 >> (x & 7); |
733 | |
734 | if (c & 0x01) |
735 | a[0] |= v; |
736 | else |
737 | a[0] &= ~v; |
738 | |
739 | if (c & 0x02) |
740 | a[1] |= v; |
741 | else |
742 | a[1] &= ~v; |
743 | } |
744 | |
745 | // 4c (ALT1) - rpix - read color of the pixel with R1, R2 as x, y |
746 | static void fx_rpix_2bit (void) |
747 | { |
748 | uint32 x = USEX8(R1); |
749 | uint32 y = USEX8(R2); |
750 | uint8 *a; |
751 | uint8 v; |
752 | |
753 | R15++; |
754 | CLRFLAGS; |
755 | |
756 | #ifdef CHECK_LIMITS |
757 | if (y >= GSU.vScreenHeight) |
758 | return; |
759 | #endif |
760 | |
761 | a = GSU.apvScreen[y >> 3] + GSU.x[x >> 3] + ((y & 7) << 1); |
762 | v = 128 >> (x & 7); |
763 | |
764 | DREG = 0; |
765 | DREG |= ((uint32) ((a[0] & v) != 0)) << 0; |
766 | DREG |= ((uint32) ((a[1] & v) != 0)) << 1; |
767 | TESTR14; |
768 | } |
769 | |
770 | // 4c - plot - plot pixel with R1, R2 as x, y and the color register as the color |
771 | static void fx_plot_4bit (void) |
772 | { |
773 | uint32 x = USEX8(R1); |
774 | uint32 y = USEX8(R2); |
775 | uint8 *a; |
776 | uint8 v, c; |
777 | |
778 | R15++; |
779 | CLRFLAGS; |
780 | R1++; |
781 | |
782 | #ifdef CHECK_LIMITS |
783 | if (y >= GSU.vScreenHeight) |
784 | return; |
785 | #endif |
786 | |
787 | if (!(GSU.vPlotOptionReg & 0x01) && !(COLR & 0xf)) |
788 | return; |
789 | |
790 | if (GSU.vPlotOptionReg & 0x02) |
791 | c = ((x ^ y) & 1) ? (uint8) (GSU.vColorReg >> 4) : (uint8) GSU.vColorReg; |
792 | else |
793 | c = (uint8) GSU.vColorReg; |
794 | |
795 | a = GSU.apvScreen[y >> 3] + GSU.x[x >> 3] + ((y & 7) << 1); |
796 | v = 128 >> (x & 7); |
797 | |
798 | if (c & 0x01) |
799 | a[0x00] |= v; |
800 | else |
801 | a[0x00] &= ~v; |
802 | |
803 | if (c & 0x02) |
804 | a[0x01] |= v; |
805 | else |
806 | a[0x01] &= ~v; |
807 | |
808 | if (c & 0x04) |
809 | a[0x10] |= v; |
810 | else |
811 | a[0x10] &= ~v; |
812 | |
813 | if (c & 0x08) |
814 | a[0x11] |= v; |
815 | else |
816 | a[0x11] &= ~v; |
817 | } |
818 | |
819 | // 4c (ALT1) - rpix - read color of the pixel with R1, R2 as x, y |
820 | static void fx_rpix_4bit (void) |
821 | { |
822 | uint32 x = USEX8(R1); |
823 | uint32 y = USEX8(R2); |
824 | uint8 *a; |
825 | uint8 v; |
826 | |
827 | R15++; |
828 | CLRFLAGS; |
829 | |
830 | #ifdef CHECK_LIMITS |
831 | if (y >= GSU.vScreenHeight) |
832 | return; |
833 | #endif |
834 | |
835 | a = GSU.apvScreen[y >> 3] + GSU.x[x >> 3] + ((y & 7) << 1); |
836 | v = 128 >> (x & 7); |
837 | |
838 | DREG = 0; |
839 | DREG |= ((uint32) ((a[0x00] & v) != 0)) << 0; |
840 | DREG |= ((uint32) ((a[0x01] & v) != 0)) << 1; |
841 | DREG |= ((uint32) ((a[0x10] & v) != 0)) << 2; |
842 | DREG |= ((uint32) ((a[0x11] & v) != 0)) << 3; |
843 | TESTR14; |
844 | } |
845 | |
846 | // 4c - plot - plot pixel with R1, R2 as x, y and the color register as the color |
847 | static void fx_plot_8bit (void) |
848 | { |
849 | uint32 x = USEX8(R1); |
850 | uint32 y = USEX8(R2); |
851 | uint8 *a; |
852 | uint8 v, c; |
853 | |
854 | R15++; |
855 | CLRFLAGS; |
856 | R1++; |
857 | |
858 | #ifdef CHECK_LIMITS |
859 | if (y >= GSU.vScreenHeight) |
860 | return; |
861 | #endif |
862 | |
863 | c = (uint8) GSU.vColorReg; |
864 | if (!(GSU.vPlotOptionReg & 0x10)) |
865 | { |
866 | if (!(GSU.vPlotOptionReg & 0x01) && (!c || ((GSU.vPlotOptionReg & 0x08) && !(c & 0xf)))) |
867 | return; |
868 | } |
869 | else |
870 | if (!(GSU.vPlotOptionReg & 0x01) && !c) |
871 | return; |
872 | |
873 | a = GSU.apvScreen[y >> 3] + GSU.x[x >> 3] + ((y & 7) << 1); |
874 | v = 128 >> (x & 7); |
875 | |
876 | if (c & 0x01) |
877 | a[0x00] |= v; |
878 | else |
879 | a[0x00] &= ~v; |
880 | |
881 | if (c & 0x02) |
882 | a[0x01] |= v; |
883 | else |
884 | a[0x01] &= ~v; |
885 | |
886 | if (c & 0x04) |
887 | a[0x10] |= v; |
888 | else |
889 | a[0x10] &= ~v; |
890 | |
891 | if (c & 0x08) |
892 | a[0x11] |= v; |
893 | else |
894 | a[0x11] &= ~v; |
895 | |
896 | if (c & 0x10) |
897 | a[0x20] |= v; |
898 | else |
899 | a[0x20] &= ~v; |
900 | |
901 | if (c & 0x20) |
902 | a[0x21] |= v; |
903 | else |
904 | a[0x21] &= ~v; |
905 | |
906 | if (c & 0x40) |
907 | a[0x30] |= v; |
908 | else |
909 | a[0x30] &= ~v; |
910 | |
911 | if (c & 0x80) |
912 | a[0x31] |= v; |
913 | else |
914 | a[0x31] &= ~v; |
915 | } |
916 | |
917 | // 4c (ALT1) - rpix - read color of the pixel with R1, R2 as x, y |
918 | static void fx_rpix_8bit (void) |
919 | { |
920 | uint32 x = USEX8(R1); |
921 | uint32 y = USEX8(R2); |
922 | uint8 *a; |
923 | uint8 v; |
924 | |
925 | R15++; |
926 | CLRFLAGS; |
927 | |
928 | #ifdef CHECK_LIMITS |
929 | if (y >= GSU.vScreenHeight) |
930 | return; |
931 | #endif |
932 | |
933 | a = GSU.apvScreen[y >> 3] + GSU.x[x >> 3] + ((y & 7) << 1); |
934 | v = 128 >> (x & 7); |
935 | |
936 | DREG = 0; |
937 | DREG |= ((uint32) ((a[0x00] & v) != 0)) << 0; |
938 | DREG |= ((uint32) ((a[0x01] & v) != 0)) << 1; |
939 | DREG |= ((uint32) ((a[0x10] & v) != 0)) << 2; |
940 | DREG |= ((uint32) ((a[0x11] & v) != 0)) << 3; |
941 | DREG |= ((uint32) ((a[0x20] & v) != 0)) << 4; |
942 | DREG |= ((uint32) ((a[0x21] & v) != 0)) << 5; |
943 | DREG |= ((uint32) ((a[0x30] & v) != 0)) << 6; |
944 | DREG |= ((uint32) ((a[0x31] & v) != 0)) << 7; |
945 | GSU.vZero = DREG; |
946 | TESTR14; |
947 | } |
948 | |
949 | // 4c - plot - plot pixel with R1, R2 as x, y and the color register as the color |
950 | static void fx_plot_obj (void) |
951 | { |
952 | #ifdef DEBUGGER |
953 | fprintf(stderr, "ERROR fx_plot_obj called\n" ); |
954 | #endif |
955 | } |
956 | |
957 | // 4c (ALT1) - rpix - read color of the pixel with R1, R2 as x, y |
958 | static void fx_rpix_obj (void) |
959 | { |
960 | #ifdef DEBUGGER |
961 | fprintf(stderr, "ERROR fx_rpix_obj called\n" ); |
962 | #endif |
963 | } |
964 | |
965 | // 4d - swap - swap upper and lower byte of a register |
966 | static void fx_swap (void) |
967 | { |
968 | uint8 c = (uint8) SREG; |
969 | uint8 d = (uint8) (SREG >> 8); |
970 | uint32 v = (((uint32) c) << 8) | ((uint32) d); |
971 | R15++; |
972 | DREG = v; |
973 | GSU.vSign = v; |
974 | GSU.vZero = v; |
975 | TESTR14; |
976 | CLRFLAGS; |
977 | } |
978 | |
979 | // 4e - color - copy source register to color register |
980 | static void fx_color (void) |
981 | { |
982 | uint8 c = (uint8) SREG; |
983 | |
984 | if (GSU.vPlotOptionReg & 0x04) |
985 | c = (c & 0xf0) | (c >> 4); |
986 | if (GSU.vPlotOptionReg & 0x08) |
987 | { |
988 | GSU.vColorReg &= 0xf0; |
989 | GSU.vColorReg |= c & 0x0f; |
990 | } |
991 | else |
992 | GSU.vColorReg = USEX8(c); |
993 | |
994 | CLRFLAGS; |
995 | R15++; |
996 | } |
997 | |
998 | // 4e (ALT1) - cmode - set plot option register |
999 | static void fx_cmode (void) |
1000 | { |
1001 | GSU.vPlotOptionReg = SREG; |
1002 | |
1003 | if (GSU.vPlotOptionReg & 0x10) |
1004 | GSU.vScreenHeight = 256; // OBJ Mode (for drawing into sprites) |
1005 | else |
1006 | GSU.vScreenHeight = GSU.vScreenRealHeight; |
1007 | |
1008 | fx_computeScreenPointers(); |
1009 | CLRFLAGS; |
1010 | R15++; |
1011 | } |
1012 | |
1013 | // 4f - not - perform exclusive exor with 1 on all bits |
1014 | static void fx_not (void) |
1015 | { |
1016 | uint32 v = ~SREG; |
1017 | R15++; |
1018 | DREG = v; |
1019 | GSU.vSign = v; |
1020 | GSU.vZero = v; |
1021 | TESTR14; |
1022 | CLRFLAGS; |
1023 | } |
1024 | |
1025 | // 50-5f - add rn - add, register + register |
1026 | #define FX_ADD(reg) \ |
1027 | int32 s = SUSEX16(SREG) + SUSEX16(GSU.avReg[reg]); \ |
1028 | GSU.vCarry = s >= 0x10000; \ |
1029 | GSU.vOverflow = ~(SREG ^ GSU.avReg[reg]) & (GSU.avReg[reg] ^ s) & 0x8000; \ |
1030 | GSU.vSign = s; \ |
1031 | GSU.vZero = s; \ |
1032 | R15++; \ |
1033 | DREG = s; \ |
1034 | TESTR14; \ |
1035 | CLRFLAGS |
1036 | |
1037 | static void fx_add_r0 (void) |
1038 | { |
1039 | FX_ADD(0); |
1040 | } |
1041 | |
1042 | static void fx_add_r1 (void) |
1043 | { |
1044 | FX_ADD(1); |
1045 | } |
1046 | |
1047 | static void fx_add_r2 (void) |
1048 | { |
1049 | FX_ADD(2); |
1050 | } |
1051 | |
1052 | static void fx_add_r3 (void) |
1053 | { |
1054 | FX_ADD(3); |
1055 | } |
1056 | |
1057 | static void fx_add_r4 (void) |
1058 | { |
1059 | FX_ADD(4); |
1060 | } |
1061 | |
1062 | static void fx_add_r5 (void) |
1063 | { |
1064 | FX_ADD(5); |
1065 | } |
1066 | |
1067 | static void fx_add_r6 (void) |
1068 | { |
1069 | FX_ADD(6); |
1070 | } |
1071 | |
1072 | static void fx_add_r7 (void) |
1073 | { |
1074 | FX_ADD(7); |
1075 | } |
1076 | |
1077 | static void fx_add_r8 (void) |
1078 | { |
1079 | FX_ADD(8); |
1080 | } |
1081 | |
1082 | static void fx_add_r9 (void) |
1083 | { |
1084 | FX_ADD(9); |
1085 | } |
1086 | |
1087 | static void fx_add_r10 (void) |
1088 | { |
1089 | FX_ADD(10); |
1090 | } |
1091 | |
1092 | static void fx_add_r11 (void) |
1093 | { |
1094 | FX_ADD(11); |
1095 | } |
1096 | |
1097 | static void fx_add_r12 (void) |
1098 | { |
1099 | FX_ADD(12); |
1100 | } |
1101 | |
1102 | static void fx_add_r13 (void) |
1103 | { |
1104 | FX_ADD(13); |
1105 | } |
1106 | |
1107 | static void fx_add_r14 (void) |
1108 | { |
1109 | FX_ADD(14); |
1110 | } |
1111 | |
1112 | static void fx_add_r15 (void) |
1113 | { |
1114 | FX_ADD(15); |
1115 | } |
1116 | |
1117 | // 50-5f (ALT1) - adc rn - add with carry, register + register |
1118 | #define FX_ADC(reg) \ |
1119 | int32 s = SUSEX16(SREG) + SUSEX16(GSU.avReg[reg]) + SEX16(GSU.vCarry); \ |
1120 | GSU.vCarry = s >= 0x10000; \ |
1121 | GSU.vOverflow = ~(SREG ^ GSU.avReg[reg]) & (GSU.avReg[reg] ^ s) & 0x8000; \ |
1122 | GSU.vSign = s; \ |
1123 | GSU.vZero = s; \ |
1124 | R15++; \ |
1125 | DREG = s; \ |
1126 | TESTR14; \ |
1127 | CLRFLAGS |
1128 | |
1129 | static void fx_adc_r0 (void) |
1130 | { |
1131 | FX_ADC(0); |
1132 | } |
1133 | |
1134 | static void fx_adc_r1 (void) |
1135 | { |
1136 | FX_ADC(1); |
1137 | } |
1138 | |
1139 | static void fx_adc_r2 (void) |
1140 | { |
1141 | FX_ADC(2); |
1142 | } |
1143 | |
1144 | static void fx_adc_r3 (void) |
1145 | { |
1146 | FX_ADC(3); |
1147 | } |
1148 | |
1149 | static void fx_adc_r4 (void) |
1150 | { |
1151 | FX_ADC(4); |
1152 | } |
1153 | |
1154 | static void fx_adc_r5 (void) |
1155 | { |
1156 | FX_ADC(5); |
1157 | } |
1158 | |
1159 | static void fx_adc_r6 (void) |
1160 | { |
1161 | FX_ADC(6); |
1162 | } |
1163 | |
1164 | static void fx_adc_r7 (void) |
1165 | { |
1166 | FX_ADC(7); |
1167 | } |
1168 | |
1169 | static void fx_adc_r8 (void) |
1170 | { |
1171 | FX_ADC(8); |
1172 | } |
1173 | |
1174 | static void fx_adc_r9 (void) |
1175 | { |
1176 | FX_ADC(9); |
1177 | } |
1178 | |
1179 | static void fx_adc_r10 (void) |
1180 | { |
1181 | FX_ADC(10); |
1182 | } |
1183 | |
1184 | static void fx_adc_r11 (void) |
1185 | { |
1186 | FX_ADC(11); |
1187 | } |
1188 | |
1189 | static void fx_adc_r12 (void) |
1190 | { |
1191 | FX_ADC(12); |
1192 | } |
1193 | |
1194 | static void fx_adc_r13 (void) |
1195 | { |
1196 | FX_ADC(13); |
1197 | } |
1198 | |
1199 | static void fx_adc_r14 (void) |
1200 | { |
1201 | FX_ADC(14); |
1202 | } |
1203 | |
1204 | static void fx_adc_r15 (void) |
1205 | { |
1206 | FX_ADC(15); |
1207 | } |
1208 | |
1209 | // 50-5f (ALT2) - add #n - add, register + immediate |
1210 | #define FX_ADD_I(imm) \ |
1211 | int32 s = SUSEX16(SREG) + imm; \ |
1212 | GSU.vCarry = s >= 0x10000; \ |
1213 | GSU.vOverflow = ~(SREG ^ imm) & (imm ^ s) & 0x8000; \ |
1214 | GSU.vSign = s; \ |
1215 | GSU.vZero = s; \ |
1216 | R15++; \ |
1217 | DREG = s; \ |
1218 | TESTR14; \ |
1219 | CLRFLAGS |
1220 | |
1221 | static void fx_add_i0 (void) |
1222 | { |
1223 | FX_ADD_I(0); |
1224 | } |
1225 | |
1226 | static void fx_add_i1 (void) |
1227 | { |
1228 | FX_ADD_I(1); |
1229 | } |
1230 | |
1231 | static void fx_add_i2 (void) |
1232 | { |
1233 | FX_ADD_I(2); |
1234 | } |
1235 | |
1236 | static void fx_add_i3 (void) |
1237 | { |
1238 | FX_ADD_I(3); |
1239 | } |
1240 | |
1241 | static void fx_add_i4 (void) |
1242 | { |
1243 | FX_ADD_I(4); |
1244 | } |
1245 | |
1246 | static void fx_add_i5 (void) |
1247 | { |
1248 | FX_ADD_I(5); |
1249 | } |
1250 | |
1251 | static void fx_add_i6 (void) |
1252 | { |
1253 | FX_ADD_I(6); |
1254 | } |
1255 | |
1256 | static void fx_add_i7 (void) |
1257 | { |
1258 | FX_ADD_I(7); |
1259 | } |
1260 | |
1261 | static void fx_add_i8 (void) |
1262 | { |
1263 | FX_ADD_I(8); |
1264 | } |
1265 | |
1266 | static void fx_add_i9 (void) |
1267 | { |
1268 | FX_ADD_I(9); |
1269 | } |
1270 | |
1271 | static void fx_add_i10 (void) |
1272 | { |
1273 | FX_ADD_I(10); |
1274 | } |
1275 | |
1276 | static void fx_add_i11 (void) |
1277 | { |
1278 | FX_ADD_I(11); |
1279 | } |
1280 | |
1281 | static void fx_add_i12 (void) |
1282 | { |
1283 | FX_ADD_I(12); |
1284 | } |
1285 | |
1286 | static void fx_add_i13 (void) |
1287 | { |
1288 | FX_ADD_I(13); |
1289 | } |
1290 | |
1291 | static void fx_add_i14 (void) |
1292 | { |
1293 | FX_ADD_I(14); |
1294 | } |
1295 | |
1296 | static void fx_add_i15 (void) |
1297 | { |
1298 | FX_ADD_I(15); |
1299 | } |
1300 | |
1301 | // 50-5f (ALT3) - adc #n - add with carry, register + immediate |
1302 | #define FX_ADC_I(imm) \ |
1303 | int32 s = SUSEX16(SREG) + imm + SUSEX16(GSU.vCarry); \ |
1304 | GSU.vCarry = s >= 0x10000; \ |
1305 | GSU.vOverflow = ~(SREG ^ imm) & (imm ^ s) & 0x8000; \ |
1306 | GSU.vSign = s; \ |
1307 | GSU.vZero = s; \ |
1308 | R15++; \ |
1309 | DREG = s; \ |
1310 | TESTR14; \ |
1311 | CLRFLAGS |
1312 | |
1313 | static void fx_adc_i0 (void) |
1314 | { |
1315 | FX_ADC_I(0); |
1316 | } |
1317 | |
1318 | static void fx_adc_i1 (void) |
1319 | { |
1320 | FX_ADC_I(1); |
1321 | } |
1322 | |
1323 | static void fx_adc_i2 (void) |
1324 | { |
1325 | FX_ADC_I(2); |
1326 | } |
1327 | |
1328 | static void fx_adc_i3 (void) |
1329 | { |
1330 | FX_ADC_I(3); |
1331 | } |
1332 | |
1333 | static void fx_adc_i4 (void) |
1334 | { |
1335 | FX_ADC_I(4); |
1336 | } |
1337 | |
1338 | static void fx_adc_i5 (void) |
1339 | { |
1340 | FX_ADC_I(5); |
1341 | } |
1342 | |
1343 | static void fx_adc_i6 (void) |
1344 | { |
1345 | FX_ADC_I(6); |
1346 | } |
1347 | |
1348 | static void fx_adc_i7 (void) |
1349 | { |
1350 | FX_ADC_I(7); |
1351 | } |
1352 | |
1353 | static void fx_adc_i8 (void) |
1354 | { |
1355 | FX_ADC_I(8); |
1356 | } |
1357 | |
1358 | static void fx_adc_i9 (void) |
1359 | { |
1360 | FX_ADC_I(9); |
1361 | } |
1362 | |
1363 | static void fx_adc_i10 (void) |
1364 | { |
1365 | FX_ADC_I(10); |
1366 | } |
1367 | |
1368 | static void fx_adc_i11 (void) |
1369 | { |
1370 | FX_ADC_I(11); |
1371 | } |
1372 | |
1373 | static void fx_adc_i12 (void) |
1374 | { |
1375 | FX_ADC_I(12); |
1376 | } |
1377 | |
1378 | static void fx_adc_i13 (void) |
1379 | { |
1380 | FX_ADC_I(13); |
1381 | } |
1382 | |
1383 | static void fx_adc_i14 (void) |
1384 | { |
1385 | FX_ADC_I(14); |
1386 | } |
1387 | |
1388 | static void fx_adc_i15 (void) |
1389 | { |
1390 | FX_ADC_I(15); |
1391 | } |
1392 | |
1393 | // 60-6f - sub rn - subtract, register - register |
1394 | #define FX_SUB(reg) \ |
1395 | int32 s = SUSEX16(SREG) - SUSEX16(GSU.avReg[reg]); \ |
1396 | GSU.vCarry = s >= 0; \ |
1397 | GSU.vOverflow = (SREG ^ GSU.avReg[reg]) & (SREG ^ s) & 0x8000; \ |
1398 | GSU.vSign = s; \ |
1399 | GSU.vZero = s; \ |
1400 | R15++; \ |
1401 | DREG = s; \ |
1402 | TESTR14; \ |
1403 | CLRFLAGS |
1404 | |
1405 | static void fx_sub_r0 (void) |
1406 | { |
1407 | FX_SUB(0); |
1408 | } |
1409 | |
1410 | static void fx_sub_r1 (void) |
1411 | { |
1412 | FX_SUB(1); |
1413 | } |
1414 | |
1415 | static void fx_sub_r2 (void) |
1416 | { |
1417 | FX_SUB(2); |
1418 | } |
1419 | |
1420 | static void fx_sub_r3 (void) |
1421 | { |
1422 | FX_SUB(3); |
1423 | } |
1424 | |
1425 | static void fx_sub_r4 (void) |
1426 | { |
1427 | FX_SUB(4); |
1428 | } |
1429 | |
1430 | static void fx_sub_r5 (void) |
1431 | { |
1432 | FX_SUB(5); |
1433 | } |
1434 | |
1435 | static void fx_sub_r6 (void) |
1436 | { |
1437 | FX_SUB(6); |
1438 | } |
1439 | |
1440 | static void fx_sub_r7 (void) |
1441 | { |
1442 | FX_SUB(7); |
1443 | } |
1444 | |
1445 | static void fx_sub_r8 (void) |
1446 | { |
1447 | FX_SUB(8); |
1448 | } |
1449 | |
1450 | static void fx_sub_r9 (void) |
1451 | { |
1452 | FX_SUB(9); |
1453 | } |
1454 | |
1455 | static void fx_sub_r10 (void) |
1456 | { |
1457 | FX_SUB(10); |
1458 | } |
1459 | |
1460 | static void fx_sub_r11 (void) |
1461 | { |
1462 | FX_SUB(11); |
1463 | } |
1464 | |
1465 | static void fx_sub_r12 (void) |
1466 | { |
1467 | FX_SUB(12); |
1468 | } |
1469 | |
1470 | static void fx_sub_r13 (void) |
1471 | { |
1472 | FX_SUB(13); |
1473 | } |
1474 | |
1475 | static void fx_sub_r14 (void) |
1476 | { |
1477 | FX_SUB(14); |
1478 | } |
1479 | |
1480 | static void fx_sub_r15 (void) |
1481 | { |
1482 | FX_SUB(15); |
1483 | } |
1484 | |
1485 | // 60-6f (ALT1) - sbc rn - subtract with carry, register - register |
1486 | #define FX_SBC(reg) \ |
1487 | int32 s = SUSEX16(SREG) - SUSEX16(GSU.avReg[reg]) - (SUSEX16(GSU.vCarry ^ 1)); \ |
1488 | GSU.vCarry = s >= 0; \ |
1489 | GSU.vOverflow = (SREG ^ GSU.avReg[reg]) & (SREG ^ s) & 0x8000; \ |
1490 | GSU.vSign = s; \ |
1491 | GSU.vZero = s; \ |
1492 | R15++; \ |
1493 | DREG = s; \ |
1494 | TESTR14; \ |
1495 | CLRFLAGS |
1496 | |
1497 | static void fx_sbc_r0 (void) |
1498 | { |
1499 | FX_SBC(0); |
1500 | } |
1501 | |
1502 | static void fx_sbc_r1 (void) |
1503 | { |
1504 | FX_SBC(1); |
1505 | } |
1506 | |
1507 | static void fx_sbc_r2 (void) |
1508 | { |
1509 | FX_SBC(2); |
1510 | } |
1511 | |
1512 | static void fx_sbc_r3 (void) |
1513 | { |
1514 | FX_SBC(3); |
1515 | } |
1516 | |
1517 | static void fx_sbc_r4 (void) |
1518 | { |
1519 | FX_SBC(4); |
1520 | } |
1521 | |
1522 | static void fx_sbc_r5 (void) |
1523 | { |
1524 | FX_SBC(5); |
1525 | } |
1526 | |
1527 | static void fx_sbc_r6 (void) |
1528 | { |
1529 | FX_SBC(6); |
1530 | } |
1531 | |
1532 | static void fx_sbc_r7 (void) |
1533 | { |
1534 | FX_SBC(7); |
1535 | } |
1536 | |
1537 | static void fx_sbc_r8 (void) |
1538 | { |
1539 | FX_SBC(8); |
1540 | } |
1541 | |
1542 | static void fx_sbc_r9 (void) |
1543 | { |
1544 | FX_SBC(9); |
1545 | } |
1546 | |
1547 | static void fx_sbc_r10 (void) |
1548 | { |
1549 | FX_SBC(10); |
1550 | } |
1551 | |
1552 | static void fx_sbc_r11 (void) |
1553 | { |
1554 | FX_SBC(11); |
1555 | } |
1556 | |
1557 | static void fx_sbc_r12 (void) |
1558 | { |
1559 | FX_SBC(12); |
1560 | } |
1561 | |
1562 | static void fx_sbc_r13 (void) |
1563 | { |
1564 | FX_SBC(13); |
1565 | } |
1566 | |
1567 | static void fx_sbc_r14 (void) |
1568 | { |
1569 | FX_SBC(14); |
1570 | } |
1571 | |
1572 | static void fx_sbc_r15 (void) |
1573 | { |
1574 | FX_SBC(15); |
1575 | } |
1576 | |
1577 | // 60-6f (ALT2) - sub #n - subtract, register - immediate |
1578 | #define FX_SUB_I(imm) \ |
1579 | int32 s = SUSEX16(SREG) - imm; \ |
1580 | GSU.vCarry = s >= 0; \ |
1581 | GSU.vOverflow = (SREG ^ imm) & (SREG ^ s) & 0x8000; \ |
1582 | GSU.vSign = s; \ |
1583 | GSU.vZero = s; \ |
1584 | R15++; \ |
1585 | DREG = s; \ |
1586 | TESTR14; \ |
1587 | CLRFLAGS |
1588 | |
1589 | static void fx_sub_i0 (void) |
1590 | { |
1591 | FX_SUB_I(0); |
1592 | } |
1593 | |
1594 | static void fx_sub_i1 (void) |
1595 | { |
1596 | FX_SUB_I(1); |
1597 | } |
1598 | |
1599 | static void fx_sub_i2 (void) |
1600 | { |
1601 | FX_SUB_I(2); |
1602 | } |
1603 | |
1604 | static void fx_sub_i3 (void) |
1605 | { |
1606 | FX_SUB_I(3); |
1607 | } |
1608 | |
1609 | static void fx_sub_i4 (void) |
1610 | { |
1611 | FX_SUB_I(4); |
1612 | } |
1613 | |
1614 | static void fx_sub_i5 (void) |
1615 | { |
1616 | FX_SUB_I(5); |
1617 | } |
1618 | |
1619 | static void fx_sub_i6 (void) |
1620 | { |
1621 | FX_SUB_I(6); |
1622 | } |
1623 | |
1624 | static void fx_sub_i7 (void) |
1625 | { |
1626 | FX_SUB_I(7); |
1627 | } |
1628 | |
1629 | static void fx_sub_i8 (void) |
1630 | { |
1631 | FX_SUB_I(8); |
1632 | } |
1633 | |
1634 | static void fx_sub_i9 (void) |
1635 | { |
1636 | FX_SUB_I(9); |
1637 | } |
1638 | |
1639 | static void fx_sub_i10 (void) |
1640 | { |
1641 | FX_SUB_I(10); |
1642 | } |
1643 | |
1644 | static void fx_sub_i11 (void) |
1645 | { |
1646 | FX_SUB_I(11); |
1647 | } |
1648 | |
1649 | static void fx_sub_i12 (void) |
1650 | { |
1651 | FX_SUB_I(12); |
1652 | } |
1653 | |
1654 | static void fx_sub_i13 (void) |
1655 | { |
1656 | FX_SUB_I(13); |
1657 | } |
1658 | |
1659 | static void fx_sub_i14 (void) |
1660 | { |
1661 | FX_SUB_I(14); |
1662 | } |
1663 | |
1664 | static void fx_sub_i15 (void) |
1665 | { |
1666 | FX_SUB_I(15); |
1667 | } |
1668 | |
1669 | // 60-6f (ALT3) - cmp rn - compare, register, register |
1670 | #define FX_CMP(reg) \ |
1671 | int32 s = SUSEX16(SREG) - SUSEX16(GSU.avReg[reg]); \ |
1672 | GSU.vCarry = s >= 0; \ |
1673 | GSU.vOverflow = (SREG ^ GSU.avReg[reg]) & (SREG ^ s) & 0x8000; \ |
1674 | GSU.vSign = s; \ |
1675 | GSU.vZero = s; \ |
1676 | R15++; \ |
1677 | CLRFLAGS |
1678 | |
1679 | static void fx_cmp_r0 (void) |
1680 | { |
1681 | FX_CMP(0); |
1682 | } |
1683 | |
1684 | static void fx_cmp_r1 (void) |
1685 | { |
1686 | FX_CMP(1); |
1687 | } |
1688 | |
1689 | static void fx_cmp_r2 (void) |
1690 | { |
1691 | FX_CMP(2); |
1692 | } |
1693 | |
1694 | static void fx_cmp_r3 (void) |
1695 | { |
1696 | FX_CMP(3); |
1697 | } |
1698 | |
1699 | static void fx_cmp_r4 (void) |
1700 | { |
1701 | FX_CMP(4); |
1702 | } |
1703 | |
1704 | static void fx_cmp_r5 (void) |
1705 | { |
1706 | FX_CMP(5); |
1707 | } |
1708 | |
1709 | static void fx_cmp_r6 (void) |
1710 | { |
1711 | FX_CMP(6); |
1712 | } |
1713 | |
1714 | static void fx_cmp_r7 (void) |
1715 | { |
1716 | FX_CMP(7); |
1717 | } |
1718 | |
1719 | static void fx_cmp_r8 (void) |
1720 | { |
1721 | FX_CMP(8); |
1722 | } |
1723 | |
1724 | static void fx_cmp_r9 (void) |
1725 | { |
1726 | FX_CMP(9); |
1727 | } |
1728 | |
1729 | static void fx_cmp_r10 (void) |
1730 | { |
1731 | FX_CMP(10); |
1732 | } |
1733 | |
1734 | static void fx_cmp_r11 (void) |
1735 | { |
1736 | FX_CMP(11); |
1737 | } |
1738 | |
1739 | static void fx_cmp_r12 (void) |
1740 | { |
1741 | FX_CMP(12); |
1742 | } |
1743 | |
1744 | static void fx_cmp_r13 (void) |
1745 | { |
1746 | FX_CMP(13); |
1747 | } |
1748 | |
1749 | static void fx_cmp_r14 (void) |
1750 | { |
1751 | FX_CMP(14); |
1752 | } |
1753 | |
1754 | static void fx_cmp_r15 (void) |
1755 | { |
1756 | FX_CMP(15); |
1757 | } |
1758 | |
1759 | // 70 - merge - R7 as upper byte, R8 as lower byte (used for texture-mapping) |
1760 | static void fx_merge (void) |
1761 | { |
1762 | uint32 v = (R7 & 0xff00) | ((R8 & 0xff00) >> 8); |
1763 | R15++; |
1764 | DREG = v; |
1765 | GSU.vOverflow = (v & 0xc0c0) << 16; |
1766 | GSU.vZero = !(v & 0xf0f0); |
1767 | GSU.vSign = ((v | (v << 8)) & 0x8000); |
1768 | GSU.vCarry = (v & 0xe0e0) != 0; |
1769 | TESTR14; |
1770 | CLRFLAGS; |
1771 | } |
1772 | |
1773 | // 71-7f - and rn - reister & register |
1774 | #define FX_AND(reg) \ |
1775 | uint32 v = SREG & GSU.avReg[reg]; \ |
1776 | R15++; \ |
1777 | DREG = v; \ |
1778 | GSU.vSign = v; \ |
1779 | GSU.vZero = v; \ |
1780 | TESTR14; \ |
1781 | CLRFLAGS |
1782 | |
1783 | static void fx_and_r1 (void) |
1784 | { |
1785 | FX_AND(1); |
1786 | } |
1787 | |
1788 | static void fx_and_r2 (void) |
1789 | { |
1790 | FX_AND(2); |
1791 | } |
1792 | |
1793 | static void fx_and_r3 (void) |
1794 | { |
1795 | FX_AND(3); |
1796 | } |
1797 | |
1798 | static void fx_and_r4 (void) |
1799 | { |
1800 | FX_AND(4); |
1801 | } |
1802 | |
1803 | static void fx_and_r5 (void) |
1804 | { |
1805 | FX_AND(5); |
1806 | } |
1807 | |
1808 | static void fx_and_r6 (void) |
1809 | { |
1810 | FX_AND(6); |
1811 | } |
1812 | |
1813 | static void fx_and_r7 (void) |
1814 | { |
1815 | FX_AND(7); |
1816 | } |
1817 | |
1818 | static void fx_and_r8 (void) |
1819 | { |
1820 | FX_AND(8); |
1821 | } |
1822 | |
1823 | static void fx_and_r9 (void) |
1824 | { |
1825 | FX_AND(9); |
1826 | } |
1827 | |
1828 | static void fx_and_r10 (void) |
1829 | { |
1830 | FX_AND(10); |
1831 | } |
1832 | |
1833 | static void fx_and_r11 (void) |
1834 | { |
1835 | FX_AND(11); |
1836 | } |
1837 | |
1838 | static void fx_and_r12 (void) |
1839 | { |
1840 | FX_AND(12); |
1841 | } |
1842 | |
1843 | static void fx_and_r13 (void) |
1844 | { |
1845 | FX_AND(13); |
1846 | } |
1847 | |
1848 | static void fx_and_r14 (void) |
1849 | { |
1850 | FX_AND(14); |
1851 | } |
1852 | |
1853 | static void fx_and_r15 (void) |
1854 | { |
1855 | FX_AND(15); |
1856 | } |
1857 | |
1858 | // 71-7f (ALT1) - bic rn - reister & ~register |
1859 | #define FX_BIC(reg) \ |
1860 | uint32 v = SREG & ~GSU.avReg[reg]; \ |
1861 | R15++; \ |
1862 | DREG = v; \ |
1863 | GSU.vSign = v; \ |
1864 | GSU.vZero = v; \ |
1865 | TESTR14; \ |
1866 | CLRFLAGS |
1867 | |
1868 | static void fx_bic_r1 (void) |
1869 | { |
1870 | FX_BIC(1); |
1871 | } |
1872 | |
1873 | static void fx_bic_r2 (void) |
1874 | { |
1875 | FX_BIC(2); |
1876 | } |
1877 | |
1878 | static void fx_bic_r3 (void) |
1879 | { |
1880 | FX_BIC(3); |
1881 | } |
1882 | |
1883 | static void fx_bic_r4 (void) |
1884 | { |
1885 | FX_BIC(4); |
1886 | } |
1887 | |
1888 | static void fx_bic_r5 (void) |
1889 | { |
1890 | FX_BIC(5); |
1891 | } |
1892 | |
1893 | static void fx_bic_r6 (void) |
1894 | { |
1895 | FX_BIC(6); |
1896 | } |
1897 | |
1898 | static void fx_bic_r7 (void) |
1899 | { |
1900 | FX_BIC(7); |
1901 | } |
1902 | |
1903 | static void fx_bic_r8 (void) |
1904 | { |
1905 | FX_BIC(8); |
1906 | } |
1907 | |
1908 | static void fx_bic_r9 (void) |
1909 | { |
1910 | FX_BIC(9); |
1911 | } |
1912 | |
1913 | static void fx_bic_r10 (void) |
1914 | { |
1915 | FX_BIC(10); |
1916 | } |
1917 | |
1918 | static void fx_bic_r11 (void) |
1919 | { |
1920 | FX_BIC(11); |
1921 | } |
1922 | |
1923 | static void fx_bic_r12 (void) |
1924 | { |
1925 | FX_BIC(12); |
1926 | } |
1927 | |
1928 | static void fx_bic_r13 (void) |
1929 | { |
1930 | FX_BIC(13); |
1931 | } |
1932 | |
1933 | static void fx_bic_r14 (void) |
1934 | { |
1935 | FX_BIC(14); |
1936 | } |
1937 | |
1938 | static void fx_bic_r15 (void) |
1939 | { |
1940 | FX_BIC(15); |
1941 | } |
1942 | |
1943 | // 71-7f (ALT2) - and #n - reister & immediate |
1944 | #define FX_AND_I(imm) \ |
1945 | uint32 v = SREG & imm; \ |
1946 | R15++; \ |
1947 | DREG = v; \ |
1948 | GSU.vSign = v; \ |
1949 | GSU.vZero = v; \ |
1950 | TESTR14; \ |
1951 | CLRFLAGS |
1952 | |
1953 | static void fx_and_i1 (void) |
1954 | { |
1955 | FX_AND_I(1); |
1956 | } |
1957 | |
1958 | static void fx_and_i2 (void) |
1959 | { |
1960 | FX_AND_I(2); |
1961 | } |
1962 | |
1963 | static void fx_and_i3 (void) |
1964 | { |
1965 | FX_AND_I(3); |
1966 | } |
1967 | |
1968 | static void fx_and_i4 (void) |
1969 | { |
1970 | FX_AND_I(4); |
1971 | } |
1972 | |
1973 | static void fx_and_i5 (void) |
1974 | { |
1975 | FX_AND_I(5); |
1976 | } |
1977 | |
1978 | static void fx_and_i6 (void) |
1979 | { |
1980 | FX_AND_I(6); |
1981 | } |
1982 | |
1983 | static void fx_and_i7 (void) |
1984 | { |
1985 | FX_AND_I(7); |
1986 | } |
1987 | |
1988 | static void fx_and_i8 (void) |
1989 | { |
1990 | FX_AND_I(8); |
1991 | } |
1992 | |
1993 | static void fx_and_i9 (void) |
1994 | { |
1995 | FX_AND_I(9); |
1996 | } |
1997 | |
1998 | static void fx_and_i10 (void) |
1999 | { |
2000 | FX_AND_I(10); |
2001 | } |
2002 | |
2003 | static void fx_and_i11 (void) |
2004 | { |
2005 | FX_AND_I(11); |
2006 | } |
2007 | |
2008 | static void fx_and_i12 (void) |
2009 | { |
2010 | FX_AND_I(12); |
2011 | } |
2012 | |
2013 | static void fx_and_i13 (void) |
2014 | { |
2015 | FX_AND_I(13); |
2016 | } |
2017 | |
2018 | static void fx_and_i14 (void) |
2019 | { |
2020 | FX_AND_I(14); |
2021 | } |
2022 | |
2023 | static void fx_and_i15 (void) |
2024 | { |
2025 | FX_AND_I(15); |
2026 | } |
2027 | |
2028 | // 71-7f (ALT3) - bic #n - reister & ~immediate |
2029 | #define FX_BIC_I(imm) \ |
2030 | uint32 v = SREG & ~imm; \ |
2031 | R15++; \ |
2032 | DREG = v; \ |
2033 | GSU.vSign = v; \ |
2034 | GSU.vZero = v; \ |
2035 | TESTR14; \ |
2036 | CLRFLAGS |
2037 | |
2038 | static void fx_bic_i1 (void) |
2039 | { |
2040 | FX_BIC_I(1); |
2041 | } |
2042 | |
2043 | static void fx_bic_i2 (void) |
2044 | { |
2045 | FX_BIC_I(2); |
2046 | } |
2047 | |
2048 | static void fx_bic_i3 (void) |
2049 | { |
2050 | FX_BIC_I(3); |
2051 | } |
2052 | |
2053 | static void fx_bic_i4 (void) |
2054 | { |
2055 | FX_BIC_I(4); |
2056 | } |
2057 | |
2058 | static void fx_bic_i5 (void) |
2059 | { |
2060 | FX_BIC_I(5); |
2061 | } |
2062 | |
2063 | static void fx_bic_i6 (void) |
2064 | { |
2065 | FX_BIC_I(6); |
2066 | } |
2067 | |
2068 | static void fx_bic_i7 (void) |
2069 | { |
2070 | FX_BIC_I(7); |
2071 | } |
2072 | |
2073 | static void fx_bic_i8 (void) |
2074 | { |
2075 | FX_BIC_I(8); |
2076 | } |
2077 | |
2078 | static void fx_bic_i9 (void) |
2079 | { |
2080 | FX_BIC_I(9); |
2081 | } |
2082 | |
2083 | static void fx_bic_i10 (void) |
2084 | { |
2085 | FX_BIC_I(10); |
2086 | } |
2087 | |
2088 | static void fx_bic_i11 (void) |
2089 | { |
2090 | FX_BIC_I(11); |
2091 | } |
2092 | |
2093 | static void fx_bic_i12 (void) |
2094 | { |
2095 | FX_BIC_I(12); |
2096 | } |
2097 | |
2098 | static void fx_bic_i13 (void) |
2099 | { |
2100 | FX_BIC_I(13); |
2101 | } |
2102 | |
2103 | static void fx_bic_i14 (void) |
2104 | { |
2105 | FX_BIC_I(14); |
2106 | } |
2107 | |
2108 | static void fx_bic_i15 (void) |
2109 | { |
2110 | FX_BIC_I(15); |
2111 | } |
2112 | |
2113 | // 80-8f - mult rn - 8 bit to 16 bit signed multiply, register * register |
2114 | #define FX_MULT(reg) \ |
2115 | uint32 v = (uint32) (SEX8(SREG) * SEX8(GSU.avReg[reg])); \ |
2116 | R15++; \ |
2117 | DREG = v; \ |
2118 | GSU.vSign = v; \ |
2119 | GSU.vZero = v; \ |
2120 | TESTR14; \ |
2121 | CLRFLAGS |
2122 | |
2123 | static void fx_mult_r0 (void) |
2124 | { |
2125 | FX_MULT(0); |
2126 | } |
2127 | |
2128 | static void fx_mult_r1 (void) |
2129 | { |
2130 | FX_MULT(1); |
2131 | } |
2132 | |
2133 | static void fx_mult_r2 (void) |
2134 | { |
2135 | FX_MULT(2); |
2136 | } |
2137 | |
2138 | static void fx_mult_r3 (void) |
2139 | { |
2140 | FX_MULT(3); |
2141 | } |
2142 | |
2143 | static void fx_mult_r4 (void) |
2144 | { |
2145 | FX_MULT(4); |
2146 | } |
2147 | |
2148 | static void fx_mult_r5 (void) |
2149 | { |
2150 | FX_MULT(5); |
2151 | } |
2152 | |
2153 | static void fx_mult_r6 (void) |
2154 | { |
2155 | FX_MULT(6); |
2156 | } |
2157 | |
2158 | static void fx_mult_r7 (void) |
2159 | { |
2160 | FX_MULT(7); |
2161 | } |
2162 | |
2163 | static void fx_mult_r8 (void) |
2164 | { |
2165 | FX_MULT(8); |
2166 | } |
2167 | |
2168 | static void fx_mult_r9 (void) |
2169 | { |
2170 | FX_MULT(9); |
2171 | } |
2172 | |
2173 | static void fx_mult_r10 (void) |
2174 | { |
2175 | FX_MULT(10); |
2176 | } |
2177 | |
2178 | static void fx_mult_r11 (void) |
2179 | { |
2180 | FX_MULT(11); |
2181 | } |
2182 | |
2183 | static void fx_mult_r12 (void) |
2184 | { |
2185 | FX_MULT(12); |
2186 | } |
2187 | |
2188 | static void fx_mult_r13 (void) |
2189 | { |
2190 | FX_MULT(13); |
2191 | } |
2192 | |
2193 | static void fx_mult_r14 (void) |
2194 | { |
2195 | FX_MULT(14); |
2196 | } |
2197 | |
2198 | static void fx_mult_r15 (void) |
2199 | { |
2200 | FX_MULT(15); |
2201 | } |
2202 | |
2203 | // 80-8f (ALT1) - umult rn - 8 bit to 16 bit unsigned multiply, register * register |
2204 | #define FX_UMULT(reg) \ |
2205 | uint32 v = USEX8(SREG) * USEX8(GSU.avReg[reg]); \ |
2206 | R15++; \ |
2207 | DREG = v; \ |
2208 | GSU.vSign = v; \ |
2209 | GSU.vZero = v; \ |
2210 | TESTR14; \ |
2211 | CLRFLAGS |
2212 | |
2213 | static void fx_umult_r0 (void) |
2214 | { |
2215 | FX_UMULT(0); |
2216 | } |
2217 | |
2218 | static void fx_umult_r1 (void) |
2219 | { |
2220 | FX_UMULT(1); |
2221 | } |
2222 | |
2223 | static void fx_umult_r2 (void) |
2224 | { |
2225 | FX_UMULT(2); |
2226 | } |
2227 | |
2228 | static void fx_umult_r3 (void) |
2229 | { |
2230 | FX_UMULT(3); |
2231 | } |
2232 | |
2233 | static void fx_umult_r4 (void) |
2234 | { |
2235 | FX_UMULT(4); |
2236 | } |
2237 | |
2238 | static void fx_umult_r5 (void) |
2239 | { |
2240 | FX_UMULT(5); |
2241 | } |
2242 | |
2243 | static void fx_umult_r6 (void) |
2244 | { |
2245 | FX_UMULT(6); |
2246 | } |
2247 | |
2248 | static void fx_umult_r7 (void) |
2249 | { |
2250 | FX_UMULT(7); |
2251 | } |
2252 | |
2253 | static void fx_umult_r8 (void) |
2254 | { |
2255 | FX_UMULT(8); |
2256 | } |
2257 | |
2258 | static void fx_umult_r9 (void) |
2259 | { |
2260 | FX_UMULT(9); |
2261 | } |
2262 | |
2263 | static void fx_umult_r10 (void) |
2264 | { |
2265 | FX_UMULT(10); |
2266 | } |
2267 | |
2268 | static void fx_umult_r11 (void) |
2269 | { |
2270 | FX_UMULT(11); |
2271 | } |
2272 | |
2273 | static void fx_umult_r12 (void) |
2274 | { |
2275 | FX_UMULT(12); |
2276 | } |
2277 | |
2278 | static void fx_umult_r13 (void) |
2279 | { |
2280 | FX_UMULT(13); |
2281 | } |
2282 | |
2283 | static void fx_umult_r14 (void) |
2284 | { |
2285 | FX_UMULT(14); |
2286 | } |
2287 | |
2288 | static void fx_umult_r15 (void) |
2289 | { |
2290 | FX_UMULT(15); |
2291 | } |
2292 | |
2293 | // 80-8f (ALT2) - mult #n - 8 bit to 16 bit signed multiply, register * immediate |
2294 | #define FX_MULT_I(imm) \ |
2295 | uint32 v = (uint32) (SEX8(SREG) * ((int32) imm)); \ |
2296 | R15++; \ |
2297 | DREG = v; \ |
2298 | GSU.vSign = v; \ |
2299 | GSU.vZero = v; \ |
2300 | TESTR14; \ |
2301 | CLRFLAGS |
2302 | |
2303 | static void fx_mult_i0 (void) |
2304 | { |
2305 | FX_MULT_I(0); |
2306 | } |
2307 | |
2308 | static void fx_mult_i1 (void) |
2309 | { |
2310 | FX_MULT_I(1); |
2311 | } |
2312 | |
2313 | static void fx_mult_i2 (void) |
2314 | { |
2315 | FX_MULT_I(2); |
2316 | } |
2317 | |
2318 | static void fx_mult_i3 (void) |
2319 | { |
2320 | FX_MULT_I(3); |
2321 | } |
2322 | |
2323 | static void fx_mult_i4 (void) |
2324 | { |
2325 | FX_MULT_I(4); |
2326 | } |
2327 | |
2328 | static void fx_mult_i5 (void) |
2329 | { |
2330 | FX_MULT_I(5); |
2331 | } |
2332 | |
2333 | static void fx_mult_i6 (void) |
2334 | { |
2335 | FX_MULT_I(6); |
2336 | } |
2337 | |
2338 | static void fx_mult_i7 (void) |
2339 | { |
2340 | FX_MULT_I(7); |
2341 | } |
2342 | |
2343 | static void fx_mult_i8 (void) |
2344 | { |
2345 | FX_MULT_I(8); |
2346 | } |
2347 | |
2348 | static void fx_mult_i9 (void) |
2349 | { |
2350 | FX_MULT_I(9); |
2351 | } |
2352 | |
2353 | static void fx_mult_i10 (void) |
2354 | { |
2355 | FX_MULT_I(10); |
2356 | } |
2357 | |
2358 | static void fx_mult_i11 (void) |
2359 | { |
2360 | FX_MULT_I(11); |
2361 | } |
2362 | |
2363 | static void fx_mult_i12 (void) |
2364 | { |
2365 | FX_MULT_I(12); |
2366 | } |
2367 | |
2368 | static void fx_mult_i13 (void) |
2369 | { |
2370 | FX_MULT_I(13); |
2371 | } |
2372 | |
2373 | static void fx_mult_i14 (void) |
2374 | { |
2375 | FX_MULT_I(14); |
2376 | } |
2377 | |
2378 | static void fx_mult_i15 (void) |
2379 | { |
2380 | FX_MULT_I(15); |
2381 | } |
2382 | |
2383 | // 80-8f (ALT3) - umult #n - 8 bit to 16 bit unsigned multiply, register * immediate |
2384 | #define FX_UMULT_I(imm) \ |
2385 | uint32 v = USEX8(SREG) * ((uint32) imm); \ |
2386 | R15++; \ |
2387 | DREG = v; \ |
2388 | GSU.vSign = v; \ |
2389 | GSU.vZero = v; \ |
2390 | TESTR14; \ |
2391 | CLRFLAGS |
2392 | |
2393 | static void fx_umult_i0 (void) |
2394 | { |
2395 | FX_UMULT_I(0); |
2396 | } |
2397 | |
2398 | static void fx_umult_i1 (void) |
2399 | { |
2400 | FX_UMULT_I(1); |
2401 | } |
2402 | |
2403 | static void fx_umult_i2 (void) |
2404 | { |
2405 | FX_UMULT_I(2); |
2406 | } |
2407 | |
2408 | static void fx_umult_i3 (void) |
2409 | { |
2410 | FX_UMULT_I(3); |
2411 | } |
2412 | |
2413 | static void fx_umult_i4 (void) |
2414 | { |
2415 | FX_UMULT_I(4); |
2416 | } |
2417 | |
2418 | static void fx_umult_i5 (void) |
2419 | { |
2420 | FX_UMULT_I(5); |
2421 | } |
2422 | |
2423 | static void fx_umult_i6 (void) |
2424 | { |
2425 | FX_UMULT_I(6); |
2426 | } |
2427 | |
2428 | static void fx_umult_i7 (void) |
2429 | { |
2430 | FX_UMULT_I(7); |
2431 | } |
2432 | |
2433 | static void fx_umult_i8 (void) |
2434 | { |
2435 | FX_UMULT_I(8); |
2436 | } |
2437 | |
2438 | static void fx_umult_i9 (void) |
2439 | { |
2440 | FX_UMULT_I(9); |
2441 | } |
2442 | |
2443 | static void fx_umult_i10 (void) |
2444 | { |
2445 | FX_UMULT_I(10); |
2446 | } |
2447 | |
2448 | static void fx_umult_i11 (void) |
2449 | { |
2450 | FX_UMULT_I(11); |
2451 | } |
2452 | |
2453 | static void fx_umult_i12 (void) |
2454 | { |
2455 | FX_UMULT_I(12); |
2456 | } |
2457 | |
2458 | static void fx_umult_i13 (void) |
2459 | { |
2460 | FX_UMULT_I(13); |
2461 | } |
2462 | |
2463 | static void fx_umult_i14 (void) |
2464 | { |
2465 | FX_UMULT_I(14); |
2466 | } |
2467 | |
2468 | static void fx_umult_i15 (void) |
2469 | { |
2470 | FX_UMULT_I(15); |
2471 | } |
2472 | |
2473 | // 90 - sbk - store word to last accessed RAM address |
2474 | static void fx_sbk (void) |
2475 | { |
2476 | RAM(GSU.vLastRamAdr) = (uint8) SREG; |
2477 | RAM(GSU.vLastRamAdr ^ 1) = (uint8) (SREG >> 8); |
2478 | CLRFLAGS; |
2479 | R15++; |
2480 | } |
2481 | |
2482 | // 91-94 - link #n - R11 = R15 + immediate |
2483 | #define FX_LINK_I(lkn) \ |
2484 | R11 = R15 + lkn; \ |
2485 | CLRFLAGS; \ |
2486 | R15++ |
2487 | |
2488 | static void fx_link_i1 (void) |
2489 | { |
2490 | FX_LINK_I(1); |
2491 | } |
2492 | |
2493 | static void fx_link_i2 (void) |
2494 | { |
2495 | FX_LINK_I(2); |
2496 | } |
2497 | |
2498 | static void fx_link_i3 (void) |
2499 | { |
2500 | FX_LINK_I(3); |
2501 | } |
2502 | |
2503 | static void fx_link_i4 (void) |
2504 | { |
2505 | FX_LINK_I(4); |
2506 | } |
2507 | |
2508 | // 95 - sex - sign extend 8 bit to 16 bit |
2509 | static void fx_sex (void) |
2510 | { |
2511 | uint32 v = (uint32) SEX8(SREG); |
2512 | R15++; |
2513 | DREG = v; |
2514 | GSU.vSign = v; |
2515 | GSU.vZero = v; |
2516 | TESTR14; |
2517 | CLRFLAGS; |
2518 | } |
2519 | |
2520 | // 96 - asr - aritmetric shift right by one |
2521 | static void fx_asr (void) |
2522 | { |
2523 | uint32 v; |
2524 | GSU.vCarry = SREG & 1; |
2525 | v = (uint32) (SEX16(SREG) >> 1); |
2526 | R15++; |
2527 | DREG = v; |
2528 | GSU.vSign = v; |
2529 | GSU.vZero = v; |
2530 | TESTR14; |
2531 | CLRFLAGS; |
2532 | } |
2533 | |
2534 | // 96 (ALT1) - div2 - aritmetric shift right by one |
2535 | static void fx_div2 (void) |
2536 | { |
2537 | uint32 v; |
2538 | int32 s = SEX16(SREG); |
2539 | GSU.vCarry = s & 1; |
2540 | if (s == -1) |
2541 | v = 0; |
2542 | else |
2543 | v = (uint32) (s >> 1); |
2544 | R15++; |
2545 | DREG = v; |
2546 | GSU.vSign = v; |
2547 | GSU.vZero = v; |
2548 | TESTR14; |
2549 | CLRFLAGS; |
2550 | } |
2551 | |
2552 | // 97 - ror - rotate right by one |
2553 | static void fx_ror (void) |
2554 | { |
2555 | uint32 v = (USEX16(SREG) >> 1) | (GSU.vCarry << 15); |
2556 | GSU.vCarry = SREG & 1; |
2557 | R15++; |
2558 | DREG = v; |
2559 | GSU.vSign = v; |
2560 | GSU.vZero = v; |
2561 | TESTR14; |
2562 | CLRFLAGS; |
2563 | } |
2564 | |
2565 | // 98-9d - jmp rn - jump to address of register |
2566 | #define FX_JMP(reg) \ |
2567 | R15 = GSU.avReg[reg]; \ |
2568 | CLRFLAGS |
2569 | |
2570 | static void fx_jmp_r8 (void) |
2571 | { |
2572 | FX_JMP(8); |
2573 | } |
2574 | |
2575 | static void fx_jmp_r9 (void) |
2576 | { |
2577 | FX_JMP(9); |
2578 | } |
2579 | |
2580 | static void fx_jmp_r10 (void) |
2581 | { |
2582 | FX_JMP(10); |
2583 | } |
2584 | |
2585 | static void fx_jmp_r11 (void) |
2586 | { |
2587 | FX_JMP(11); |
2588 | } |
2589 | |
2590 | static void fx_jmp_r12 (void) |
2591 | { |
2592 | FX_JMP(12); |
2593 | } |
2594 | |
2595 | static void fx_jmp_r13 (void) |
2596 | { |
2597 | FX_JMP(13); |
2598 | } |
2599 | |
2600 | // 98-9d (ALT1) - ljmp rn - set program bank to source register and jump to address of register |
2601 | #define FX_LJMP(reg) \ |
2602 | GSU.vPrgBankReg = GSU.avReg[reg] & 0x7f; \ |
2603 | GSU.pvPrgBank = GSU.apvRomBank[GSU.vPrgBankReg]; \ |
2604 | R15 = SREG; \ |
2605 | GSU.bCacheActive = FALSE; \ |
2606 | fx_cache(); \ |
2607 | R15-- |
2608 | |
2609 | static void fx_ljmp_r8 (void) |
2610 | { |
2611 | FX_LJMP(8); |
2612 | } |
2613 | |
2614 | static void fx_ljmp_r9 (void) |
2615 | { |
2616 | FX_LJMP(9); |
2617 | } |
2618 | |
2619 | static void fx_ljmp_r10 (void) |
2620 | { |
2621 | FX_LJMP(10); |
2622 | } |
2623 | |
2624 | static void fx_ljmp_r11 (void) |
2625 | { |
2626 | FX_LJMP(11); |
2627 | } |
2628 | |
2629 | static void fx_ljmp_r12 (void) |
2630 | { |
2631 | FX_LJMP(12); |
2632 | } |
2633 | |
2634 | static void fx_ljmp_r13 (void) |
2635 | { |
2636 | FX_LJMP(13); |
2637 | } |
2638 | |
2639 | // 9e - lob - set upper byte to zero (keep low byte) |
2640 | static void fx_lob (void) |
2641 | { |
2642 | uint32 v = USEX8(SREG); |
2643 | R15++; |
2644 | DREG = v; |
2645 | GSU.vSign = v << 8; |
2646 | GSU.vZero = v << 8; |
2647 | TESTR14; |
2648 | CLRFLAGS; |
2649 | } |
2650 | |
2651 | // 9f - fmult - 16 bit to 32 bit signed multiplication, upper 16 bits only |
2652 | static void fx_fmult (void) |
2653 | { |
2654 | uint32 v; |
2655 | uint32 c = (uint32) (SEX16(SREG) * SEX16(R6)); |
2656 | v = c >> 16; |
2657 | R15++; |
2658 | DREG = v; |
2659 | GSU.vSign = v; |
2660 | GSU.vZero = v; |
2661 | GSU.vCarry = (c >> 15) & 1; |
2662 | TESTR14; |
2663 | CLRFLAGS; |
2664 | } |
2665 | |
2666 | // 9f (ALT1) - lmult - 16 bit to 32 bit signed multiplication |
2667 | static void fx_lmult (void) |
2668 | { |
2669 | uint32 v; |
2670 | uint32 c = (uint32) (SEX16(SREG) * SEX16(R6)); |
2671 | R4 = c; |
2672 | v = c >> 16; |
2673 | R15++; |
2674 | DREG = v; |
2675 | GSU.vSign = v; |
2676 | GSU.vZero = v; |
2677 | // XXX: R6 or R4? |
2678 | GSU.vCarry = (R4 >> 15) & 1; // should it be bit 15 of R4 instead ? |
2679 | TESTR14; |
2680 | CLRFLAGS; |
2681 | } |
2682 | |
2683 | // a0-af - ibt rn, #pp - immediate byte transfer |
2684 | #define FX_IBT(reg) \ |
2685 | uint8 v = PIPE; \ |
2686 | R15++; \ |
2687 | FETCHPIPE; \ |
2688 | R15++; \ |
2689 | GSU.avReg[reg] = SEX8(v); \ |
2690 | CLRFLAGS |
2691 | |
2692 | static void fx_ibt_r0 (void) |
2693 | { |
2694 | FX_IBT(0); |
2695 | } |
2696 | |
2697 | static void fx_ibt_r1 (void) |
2698 | { |
2699 | FX_IBT(1); |
2700 | } |
2701 | |
2702 | static void fx_ibt_r2 (void) |
2703 | { |
2704 | FX_IBT(2); |
2705 | } |
2706 | |
2707 | static void fx_ibt_r3 (void) |
2708 | { |
2709 | FX_IBT(3); |
2710 | } |
2711 | |
2712 | static void fx_ibt_r4 (void) |
2713 | { |
2714 | FX_IBT(4); |
2715 | } |
2716 | |
2717 | static void fx_ibt_r5 (void) |
2718 | { |
2719 | FX_IBT(5); |
2720 | } |
2721 | |
2722 | static void fx_ibt_r6 (void) |
2723 | { |
2724 | FX_IBT(6); |
2725 | } |
2726 | |
2727 | static void fx_ibt_r7 (void) |
2728 | { |
2729 | FX_IBT(7); |
2730 | } |
2731 | |
2732 | static void fx_ibt_r8 (void) |
2733 | { |
2734 | FX_IBT(8); |
2735 | } |
2736 | |
2737 | static void fx_ibt_r9 (void) |
2738 | { |
2739 | FX_IBT(9); |
2740 | } |
2741 | |
2742 | static void fx_ibt_r10 (void) |
2743 | { |
2744 | FX_IBT(10); |
2745 | } |
2746 | |
2747 | static void fx_ibt_r11 (void) |
2748 | { |
2749 | FX_IBT(11); |
2750 | } |
2751 | |
2752 | static void fx_ibt_r12 (void) |
2753 | { |
2754 | FX_IBT(12); |
2755 | } |
2756 | |
2757 | static void fx_ibt_r13 (void) |
2758 | { |
2759 | FX_IBT(13); |
2760 | } |
2761 | |
2762 | static void fx_ibt_r14 (void) |
2763 | { |
2764 | FX_IBT(14); |
2765 | READR14; |
2766 | } |
2767 | |
2768 | static void fx_ibt_r15 (void) |
2769 | { |
2770 | FX_IBT(15); |
2771 | } |
2772 | |
2773 | // a0-af (ALT1) - lms rn, (yy) - load word from RAM (short address) |
2774 | #define FX_LMS(reg) \ |
2775 | GSU.vLastRamAdr = ((uint32) PIPE) << 1; \ |
2776 | R15++; \ |
2777 | FETCHPIPE; \ |
2778 | R15++; \ |
2779 | GSU.avReg[reg] = (uint32) RAM(GSU.vLastRamAdr); \ |
2780 | GSU.avReg[reg] |= ((uint32) RAM(GSU.vLastRamAdr + 1)) << 8; \ |
2781 | CLRFLAGS |
2782 | |
2783 | static void fx_lms_r0 (void) |
2784 | { |
2785 | FX_LMS(0); |
2786 | } |
2787 | |
2788 | static void fx_lms_r1 (void) |
2789 | { |
2790 | FX_LMS(1); |
2791 | } |
2792 | |
2793 | static void fx_lms_r2 (void) |
2794 | { |
2795 | FX_LMS(2); |
2796 | } |
2797 | |
2798 | static void fx_lms_r3 (void) |
2799 | { |
2800 | FX_LMS(3); |
2801 | } |
2802 | |
2803 | static void fx_lms_r4 (void) |
2804 | { |
2805 | FX_LMS(4); |
2806 | } |
2807 | |
2808 | static void fx_lms_r5 (void) |
2809 | { |
2810 | FX_LMS(5); |
2811 | } |
2812 | |
2813 | static void fx_lms_r6 (void) |
2814 | { |
2815 | FX_LMS(6); |
2816 | } |
2817 | |
2818 | static void fx_lms_r7 (void) |
2819 | { |
2820 | FX_LMS(7); |
2821 | } |
2822 | |
2823 | static void fx_lms_r8 (void) |
2824 | { |
2825 | FX_LMS(8); |
2826 | } |
2827 | |
2828 | static void fx_lms_r9 (void) |
2829 | { |
2830 | FX_LMS(9); |
2831 | } |
2832 | |
2833 | static void fx_lms_r10 (void) |
2834 | { |
2835 | FX_LMS(10); |
2836 | } |
2837 | |
2838 | static void fx_lms_r11 (void) |
2839 | { |
2840 | FX_LMS(11); |
2841 | } |
2842 | |
2843 | static void fx_lms_r12 (void) |
2844 | { |
2845 | FX_LMS(12); |
2846 | } |
2847 | |
2848 | static void fx_lms_r13 (void) |
2849 | { |
2850 | FX_LMS(13); |
2851 | } |
2852 | |
2853 | static void fx_lms_r14 (void) |
2854 | { |
2855 | FX_LMS(14); |
2856 | READR14; |
2857 | } |
2858 | |
2859 | static void fx_lms_r15 (void) |
2860 | { |
2861 | FX_LMS(15); |
2862 | } |
2863 | |
2864 | // a0-af (ALT2) - sms (yy), rn - store word in RAM (short address) |
2865 | // XXX: If rn == r15, is the value of r15 before or after the extra byte is read ? |
2866 | #define FX_SMS(reg) \ |
2867 | uint32 v = GSU.avReg[reg]; \ |
2868 | GSU.vLastRamAdr = ((uint32) PIPE) << 1; \ |
2869 | R15++; \ |
2870 | FETCHPIPE; \ |
2871 | RAM(GSU.vLastRamAdr) = (uint8) v; \ |
2872 | RAM(GSU.vLastRamAdr + 1) = (uint8) (v >> 8); \ |
2873 | CLRFLAGS; \ |
2874 | R15++ |
2875 | |
2876 | static void fx_sms_r0 (void) |
2877 | { |
2878 | FX_SMS(0); |
2879 | } |
2880 | |
2881 | static void fx_sms_r1 (void) |
2882 | { |
2883 | FX_SMS(1); |
2884 | } |
2885 | |
2886 | static void fx_sms_r2 (void) |
2887 | { |
2888 | FX_SMS(2); |
2889 | } |
2890 | |
2891 | static void fx_sms_r3 (void) |
2892 | { |
2893 | FX_SMS(3); |
2894 | } |
2895 | |
2896 | static void fx_sms_r4 (void) |
2897 | { |
2898 | FX_SMS(4); |
2899 | } |
2900 | |
2901 | static void fx_sms_r5 (void) |
2902 | { |
2903 | FX_SMS(5); |
2904 | } |
2905 | |
2906 | static void fx_sms_r6 (void) |
2907 | { |
2908 | FX_SMS(6); |
2909 | } |
2910 | |
2911 | static void fx_sms_r7 (void) |
2912 | { |
2913 | FX_SMS(7); |
2914 | } |
2915 | |
2916 | static void fx_sms_r8 (void) |
2917 | { |
2918 | FX_SMS(8); |
2919 | } |
2920 | |
2921 | static void fx_sms_r9 (void) |
2922 | { |
2923 | FX_SMS(9); |
2924 | } |
2925 | |
2926 | static void fx_sms_r10 (void) |
2927 | { |
2928 | FX_SMS(10); |
2929 | } |
2930 | |
2931 | static void fx_sms_r11 (void) |
2932 | { |
2933 | FX_SMS(11); |
2934 | } |
2935 | |
2936 | static void fx_sms_r12 (void) |
2937 | { |
2938 | FX_SMS(12); |
2939 | } |
2940 | |
2941 | static void fx_sms_r13 (void) |
2942 | { |
2943 | FX_SMS(13); |
2944 | } |
2945 | |
2946 | static void fx_sms_r14 (void) |
2947 | { |
2948 | FX_SMS(14); |
2949 | } |
2950 | |
2951 | static void fx_sms_r15 (void) |
2952 | { |
2953 | FX_SMS(15); |
2954 | } |
2955 | |
2956 | // b0-bf - from rn - set source register |
2957 | // b0-bf (B) - moves rn - move register to register, and set flags, (if B flag is set) |
2958 | #define FX_FROM(reg) \ |
2959 | if (TF(B)) \ |
2960 | { \ |
2961 | uint32 v = GSU.avReg[reg]; \ |
2962 | R15++; \ |
2963 | DREG = v; \ |
2964 | GSU.vOverflow = (v & 0x80) << 16; \ |
2965 | GSU.vSign = v; \ |
2966 | GSU.vZero = v; \ |
2967 | TESTR14; \ |
2968 | CLRFLAGS; \ |
2969 | } \ |
2970 | else \ |
2971 | { \ |
2972 | GSU.pvSreg = &GSU.avReg[reg]; \ |
2973 | R15++; \ |
2974 | } |
2975 | |
2976 | static void fx_from_r0 (void) |
2977 | { |
2978 | FX_FROM(0); |
2979 | } |
2980 | |
2981 | static void fx_from_r1 (void) |
2982 | { |
2983 | FX_FROM(1); |
2984 | } |
2985 | |
2986 | static void fx_from_r2 (void) |
2987 | { |
2988 | FX_FROM(2); |
2989 | } |
2990 | |
2991 | static void fx_from_r3 (void) |
2992 | { |
2993 | FX_FROM(3); |
2994 | } |
2995 | |
2996 | static void fx_from_r4 (void) |
2997 | { |
2998 | FX_FROM(4); |
2999 | } |
3000 | |
3001 | static void fx_from_r5 (void) |
3002 | { |
3003 | FX_FROM(5); |
3004 | } |
3005 | |
3006 | static void fx_from_r6 (void) |
3007 | { |
3008 | FX_FROM(6); |
3009 | } |
3010 | |
3011 | static void fx_from_r7 (void) |
3012 | { |
3013 | FX_FROM(7); |
3014 | } |
3015 | |
3016 | static void fx_from_r8 (void) |
3017 | { |
3018 | FX_FROM(8); |
3019 | } |
3020 | |
3021 | static void fx_from_r9 (void) |
3022 | { |
3023 | FX_FROM(9); |
3024 | } |
3025 | |
3026 | static void fx_from_r10 (void) |
3027 | { |
3028 | FX_FROM(10); |
3029 | } |
3030 | |
3031 | static void fx_from_r11 (void) |
3032 | { |
3033 | FX_FROM(11); |
3034 | } |
3035 | |
3036 | static void fx_from_r12 (void) |
3037 | { |
3038 | FX_FROM(12); |
3039 | } |
3040 | |
3041 | static void fx_from_r13 (void) |
3042 | { |
3043 | FX_FROM(13); |
3044 | } |
3045 | |
3046 | static void fx_from_r14 (void) |
3047 | { |
3048 | FX_FROM(14); |
3049 | } |
3050 | |
3051 | static void fx_from_r15 (void) |
3052 | { |
3053 | FX_FROM(15); |
3054 | } |
3055 | |
3056 | // c0 - hib - move high-byte to low-byte |
3057 | static void fx_hib (void) |
3058 | { |
3059 | uint32 v = USEX8(SREG >> 8); |
3060 | R15++; |
3061 | DREG = v; |
3062 | GSU.vSign = v << 8; |
3063 | GSU.vZero = v << 8; |
3064 | TESTR14; |
3065 | CLRFLAGS; |
3066 | } |
3067 | |
3068 | // c1-cf - or rn |
3069 | #define FX_OR(reg) \ |
3070 | uint32 v = SREG | GSU.avReg[reg]; \ |
3071 | R15++; \ |
3072 | DREG = v; \ |
3073 | GSU.vSign = v; \ |
3074 | GSU.vZero = v; \ |
3075 | TESTR14; \ |
3076 | CLRFLAGS |
3077 | |
3078 | static void fx_or_r1 (void) |
3079 | { |
3080 | FX_OR(1); |
3081 | } |
3082 | |
3083 | static void fx_or_r2 (void) |
3084 | { |
3085 | FX_OR(2); |
3086 | } |
3087 | |
3088 | static void fx_or_r3 (void) |
3089 | { |
3090 | FX_OR(3); |
3091 | } |
3092 | |
3093 | static void fx_or_r4 (void) |
3094 | { |
3095 | FX_OR(4); |
3096 | } |
3097 | |
3098 | static void fx_or_r5 (void) |
3099 | { |
3100 | FX_OR(5); |
3101 | } |
3102 | |
3103 | static void fx_or_r6 (void) |
3104 | { |
3105 | FX_OR(6); |
3106 | } |
3107 | |
3108 | static void fx_or_r7 (void) |
3109 | { |
3110 | FX_OR(7); |
3111 | } |
3112 | |
3113 | static void fx_or_r8 (void) |
3114 | { |
3115 | FX_OR(8); |
3116 | } |
3117 | |
3118 | static void fx_or_r9 (void) |
3119 | { |
3120 | FX_OR(9); |
3121 | } |
3122 | |
3123 | static void fx_or_r10 (void) |
3124 | { |
3125 | FX_OR(10); |
3126 | } |
3127 | |
3128 | static void fx_or_r11 (void) |
3129 | { |
3130 | FX_OR(11); |
3131 | } |
3132 | |
3133 | static void fx_or_r12 (void) |
3134 | { |
3135 | FX_OR(12); |
3136 | } |
3137 | |
3138 | static void fx_or_r13 (void) |
3139 | { |
3140 | FX_OR(13); |
3141 | } |
3142 | |
3143 | static void fx_or_r14 (void) |
3144 | { |
3145 | FX_OR(14); |
3146 | } |
3147 | |
3148 | static void fx_or_r15 (void) |
3149 | { |
3150 | FX_OR(15); |
3151 | } |
3152 | |
3153 | // c1-cf (ALT1) - xor rn |
3154 | #define FX_XOR(reg) \ |
3155 | uint32 v = SREG ^ GSU.avReg[reg]; \ |
3156 | R15++; \ |
3157 | DREG = v; \ |
3158 | GSU.vSign = v; \ |
3159 | GSU.vZero = v; \ |
3160 | TESTR14; \ |
3161 | CLRFLAGS |
3162 | |
3163 | static void fx_xor_r1 (void) |
3164 | { |
3165 | FX_XOR(1); |
3166 | } |
3167 | |
3168 | static void fx_xor_r2 (void) |
3169 | { |
3170 | FX_XOR(2); |
3171 | } |
3172 | |
3173 | static void fx_xor_r3 (void) |
3174 | { |
3175 | FX_XOR(3); |
3176 | } |
3177 | |
3178 | static void fx_xor_r4 (void) |
3179 | { |
3180 | FX_XOR(4); |
3181 | } |
3182 | |
3183 | static void fx_xor_r5 (void) |
3184 | { |
3185 | FX_XOR(5); |
3186 | } |
3187 | |
3188 | static void fx_xor_r6 (void) |
3189 | { |
3190 | FX_XOR(6); |
3191 | } |
3192 | |
3193 | static void fx_xor_r7 (void) |
3194 | { |
3195 | FX_XOR(7); |
3196 | } |
3197 | |
3198 | static void fx_xor_r8 (void) |
3199 | { |
3200 | FX_XOR(8); |
3201 | } |
3202 | |
3203 | static void fx_xor_r9 (void) |
3204 | { |
3205 | FX_XOR(9); |
3206 | } |
3207 | |
3208 | static void fx_xor_r10 (void) |
3209 | { |
3210 | FX_XOR(10); |
3211 | } |
3212 | |
3213 | static void fx_xor_r11 (void) |
3214 | { |
3215 | FX_XOR(11); |
3216 | } |
3217 | |
3218 | static void fx_xor_r12 (void) |
3219 | { |
3220 | FX_XOR(12); |
3221 | } |
3222 | |
3223 | static void fx_xor_r13 (void) |
3224 | { |
3225 | FX_XOR(13); |
3226 | } |
3227 | |
3228 | static void fx_xor_r14 (void) |
3229 | { |
3230 | FX_XOR(14); |
3231 | } |
3232 | |
3233 | static void fx_xor_r15 (void) |
3234 | { |
3235 | FX_XOR(15); |
3236 | } |
3237 | |
3238 | // c1-cf (ALT2) - or #n |
3239 | #define FX_OR_I(imm) \ |
3240 | uint32 v = SREG | imm; \ |
3241 | R15++; \ |
3242 | DREG = v; \ |
3243 | GSU.vSign = v; \ |
3244 | GSU.vZero = v; \ |
3245 | TESTR14; \ |
3246 | CLRFLAGS |
3247 | |
3248 | static void fx_or_i1 (void) |
3249 | { |
3250 | FX_OR_I(1); |
3251 | } |
3252 | |
3253 | static void fx_or_i2 (void) |
3254 | { |
3255 | FX_OR_I(2); |
3256 | } |
3257 | |
3258 | static void fx_or_i3 (void) |
3259 | { |
3260 | FX_OR_I(3); |
3261 | } |
3262 | |
3263 | static void fx_or_i4 (void) |
3264 | { |
3265 | FX_OR_I(4); |
3266 | } |
3267 | |
3268 | static void fx_or_i5 (void) |
3269 | { |
3270 | FX_OR_I(5); |
3271 | } |
3272 | |
3273 | static void fx_or_i6 (void) |
3274 | { |
3275 | FX_OR_I(6); |
3276 | } |
3277 | |
3278 | static void fx_or_i7 (void) |
3279 | { |
3280 | FX_OR_I(7); |
3281 | } |
3282 | |
3283 | static void fx_or_i8 (void) |
3284 | { |
3285 | FX_OR_I(8); |
3286 | } |
3287 | |
3288 | static void fx_or_i9 (void) |
3289 | { |
3290 | FX_OR_I(9); |
3291 | } |
3292 | |
3293 | static void fx_or_i10 (void) |
3294 | { |
3295 | FX_OR_I(10); |
3296 | } |
3297 | |
3298 | static void fx_or_i11 (void) |
3299 | { |
3300 | FX_OR_I(11); |
3301 | } |
3302 | |
3303 | static void fx_or_i12 (void) |
3304 | { |
3305 | FX_OR_I(12); |
3306 | } |
3307 | |
3308 | static void fx_or_i13 (void) |
3309 | { |
3310 | FX_OR_I(13); |
3311 | } |
3312 | |
3313 | static void fx_or_i14 (void) |
3314 | { |
3315 | FX_OR_I(14); |
3316 | } |
3317 | |
3318 | static void fx_or_i15 (void) |
3319 | { |
3320 | FX_OR_I(15); |
3321 | } |
3322 | |
3323 | // c1-cf (ALT3) - xor #n |
3324 | #define FX_XOR_I(imm) \ |
3325 | uint32 v = SREG ^ imm; \ |
3326 | R15++; \ |
3327 | DREG = v; \ |
3328 | GSU.vSign = v; \ |
3329 | GSU.vZero = v; \ |
3330 | TESTR14; \ |
3331 | CLRFLAGS |
3332 | |
3333 | static void fx_xor_i1 (void) |
3334 | { |
3335 | FX_XOR_I(1); |
3336 | } |
3337 | |
3338 | static void fx_xor_i2 (void) |
3339 | { |
3340 | FX_XOR_I(2); |
3341 | } |
3342 | |
3343 | static void fx_xor_i3 (void) |
3344 | { |
3345 | FX_XOR_I(3); |
3346 | } |
3347 | |
3348 | static void fx_xor_i4 (void) |
3349 | { |
3350 | FX_XOR_I(4); |
3351 | } |
3352 | |
3353 | static void fx_xor_i5 (void) |
3354 | { |
3355 | FX_XOR_I(5); |
3356 | } |
3357 | |
3358 | static void fx_xor_i6 (void) |
3359 | { |
3360 | FX_XOR_I(6); |
3361 | } |
3362 | |
3363 | static void fx_xor_i7 (void) |
3364 | { |
3365 | FX_XOR_I(7); |
3366 | } |
3367 | |
3368 | static void fx_xor_i8 (void) |
3369 | { |
3370 | FX_XOR_I(8); |
3371 | } |
3372 | |
3373 | static void fx_xor_i9 (void) |
3374 | { |
3375 | FX_XOR_I(9); |
3376 | } |
3377 | |
3378 | static void fx_xor_i10 (void) |
3379 | { |
3380 | FX_XOR_I(10); |
3381 | } |
3382 | |
3383 | static void fx_xor_i11 (void) |
3384 | { |
3385 | FX_XOR_I(11); |
3386 | } |
3387 | |
3388 | static void fx_xor_i12 (void) |
3389 | { |
3390 | FX_XOR_I(12); |
3391 | } |
3392 | |
3393 | static void fx_xor_i13 (void) |
3394 | { |
3395 | FX_XOR_I(13); |
3396 | } |
3397 | |
3398 | static void fx_xor_i14 (void) |
3399 | { |
3400 | FX_XOR_I(14); |
3401 | } |
3402 | |
3403 | static void fx_xor_i15 (void) |
3404 | { |
3405 | FX_XOR_I(15); |
3406 | } |
3407 | |
3408 | // d0-de - inc rn - increase by one |
3409 | #define FX_INC(reg) \ |
3410 | GSU.avReg[reg] += 1; \ |
3411 | GSU.vSign = GSU.avReg[reg]; \ |
3412 | GSU.vZero = GSU.avReg[reg]; \ |
3413 | CLRFLAGS; \ |
3414 | R15++ |
3415 | |
3416 | static void fx_inc_r0 (void) |
3417 | { |
3418 | FX_INC(0); |
3419 | } |
3420 | |
3421 | static void fx_inc_r1 (void) |
3422 | { |
3423 | FX_INC(1); |
3424 | } |
3425 | |
3426 | static void fx_inc_r2 (void) |
3427 | { |
3428 | FX_INC(2); |
3429 | } |
3430 | |
3431 | static void fx_inc_r3 (void) |
3432 | { |
3433 | FX_INC(3); |
3434 | } |
3435 | |
3436 | static void fx_inc_r4 (void) |
3437 | { |
3438 | FX_INC(4); |
3439 | } |
3440 | |
3441 | static void fx_inc_r5 (void) |
3442 | { |
3443 | FX_INC(5); |
3444 | } |
3445 | |
3446 | static void fx_inc_r6 (void) |
3447 | { |
3448 | FX_INC(6); |
3449 | } |
3450 | |
3451 | static void fx_inc_r7 (void) |
3452 | { |
3453 | FX_INC(7); |
3454 | } |
3455 | |
3456 | static void fx_inc_r8 (void) |
3457 | { |
3458 | FX_INC(8); |
3459 | } |
3460 | |
3461 | static void fx_inc_r9 (void) |
3462 | { |
3463 | FX_INC(9); |
3464 | } |
3465 | |
3466 | static void fx_inc_r10 (void) |
3467 | { |
3468 | FX_INC(10); |
3469 | } |
3470 | |
3471 | static void fx_inc_r11 (void) |
3472 | { |
3473 | FX_INC(11); |
3474 | } |
3475 | |
3476 | static void fx_inc_r12 (void) |
3477 | { |
3478 | FX_INC(12); |
3479 | } |
3480 | |
3481 | static void fx_inc_r13 (void) |
3482 | { |
3483 | FX_INC(13); |
3484 | } |
3485 | |
3486 | static void fx_inc_r14 (void) |
3487 | { |
3488 | FX_INC(14); |
3489 | READR14; |
3490 | } |
3491 | |
3492 | // df - getc - transfer ROM buffer to color register |
3493 | static void fx_getc (void) |
3494 | { |
3495 | #ifndef FX_DO_ROMBUFFER |
3496 | uint8 c = ROM(R14); |
3497 | #else |
3498 | uint8 c = GSU.vRomBuffer; |
3499 | #endif |
3500 | |
3501 | if (GSU.vPlotOptionReg & 0x04) |
3502 | c = (c & 0xf0) | (c >> 4); |
3503 | |
3504 | if (GSU.vPlotOptionReg & 0x08) |
3505 | { |
3506 | GSU.vColorReg &= 0xf0; |
3507 | GSU.vColorReg |= c & 0x0f; |
3508 | } |
3509 | else |
3510 | GSU.vColorReg = USEX8(c); |
3511 | |
3512 | CLRFLAGS; |
3513 | R15++; |
3514 | } |
3515 | |
3516 | // df (ALT2) - ramb - set current RAM bank |
3517 | static void fx_ramb (void) |
3518 | { |
3519 | GSU.vRamBankReg = SREG & (FX_RAM_BANKS - 1); |
3520 | GSU.pvRamBank = GSU.apvRamBank[GSU.vRamBankReg & 0x3]; |
3521 | CLRFLAGS; |
3522 | R15++; |
3523 | } |
3524 | |
3525 | // df (ALT3) - romb - set current ROM bank |
3526 | static void fx_romb (void) |
3527 | { |
3528 | GSU.vRomBankReg = USEX8(SREG) & 0x7f; |
3529 | GSU.pvRomBank = GSU.apvRomBank[GSU.vRomBankReg]; |
3530 | CLRFLAGS; |
3531 | R15++; |
3532 | } |
3533 | |
3534 | // e0-ee - dec rn - decrement by one |
3535 | #define FX_DEC(reg) \ |
3536 | GSU.avReg[reg] -= 1; \ |
3537 | GSU.vSign = GSU.avReg[reg]; \ |
3538 | GSU.vZero = GSU.avReg[reg]; \ |
3539 | CLRFLAGS; \ |
3540 | R15++ |
3541 | |
3542 | static void fx_dec_r0 (void) |
3543 | { |
3544 | FX_DEC(0); |
3545 | } |
3546 | |
3547 | static void fx_dec_r1 (void) |
3548 | { |
3549 | FX_DEC(1); |
3550 | } |
3551 | |
3552 | static void fx_dec_r2 (void) |
3553 | { |
3554 | FX_DEC(2); |
3555 | } |
3556 | |
3557 | static void fx_dec_r3 (void) |
3558 | { |
3559 | FX_DEC(3); |
3560 | } |
3561 | |
3562 | static void fx_dec_r4 (void) |
3563 | { |
3564 | FX_DEC(4); |
3565 | } |
3566 | |
3567 | static void fx_dec_r5 (void) |
3568 | { |
3569 | FX_DEC(5); |
3570 | } |
3571 | |
3572 | static void fx_dec_r6 (void) |
3573 | { |
3574 | FX_DEC(6); |
3575 | } |
3576 | |
3577 | static void fx_dec_r7 (void) |
3578 | { |
3579 | FX_DEC(7); |
3580 | } |
3581 | |
3582 | static void fx_dec_r8 (void) |
3583 | { |
3584 | FX_DEC(8); |
3585 | } |
3586 | |
3587 | static void fx_dec_r9 (void) |
3588 | { |
3589 | FX_DEC(9); |
3590 | } |
3591 | |
3592 | static void fx_dec_r10 (void) |
3593 | { |
3594 | FX_DEC(10); |
3595 | } |
3596 | |
3597 | static void fx_dec_r11 (void) |
3598 | { |
3599 | FX_DEC(11); |
3600 | } |
3601 | |
3602 | static void fx_dec_r12 (void) |
3603 | { |
3604 | FX_DEC(12); |
3605 | } |
3606 | |
3607 | static void fx_dec_r13 (void) |
3608 | { |
3609 | FX_DEC(13); |
3610 | } |
3611 | |
3612 | static void fx_dec_r14 (void) |
3613 | { |
3614 | FX_DEC(14); |
3615 | READR14; |
3616 | } |
3617 | |
3618 | // ef - getb - get byte from ROM at address R14 |
3619 | static void fx_getb (void) |
3620 | { |
3621 | uint32 v; |
3622 | #ifndef FX_DO_ROMBUFFER |
3623 | v = (uint32) ROM(R14); |
3624 | #else |
3625 | v = (uint32) GSU.vRomBuffer; |
3626 | #endif |
3627 | R15++; |
3628 | DREG = v; |
3629 | TESTR14; |
3630 | CLRFLAGS; |
3631 | } |
3632 | |
3633 | // ef (ALT1) - getbh - get high-byte from ROM at address R14 |
3634 | static void fx_getbh (void) |
3635 | { |
3636 | uint32 v; |
3637 | #ifndef FX_DO_ROMBUFFER |
3638 | uint32 c = (uint32) ROM(R14); |
3639 | #else |
3640 | uint32 c = USEX8(GSU.vRomBuffer); |
3641 | #endif |
3642 | v = USEX8(SREG) | (c << 8); |
3643 | R15++; |
3644 | DREG = v; |
3645 | TESTR14; |
3646 | CLRFLAGS; |
3647 | } |
3648 | |
3649 | // ef (ALT2) - getbl - get low-byte from ROM at address R14 |
3650 | static void fx_getbl (void) |
3651 | { |
3652 | uint32 v; |
3653 | #ifndef FX_DO_ROMBUFFER |
3654 | uint32 c = (uint32) ROM(R14); |
3655 | #else |
3656 | uint32 c = USEX8(GSU.vRomBuffer); |
3657 | #endif |
3658 | v = (SREG & 0xff00) | c; |
3659 | R15++; |
3660 | DREG = v; |
3661 | TESTR14; |
3662 | CLRFLAGS; |
3663 | } |
3664 | |
3665 | // ef (ALT3) - getbs - get sign extended byte from ROM at address R14 |
3666 | static void fx_getbs (void) |
3667 | { |
3668 | uint32 v; |
3669 | #ifndef FX_DO_ROMBUFFER |
3670 | int8 c; |
3671 | c = ROM(R14); |
3672 | v = SEX8(c); |
3673 | #else |
3674 | v = SEX8(GSU.vRomBuffer); |
3675 | #endif |
3676 | R15++; |
3677 | DREG = v; |
3678 | TESTR14; |
3679 | CLRFLAGS; |
3680 | } |
3681 | |
3682 | // f0-ff - iwt rn, #xx - immediate word transfer to register |
3683 | #define FX_IWT(reg) \ |
3684 | uint32 v = PIPE; \ |
3685 | R15++; \ |
3686 | FETCHPIPE; \ |
3687 | R15++; \ |
3688 | v |= USEX8(PIPE) << 8; \ |
3689 | FETCHPIPE; \ |
3690 | R15++; \ |
3691 | GSU.avReg[reg] = v; \ |
3692 | CLRFLAGS |
3693 | |
3694 | static void fx_iwt_r0 (void) |
3695 | { |
3696 | FX_IWT(0); |
3697 | } |
3698 | |
3699 | static void fx_iwt_r1 (void) |
3700 | { |
3701 | FX_IWT(1); |
3702 | } |
3703 | |
3704 | static void fx_iwt_r2 (void) |
3705 | { |
3706 | FX_IWT(2); |
3707 | } |
3708 | |
3709 | static void fx_iwt_r3 (void) |
3710 | { |
3711 | FX_IWT(3); |
3712 | } |
3713 | |
3714 | static void fx_iwt_r4 (void) |
3715 | { |
3716 | FX_IWT(4); |
3717 | } |
3718 | |
3719 | static void fx_iwt_r5 (void) |
3720 | { |
3721 | FX_IWT(5); |
3722 | } |
3723 | |
3724 | static void fx_iwt_r6 (void) |
3725 | { |
3726 | FX_IWT(6); |
3727 | } |
3728 | |
3729 | static void fx_iwt_r7 (void) |
3730 | { |
3731 | FX_IWT(7); |
3732 | } |
3733 | |
3734 | static void fx_iwt_r8 (void) |
3735 | { |
3736 | FX_IWT(8); |
3737 | } |
3738 | |
3739 | static void fx_iwt_r9 (void) |
3740 | { |
3741 | FX_IWT(9); |
3742 | } |
3743 | |
3744 | static void fx_iwt_r10 (void) |
3745 | { |
3746 | FX_IWT(10); |
3747 | } |
3748 | |
3749 | static void fx_iwt_r11 (void) |
3750 | { |
3751 | FX_IWT(11); |
3752 | } |
3753 | |
3754 | static void fx_iwt_r12 (void) |
3755 | { |
3756 | FX_IWT(12); |
3757 | } |
3758 | |
3759 | static void fx_iwt_r13 (void) |
3760 | { |
3761 | FX_IWT(13); |
3762 | } |
3763 | |
3764 | static void fx_iwt_r14 (void) |
3765 | { |
3766 | FX_IWT(14); |
3767 | READR14; |
3768 | } |
3769 | |
3770 | static void fx_iwt_r15 (void) |
3771 | { |
3772 | FX_IWT(15); |
3773 | } |
3774 | |
3775 | // f0-ff (ALT1) - lm rn, (xx) - load word from RAM |
3776 | #define FX_LM(reg) \ |
3777 | GSU.vLastRamAdr = PIPE; \ |
3778 | R15++; \ |
3779 | FETCHPIPE; \ |
3780 | R15++; \ |
3781 | GSU.vLastRamAdr |= USEX8(PIPE) << 8; \ |
3782 | FETCHPIPE; \ |
3783 | R15++; \ |
3784 | GSU.avReg[reg] = RAM(GSU.vLastRamAdr); \ |
3785 | GSU.avReg[reg] |= USEX8(RAM(GSU.vLastRamAdr ^ 1)) << 8; \ |
3786 | CLRFLAGS |
3787 | |
3788 | static void fx_lm_r0 (void) |
3789 | { |
3790 | FX_LM(0); |
3791 | } |
3792 | |
3793 | static void fx_lm_r1 (void) |
3794 | { |
3795 | FX_LM(1); |
3796 | } |
3797 | |
3798 | static void fx_lm_r2 (void) |
3799 | { |
3800 | FX_LM(2); |
3801 | } |
3802 | |
3803 | static void fx_lm_r3 (void) |
3804 | { |
3805 | FX_LM(3); |
3806 | } |
3807 | |
3808 | static void fx_lm_r4 (void) |
3809 | { |
3810 | FX_LM(4); |
3811 | } |
3812 | |
3813 | static void fx_lm_r5 (void) |
3814 | { |
3815 | FX_LM(5); |
3816 | } |
3817 | |
3818 | static void fx_lm_r6 (void) |
3819 | { |
3820 | FX_LM(6); |
3821 | } |
3822 | |
3823 | static void fx_lm_r7 (void) |
3824 | { |
3825 | FX_LM(7); |
3826 | } |
3827 | |
3828 | static void fx_lm_r8 (void) |
3829 | { |
3830 | FX_LM(8); |
3831 | } |
3832 | |
3833 | static void fx_lm_r9 (void) |
3834 | { |
3835 | FX_LM(9); |
3836 | } |
3837 | |
3838 | static void fx_lm_r10 (void) |
3839 | { |
3840 | FX_LM(10); |
3841 | } |
3842 | |
3843 | static void fx_lm_r11 (void) |
3844 | { |
3845 | FX_LM(11); |
3846 | } |
3847 | |
3848 | static void fx_lm_r12 (void) |
3849 | { |
3850 | FX_LM(12); |
3851 | } |
3852 | |
3853 | static void fx_lm_r13 (void) |
3854 | { |
3855 | FX_LM(13); |
3856 | } |
3857 | |
3858 | static void fx_lm_r14 (void) |
3859 | { |
3860 | FX_LM(14); |
3861 | READR14; |
3862 | } |
3863 | |
3864 | static void fx_lm_r15 (void) |
3865 | { |
3866 | FX_LM(15); |
3867 | } |
3868 | |
3869 | // f0-ff (ALT2) - sm (xx), rn - store word in RAM |
3870 | // XXX: If rn == r15, is the value of r15 before or after the extra bytes are read ? |
3871 | #define FX_SM(reg) \ |
3872 | uint32 v = GSU.avReg[reg]; \ |
3873 | GSU.vLastRamAdr = PIPE; \ |
3874 | R15++; \ |
3875 | FETCHPIPE; \ |
3876 | R15++; \ |
3877 | GSU.vLastRamAdr |= USEX8(PIPE) << 8; \ |
3878 | FETCHPIPE; \ |
3879 | RAM(GSU.vLastRamAdr) = (uint8) v; \ |
3880 | RAM(GSU.vLastRamAdr ^ 1) = (uint8) (v >> 8); \ |
3881 | CLRFLAGS; \ |
3882 | R15++ |
3883 | |
3884 | static void fx_sm_r0 (void) |
3885 | { |
3886 | FX_SM(0); |
3887 | } |
3888 | |
3889 | static void fx_sm_r1 (void) |
3890 | { |
3891 | FX_SM(1); |
3892 | } |
3893 | |
3894 | static void fx_sm_r2 (void) |
3895 | { |
3896 | FX_SM(2); |
3897 | } |
3898 | |
3899 | static void fx_sm_r3 (void) |
3900 | { |
3901 | FX_SM(3); |
3902 | } |
3903 | |
3904 | static void fx_sm_r4 (void) |
3905 | { |
3906 | FX_SM(4); |
3907 | } |
3908 | |
3909 | static void fx_sm_r5 (void) |
3910 | { |
3911 | FX_SM(5); |
3912 | } |
3913 | |
3914 | static void fx_sm_r6 (void) |
3915 | { |
3916 | FX_SM(6); |
3917 | } |
3918 | |
3919 | static void fx_sm_r7 (void) |
3920 | { |
3921 | FX_SM(7); |
3922 | } |
3923 | |
3924 | static void fx_sm_r8 (void) |
3925 | { |
3926 | FX_SM(8); |
3927 | } |
3928 | |
3929 | static void fx_sm_r9 (void) |
3930 | { |
3931 | FX_SM(9); |
3932 | } |
3933 | |
3934 | static void fx_sm_r10 (void) |
3935 | { |
3936 | FX_SM(10); |
3937 | } |
3938 | |
3939 | static void fx_sm_r11 (void) |
3940 | { |
3941 | FX_SM(11); |
3942 | } |
3943 | |
3944 | static void fx_sm_r12 (void) |
3945 | { |
3946 | FX_SM(12); |
3947 | } |
3948 | |
3949 | static void fx_sm_r13 (void) |
3950 | { |
3951 | FX_SM(13); |
3952 | } |
3953 | |
3954 | static void fx_sm_r14 (void) |
3955 | { |
3956 | FX_SM(14); |
3957 | } |
3958 | |
3959 | static void fx_sm_r15 (void) |
3960 | { |
3961 | FX_SM(15); |
3962 | } |
3963 | |
3964 | // GSU executions functions |
3965 | |
3966 | uint32 fx_run (uint32 nInstructions) |
3967 | { |
3968 | GSU.vCounter = nInstructions; |
3969 | while (TF(G) && (GSU.vCounter-- > 0)) |
3970 | FX_STEP; |
3971 | #if 0 |
3972 | #ifndef FX_ADDRESS_CHECK |
3973 | GSU.vPipeAdr = USEX16(R15 - 1) | (USEX8(GSU.vPrgBankReg) << 16); |
3974 | #endif |
3975 | #endif |
3976 | |
3977 | return (nInstructions - GSU.vInstCount); |
3978 | } |
3979 | |
3980 | /* |
3981 | uint32 fx_run_to_breakpoint (uint32 nInstructions) |
3982 | { |
3983 | uint32 vCounter = 0; |
3984 | |
3985 | while (TF(G) && vCounter < nInstructions) |
3986 | { |
3987 | vCounter++; |
3988 | FX_STEP; |
3989 | |
3990 | if (USEX16(R15) == GSU.vBreakPoint) |
3991 | { |
3992 | GSU.vErrorCode = FX_BREAKPOINT; |
3993 | break; |
3994 | } |
3995 | } |
3996 | |
3997 | #if 0 |
3998 | #ifndef FX_ADDRESS_CHECK |
3999 | GSU.vPipeAdr = USEX16(R15 - 1) | (USEX8(GSU.vPrgBankReg) << 16); |
4000 | #endif |
4001 | #endif |
4002 | |
4003 | return (vCounter); |
4004 | } |
4005 | */ |
4006 | |
4007 | /* |
4008 | uint32 fx_step_over (uint32 nInstructions) |
4009 | { |
4010 | uint32 vCounter = 0; |
4011 | |
4012 | while (TF(G) && vCounter < nInstructions) |
4013 | { |
4014 | vCounter++; |
4015 | FX_STEP; |
4016 | |
4017 | if (USEX16(R15) == GSU.vBreakPoint) |
4018 | { |
4019 | GSU.vErrorCode = FX_BREAKPOINT; |
4020 | break; |
4021 | } |
4022 | |
4023 | if (USEX16(R15) == GSU.vStepPoint) |
4024 | break; |
4025 | } |
4026 | |
4027 | #if 0 |
4028 | #ifndef FX_ADDRESS_CHECK |
4029 | GSU.vPipeAdr = USEX16(R15 - 1) | (USEX8(GSU.vPrgBankReg) << 16); |
4030 | #endif |
4031 | #endif |
4032 | |
4033 | return (vCounter); |
4034 | } |
4035 | */ |
4036 | |
4037 | // Special table for the different plot configurations |
4038 | |
4039 | void (*fx_PlotTable[]) (void) = |
4040 | { |
4041 | &fx_plot_2bit, &fx_plot_4bit, &fx_plot_4bit, &fx_plot_8bit, &fx_plot_obj, |
4042 | &fx_rpix_2bit, &fx_rpix_4bit, &fx_rpix_4bit, &fx_rpix_8bit, &fx_rpix_obj |
4043 | }; |
4044 | |
4045 | // Opcode table |
4046 | |
4047 | void (*fx_OpcodeTable[]) (void) = |
4048 | { |
4049 | // ALT0 Table |
4050 | |
4051 | // 00 - 0f |
4052 | &fx_stop, &fx_nop, &fx_cache, &fx_lsr, &fx_rol, &fx_bra, &fx_bge, &fx_blt, |
4053 | &fx_bne, &fx_beq, &fx_bpl, &fx_bmi, &fx_bcc, &fx_bcs, &fx_bvc, &fx_bvs, |
4054 | // 10 - 1f |
4055 | &fx_to_r0, &fx_to_r1, &fx_to_r2, &fx_to_r3, &fx_to_r4, &fx_to_r5, &fx_to_r6, &fx_to_r7, |
4056 | &fx_to_r8, &fx_to_r9, &fx_to_r10, &fx_to_r11, &fx_to_r12, &fx_to_r13, &fx_to_r14, &fx_to_r15, |
4057 | // 20 - 2f |
4058 | &fx_with_r0, &fx_with_r1, &fx_with_r2, &fx_with_r3, &fx_with_r4, &fx_with_r5, &fx_with_r6, &fx_with_r7, |
4059 | &fx_with_r8, &fx_with_r9, &fx_with_r10, &fx_with_r11, &fx_with_r12, &fx_with_r13, &fx_with_r14, &fx_with_r15, |
4060 | // 30 - 3f |
4061 | &fx_stw_r0, &fx_stw_r1, &fx_stw_r2, &fx_stw_r3, &fx_stw_r4, &fx_stw_r5, &fx_stw_r6, &fx_stw_r7, |
4062 | &fx_stw_r8, &fx_stw_r9, &fx_stw_r10, &fx_stw_r11, &fx_loop, &fx_alt1, &fx_alt2, &fx_alt3, |
4063 | // 40 - 4f |
4064 | &fx_ldw_r0, &fx_ldw_r1, &fx_ldw_r2, &fx_ldw_r3, &fx_ldw_r4, &fx_ldw_r5, &fx_ldw_r6, &fx_ldw_r7, |
4065 | &fx_ldw_r8, &fx_ldw_r9, &fx_ldw_r10, &fx_ldw_r11, &fx_plot_2bit, &fx_swap, &fx_color, &fx_not, |
4066 | // 50 - 5f |
4067 | &fx_add_r0, &fx_add_r1, &fx_add_r2, &fx_add_r3, &fx_add_r4, &fx_add_r5, &fx_add_r6, &fx_add_r7, |
4068 | &fx_add_r8, &fx_add_r9, &fx_add_r10, &fx_add_r11, &fx_add_r12, &fx_add_r13, &fx_add_r14, &fx_add_r15, |
4069 | // 60 - 6f |
4070 | &fx_sub_r0, &fx_sub_r1, &fx_sub_r2, &fx_sub_r3, &fx_sub_r4, &fx_sub_r5, &fx_sub_r6, &fx_sub_r7, |
4071 | &fx_sub_r8, &fx_sub_r9, &fx_sub_r10, &fx_sub_r11, &fx_sub_r12, &fx_sub_r13, &fx_sub_r14, &fx_sub_r15, |
4072 | // 70 - 7f |
4073 | &fx_merge, &fx_and_r1, &fx_and_r2, &fx_and_r3, &fx_and_r4, &fx_and_r5, &fx_and_r6, &fx_and_r7, |
4074 | &fx_and_r8, &fx_and_r9, &fx_and_r10, &fx_and_r11, &fx_and_r12, &fx_and_r13, &fx_and_r14, &fx_and_r15, |
4075 | // 80 - 8f |
4076 | &fx_mult_r0, &fx_mult_r1, &fx_mult_r2, &fx_mult_r3, &fx_mult_r4, &fx_mult_r5, &fx_mult_r6, &fx_mult_r7, |
4077 | &fx_mult_r8, &fx_mult_r9, &fx_mult_r10, &fx_mult_r11, &fx_mult_r12, &fx_mult_r13, &fx_mult_r14, &fx_mult_r15, |
4078 | // 90 - 9f |
4079 | &fx_sbk, &fx_link_i1, &fx_link_i2, &fx_link_i3, &fx_link_i4, &fx_sex, &fx_asr, &fx_ror, |
4080 | &fx_jmp_r8, &fx_jmp_r9, &fx_jmp_r10, &fx_jmp_r11, &fx_jmp_r12, &fx_jmp_r13, &fx_lob, &fx_fmult, |
4081 | // a0 - af |
4082 | &fx_ibt_r0, &fx_ibt_r1, &fx_ibt_r2, &fx_ibt_r3, &fx_ibt_r4, &fx_ibt_r5, &fx_ibt_r6, &fx_ibt_r7, |
4083 | &fx_ibt_r8, &fx_ibt_r9, &fx_ibt_r10, &fx_ibt_r11, &fx_ibt_r12, &fx_ibt_r13, &fx_ibt_r14, &fx_ibt_r15, |
4084 | // b0 - bf |
4085 | &fx_from_r0, &fx_from_r1, &fx_from_r2, &fx_from_r3, &fx_from_r4, &fx_from_r5, &fx_from_r6, &fx_from_r7, |
4086 | &fx_from_r8, &fx_from_r9, &fx_from_r10, &fx_from_r11, &fx_from_r12, &fx_from_r13, &fx_from_r14, &fx_from_r15, |
4087 | // c0 - cf |
4088 | &fx_hib, &fx_or_r1, &fx_or_r2, &fx_or_r3, &fx_or_r4, &fx_or_r5, &fx_or_r6, &fx_or_r7, |
4089 | &fx_or_r8, &fx_or_r9, &fx_or_r10, &fx_or_r11, &fx_or_r12, &fx_or_r13, &fx_or_r14, &fx_or_r15, |
4090 | // d0 - df |
4091 | &fx_inc_r0, &fx_inc_r1, &fx_inc_r2, &fx_inc_r3, &fx_inc_r4, &fx_inc_r5, &fx_inc_r6, &fx_inc_r7, |
4092 | &fx_inc_r8, &fx_inc_r9, &fx_inc_r10, &fx_inc_r11, &fx_inc_r12, &fx_inc_r13, &fx_inc_r14, &fx_getc, |
4093 | // e0 - ef |
4094 | &fx_dec_r0, &fx_dec_r1, &fx_dec_r2, &fx_dec_r3, &fx_dec_r4, &fx_dec_r5, &fx_dec_r6, &fx_dec_r7, |
4095 | &fx_dec_r8, &fx_dec_r9, &fx_dec_r10, &fx_dec_r11, &fx_dec_r12, &fx_dec_r13, &fx_dec_r14, &fx_getb, |
4096 | // f0 - ff |
4097 | &fx_iwt_r0, &fx_iwt_r1, &fx_iwt_r2, &fx_iwt_r3, &fx_iwt_r4, &fx_iwt_r5, &fx_iwt_r6, &fx_iwt_r7, |
4098 | &fx_iwt_r8, &fx_iwt_r9, &fx_iwt_r10, &fx_iwt_r11, &fx_iwt_r12, &fx_iwt_r13, &fx_iwt_r14, &fx_iwt_r15, |
4099 | |
4100 | // ALT1 Table |
4101 | |
4102 | // 00 - 0f |
4103 | &fx_stop, &fx_nop, &fx_cache, &fx_lsr, &fx_rol, &fx_bra, &fx_bge, &fx_blt, |
4104 | &fx_bne, &fx_beq, &fx_bpl, &fx_bmi, &fx_bcc, &fx_bcs, &fx_bvc, &fx_bvs, |
4105 | // 10 - 1f |
4106 | &fx_to_r0, &fx_to_r1, &fx_to_r2, &fx_to_r3, &fx_to_r4, &fx_to_r5, &fx_to_r6, &fx_to_r7, |
4107 | &fx_to_r8, &fx_to_r9, &fx_to_r10, &fx_to_r11, &fx_to_r12, &fx_to_r13, &fx_to_r14, &fx_to_r15, |
4108 | // 20 - 2f |
4109 | &fx_with_r0, &fx_with_r1, &fx_with_r2, &fx_with_r3, &fx_with_r4, &fx_with_r5, &fx_with_r6, &fx_with_r7, |
4110 | &fx_with_r8, &fx_with_r9, &fx_with_r10, &fx_with_r11, &fx_with_r12, &fx_with_r13, &fx_with_r14, &fx_with_r15, |
4111 | // 30 - 3f |
4112 | &fx_stb_r0, &fx_stb_r1, &fx_stb_r2, &fx_stb_r3, &fx_stb_r4, &fx_stb_r5, &fx_stb_r6, &fx_stb_r7, |
4113 | &fx_stb_r8, &fx_stb_r9, &fx_stb_r10, &fx_stb_r11, &fx_loop, &fx_alt1, &fx_alt2, &fx_alt3, |
4114 | // 40 - 4f |
4115 | &fx_ldb_r0, &fx_ldb_r1, &fx_ldb_r2, &fx_ldb_r3, &fx_ldb_r4, &fx_ldb_r5, &fx_ldb_r6, &fx_ldb_r7, |
4116 | &fx_ldb_r8, &fx_ldb_r9, &fx_ldb_r10, &fx_ldb_r11, &fx_rpix_2bit, &fx_swap, &fx_cmode, &fx_not, |
4117 | // 50 - 5f |
4118 | &fx_adc_r0, &fx_adc_r1, &fx_adc_r2, &fx_adc_r3, &fx_adc_r4, &fx_adc_r5, &fx_adc_r6, &fx_adc_r7, |
4119 | &fx_adc_r8, &fx_adc_r9, &fx_adc_r10, &fx_adc_r11, &fx_adc_r12, &fx_adc_r13, &fx_adc_r14, &fx_adc_r15, |
4120 | // 60 - 6f |
4121 | &fx_sbc_r0, &fx_sbc_r1, &fx_sbc_r2, &fx_sbc_r3, &fx_sbc_r4, &fx_sbc_r5, &fx_sbc_r6, &fx_sbc_r7, |
4122 | &fx_sbc_r8, &fx_sbc_r9, &fx_sbc_r10, &fx_sbc_r11, &fx_sbc_r12, &fx_sbc_r13, &fx_sbc_r14, &fx_sbc_r15, |
4123 | // 70 - 7f |
4124 | &fx_merge, &fx_bic_r1, &fx_bic_r2, &fx_bic_r3, &fx_bic_r4, &fx_bic_r5, &fx_bic_r6, &fx_bic_r7, |
4125 | &fx_bic_r8, &fx_bic_r9, &fx_bic_r10, &fx_bic_r11, &fx_bic_r12, &fx_bic_r13, &fx_bic_r14, &fx_bic_r15, |
4126 | // 80 - 8f |
4127 | &fx_umult_r0, &fx_umult_r1, &fx_umult_r2, &fx_umult_r3, &fx_umult_r4, &fx_umult_r5, &fx_umult_r6, &fx_umult_r7, |
4128 | &fx_umult_r8, &fx_umult_r9, &fx_umult_r10, &fx_umult_r11, &fx_umult_r12, &fx_umult_r13, &fx_umult_r14, &fx_umult_r15, |
4129 | // 90 - 9f |
4130 | &fx_sbk, &fx_link_i1, &fx_link_i2, &fx_link_i3, &fx_link_i4, &fx_sex, &fx_div2, &fx_ror, |
4131 | &fx_ljmp_r8, &fx_ljmp_r9, &fx_ljmp_r10, &fx_ljmp_r11, &fx_ljmp_r12, &fx_ljmp_r13, &fx_lob, &fx_lmult, |
4132 | // a0 - af |
4133 | &fx_lms_r0, &fx_lms_r1, &fx_lms_r2, &fx_lms_r3, &fx_lms_r4, &fx_lms_r5, &fx_lms_r6, &fx_lms_r7, |
4134 | &fx_lms_r8, &fx_lms_r9, &fx_lms_r10, &fx_lms_r11, &fx_lms_r12, &fx_lms_r13, &fx_lms_r14, &fx_lms_r15, |
4135 | // b0 - bf |
4136 | &fx_from_r0, &fx_from_r1, &fx_from_r2, &fx_from_r3, &fx_from_r4, &fx_from_r5, &fx_from_r6, &fx_from_r7, |
4137 | &fx_from_r8, &fx_from_r9, &fx_from_r10, &fx_from_r11, &fx_from_r12, &fx_from_r13, &fx_from_r14, &fx_from_r15, |
4138 | // c0 - cf |
4139 | &fx_hib, &fx_xor_r1, &fx_xor_r2, &fx_xor_r3, &fx_xor_r4, &fx_xor_r5, &fx_xor_r6, &fx_xor_r7, |
4140 | &fx_xor_r8, &fx_xor_r9, &fx_xor_r10, &fx_xor_r11, &fx_xor_r12, &fx_xor_r13, &fx_xor_r14, &fx_xor_r15, |
4141 | // d0 - df |
4142 | &fx_inc_r0, &fx_inc_r1, &fx_inc_r2, &fx_inc_r3, &fx_inc_r4, &fx_inc_r5, &fx_inc_r6, &fx_inc_r7, |
4143 | &fx_inc_r8, &fx_inc_r9, &fx_inc_r10, &fx_inc_r11, &fx_inc_r12, &fx_inc_r13, &fx_inc_r14, &fx_getc, |
4144 | // e0 - ef |
4145 | &fx_dec_r0, &fx_dec_r1, &fx_dec_r2, &fx_dec_r3, &fx_dec_r4, &fx_dec_r5, &fx_dec_r6, &fx_dec_r7, |
4146 | &fx_dec_r8, &fx_dec_r9, &fx_dec_r10, &fx_dec_r11, &fx_dec_r12, &fx_dec_r13, &fx_dec_r14, &fx_getbh, |
4147 | // f0 - ff |
4148 | &fx_lm_r0, &fx_lm_r1, &fx_lm_r2, &fx_lm_r3, &fx_lm_r4, &fx_lm_r5, &fx_lm_r6, &fx_lm_r7, |
4149 | &fx_lm_r8, &fx_lm_r9, &fx_lm_r10, &fx_lm_r11, &fx_lm_r12, &fx_lm_r13, &fx_lm_r14, &fx_lm_r15, |
4150 | |
4151 | // ALT2 Table |
4152 | |
4153 | // 00 - 0f |
4154 | &fx_stop, &fx_nop, &fx_cache, &fx_lsr, &fx_rol, &fx_bra, &fx_bge, &fx_blt, |
4155 | &fx_bne, &fx_beq, &fx_bpl, &fx_bmi, &fx_bcc, &fx_bcs, &fx_bvc, &fx_bvs, |
4156 | // 10 - 1f |
4157 | &fx_to_r0, &fx_to_r1, &fx_to_r2, &fx_to_r3, &fx_to_r4, &fx_to_r5, &fx_to_r6, &fx_to_r7, |
4158 | &fx_to_r8, &fx_to_r9, &fx_to_r10, &fx_to_r11, &fx_to_r12, &fx_to_r13, &fx_to_r14, &fx_to_r15, |
4159 | // 20 - 2f |
4160 | &fx_with_r0, &fx_with_r1, &fx_with_r2, &fx_with_r3, &fx_with_r4, &fx_with_r5, &fx_with_r6, &fx_with_r7, |
4161 | &fx_with_r8, &fx_with_r9, &fx_with_r10, &fx_with_r11, &fx_with_r12, &fx_with_r13, &fx_with_r14, &fx_with_r15, |
4162 | // 30 - 3f |
4163 | &fx_stw_r0, &fx_stw_r1, &fx_stw_r2, &fx_stw_r3, &fx_stw_r4, &fx_stw_r5, &fx_stw_r6, &fx_stw_r7, |
4164 | &fx_stw_r8, &fx_stw_r9, &fx_stw_r10, &fx_stw_r11, &fx_loop, &fx_alt1, &fx_alt2, &fx_alt3, |
4165 | // 40 - 4f |
4166 | &fx_ldw_r0, &fx_ldw_r1, &fx_ldw_r2, &fx_ldw_r3, &fx_ldw_r4, &fx_ldw_r5, &fx_ldw_r6, &fx_ldw_r7, |
4167 | &fx_ldw_r8, &fx_ldw_r9, &fx_ldw_r10, &fx_ldw_r11, &fx_plot_2bit, &fx_swap, &fx_color, &fx_not, |
4168 | // 50 - 5f |
4169 | &fx_add_i0, &fx_add_i1, &fx_add_i2, &fx_add_i3, &fx_add_i4, &fx_add_i5, &fx_add_i6, &fx_add_i7, |
4170 | &fx_add_i8, &fx_add_i9, &fx_add_i10, &fx_add_i11, &fx_add_i12, &fx_add_i13, &fx_add_i14, &fx_add_i15, |
4171 | // 60 - 6f |
4172 | &fx_sub_i0, &fx_sub_i1, &fx_sub_i2, &fx_sub_i3, &fx_sub_i4, &fx_sub_i5, &fx_sub_i6, &fx_sub_i7, |
4173 | &fx_sub_i8, &fx_sub_i9, &fx_sub_i10, &fx_sub_i11, &fx_sub_i12, &fx_sub_i13, &fx_sub_i14, &fx_sub_i15, |
4174 | // 70 - 7f |
4175 | &fx_merge, &fx_and_i1, &fx_and_i2, &fx_and_i3, &fx_and_i4, &fx_and_i5, &fx_and_i6, &fx_and_i7, |
4176 | &fx_and_i8, &fx_and_i9, &fx_and_i10, &fx_and_i11, &fx_and_i12, &fx_and_i13, &fx_and_i14, &fx_and_i15, |
4177 | // 80 - 8f |
4178 | &fx_mult_i0, &fx_mult_i1, &fx_mult_i2, &fx_mult_i3, &fx_mult_i4, &fx_mult_i5, &fx_mult_i6, &fx_mult_i7, |
4179 | &fx_mult_i8, &fx_mult_i9, &fx_mult_i10, &fx_mult_i11, &fx_mult_i12, &fx_mult_i13, &fx_mult_i14, &fx_mult_i15, |
4180 | // 90 - 9f |
4181 | &fx_sbk, &fx_link_i1, &fx_link_i2, &fx_link_i3, &fx_link_i4, &fx_sex, &fx_asr, &fx_ror, |
4182 | &fx_jmp_r8, &fx_jmp_r9, &fx_jmp_r10, &fx_jmp_r11, &fx_jmp_r12, &fx_jmp_r13, &fx_lob, &fx_fmult, |
4183 | // a0 - af |
4184 | &fx_sms_r0, &fx_sms_r1, &fx_sms_r2, &fx_sms_r3, &fx_sms_r4, &fx_sms_r5, &fx_sms_r6, &fx_sms_r7, |
4185 | &fx_sms_r8, &fx_sms_r9, &fx_sms_r10, &fx_sms_r11, &fx_sms_r12, &fx_sms_r13, &fx_sms_r14, &fx_sms_r15, |
4186 | // b0 - bf |
4187 | &fx_from_r0, &fx_from_r1, &fx_from_r2, &fx_from_r3, &fx_from_r4, &fx_from_r5, &fx_from_r6, &fx_from_r7, |
4188 | &fx_from_r8, &fx_from_r9, &fx_from_r10, &fx_from_r11, &fx_from_r12, &fx_from_r13, &fx_from_r14, &fx_from_r15, |
4189 | // c0 - cf |
4190 | &fx_hib, &fx_or_i1, &fx_or_i2, &fx_or_i3, &fx_or_i4, &fx_or_i5, &fx_or_i6, &fx_or_i7, |
4191 | &fx_or_i8, &fx_or_i9, &fx_or_i10, &fx_or_i11, &fx_or_i12, &fx_or_i13, &fx_or_i14, &fx_or_i15, |
4192 | // d0 - df |
4193 | &fx_inc_r0, &fx_inc_r1, &fx_inc_r2, &fx_inc_r3, &fx_inc_r4, &fx_inc_r5, &fx_inc_r6, &fx_inc_r7, |
4194 | &fx_inc_r8, &fx_inc_r9, &fx_inc_r10, &fx_inc_r11, &fx_inc_r12, &fx_inc_r13, &fx_inc_r14, &fx_ramb, |
4195 | // e0 - ef |
4196 | &fx_dec_r0, &fx_dec_r1, &fx_dec_r2, &fx_dec_r3, &fx_dec_r4, &fx_dec_r5, &fx_dec_r6, &fx_dec_r7, |
4197 | &fx_dec_r8, &fx_dec_r9, &fx_dec_r10, &fx_dec_r11, &fx_dec_r12, &fx_dec_r13, &fx_dec_r14, &fx_getbl, |
4198 | // f0 - ff |
4199 | &fx_sm_r0, &fx_sm_r1, &fx_sm_r2, &fx_sm_r3, &fx_sm_r4, &fx_sm_r5, &fx_sm_r6, &fx_sm_r7, |
4200 | &fx_sm_r8, &fx_sm_r9, &fx_sm_r10, &fx_sm_r11, &fx_sm_r12, &fx_sm_r13, &fx_sm_r14, &fx_sm_r15, |
4201 | |
4202 | // ALT3 Table |
4203 | |
4204 | // 00 - 0f |
4205 | &fx_stop, &fx_nop, &fx_cache, &fx_lsr, &fx_rol, &fx_bra, &fx_bge, &fx_blt, |
4206 | &fx_bne, &fx_beq, &fx_bpl, &fx_bmi, &fx_bcc, &fx_bcs, &fx_bvc, &fx_bvs, |
4207 | // 10 - 1f |
4208 | &fx_to_r0, &fx_to_r1, &fx_to_r2, &fx_to_r3, &fx_to_r4, &fx_to_r5, &fx_to_r6, &fx_to_r7, |
4209 | &fx_to_r8, &fx_to_r9, &fx_to_r10, &fx_to_r11, &fx_to_r12, &fx_to_r13, &fx_to_r14, &fx_to_r15, |
4210 | // 20 - 2f |
4211 | &fx_with_r0, &fx_with_r1, &fx_with_r2, &fx_with_r3, &fx_with_r4, &fx_with_r5, &fx_with_r6, &fx_with_r7, |
4212 | &fx_with_r8, &fx_with_r9, &fx_with_r10, &fx_with_r11, &fx_with_r12, &fx_with_r13, &fx_with_r14, &fx_with_r15, |
4213 | // 30 - 3f |
4214 | &fx_stb_r0, &fx_stb_r1, &fx_stb_r2, &fx_stb_r3, &fx_stb_r4, &fx_stb_r5, &fx_stb_r6, &fx_stb_r7, |
4215 | &fx_stb_r8, &fx_stb_r9, &fx_stb_r10, &fx_stb_r11, &fx_loop, &fx_alt1, &fx_alt2, &fx_alt3, |
4216 | // 40 - 4f |
4217 | &fx_ldb_r0, &fx_ldb_r1, &fx_ldb_r2, &fx_ldb_r3, &fx_ldb_r4, &fx_ldb_r5, &fx_ldb_r6, &fx_ldb_r7, |
4218 | &fx_ldb_r8, &fx_ldb_r9, &fx_ldb_r10, &fx_ldb_r11, &fx_rpix_2bit, &fx_swap, &fx_cmode, &fx_not, |
4219 | // 50 - 5f |
4220 | &fx_adc_i0, &fx_adc_i1, &fx_adc_i2, &fx_adc_i3, &fx_adc_i4, &fx_adc_i5, &fx_adc_i6, &fx_adc_i7, |
4221 | &fx_adc_i8, &fx_adc_i9, &fx_adc_i10, &fx_adc_i11, &fx_adc_i12, &fx_adc_i13, &fx_adc_i14, &fx_adc_i15, |
4222 | // 60 - 6f |
4223 | &fx_cmp_r0, &fx_cmp_r1, &fx_cmp_r2, &fx_cmp_r3, &fx_cmp_r4, &fx_cmp_r5, &fx_cmp_r6, &fx_cmp_r7, |
4224 | &fx_cmp_r8, &fx_cmp_r9, &fx_cmp_r10, &fx_cmp_r11, &fx_cmp_r12, &fx_cmp_r13, &fx_cmp_r14, &fx_cmp_r15, |
4225 | // 70 - 7f |
4226 | &fx_merge, &fx_bic_i1, &fx_bic_i2, &fx_bic_i3, &fx_bic_i4, &fx_bic_i5, &fx_bic_i6, &fx_bic_i7, |
4227 | &fx_bic_i8, &fx_bic_i9, &fx_bic_i10, &fx_bic_i11, &fx_bic_i12, &fx_bic_i13, &fx_bic_i14, &fx_bic_i15, |
4228 | // 80 - 8f |
4229 | &fx_umult_i0, &fx_umult_i1, &fx_umult_i2, &fx_umult_i3, &fx_umult_i4, &fx_umult_i5, &fx_umult_i6, &fx_umult_i7, |
4230 | &fx_umult_i8, &fx_umult_i9, &fx_umult_i10, &fx_umult_i11, &fx_umult_i12, &fx_umult_i13, &fx_umult_i14, &fx_umult_i15, |
4231 | // 90 - 9f |
4232 | &fx_sbk, &fx_link_i1, &fx_link_i2, &fx_link_i3, &fx_link_i4, &fx_sex, &fx_div2, &fx_ror, |
4233 | &fx_ljmp_r8, &fx_ljmp_r9, &fx_ljmp_r10, &fx_ljmp_r11, &fx_ljmp_r12, &fx_ljmp_r13, &fx_lob, &fx_lmult, |
4234 | // a0 - af |
4235 | &fx_lms_r0, &fx_lms_r1, &fx_lms_r2, &fx_lms_r3, &fx_lms_r4, &fx_lms_r5, &fx_lms_r6, &fx_lms_r7, |
4236 | &fx_lms_r8, &fx_lms_r9, &fx_lms_r10, &fx_lms_r11, &fx_lms_r12, &fx_lms_r13, &fx_lms_r14, &fx_lms_r15, |
4237 | // b0 - bf |
4238 | &fx_from_r0, &fx_from_r1, &fx_from_r2, &fx_from_r3, &fx_from_r4, &fx_from_r5, &fx_from_r6, &fx_from_r7, |
4239 | &fx_from_r8, &fx_from_r9, &fx_from_r10, &fx_from_r11, &fx_from_r12, &fx_from_r13, &fx_from_r14, &fx_from_r15, |
4240 | // c0 - cf |
4241 | &fx_hib, &fx_xor_i1, &fx_xor_i2, &fx_xor_i3, &fx_xor_i4, &fx_xor_i5, &fx_xor_i6, &fx_xor_i7, |
4242 | &fx_xor_i8, &fx_xor_i9, &fx_xor_i10, &fx_xor_i11, &fx_xor_i12, &fx_xor_i13, &fx_xor_i14, &fx_xor_i15, |
4243 | // d0 - df |
4244 | &fx_inc_r0, &fx_inc_r1, &fx_inc_r2, &fx_inc_r3, &fx_inc_r4, &fx_inc_r5, &fx_inc_r6, &fx_inc_r7, |
4245 | &fx_inc_r8, &fx_inc_r9, &fx_inc_r10, &fx_inc_r11, &fx_inc_r12, &fx_inc_r13, &fx_inc_r14, &fx_romb, |
4246 | // e0 - ef |
4247 | &fx_dec_r0, &fx_dec_r1, &fx_dec_r2, &fx_dec_r3, &fx_dec_r4, &fx_dec_r5, &fx_dec_r6, &fx_dec_r7, |
4248 | &fx_dec_r8, &fx_dec_r9, &fx_dec_r10, &fx_dec_r11, &fx_dec_r12, &fx_dec_r13, &fx_dec_r14, &fx_getbs, |
4249 | // f0 - ff |
4250 | &fx_lm_r0, &fx_lm_r1, &fx_lm_r2, &fx_lm_r3, &fx_lm_r4, &fx_lm_r5, &fx_lm_r6, &fx_lm_r7, |
4251 | &fx_lm_r8, &fx_lm_r9, &fx_lm_r10, &fx_lm_r11, &fx_lm_r12, &fx_lm_r13, &fx_lm_r14, &fx_lm_r15 |
4252 | }; |
4253 | |