1 | // Licensed to the Apache Software Foundation (ASF) under one |
2 | // or more contributor license agreements. See the NOTICE file |
3 | // distributed with this work for additional information |
4 | // regarding copyright ownership. The ASF licenses this file |
5 | // to you under the Apache License, Version 2.0 (the |
6 | // "License"); you may not use this file except in compliance |
7 | // with the License. You may obtain a copy of the License at |
8 | // |
9 | // http://www.apache.org/licenses/LICENSE-2.0 |
10 | // |
11 | // Unless required by applicable law or agreed to in writing, |
12 | // software distributed under the License is distributed on an |
13 | // "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY |
14 | // KIND, either express or implied. See the License for the |
15 | // specific language governing permissions and limitations |
16 | // under the License. |
17 | |
18 | // From Apache Impala (incubating) as of 2016-01-29. Pared down to a minimal |
19 | // set of functions needed for Apache Arrow / Apache parquet-cpp |
20 | |
21 | #ifndef ARROW_UTIL_CPU_INFO_H |
22 | #define ARROW_UTIL_CPU_INFO_H |
23 | |
24 | #include <cstdint> |
25 | #include <string> |
26 | |
27 | #include "arrow/util/visibility.h" |
28 | |
29 | namespace arrow { |
30 | namespace internal { |
31 | |
32 | /// CpuInfo is an interface to query for cpu information at runtime. The caller can |
33 | /// ask for the sizes of the caches and what hardware features are supported. |
34 | /// On Linux, this information is pulled from a couple of sys files (/proc/cpuinfo and |
35 | /// /sys/devices) |
36 | class ARROW_EXPORT CpuInfo { |
37 | public: |
38 | static constexpr int64_t SSSE3 = (1 << 1); |
39 | static constexpr int64_t SSE4_1 = (1 << 2); |
40 | static constexpr int64_t SSE4_2 = (1 << 3); |
41 | static constexpr int64_t POPCNT = (1 << 4); |
42 | |
43 | /// Cache enums for L1 (data), L2 and L3 |
44 | enum CacheLevel { |
45 | L1_CACHE = 0, |
46 | L2_CACHE = 1, |
47 | L3_CACHE = 2, |
48 | }; |
49 | |
50 | static CpuInfo* GetInstance(); |
51 | |
52 | /// Determine if the CPU meets the minimum CPU requirements and if not, issue an error |
53 | /// and terminate. |
54 | void VerifyCpuRequirements(); |
55 | |
56 | /// Returns all the flags for this cpu |
57 | int64_t hardware_flags(); |
58 | |
59 | /// Returns whether of not the cpu supports this flag |
60 | bool IsSupported(int64_t flag) const { return (hardware_flags_ & flag) != 0; } |
61 | |
62 | /// \brief The processor supports SSE4.2 and the Arrow libraries are built |
63 | /// with support for it |
64 | bool CanUseSSE4_2() const; |
65 | |
66 | /// Toggle a hardware feature on and off. It is not valid to turn on a feature |
67 | /// that the underlying hardware cannot support. This is useful for testing. |
68 | void EnableFeature(int64_t flag, bool enable); |
69 | |
70 | /// Returns the size of the cache in KB at this cache level |
71 | int64_t CacheSize(CacheLevel level); |
72 | |
73 | /// Returns the number of cpu cycles per millisecond |
74 | int64_t cycles_per_ms(); |
75 | |
76 | /// Returns the number of cores (including hyper-threaded) on this machine. |
77 | int num_cores(); |
78 | |
79 | /// Returns the model name of the cpu (e.g. Intel i7-2600) |
80 | std::string model_name(); |
81 | |
82 | private: |
83 | CpuInfo(); |
84 | |
85 | void Init(); |
86 | |
87 | /// Inits CPU cache size variables with default values |
88 | void SetDefaultCacheSize(); |
89 | |
90 | int64_t hardware_flags_; |
91 | int64_t original_hardware_flags_; |
92 | int64_t cache_sizes_[L3_CACHE + 1]; |
93 | int64_t cycles_per_ms_; |
94 | int num_cores_; |
95 | std::string model_name_; |
96 | }; |
97 | |
98 | } // namespace internal |
99 | } // namespace arrow |
100 | |
101 | #endif // ARROW_UTIL_CPU_INFO_H |
102 | |