| 1 | #include "ia32_insn.h" |
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| 2 | |
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| 3 | #include "ia32_reg.h" |
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| 4 | |
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| 5 | #include "ia32_opcode_tables.h" |
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| 6 | |
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| 7 | static ia32_insn_t tbl_Main[] = { /* One-byte Opcodes */ |
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| 8 | { 0, INS_ADD, 0, ADDRMETH_E | OPTYPE_b | OP_W | OP_R, ADDRMETH_G | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "add" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
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| 9 | { 0, INS_ADD, 0, ADDRMETH_E | OPTYPE_v | OP_W | OP_R, ADDRMETH_G | OPTYPE_v | OP_R, ARG_NONE, cpu_80386 | isa_GP, "add" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
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| 10 | { 0, INS_ADD, 0, ADDRMETH_G | OPTYPE_b | OP_W | OP_R, ADDRMETH_E | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "add" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
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| 11 | { 0, INS_ADD, 0, ADDRMETH_G | OPTYPE_v | OP_W | OP_R, ADDRMETH_E | OPTYPE_v | OP_R, ARG_NONE, cpu_80386 | isa_GP, "add" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
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| 12 | { 0, INS_ADD, 0, ADDRMETH_RR | OPTYPE_b | OP_W | OP_R, ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R, ARG_NONE, cpu_80386 | isa_GP, "add" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
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| 13 | { 0, INS_ADD, 0, ADDRMETH_RR | OPTYPE_v | OP_W | OP_R, ADDRMETH_I | OPTYPE_v | OP_SIGNED | OP_R, ARG_NONE, cpu_80386 | isa_GP, "add" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
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| 14 | { 0, INS_PUSH, 0, ADDRMETH_RS | OPTYPE_w | OP_R, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "push" , "" , 0, 0, 0, 0 , 33 }, |
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| 15 | { 0, INS_POP, 0, ADDRMETH_RS | OPTYPE_w | OP_W, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "pop" , "" , 0, 0, 0, 0 , 33 }, |
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| 16 | { 0, INS_OR, 0, ADDRMETH_E | OPTYPE_b | OP_W | OP_R, ADDRMETH_G | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "or" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
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| 17 | { 0, INS_OR, 0, ADDRMETH_E | OPTYPE_v | OP_W | OP_R, ADDRMETH_G | OPTYPE_v | OP_R, ARG_NONE, cpu_80386 | isa_GP, "or" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
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| 18 | { 0, INS_OR, 0, ADDRMETH_G | OPTYPE_b | OP_W | OP_R, ADDRMETH_E | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "or" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
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| 19 | { 0, INS_OR, 0, ADDRMETH_G | OPTYPE_v | OP_W | OP_R, ADDRMETH_E | OPTYPE_v | OP_R, ARG_NONE, cpu_80386 | isa_GP, "or" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
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| 20 | { 0, INS_OR, 0, ADDRMETH_RR | OPTYPE_b | OP_W | OP_R, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "or" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
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| 21 | { 0, INS_OR, 0, ADDRMETH_RR | OPTYPE_v | OP_W | OP_R, ADDRMETH_I | OPTYPE_v | OP_R, ARG_NONE, cpu_80386 | isa_GP, "or" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
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| 22 | { 0, INS_PUSH, 0, ADDRMETH_RS | OPTYPE_w | OP_R, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "push" , "" , 1, 0, 0, 0 , 33 }, |
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| 23 | { idx_0F, 0, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "" , "" , 0, 0, 0, 0 , 0 }, |
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| 24 | /* 0x10 */ |
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| 25 | { 0, INS_ADD, 0, ADDRMETH_E | OPTYPE_b | OP_W | OP_R, ADDRMETH_G | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "adc" , "" , 0, 0, 0, INS_SET_ALL|INS_TEST_CARRY, 0 }, |
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| 26 | { 0, INS_ADD, 0, ADDRMETH_E | OPTYPE_v | OP_W | OP_R, ADDRMETH_G | OPTYPE_v | OP_R, ARG_NONE, cpu_80386 | isa_GP, "adc" , "" , 0, 0, 0, INS_SET_ALL|INS_TEST_CARRY, 0 }, |
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| 27 | { 0, INS_ADD, 0, ADDRMETH_G | OPTYPE_b | OP_W | OP_R, ADDRMETH_E | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "adc" , "" , 0, 0, 0, INS_SET_ALL|INS_TEST_CARRY, 0 }, |
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| 28 | { 0, INS_ADD, 0, ADDRMETH_G | OPTYPE_v | OP_W | OP_R, ADDRMETH_E | OPTYPE_v | OP_R, ARG_NONE, cpu_80386 | isa_GP, "adc" , "" , 0, 0, 0, INS_SET_ALL|INS_TEST_CARRY, 0 }, |
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| 29 | { 0, INS_ADD, 0, ADDRMETH_RR | OPTYPE_b | OP_W | OP_R, ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R, ARG_NONE, cpu_80386 | isa_GP, "adc" , "" , 0, 0, 0, INS_SET_ALL|INS_TEST_CARRY, 0 }, |
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| 30 | { 0, INS_ADD, 0, ADDRMETH_RR | OPTYPE_v | OP_W | OP_R, ADDRMETH_I | OPTYPE_v | OP_SIGNED | OP_R, ARG_NONE, cpu_80386 | isa_GP, "adc" , "" , 0, 0, 0, INS_SET_ALL|INS_TEST_CARRY, 0 }, |
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| 31 | { 0, INS_PUSH, 0, ADDRMETH_RS | OPTYPE_w | OP_R, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "push" , "" , 2, 0, 0, 0 , 33 }, |
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| 32 | { 0, INS_POP, 0, ADDRMETH_RS | OPTYPE_w | OP_W, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "pop" , "" , 2, 0, 0, 0 , 33 }, |
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| 33 | { 0, INS_SUB, 0, ADDRMETH_E | OPTYPE_b | OP_SIGNED | OP_W | OP_R, ADDRMETH_G | OPTYPE_b | OP_SIGNED | OP_R, ARG_NONE, cpu_80386 | isa_GP, "sbb" , "" , 0, 0, 0, INS_SET_ALL|INS_TEST_CARRY, 0 }, |
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| 34 | { 0, INS_SUB, 0, ADDRMETH_E | OPTYPE_v | OP_SIGNED | OP_W | OP_R, ADDRMETH_G | OPTYPE_v | OP_SIGNED | OP_R, ARG_NONE, cpu_80386 | isa_GP, "sbb" , "" , 0, 0, 0, INS_SET_ALL|INS_TEST_CARRY, 0 }, |
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| 35 | { 0, INS_SUB, 0, ADDRMETH_G | OPTYPE_b | OP_W | OP_SIGNED | OP_R, ADDRMETH_E | OPTYPE_b | OP_SIGNED | OP_R, ARG_NONE, cpu_80386 | isa_GP, "sbb" , "" , 0, 0, 0, INS_SET_ALL|INS_TEST_CARRY, 0 }, |
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| 36 | { 0, INS_SUB, 0, ADDRMETH_G | OPTYPE_v | OP_SIGNED | OP_W | OP_R, ADDRMETH_E | OPTYPE_v | OP_SIGNED | OP_R, ARG_NONE, cpu_80386 | isa_GP, "sbb" , "" , 0, 0, 0, INS_SET_ALL|INS_TEST_CARRY, 0 }, |
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| 37 | { 0, INS_SUB, 0, ADDRMETH_RR | OPTYPE_b | OP_SIGNED | OP_W | OP_R, ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R, ARG_NONE, cpu_80386 | isa_GP, "sbb" , "" , 0, 0, 0, INS_SET_ALL|INS_TEST_CARRY, 0 }, |
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| 38 | { 0, INS_SUB, 0, ADDRMETH_RR | OPTYPE_v | OP_SIGNED | OP_W | OP_R, ADDRMETH_I | OPTYPE_v | OP_SIGNED | OP_R, ARG_NONE, cpu_80386 | isa_GP, "sbb" , "" , 0, 0, 0, INS_SET_ALL|INS_TEST_CARRY, 0 }, |
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| 39 | { 0, INS_PUSH, 0, ADDRMETH_RS | OPTYPE_w | OP_R, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "push" , "" , 3, 0, 0, 0 , 33 }, |
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| 40 | { 0, INS_POP, 0, ADDRMETH_RS | OPTYPE_w | OP_W, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "pop" , "" , 3, 0, 0, 0 , 33 }, |
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| 41 | /* 0x20 */ |
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| 42 | { 0, INS_AND, 0, ADDRMETH_E | OPTYPE_b | OP_W | OP_R, ADDRMETH_G | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "and" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
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| 43 | { 0, INS_AND, 0, ADDRMETH_E | OPTYPE_v | OP_W | OP_R, ADDRMETH_G | OPTYPE_v | OP_R, ARG_NONE, cpu_80386 | isa_GP, "and" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
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| 44 | { 0, INS_AND, 0, ADDRMETH_G | OPTYPE_b | OP_W | OP_R, ADDRMETH_E | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "and" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
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| 45 | { 0, INS_AND, 0, ADDRMETH_G | OPTYPE_v | OP_W | OP_R, ADDRMETH_E | OPTYPE_v | OP_R, ARG_NONE, cpu_80386 | isa_GP, "and" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
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| 46 | { 0, INS_AND, 0, ADDRMETH_RR | OPTYPE_b | OP_W | OP_R, ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R, ARG_NONE, cpu_80386 | isa_GP, "and" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
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| 47 | { 0, INS_AND, 0, ADDRMETH_RR | OPTYPE_v | OP_W | OP_R, ADDRMETH_I | OPTYPE_v | OP_R, ARG_NONE, cpu_80386 | isa_GP, "and" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
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| 48 | { 0, INS_FLAG_PREFIX | PREFIX_ES, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "" , "" , 0, 0, 0, 0 , 0 }, |
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| 49 | { 0, INS_BCDCONV, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "daa" , "" , 0, 0, 0, INS_SET_SIGN|INS_SET_ZERO|INS_SET_CARRY|INS_SET_PARITY|INS_TEST_CARRY, 12 }, |
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| 50 | { 0, INS_SUB, 0, ADDRMETH_E | OPTYPE_b | OP_SIGNED | OP_W | OP_R, ADDRMETH_G | OPTYPE_b | OP_SIGNED | OP_R, ARG_NONE, cpu_80386 | isa_GP, "sub" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
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| 51 | { 0, INS_SUB, 0, ADDRMETH_E | OPTYPE_v | OP_SIGNED | OP_W | OP_R, ADDRMETH_G | OPTYPE_v | OP_SIGNED | OP_R, ARG_NONE, cpu_80386 | isa_GP, "sub" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
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| 52 | { 0, INS_SUB, 0, ADDRMETH_G | OPTYPE_b | OP_SIGNED | OP_W | OP_R, ADDRMETH_E | OPTYPE_b | OP_SIGNED | OP_R, ARG_NONE, cpu_80386 | isa_GP, "sub" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
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| 53 | { 0, INS_SUB, 0, ADDRMETH_G | OPTYPE_v | OP_SIGNED | OP_W | OP_R, ADDRMETH_E | OPTYPE_v | OP_SIGNED | OP_R, ARG_NONE, cpu_80386 | isa_GP, "sub" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
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| 54 | { 0, INS_SUB, 0, ADDRMETH_RR | OPTYPE_b | OP_SIGNED | OP_W | OP_R, ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R, ARG_NONE, cpu_80386 | isa_GP, "sub" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
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| 55 | { 0, INS_SUB, 0, ADDRMETH_RR | OPTYPE_v | OP_SIGNED | OP_W | OP_R, ADDRMETH_I | OPTYPE_v | OP_SIGNED | OP_R, ARG_NONE, cpu_80386 | isa_GP, "sub" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
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| 56 | { 0, INS_FLAG_PREFIX | PREFIX_CS | PREFIX_NOTTAKEN, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "" , "" , 0, 0, 0, 0 , 0 }, |
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| 57 | { 0, INS_BCDCONV, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "das" , "" , 0, 0, 0, INS_SET_SIGN|INS_SET_ZERO|INS_SET_CARRY|INS_SET_PARITY|INS_TEST_CARRY, 0 }, |
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| 58 | /* 0x30 */ |
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| 59 | { 0, INS_XOR, 0, ADDRMETH_E | OPTYPE_b | OP_W | OP_R, ADDRMETH_G | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "xor" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
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| 60 | { 0, INS_XOR, 0, ADDRMETH_E | OPTYPE_v | OP_W | OP_R, ADDRMETH_G | OPTYPE_v | OP_R, ARG_NONE, cpu_80386 | isa_GP, "xor" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
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| 61 | { 0, INS_XOR, 0, ADDRMETH_G | OPTYPE_b | OP_W | OP_R, ADDRMETH_E | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "xor" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
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| 62 | { 0, INS_XOR, 0, ADDRMETH_G | OPTYPE_v | OP_W | OP_R, ADDRMETH_E | OPTYPE_v | OP_R, ARG_NONE, cpu_80386 | isa_GP, "xor" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
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| 63 | { 0, INS_XOR, 0, ADDRMETH_RR | OPTYPE_b | OP_W | OP_R, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "xor" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
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| 64 | { 0, INS_XOR, 0, ADDRMETH_RR | OPTYPE_v | OP_W | OP_R, ADDRMETH_I | OPTYPE_v | OP_R, ARG_NONE, cpu_80386 | isa_GP, "xor" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
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| 65 | { 0, INS_FLAG_PREFIX | PREFIX_SS, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "" , "" , 0, 0, 0, 0 , 0 }, |
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| 66 | { 0, INS_BCDCONV, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "aaa" , "" , 0, 0, 0, INS_SET_CARRY, 1 }, |
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| 67 | { 0, INS_CMP, 0, ADDRMETH_E | OPTYPE_b | OP_R, ADDRMETH_G | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "cmp" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
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| 68 | { 0, INS_CMP, 0, ADDRMETH_E | OPTYPE_v | OP_R, ADDRMETH_G | OPTYPE_v | OP_R, ARG_NONE, cpu_80386 | isa_GP, "cmp" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
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| 69 | { 0, INS_CMP, 0, ADDRMETH_G | OPTYPE_b | OP_R, ADDRMETH_E | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "cmp" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
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| 70 | { 0, INS_CMP, 0, ADDRMETH_G | OPTYPE_v | OP_R, ADDRMETH_E | OPTYPE_v | OP_R, ARG_NONE, cpu_80386 | isa_GP, "cmp" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
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| 71 | { 0, INS_CMP, 0, ADDRMETH_RR | OPTYPE_b | OP_R, ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R, ARG_NONE, cpu_80386 | isa_GP, "cmp" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
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| 72 | { 0, INS_CMP, 0, ADDRMETH_RR | OPTYPE_v | OP_R, ADDRMETH_I | OPTYPE_v | OP_SIGNED | OP_R, ARG_NONE, cpu_80386 | isa_GP, "cmp" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
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| 73 | { 0, INS_FLAG_PREFIX | PREFIX_DS | PREFIX_TAKEN, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "" , "" , 0, 0, 0, 0 , 0 }, |
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| 74 | { 0, INS_BCDCONV, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "aas" , "" , 0, 0, 0, INS_SET_CARRY, 0 }, |
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| 75 | /* 0x40 */ |
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| 76 | { 0, INS_INC, 0, ADDRMETH_RR | OPTYPE_v | OP_R | OP_W, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "inc" , "" , 0, 0, 0, INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY, 0 }, |
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| 77 | { 0, INS_INC, 0, ADDRMETH_RR | OPTYPE_v | OP_R | OP_W, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "inc" , "" , 1, 0, 0, INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY, 0 }, |
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| 78 | { 0, INS_INC, 0, ADDRMETH_RR | OPTYPE_v | OP_R | OP_W, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "inc" , "" , 2, 0, 0, INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY, 0 }, |
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| 79 | { 0, INS_INC, 0, ADDRMETH_RR | OPTYPE_v | OP_R | OP_W, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "inc" , "" , 3, 0, 0, INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY, 0 }, |
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| 80 | { 0, INS_INC, 0, ADDRMETH_RR | OPTYPE_v | OP_R | OP_W, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "inc" , "" , 4, 0, 0, INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY, 0 }, |
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| 81 | { 0, INS_INC, 0, ADDRMETH_RR | OPTYPE_v | OP_R | OP_W, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "inc" , "" , 5, 0, 0, INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY, 0 }, |
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| 82 | { 0, INS_INC, 0, ADDRMETH_RR | OPTYPE_v | OP_R | OP_W, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "inc" , "" , 6, 0, 0, INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY, 0 }, |
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| 83 | { 0, INS_INC, 0, ADDRMETH_RR | OPTYPE_v | OP_R | OP_W, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "inc" , "" , 7, 0, 0, INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY, 0 }, |
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| 84 | { 0, INS_DEC, 0, ADDRMETH_RR | OPTYPE_v | OP_W | OP_R, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "dec" , "" , 0, 0, 0, INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY, 0 }, |
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| 85 | { 0, INS_DEC, 0, ADDRMETH_RR | OPTYPE_v | OP_W | OP_R, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "dec" , "" , 1, 0, 0, INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY, 0 }, |
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| 86 | { 0, INS_DEC, 0, ADDRMETH_RR | OPTYPE_v | OP_W | OP_R, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "dec" , "" , 2, 0, 0, INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY, 0 }, |
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| 87 | { 0, INS_DEC, 0, ADDRMETH_RR | OPTYPE_v | OP_W | OP_R, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "dec" , "" , 3, 0, 0, INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY, 0 }, |
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| 88 | { 0, INS_DEC, 0, ADDRMETH_RR | OPTYPE_v | OP_W | OP_R, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "dec" , "" , 4, 0, 0, INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY, 0 }, |
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| 89 | { 0, INS_DEC, 0, ADDRMETH_RR | OPTYPE_v | OP_W | OP_R, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "dec" , "" , 5, 0, 0, INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY, 0 }, |
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| 90 | { 0, INS_DEC, 0, ADDRMETH_RR | OPTYPE_v | OP_W | OP_R, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "dec" , "" , 6, 0, 0, INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY, 0 }, |
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| 91 | { 0, INS_DEC, 0, ADDRMETH_RR | OPTYPE_v | OP_W | OP_R, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "dec" , "" , 7, 0, 0, INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY, 0 }, |
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| 92 | /* 0x50 */ |
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| 93 | { 0, INS_PUSH, 0, ADDRMETH_RR | OPTYPE_v | OP_R, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "push" , "" , 0, 0, 0, 0 , 33 }, |
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| 94 | { 0, INS_PUSH, 0, ADDRMETH_RR | OPTYPE_v | OP_R, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "push" , "" , 1, 0, 0, 0 , 33 }, |
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| 95 | { 0, INS_PUSH, 0, ADDRMETH_RR | OPTYPE_v | OP_R, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "push" , "" , 2, 0, 0, 0 , 33 }, |
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| 96 | { 0, INS_PUSH, 0, ADDRMETH_RR | OPTYPE_v | OP_R, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "push" , "" , 3, 0, 0, 0 , 33 }, |
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| 97 | { 0, INS_PUSH, 0, ADDRMETH_RR | OPTYPE_v | OP_R, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "push" , "" , 4, 0, 0, 0 , 33 }, |
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| 98 | { 0, INS_PUSH, 0, ADDRMETH_RR | OPTYPE_v | OP_R, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "push" , "" , 5, 0, 0, 0 , 33 }, |
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| 99 | { 0, INS_PUSH, 0, ADDRMETH_RR | OPTYPE_v | OP_R, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "push" , "" , 6, 0, 0, 0 , 33 }, |
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| 100 | { 0, INS_PUSH, 0, ADDRMETH_RR | OPTYPE_v | OP_R, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "push" , "" , 7, 0, 0, 0 , 33 }, |
|---|
| 101 | { 0, INS_POP, 0, ADDRMETH_RR | OPTYPE_v | OP_W, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "pop" , "" , 0, 0, 0, 0 , 33 }, |
|---|
| 102 | { 0, INS_POP, 0, ADDRMETH_RR | OPTYPE_v | OP_W, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "pop" , "" , 1, 0, 0, 0 , 33 }, |
|---|
| 103 | { 0, INS_POP, 0, ADDRMETH_RR | OPTYPE_v | OP_W, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "pop" , "" , 2, 0, 0, 0 , 33 }, |
|---|
| 104 | { 0, INS_POP, 0, ADDRMETH_RR | OPTYPE_v | OP_W, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "pop" , "" , 3, 0, 0, 0 , 33 }, |
|---|
| 105 | { 0, INS_POP, 0, ADDRMETH_RR | OPTYPE_v | OP_W, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "pop" , "" , 4, 0, 0, 0 , 33 }, |
|---|
| 106 | { 0, INS_POP, 0, ADDRMETH_RR | OPTYPE_v | OP_W, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "pop" , "" , 5, 0, 0, 0 , 33 }, |
|---|
| 107 | { 0, INS_POP, 0, ADDRMETH_RR | OPTYPE_v | OP_W, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "pop" , "" , 6, 0, 0, 0 , 33 }, |
|---|
| 108 | { 0, INS_POP, 0, ADDRMETH_RR | OPTYPE_v | OP_W, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "pop" , "" , 7, 0, 0, 0 , 33 }, |
|---|
| 109 | /* 0x60 */ |
|---|
| 110 | { 0, INS_PUSHREGS, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "pusha" , "" , 0, 0, 0, 0 , 36 }, |
|---|
| 111 | { 0, INS_POPREGS, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "popa" , "" , 0, 0, 0, 0 , 34 }, |
|---|
| 112 | { 0, INS_BOUNDS, INS_NOTE_NONSWAP, ADDRMETH_G | OPTYPE_v | OP_R, ADDRMETH_M | OPTYPE_a | OP_SIGNED | OP_R, ARG_NONE, cpu_80386 | isa_GP, "bound" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 113 | { 0, INS_SYSTEM, 0, ADDRMETH_E | OPTYPE_w | OP_R | OP_W, ADDRMETH_G | OPTYPE_w | OP_R, ARG_NONE, cpu_80386 | isa_GP, "arpl" , "" , 0, 0, 0, INS_SET_ZERO, 0 }, |
|---|
| 114 | { 0, INS_FLAG_PREFIX | PREFIX_FS, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 115 | { 0, INS_FLAG_PREFIX | PREFIX_GS, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 116 | { idx_66, INS_FLAG_PREFIX | PREFIX_OP_SIZE, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 117 | { 0, INS_FLAG_PREFIX | PREFIX_ADDR_SIZE, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 118 | { 0, INS_PUSH, 0, ADDRMETH_I | OPTYPE_v | OP_R, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "push" , "" , 0, 0, 0, 0 , 33 }, |
|---|
| 119 | { 0, INS_MUL, 0, ADDRMETH_G | OPTYPE_v | OP_SIGNED | OP_R | OP_W, ADDRMETH_E | OPTYPE_v | OP_SIGNED | OP_R, ADDRMETH_I | OPTYPE_v | OP_SIGNED | OP_R, cpu_80386 | isa_GP, "imul" , "" , 0, 0, 0, INS_SET_OFLOW|INS_SET_CARRY, 0 }, |
|---|
| 120 | { 0, INS_PUSH, 0, ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "push" , "" , 0, 0, 0, 0 , 33 }, |
|---|
| 121 | { 0, INS_MUL, 0, ADDRMETH_G | OPTYPE_v | OP_SIGNED | OP_R | OP_W, ADDRMETH_E | OPTYPE_v | OP_SIGNED | OP_R, ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R, cpu_80386 | isa_GP, "imul" , "" , 0, 0, 0, INS_SET_OFLOW|INS_SET_CARRY, 0 }, |
|---|
| 122 | { 0, INS_IN, 0, ADDRMETH_Y | OPTYPE_b | OP_W, ADDRMETH_RR | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "ins" , "" , 0, 2, 0, 0 , 0 }, |
|---|
| 123 | { 0, INS_IN, 0, ADDRMETH_Y | OPTYPE_v | OP_W, ADDRMETH_RR | OPTYPE_v | OP_R, ARG_NONE, cpu_80386 | isa_GP, "ins" , "" , 0, 2, 0, 0 , 0 }, |
|---|
| 124 | { 0, INS_OUT, 0, ADDRMETH_RR | OPTYPE_b | OP_R, ADDRMETH_X | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "outs" , "" , 2, 0, 0, 0 , 0 }, |
|---|
| 125 | { 0, INS_OUT, 0, ADDRMETH_RR | OPTYPE_v | OP_R, ADDRMETH_X | OPTYPE_v | OP_R, ARG_NONE, cpu_80386 | isa_GP, "outs" , "" , 2, 0, 0, 0 , 0 }, |
|---|
| 126 | /* 0x70 */ |
|---|
| 127 | { 0, INS_BRANCHCC, 0, ADDRMETH_J | OPTYPE_b | OP_X, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "jo" , "" , 0, 0, 0, INS_TEST_OFLOW, 0 }, |
|---|
| 128 | { 0, INS_BRANCHCC, 0, ADDRMETH_J | OPTYPE_b | OP_X, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "jno" , "" , 0, 0, 0, INS_TEST_NOFLOW, 0 }, |
|---|
| 129 | { 0, INS_BRANCHCC, 0, ADDRMETH_J | OPTYPE_b | OP_X, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "jc" , "" , 0, 0, 0, INS_TEST_CARRY, 0 }, |
|---|
| 130 | { 0, INS_BRANCHCC, 0, ADDRMETH_J | OPTYPE_b | OP_X, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "jnc" , "" , 0, 0, 0, INS_TEST_NCARRY, 0 }, |
|---|
| 131 | { 0, INS_BRANCHCC, 0, ADDRMETH_J | OPTYPE_b | OP_X, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "jz" , "" , 0, 0, 0, INS_TEST_ZERO, 0 }, |
|---|
| 132 | { 0, INS_BRANCHCC, 0, ADDRMETH_J | OPTYPE_b | OP_X, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "jnz" , "" , 0, 0, 0, INS_TEST_NZERO, 0 }, |
|---|
| 133 | { 0, INS_BRANCHCC, 0, ADDRMETH_J | OPTYPE_b | OP_X, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "jbe" , "" , 0, 0, 0, INS_TEST_CARRY|INS_TEST_OR|INS_TEST_ZERO, 0 }, |
|---|
| 134 | { 0, INS_BRANCHCC, 0, ADDRMETH_J | OPTYPE_b | OP_X, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "ja" , "" , 0, 0, 0, INS_TEST_NCARRY|INS_TEST_NZERO, 0 }, |
|---|
| 135 | { 0, INS_BRANCHCC, 0, ADDRMETH_J | OPTYPE_b | OP_X, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "js" , "" , 0, 0, 0, INS_TEST_SIGN, 0 }, |
|---|
| 136 | { 0, INS_BRANCHCC, 0, ADDRMETH_J | OPTYPE_b | OP_X, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "jns" , "" , 0, 0, 0, INS_TEST_NSIGN, 0 }, |
|---|
| 137 | { 0, INS_BRANCHCC, 0, ADDRMETH_J | OPTYPE_b | OP_X, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "jpe" , "" , 0, 0, 0, INS_TEST_PARITY, 0 }, |
|---|
| 138 | { 0, INS_BRANCHCC, 0, ADDRMETH_J | OPTYPE_b | OP_X, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "jpo" , "" , 0, 0, 0, INS_TEST_NPARITY, 0 }, |
|---|
| 139 | { 0, INS_BRANCHCC, 0, ADDRMETH_J | OPTYPE_b | OP_X, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "jl" , "" , 0, 0, 0, INS_TEST_SFNEOF, 0 }, |
|---|
| 140 | { 0, INS_BRANCHCC, 0, ADDRMETH_J | OPTYPE_b | OP_X, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "jge" , "" , 0, 0, 0, INS_TEST_SFEQOF, 0 }, |
|---|
| 141 | { 0, INS_BRANCHCC, 0, ADDRMETH_J | OPTYPE_b | OP_X, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "jle" , "" , 0, 0, 0, INS_TEST_ZERO|INS_TEST_OR|INS_TEST_SFNEOF, 0 }, |
|---|
| 142 | { 0, INS_BRANCHCC, 0, ADDRMETH_J | OPTYPE_b | OP_X, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "jg" , "" , 0, 0, 0, INS_TEST_NZERO|INS_TEST_SFEQOF, 0 }, |
|---|
| 143 | /* 0x80 */ |
|---|
| 144 | { idx_80, 0, 0, ADDRMETH_E | OPTYPE_b, ADDRMETH_I | OPTYPE_b, ARG_NONE, cpu_80386 | isa_GP, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 145 | { idx_81, 0, 0, ADDRMETH_E | OPTYPE_v, ADDRMETH_I | OPTYPE_v, ARG_NONE, cpu_80386 | isa_GP, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 146 | { idx_82, 0, 0, ADDRMETH_E | OPTYPE_b, ADDRMETH_I | OPTYPE_b, ARG_NONE, cpu_80386 | isa_GP, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 147 | { idx_83, 0, 0, ADDRMETH_E | OPTYPE_v, ADDRMETH_I | OPTYPE_b, ARG_NONE, cpu_80386 | isa_GP, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 148 | { 0, INS_TEST, 0, ADDRMETH_E | OPTYPE_b | OP_R, ADDRMETH_G | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "test" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
|---|
| 149 | { 0, INS_TEST, 0, ADDRMETH_E | OPTYPE_v | OP_R, ADDRMETH_G | OPTYPE_v | OP_R, ARG_NONE, cpu_80386 | isa_GP, "test" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
|---|
| 150 | { 0, INS_XCHG, 0, ADDRMETH_E | OPTYPE_b | OP_W | OP_R, ADDRMETH_G | OPTYPE_b | OP_W | OP_R, ARG_NONE, cpu_80386 | isa_GP, "xchg" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 151 | { 0, INS_XCHG, 0, ADDRMETH_E | OPTYPE_v | OP_W | OP_R, ADDRMETH_G | OPTYPE_v | OP_W | OP_R, ARG_NONE, cpu_80386 | isa_GP, "xchg" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 152 | { 0, INS_MOV, 0, ADDRMETH_E | OPTYPE_b | OP_W, ADDRMETH_G | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "mov" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 153 | { 0, INS_MOV, 0, ADDRMETH_E | OPTYPE_v | OP_W, ADDRMETH_G | OPTYPE_v | OP_R, ARG_NONE, cpu_80386 | isa_GP, "mov" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 154 | { 0, INS_MOV, 0, ADDRMETH_G | OPTYPE_b | OP_W, ADDRMETH_E | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "mov" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 155 | { 0, INS_MOV, 0, ADDRMETH_G | OPTYPE_v | OP_W, ADDRMETH_E | OPTYPE_v | OP_R, ARG_NONE, cpu_80386 | isa_GP, "mov" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 156 | { 0, INS_MOV, 0, ADDRMETH_E | OPTYPE_w | OP_W, ADDRMETH_S | OPTYPE_w | OP_R, ARG_NONE, cpu_80386 | isa_GP, "mov" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 157 | { 0, INS_MOV, 0, ADDRMETH_G | OPTYPE_v | OP_W, ADDRMETH_M | OPTYPE_m | OP_R, ARG_NONE, cpu_80386 | isa_GP, "lea" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 158 | { 0, INS_MOV, 0, ADDRMETH_S | OPTYPE_w | OP_W, ADDRMETH_E | OPTYPE_w | OP_R, ARG_NONE, cpu_80386 | isa_GP, "mov" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 159 | { 0, INS_POP, 0, ADDRMETH_E | OPTYPE_v | OP_W, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "pop" , "" , 0, 0, 0, 0 , 33 }, |
|---|
| 160 | /* 0x90 */ |
|---|
| 161 | { 0, INS_NOP, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "nop" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 162 | { 0, INS_XCHG, 0, ADDRMETH_RR | OPTYPE_v | OP_W | OP_R, ADDRMETH_RR | OPTYPE_v | OP_W | OP_R, ARG_NONE, cpu_80386 | isa_GP, "xchg" , "" , 0, 1, 0, 0 , 0 }, |
|---|
| 163 | { 0, INS_XCHG, 0, ADDRMETH_RR | OPTYPE_v | OP_W | OP_R, ADDRMETH_RR | OPTYPE_v | OP_W | OP_R, ARG_NONE, cpu_80386 | isa_GP, "xchg" , "" , 0, 2, 0, 0 , 0 }, |
|---|
| 164 | { 0, INS_XCHG, 0, ADDRMETH_RR | OPTYPE_v | OP_W | OP_R, ADDRMETH_RR | OPTYPE_v | OP_W | OP_R, ARG_NONE, cpu_80386 | isa_GP, "xchg" , "" , 0, 3, 0, 0 , 0 }, |
|---|
| 165 | { 0, INS_XCHG, 0, ADDRMETH_RR | OPTYPE_v | OP_W | OP_R, ADDRMETH_RR | OPTYPE_v | OP_W | OP_R, ARG_NONE, cpu_80386 | isa_GP, "xchg" , "" , 0, 4, 0, 0 , 0 }, |
|---|
| 166 | { 0, INS_XCHG, 0, ADDRMETH_RR | OPTYPE_v | OP_W | OP_R, ADDRMETH_RR | OPTYPE_v | OP_W | OP_R, ARG_NONE, cpu_80386 | isa_GP, "xchg" , "" , 0, 5, 0, 0 , 0 }, |
|---|
| 167 | { 0, INS_XCHG, 0, ADDRMETH_RR | OPTYPE_v | OP_W | OP_R, ADDRMETH_RR | OPTYPE_v | OP_W | OP_R, ARG_NONE, cpu_80386 | isa_GP, "xchg" , "" , 0, 6, 0, 0 , 0 }, |
|---|
| 168 | { 0, INS_XCHG, 0, ADDRMETH_RR | OPTYPE_v | OP_W | OP_R, ADDRMETH_RR | OPTYPE_v | OP_W | OP_R, ARG_NONE, cpu_80386 | isa_GP, "xchg" , "" , 0, 7, 0, 0 , 0 }, |
|---|
| 169 | { 0, INS_SZCONV, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "cwde" , "" , 0, 0, 0, 0 , 5 }, |
|---|
| 170 | { 0, INS_SZCONV, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "cdq" , "" , 0, 0, 0, 0 , 11 }, |
|---|
| 171 | { 0, INS_CALL, 0, ADDRMETH_A | OPTYPE_p | OP_X, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "callf" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 172 | { 0, INS_SYSTEM, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "wait" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 173 | { 0, INS_PUSHFLAGS, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "pushf" , "" , 0, 0, 0, 0 , 37 }, |
|---|
| 174 | { 0, INS_POPFLAGS, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "popf" , "" , 0, 0, 0, 0 , 35 }, |
|---|
| 175 | { 0, INS_MOV, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "sahf" , "" , 0, 0, 0, INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY, 43 }, |
|---|
| 176 | { 0, INS_MOV, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "lahf" , "" , 0, 0, 0, 0 , 24 }, |
|---|
| 177 | /* 0xa0 */ |
|---|
| 178 | { 0, INS_MOV, 0, ADDRMETH_RR | OPTYPE_b | OP_W, ADDRMETH_O | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "mov" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 179 | { 0, INS_MOV, 0, ADDRMETH_RR | OPTYPE_v | OP_W, ADDRMETH_O | OPTYPE_v | OP_R, ARG_NONE, cpu_80386 | isa_GP, "mov" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 180 | { 0, INS_MOV, 0, ADDRMETH_O | OPTYPE_b | OP_W, ADDRMETH_RR | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "mov" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 181 | { 0, INS_MOV, 0, ADDRMETH_O | OPTYPE_v | OP_W, ADDRMETH_RR | OPTYPE_v | OP_R, ARG_NONE, cpu_80386 | isa_GP, "mov" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 182 | { 0, INS_STRMOV, 0, ADDRMETH_Y | OPTYPE_b | OP_W, ADDRMETH_X | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "movs" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 183 | { 0, INS_STRMOV, 0, ADDRMETH_Y | OPTYPE_v | OP_W, ADDRMETH_X | OPTYPE_v | OP_R, ARG_NONE, cpu_80386 | isa_GP, "movs" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 184 | { 0, INS_STRCMP, 0, ADDRMETH_Y | OPTYPE_b | OP_R, ADDRMETH_X | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "cmps" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 185 | { 0, INS_STRCMP, 0, ADDRMETH_X | OPTYPE_v | OP_R, ADDRMETH_Y | OPTYPE_v | OP_R, ARG_NONE, cpu_80386 | isa_GP, "cmps" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 186 | { 0, INS_TEST, 0, ADDRMETH_RR | OPTYPE_b | OP_R, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "test" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
|---|
| 187 | { 0, INS_TEST, 0, ADDRMETH_RR | OPTYPE_v | OP_R, ADDRMETH_I | OPTYPE_v | OP_R, ARG_NONE, cpu_80386 | isa_GP, "test" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
|---|
| 188 | { 0, INS_STRSTOR, 0, ADDRMETH_Y | OPTYPE_b | OP_W, ADDRMETH_RR | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "stos" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 189 | { 0, INS_STRSTOR, 0, ADDRMETH_Y | OPTYPE_v | OP_W, ADDRMETH_RR | OPTYPE_v |OP_R, ARG_NONE, cpu_80386 | isa_GP, "stos" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 190 | { 0, INS_STRLOAD, 0, ADDRMETH_RR | OPTYPE_b | OP_W, ADDRMETH_X| OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "lods" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 191 | { 0, INS_STRLOAD, 0, ADDRMETH_RR | OPTYPE_v | OP_W, ADDRMETH_X| OPTYPE_v | OP_R, ARG_NONE, cpu_80386 | isa_GP, "lods" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 192 | { 0, INS_STRCMP, 0, ADDRMETH_RR | OPTYPE_b | OP_R, ADDRMETH_Y | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "scas" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 193 | { 0, INS_STRCMP, 0, ADDRMETH_RR | OPTYPE_v | OP_R, ADDRMETH_Y | OPTYPE_v | OP_R, ARG_NONE, cpu_80386 | isa_GP, "scas" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 194 | /* 0xb0 */ |
|---|
| 195 | { 0, INS_MOV, 0, ADDRMETH_RR | OPTYPE_b | OP_W, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "mov" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 196 | { 0, INS_MOV, 0, ADDRMETH_RR | OPTYPE_b | OP_W, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "mov" , "" , 1, 0, 0, 0 , 0 }, |
|---|
| 197 | { 0, INS_MOV, 0, ADDRMETH_RR | OPTYPE_b | OP_W, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "mov" , "" , 2, 0, 0, 0 , 0 }, |
|---|
| 198 | { 0, INS_MOV, 0, ADDRMETH_RR | OPTYPE_b | OP_W, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "mov" , "" , 3, 0, 0, 0 , 0 }, |
|---|
| 199 | { 0, INS_MOV, 0, ADDRMETH_RR | OPTYPE_b | OP_W, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "mov" , "" , 4, 0, 0, 0 , 0 }, |
|---|
| 200 | { 0, INS_MOV, 0, ADDRMETH_RR | OPTYPE_b | OP_W, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "mov" , "" , 5, 0, 0, 0 , 0 }, |
|---|
| 201 | { 0, INS_MOV, 0, ADDRMETH_RR | OPTYPE_b | OP_W, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "mov" , "" , 6, 0, 0, 0 , 0 }, |
|---|
| 202 | { 0, INS_MOV, 0, ADDRMETH_RR | OPTYPE_b | OP_W, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "mov" , "" , 7, 0, 0, 0 , 0 }, |
|---|
| 203 | { 0, INS_MOV, 0, ADDRMETH_RR | OPTYPE_v | OP_W, ADDRMETH_I | OPTYPE_v | OP_R, ARG_NONE, cpu_80386 | isa_GP, "mov" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 204 | { 0, INS_MOV, 0, ADDRMETH_RR | OPTYPE_v | OP_W, ADDRMETH_I | OPTYPE_v | OP_R, ARG_NONE, cpu_80386 | isa_GP, "mov" , "" , 1, 0, 0, 0 , 0 }, |
|---|
| 205 | { 0, INS_MOV, 0, ADDRMETH_RR | OPTYPE_v | OP_W, ADDRMETH_I | OPTYPE_v | OP_R, ARG_NONE, cpu_80386 | isa_GP, "mov" , "" , 2, 0, 0, 0 , 0 }, |
|---|
| 206 | { 0, INS_MOV, 0, ADDRMETH_RR | OPTYPE_v | OP_W, ADDRMETH_I | OPTYPE_v | OP_R, ARG_NONE, cpu_80386 | isa_GP, "mov" , "" , 3, 0, 0, 0 , 0 }, |
|---|
| 207 | { 0, INS_MOV, 0, ADDRMETH_RR | OPTYPE_v | OP_W, ADDRMETH_I | OPTYPE_v | OP_R, ARG_NONE, cpu_80386 | isa_GP, "mov" , "" , 4, 0, 0, 0 , 0 }, |
|---|
| 208 | { 0, INS_MOV, 0, ADDRMETH_RR | OPTYPE_v | OP_W, ADDRMETH_I | OPTYPE_v | OP_R, ARG_NONE, cpu_80386 | isa_GP, "mov" , "" , 5, 0, 0, 0 , 0 }, |
|---|
| 209 | { 0, INS_MOV, 0, ADDRMETH_RR | OPTYPE_v | OP_W, ADDRMETH_I | OPTYPE_v | OP_R, ARG_NONE, cpu_80386 | isa_GP, "mov" , "" , 6, 0, 0, 0 , 0 }, |
|---|
| 210 | { 0, INS_MOV, 0, ADDRMETH_RR | OPTYPE_v | OP_W, ADDRMETH_I | OPTYPE_v | OP_R, ARG_NONE, cpu_80386 | isa_GP, "mov" , "" , 7, 0, 0, 0 , 0 }, |
|---|
| 211 | /* 0xc0 */ |
|---|
| 212 | { idx_C0, 0, 0, ADDRMETH_E | OPTYPE_b, ADDRMETH_I | OPTYPE_b, ARG_NONE, cpu_80386 | isa_GP, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 213 | { idx_C1, 0, 0, ADDRMETH_E | OPTYPE_v, ADDRMETH_I | OPTYPE_b, ARG_NONE, cpu_80386 | isa_GP, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 214 | { 0, INS_RET, 0, ADDRMETH_I | OPTYPE_w | OP_R, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "ret" , "" , 0, 0, 0, 0 , 3 }, |
|---|
| 215 | { 0, INS_RET, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "ret" , "" , 0, 0, 0, 0 , 3 }, |
|---|
| 216 | { 0, INS_MOV, 0, ADDRMETH_G | OPTYPE_v | OP_W, ADDRMETH_M | OPTYPE_p | OP_R, ARG_NONE, cpu_80386 | isa_GP, "les" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 217 | { 0, INS_MOV, 0, ADDRMETH_G | OPTYPE_v | OP_W, ADDRMETH_M | OPTYPE_p | OP_R, ARG_NONE, cpu_80386 | isa_GP, "lds" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 218 | { idx_C6, 0, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 219 | { idx_C7, 0, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 220 | { 0, INS_ENTER, INS_NOTE_NONSWAP, ADDRMETH_I | OPTYPE_w | OP_R, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "enter" , "" , 0, 0, 0, 0 , 15 }, |
|---|
| 221 | { 0, INS_LEAVE, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "leave" , "" , 0, 0, 0, 0 , 26 }, |
|---|
| 222 | { 0, INS_RET, 0, ADDRMETH_I | OPTYPE_w | OP_R, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "retf" , "lret" , 0, 0, 0, 0 , 3 }, |
|---|
| 223 | { 0, INS_RET, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "retf" , "lret" , 0, 0, 0, 0 , 3 }, |
|---|
| 224 | { 0, INS_DEBUG, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "int3" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 225 | { 0, INS_TRAP, 0, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "int" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 226 | { 0, INS_OFLOW, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "into" , "" , 0, 0, 0, INS_TEST_OFLOW, 0 }, |
|---|
| 227 | { 0, INS_TRET, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "iret" , "" , 0, 0, 0, INS_SET_ALL|INS_SET_DIR, 0 }, |
|---|
| 228 | /* 0xd0 */ |
|---|
| 229 | { idx_D0, 0, 0, ADDRMETH_E | OPTYPE_b, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "" , "" , 0, 1, 0, 0 , 0 }, |
|---|
| 230 | { idx_D1, 0, 0, ADDRMETH_E | OPTYPE_v, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "" , "" , 0, 1, 0, 0 , 0 }, |
|---|
| 231 | { idx_D2, 0, 0, ADDRMETH_E | OPTYPE_b, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "" , "" , 0, 1, 0, 0 , 0 }, |
|---|
| 232 | { idx_D3, 0, 0, ADDRMETH_E | OPTYPE_v, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "" , "" , 0, 1, 0, 0 , 0 }, |
|---|
| 233 | { 0, INS_BCDCONV, 0, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "aam" , "" , 0, 0, 0, INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY, 0 }, |
|---|
| 234 | { 0, INS_BCDCONV, 0, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "aad" , "" , 0, 0, 0, INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY, 2 }, |
|---|
| 235 | { 0, INS_SALC, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "salc" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 236 | { 0, INS_XLAT, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "xlat" , "" , 0, 0, 0, 0 , 53 }, |
|---|
| 237 | { idx_D8, 0, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 238 | { idx_D9, 0, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 239 | { idx_DA, 0, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 240 | { idx_DB, 0, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 241 | { idx_DC, 0, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 242 | { idx_DD, 0, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 243 | { idx_DE, 0, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 244 | { idx_DF, 0, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 245 | /* 0xe0 */ |
|---|
| 246 | { 0, INS_BRANCHCC, 0, ADDRMETH_J | OPTYPE_b | OP_X, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "loopnz" , "" , 0, 0, 0, INS_TEST_NZERO, 31 }, |
|---|
| 247 | { 0, INS_BRANCHCC, 0, ADDRMETH_J | OPTYPE_b | OP_X, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "loopz" , "" , 0, 0, 0, INS_TEST_ZERO, 31 }, |
|---|
| 248 | { 0, INS_BRANCHCC, 0, ADDRMETH_J | OPTYPE_b | OP_X, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "loop" , "" , 0, 0, 0, 0 , 31 }, |
|---|
| 249 | { 0, INS_BRANCHCC, 0, ADDRMETH_J | OPTYPE_b | OP_X, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "jcxz" , "" , 0, 0, 0, 0 , 31 }, |
|---|
| 250 | { 0, INS_IN, 0, ADDRMETH_RR | OPTYPE_b | OP_W, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "in" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 251 | { 0, INS_IN, 0, ADDRMETH_RR | OPTYPE_b | OP_W, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "in" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 252 | { 0, INS_OUT, 0, ADDRMETH_I | OPTYPE_b | OP_R, ADDRMETH_RR | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "out" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 253 | { 0, INS_OUT, 0, ADDRMETH_I | OPTYPE_b | OP_R, ADDRMETH_RR | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "out" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 254 | { 0, INS_CALL, 0, ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "call" , "" , 0, 0, 0, 0 , 3 }, |
|---|
| 255 | { 0, INS_BRANCH, 0, ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "jmp" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 256 | { 0, INS_BRANCH, 0, ADDRMETH_A | OPTYPE_p | OP_X, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "jmp" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 257 | { 0, INS_BRANCH, 0, ADDRMETH_J | OPTYPE_b | OP_X | OP_SIGNED, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "jmp" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 258 | { 0, INS_IN, 0, ADDRMETH_RR | OPTYPE_b| OP_W, ADDRMETH_RR | OPTYPE_w| OP_R, ARG_NONE, cpu_80386 | isa_GP, "in" , "" , 0, 2, 0, 0 , 0 }, |
|---|
| 259 | { 0, INS_IN, 0, ADDRMETH_RR | OPTYPE_v | OP_W, ADDRMETH_RR | OPTYPE_w| OP_R, ARG_NONE, cpu_80386 | isa_GP, "in" , "" , 0, 2, 0, 0 , 0 }, |
|---|
| 260 | { 0, INS_OUT, 0, ADDRMETH_RR | OPTYPE_w| OP_R, ADDRMETH_RR | OPTYPE_b| OP_R, ARG_NONE, cpu_80386 | isa_GP, "out" , "" , 2, 0, 0, 0 , 0 }, |
|---|
| 261 | { 0, INS_OUT, 0, ADDRMETH_RR | OPTYPE_w| OP_R, ADDRMETH_RR | OPTYPE_v| OP_R, ARG_NONE, cpu_80386 | isa_GP, "out" , "" , 2, 0, 0, 0 , 0 }, |
|---|
| 262 | /* 0xf0 */ |
|---|
| 263 | { 0, INS_FLAG_PREFIX | PREFIX_LOCK, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 264 | { 0, INS_ICEBP, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "icebp" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 265 | { idx_F2, INS_FLAG_PREFIX | PREFIX_REPNZ, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 266 | { idx_F3, INS_FLAG_PREFIX | PREFIX_REPZ, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 267 | { 0, INS_HALT, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "hlt" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 268 | { 0, INS_TOGCF, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "cmc" , "" , 0, 0, 0, INS_SET_CARRY, 0 }, |
|---|
| 269 | { idx_F6, 0, 0, ADDRMETH_E | OPTYPE_b, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 270 | { idx_F7, 0, 0, ADDRMETH_E | OPTYPE_v, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 271 | { 0, INS_CLEARCF, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "clc" , "" , 0, 0, 0, INS_SET_NCARRY, 0 }, |
|---|
| 272 | { 0, INS_SETCF, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "stc" , "" , 0, 0, 0, INS_SET_CARRY, 0 }, |
|---|
| 273 | { 0, INS_SYSTEM, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "cli" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 274 | { 0, INS_SYSTEM, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "sti" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 275 | { 0, INS_CLEARDF, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "cld" , "" , 0, 0, 0, INS_SET_NDIR, 0 }, |
|---|
| 276 | { 0, INS_SETDF, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "std" , "" , 0, 0, 0, INS_SET_DIR, 0 }, |
|---|
| 277 | { idx_FE, 0, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 278 | { idx_FF, 0, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "" , "" , 0, 0, 0, 0 , 0 } |
|---|
| 279 | }; |
|---|
| 280 | |
|---|
| 281 | |
|---|
| 282 | static ia32_insn_t tbl_66[] = { /* SIMD 66 one-byte Opcodes */ |
|---|
| 283 | { idx_660F, 0, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "" , "" , 0, 0, 0, 0 , 0 } |
|---|
| 284 | }; |
|---|
| 285 | |
|---|
| 286 | |
|---|
| 287 | static ia32_insn_t tbl_F2[] = { /* SIMD F2 one-byte Opcodes */ |
|---|
| 288 | { idx_F20F, 0, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "" , "" , 0, 0, 0, 0 , 0 } |
|---|
| 289 | }; |
|---|
| 290 | |
|---|
| 291 | |
|---|
| 292 | static ia32_insn_t tbl_F3[] = { /* SIMD F3 one-byte Opcodes */ |
|---|
| 293 | { idx_F30F, 0, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 294 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 295 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 296 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 297 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 298 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 299 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 300 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 301 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 302 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 303 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 304 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 305 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 306 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 307 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 308 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 309 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 310 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 311 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 312 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 313 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 314 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 315 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 316 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 317 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 318 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 319 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 320 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 321 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 322 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 323 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 324 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 325 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 326 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 327 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 328 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 329 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 330 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 331 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 332 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 333 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 334 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 335 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 336 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 337 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 338 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 339 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 340 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 341 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 342 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 343 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 344 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 345 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 346 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 347 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 348 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 349 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 350 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 351 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 352 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 353 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 354 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 355 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 356 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 357 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 358 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 359 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 360 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 361 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 362 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 363 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 364 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 365 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 366 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 367 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 368 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 369 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 370 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 371 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 372 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 373 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 374 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 375 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 376 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 377 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 378 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 379 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 380 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 381 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 382 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 383 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 384 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 385 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 386 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 387 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 388 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 389 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 390 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 391 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 392 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 393 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 394 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 395 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 396 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 397 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 398 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 399 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 400 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 401 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 402 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 403 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 404 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 405 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 406 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 407 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 408 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 409 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 410 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 411 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 412 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 413 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 414 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 415 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 416 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 417 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 418 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 419 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 420 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 421 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 422 | { 0, INS_SYSTEM, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "pause" , "" , 0, 0, 0, 0, 0 } |
|---|
| 423 | }; |
|---|
| 424 | |
|---|
| 425 | |
|---|
| 426 | static ia32_insn_t tbl_0F[] = { /* Two-byte Opcodes */ |
|---|
| 427 | { idx_0F00, 0, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 428 | { idx_0F01, 0, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 429 | { 0, INS_SYSTEM, 0, ADDRMETH_G | OPTYPE_v | OP_W, ADDRMETH_E | OPTYPE_w | OP_R, ARG_NONE, cpu_80386 | isa_GP, "lar" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 430 | { 0, INS_SYSTEM, 0, ADDRMETH_G | OPTYPE_v | OP_W, ADDRMETH_E | OPTYPE_w | OP_R, ARG_NONE, cpu_80386 | isa_GP, "lsl" , "" , 0, 0, 0, INS_SET_ZERO, 0 }, |
|---|
| 431 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 432 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 433 | { 0, INS_SYSTEM, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "clts" , "" , 0, 0, 0, 0 , 6 }, |
|---|
| 434 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 435 | { 0, INS_SYSTEM, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80486 | isa_GP, "invd" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 436 | { 0, INS_SYSTEM, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80486 | isa_GP, "wbinvd" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 437 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 438 | { 0, INS_UNKNOWN, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTPRO | isa_GP, "ud2" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 439 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 440 | { 0, INS_SYSTEM, 0, ADDRMETH_M | OPTYPE_b | OP_R, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "prefetch" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 441 | { 0, INS_SYSTEM, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "femms" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 442 | { idx_0F0F, INS_FLAG_SUFFIX, 0, ADDRMETH_P | OPTYPE_pi | OP_R | OP_W, ADDRMETH_Q | OPTYPE_q |OP_R, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 443 | { 0, INS_MOV, 0, ADDRMETH_V | OPTYPE_ps | OP_W, ADDRMETH_W | OPTYPE_ps | OP_R, ARG_NONE, cpu_PENTIUM2 | isa_GP, "movups" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 444 | { 0, INS_MOV, 0, ADDRMETH_W | OPTYPE_ps | OP_W, ADDRMETH_V | OPTYPE_ps | OP_R, ARG_NONE, cpu_PENTIUM2 | isa_GP, "movups" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 445 | { idx_0F12, 0, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 446 | { 0, INS_MOV, INS_NOTE_NOSUFFIX, ADDRMETH_V | OPTYPE_q | OP_W, ADDRMETH_W | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM2 | isa_GP, "movlps" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 447 | { 0, INS_OTHER, 0, ADDRMETH_V | OPTYPE_ps | OP_W, ADDRMETH_W | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM2 | isa_GP, "unpcklps" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 448 | { 0, INS_OTHER, 0, ADDRMETH_V | OPTYPE_ps | OP_W, ADDRMETH_W | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM2 | isa_GP, "unpckhps" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 449 | { idx_0F16, 0, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 450 | { 0, INS_OTHER, 0, ADDRMETH_W | OPTYPE_q | OP_W, ADDRMETH_V | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM2 | isa_GP, "movhps" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 451 | { idx_0F18, 0, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 452 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 453 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 454 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 455 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 456 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 457 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 458 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 459 | { 0, INS_MOV, 0, ADDRMETH_R | OPTYPE_d | OP_W, ADDRMETH_C | OPTYPE_d | OP_R, ARG_NONE, cpu_80386 | isa_GP, "mov" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 460 | { 0, INS_MOV, 0, ADDRMETH_R | OPTYPE_d | OP_W, ADDRMETH_D | OPTYPE_d | OP_R, ARG_NONE, cpu_80386 | isa_GP, "mov" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 461 | { 0, INS_MOV, 0, ADDRMETH_C | OPTYPE_d | OP_W, ADDRMETH_R | OPTYPE_d | OP_R, ARG_NONE, cpu_80386 | isa_GP, "mov" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 462 | { 0, INS_MOV, 0, ADDRMETH_D | OPTYPE_d | OP_W, ADDRMETH_R | OPTYPE_d | OP_R, ARG_NONE, cpu_80386 | isa_GP, "mov" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 463 | { 0, INS_MOV, 0, ADDRMETH_R | OPTYPE_d | OP_W, ADDRMETH_T | OPTYPE_d | OP_R, ARG_NONE, cpu_80386 | isa_GP, "mov" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 464 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 465 | { 0, INS_MOV, 0, ADDRMETH_T | OPTYPE_d | OP_W, ADDRMETH_R | OPTYPE_d | OP_R, ARG_NONE, cpu_80386 | isa_GP, "mov" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 466 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 467 | { 0, INS_MOV, 0, ADDRMETH_V | OPTYPE_ps | OP_W, ADDRMETH_W | OPTYPE_ps | OP_R, ARG_NONE, cpu_PENTIUM2 | isa_GP, "movaps" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 468 | { 0, INS_MOV, 0, ADDRMETH_W | OPTYPE_ps | OP_W, ADDRMETH_V | OPTYPE_ps | OP_R, ARG_NONE, cpu_PENTIUM2 | isa_GP, "movaps" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 469 | { 0, INS_MOV, 0, ADDRMETH_V | OPTYPE_ps | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM2 | isa_GP, "cvtpi2ps" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 470 | { 0, INS_MOV, 0, ADDRMETH_W | OPTYPE_ps | OP_W, ADDRMETH_V | OPTYPE_ps | OP_R, ARG_NONE, cpu_PENTIUM2 | isa_GP, "movntps" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 471 | { 0, INS_MOV, 0, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_W | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM2 | isa_GP, "cvttps2pi" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 472 | { 0, INS_MOV, 0, ADDRMETH_P | OPTYPE_q | OP_W , ADDRMETH_W | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM2 | isa_GP, "cvtps2pi" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 473 | { 0, INS_OTHER, 0, ADDRMETH_V | OPTYPE_ss | OP_W, ADDRMETH_W | OPTYPE_ss | OP_R, ARG_NONE, cpu_PENTIUM2 | isa_GP, "ucomiss" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
|---|
| 474 | { 0, INS_OTHER, 0, ADDRMETH_V | OPTYPE_ps | OP_W, ADDRMETH_W | OPTYPE_ss | OP_W, ARG_NONE, cpu_PENTIUM2 | isa_GP, "comiss" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
|---|
| 475 | { 0, INS_SYSTEM, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM | isa_GP, "wrmsr" , "" , 0, 0, 0, 0 , 52 }, |
|---|
| 476 | { 0, INS_SYSTEM, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM | isa_GP, "rdtsc" , "" , 0, 0, 0, 0 , 40 }, |
|---|
| 477 | { 0, INS_SYSTEM, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM | isa_GP, "rdmsr" , "" , 0, 0, 0, 0 , 38 }, |
|---|
| 478 | { 0, INS_SYSTEM, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTPRO | isa_GP, "rdpmc" , "" , 0, 0, 0, 0 , 39 }, |
|---|
| 479 | { 0, INS_SYSTEM, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM2 | isa_GP, "sysenter" , "" , 0, 0, 0, 0 , 50 }, |
|---|
| 480 | { 0, INS_SYSTEM, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM2 | isa_GP, "sysexit" , "" , 0, 0, 0, 0 , 51 }, |
|---|
| 481 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 482 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 483 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 484 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 485 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 486 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 487 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 488 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 489 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 490 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 491 | { 0, INS_MOVCC, 0, ADDRMETH_G | OPTYPE_v | OP_W, ADDRMETH_E | OPTYPE_v | OP_R, ARG_NONE, cpu_PENTPRO | isa_GP, "cmovo" , "" , 0, 0, 0, INS_TEST_OFLOW, 0 }, |
|---|
| 492 | { 0, INS_MOVCC, 0, ADDRMETH_G | OPTYPE_v | OP_W, ADDRMETH_E | OPTYPE_v | OP_R, ARG_NONE, cpu_PENTPRO | isa_GP, "cmovno" , "" , 0, 0, 0, INS_TEST_NOFLOW, 0 }, |
|---|
| 493 | { 0, INS_MOVCC, 0, ADDRMETH_G | OPTYPE_v | OP_W, ADDRMETH_E | OPTYPE_v | OP_R, ARG_NONE, cpu_PENTPRO | isa_GP, "cmovc" , "" , 0, 0, 0, INS_TEST_CARRY, 0 }, |
|---|
| 494 | { 0, INS_MOVCC, 0, ADDRMETH_G | OPTYPE_v | OP_W, ADDRMETH_E | OPTYPE_v | OP_R, ARG_NONE, cpu_PENTPRO | isa_GP, "cmovnc" , "" , 0, 0, 0, INS_TEST_NCARRY, 0 }, |
|---|
| 495 | { 0, INS_MOVCC, 0, ADDRMETH_G | OPTYPE_v | OP_W, ADDRMETH_E | OPTYPE_v | OP_R, ARG_NONE, cpu_PENTPRO | isa_GP, "cmovz" , "" , 0, 0, 0, INS_TEST_ZERO, 0 }, |
|---|
| 496 | { 0, INS_MOVCC, 0, ADDRMETH_G | OPTYPE_v | OP_W, ADDRMETH_E | OPTYPE_v | OP_R, ARG_NONE, cpu_PENTPRO | isa_GP, "cmovnz" , "" , 0, 0, 0, INS_TEST_NZERO, 0 }, |
|---|
| 497 | { 0, INS_MOVCC, 0, ADDRMETH_G | OPTYPE_v | OP_W, ADDRMETH_E | OPTYPE_v | OP_R, ARG_NONE, cpu_PENTPRO | isa_GP, "cmovbe" , "" , 0, 0, 0, INS_TEST_CARRY|INS_TEST_OR|INS_TEST_ZERO, 0 }, |
|---|
| 498 | { 0, INS_MOVCC, 0, ADDRMETH_G | OPTYPE_v | OP_W, ADDRMETH_E | OPTYPE_v | OP_R, ARG_NONE, cpu_PENTPRO | isa_GP, "cmova" , "" , 0, 0, 0, INS_TEST_NZERO|INS_TEST_NCARRY, 0 }, |
|---|
| 499 | { 0, INS_MOVCC, 0, ADDRMETH_G | OPTYPE_v | OP_W, ADDRMETH_E | OPTYPE_v | OP_R, ARG_NONE, cpu_PENTPRO | isa_GP, "cmovs" , "" , 0, 0, 0, INS_TEST_SIGN, 0 }, |
|---|
| 500 | { 0, INS_MOVCC, 0, ADDRMETH_G | OPTYPE_v | OP_W, ADDRMETH_E | OPTYPE_v | OP_R, ARG_NONE, cpu_PENTPRO | isa_GP, "cmovns" , "" , 0, 0, 0, INS_TEST_NSIGN, 0 }, |
|---|
| 501 | { 0, INS_MOVCC, 0, ADDRMETH_G | OPTYPE_v | OP_W, ADDRMETH_E | OPTYPE_v | OP_R, ARG_NONE, cpu_PENTPRO | isa_GP, "cmovp" , "" , 0, 0, 0, INS_TEST_PARITY, 0 }, |
|---|
| 502 | { 0, INS_MOVCC, 0, ADDRMETH_G | OPTYPE_v | OP_W, ADDRMETH_E | OPTYPE_v | OP_R, ARG_NONE, cpu_PENTPRO | isa_GP, "cmovnp" , "" , 0, 0, 0, INS_TEST_NPARITY, 0 }, |
|---|
| 503 | { 0, INS_MOVCC, 0, ADDRMETH_G | OPTYPE_v | OP_W, ADDRMETH_E | OPTYPE_v | OP_R, ARG_NONE, cpu_PENTPRO | isa_GP, "cmovl" , "" , 0, 0, 0, INS_TEST_SFNEOF, 0 }, |
|---|
| 504 | { 0, INS_MOVCC, 0, ADDRMETH_G | OPTYPE_v | OP_W, ADDRMETH_E | OPTYPE_v | OP_R, ARG_NONE, cpu_PENTPRO | isa_GP, "cmovge" , "" , 0, 0, 0, INS_TEST_SFEQOF, 0 }, |
|---|
| 505 | { 0, INS_MOVCC, 0, ADDRMETH_G | OPTYPE_v | OP_W, ADDRMETH_E | OPTYPE_v | OP_R, ARG_NONE, cpu_PENTPRO | isa_GP, "cmovle" , "" , 0, 0, 0, INS_TEST_ZERO|INS_TEST_OR|INS_TEST_SFNEOF, 0 }, |
|---|
| 506 | { 0, INS_MOVCC, 0, ADDRMETH_G | OPTYPE_v | OP_W, ADDRMETH_E | OPTYPE_v | OP_R, ARG_NONE, cpu_PENTPRO | isa_GP, "cmovg" , "" , 0, 0, 0, INS_TEST_NZERO|INS_TEST_SFEQOF, 0 }, |
|---|
| 507 | { 0, INS_MOV, 0, ADDRMETH_G | OPTYPE_d | OP_W, ADDRMETH_W | OPTYPE_ps | OP_R, ARG_NONE, cpu_PENTIUM2 | isa_GP, "movmskps" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 508 | { 0, INS_ARITH, 0, ADDRMETH_V | OPTYPE_ps | OP_W, ADDRMETH_W | OPTYPE_ps | OP_R, ARG_NONE, cpu_PENTIUM2 | isa_GP, "sqrtps" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 509 | { 0, INS_ARITH, 0, ADDRMETH_V | OPTYPE_ps | OP_W, ADDRMETH_W | OPTYPE_ps | OP_R, ARG_NONE, cpu_PENTIUM2 | isa_GP, "rsqrtps" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 510 | { 0, INS_OTHER, 0, ADDRMETH_V | OPTYPE_ps | OP_W, ADDRMETH_W | OPTYPE_ps | OP_R, ARG_NONE, cpu_PENTIUM2 | isa_GP, "rcpps" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 511 | { 0, INS_AND, 0, ADDRMETH_V | OPTYPE_ps | OP_W, ADDRMETH_W | OPTYPE_ps | OP_R, ARG_NONE, cpu_PENTIUM2 | isa_GP, "andps" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 512 | { 0, INS_AND, 0, ADDRMETH_V | OPTYPE_ps | OP_W, ADDRMETH_W | OPTYPE_ps | OP_R, ARG_NONE, cpu_PENTIUM2 | isa_GP, "andnps" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 513 | { 0, INS_OR, 0, ADDRMETH_V | OPTYPE_ps | OP_W, ADDRMETH_W | OPTYPE_ps | OP_R, ARG_NONE, cpu_PENTIUM2 | isa_GP, "orps" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 514 | { 0, INS_XOR, 0, ADDRMETH_V | OPTYPE_ps | OP_W, ADDRMETH_W | OPTYPE_ps | OP_R, ARG_NONE, cpu_PENTIUM2 | isa_GP, "xorps" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 515 | { 0, INS_ADD, 0, ADDRMETH_V | OPTYPE_ps | OP_W, ADDRMETH_W | OPTYPE_ps | OP_R, ARG_NONE, cpu_PENTIUM2 | isa_GP, "addps" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 516 | { 0, INS_MUL, 0, ADDRMETH_V | OPTYPE_ps | OP_R, ADDRMETH_W | OPTYPE_ps | OP_R, ARG_NONE, cpu_PENTIUM2 | isa_GP, "mulps" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 517 | { 0, INS_MOV, 0, ADDRMETH_V | OPTYPE_pd, ADDRMETH_W | OPTYPE_q, ARG_NONE, cpu_PENTIUM4 | isa_GP, "cvtps2pd" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 518 | { 0, INS_MOV, 0, ADDRMETH_V | OPTYPE_ps | OP_W, ADDRMETH_W | OPTYPE_dq | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "cvtdq2ps" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 519 | { 0, INS_SUB, 0, ADDRMETH_V | OPTYPE_ps | OP_W, ADDRMETH_W | OPTYPE_ps | OP_R, ARG_NONE, cpu_PENTIUM2 | isa_GP, "subps" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 520 | { 0, INS_ARITH, 0, ADDRMETH_V | OPTYPE_ps | OP_W, ADDRMETH_W | OPTYPE_ps | OP_R, ARG_NONE, cpu_PENTIUM2 | isa_GP, "minps" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 521 | { 0, INS_DIV, 0, ADDRMETH_V | OPTYPE_ps | OP_W, ADDRMETH_W | OPTYPE_ps | OP_R, ARG_NONE, cpu_PENTIUM2 | isa_GP, "divps" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 522 | { 0, INS_ARITH, 0, ADDRMETH_V | OPTYPE_ps | OP_W, ADDRMETH_W | OPTYPE_ps | OP_R, ARG_NONE, cpu_PENTIUM2 | isa_GP, "maxps" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 523 | { 0, INS_OTHER, 0, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_d | OP_R, ARG_NONE, cpu_PENTIUM | isa_MMX, "punpcklbw" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 524 | { 0, INS_OTHER, 0, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_d | OP_R, ARG_NONE, cpu_PENTIUM | isa_MMX, "punpcklwd" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 525 | { 0, INS_OTHER, 0, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_d | OP_R, ARG_NONE, cpu_PENTIUM | isa_MMX, "punpckldq" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 526 | { 0, INS_OTHER, 0, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_d | OP_R, ARG_NONE, cpu_PENTIUM | isa_MMX, "packsswb" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 527 | { 0, INS_OTHER, 0, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_d | OP_R, ARG_NONE, cpu_PENTIUM | isa_MMX, "pcmpgtb" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 528 | { 0, INS_OTHER, 0, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_d | OP_R, ARG_NONE, cpu_PENTIUM | isa_MMX, "pcmpgtw" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 529 | { 0, INS_OTHER, 0, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_d | OP_R, ARG_NONE, cpu_PENTIUM | isa_MMX, "pcmpgtd" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 530 | { 0, INS_OTHER, 0, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_d | OP_R, ARG_NONE, cpu_PENTIUM | isa_MMX, "packuswb" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 531 | { 0, INS_OTHER, 0, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_d | OP_R, ARG_NONE, cpu_PENTIUM | isa_MMX, "punpckhbw" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 532 | { 0, INS_OTHER, 0, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_d | OP_R, ARG_NONE, cpu_PENTIUM | isa_MMX, "punpckhwd" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 533 | { 0, INS_OTHER, 0, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_d | OP_R, ARG_NONE, cpu_PENTIUM | isa_MMX, "punpckhdq" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 534 | { 0, INS_OTHER, 0, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_d | OP_R, ARG_NONE, cpu_PENTIUM | isa_MMX, "packssdw" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 535 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 536 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 537 | { 0, INS_MOV, 0, ADDRMETH_P | OPTYPE_d | OP_W, ADDRMETH_E | OPTYPE_d | OP_R, ARG_NONE, cpu_PENTIUM | isa_MMX, "movd" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 538 | { 0, INS_MOV, 0, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM | isa_MMX, "movq" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 539 | { 0, INS_MOV, 0, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ADDRMETH_I | OPTYPE_b | OP_R, cpu_PENTIUM2 | isa_GP, "pshufw" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 540 | { idx_0F71, 0, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM | isa_MMX, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 541 | { idx_0F72, 0, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM | isa_MMX, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 542 | { idx_0F73, 0, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM | isa_MMX, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 543 | { 0, INS_OTHER, 0, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM | isa_MMX, "pcmpeqb" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 544 | { 0, INS_CMP, 0, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM | isa_MMX, "pcmpeqw" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 545 | { 0, INS_CMP, 0, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM | isa_MMX, "pcmpeqd" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 546 | { 0, INS_OTHER, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM | isa_MMX, "emms" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 547 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 548 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 549 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 550 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 551 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 552 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 553 | { 0, INS_MOV, 0, ADDRMETH_E | OPTYPE_d | OP_W, ADDRMETH_P | OPTYPE_d | OP_R, ARG_NONE, cpu_PENTIUM | isa_MMX, "movd" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 554 | { 0, INS_MOV, 0, ADDRMETH_Q | OPTYPE_q | OP_W, ADDRMETH_P | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM | isa_MMX, "movq" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 555 | { 0, INS_BRANCHCC, 0, ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "jo" , "" , 0, 0, 0, INS_TEST_OFLOW, 0 }, |
|---|
| 556 | { 0, INS_BRANCHCC, 0, ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "jno" , "" , 0, 0, 0, INS_TEST_NOFLOW, 0 }, |
|---|
| 557 | { 0, INS_BRANCHCC, 0, ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "jc" , "" , 0, 0, 0, INS_TEST_CARRY, 0 }, |
|---|
| 558 | { 0, INS_BRANCHCC, 0, ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "jnc" , "" , 0, 0, 0, INS_TEST_NCARRY, 0 }, |
|---|
| 559 | { 0, INS_BRANCHCC, 0, ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "jz" , "" , 0, 0, 0, INS_TEST_ZERO, 0 }, |
|---|
| 560 | { 0, INS_BRANCHCC, 0, ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "jnz" , "" , 0, 0, 0, INS_TEST_NZERO, 0 }, |
|---|
| 561 | { 0, INS_BRANCHCC, 0, ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "jbe" , "" , 0, 0, 0, INS_TEST_CARRY|INS_TEST_OR|INS_TEST_ZERO, 0 }, |
|---|
| 562 | { 0, INS_BRANCHCC, 0, ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "ja" , "" , 0, 0, 0, INS_TEST_NCARRY|INS_TEST_NZERO, 0 }, |
|---|
| 563 | { 0, INS_BRANCHCC, 0, ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "js" , "" , 0, 0, 0, INS_TEST_SIGN, 0 }, |
|---|
| 564 | { 0, INS_BRANCHCC, 0, ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "jns" , "" , 0, 0, 0, INS_TEST_NSIGN, 0 }, |
|---|
| 565 | { 0, INS_BRANCHCC, 0, ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "jpe" , "" , 0, 0, 0, INS_TEST_PARITY, 0 }, |
|---|
| 566 | { 0, INS_BRANCHCC, 0, ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "jpo" , "" , 0, 0, 0, INS_TEST_NPARITY, 0 }, |
|---|
| 567 | { 0, INS_BRANCHCC, 0, ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "jl" , "" , 0, 0, 0, INS_TEST_SFNEOF, 0 }, |
|---|
| 568 | { 0, INS_BRANCHCC, 0, ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "jge" , "" , 0, 0, 0, INS_TEST_SFEQOF, 0 }, |
|---|
| 569 | { 0, INS_BRANCHCC, 0, ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "jle" , "" , 0, 0, 0, INS_TEST_ZERO|INS_TEST_OR|INS_TEST_SFNEOF, 0 }, |
|---|
| 570 | { 0, INS_BRANCHCC, 0, ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "jg" , "" , 0, 0, 0, INS_TEST_NZERO|INS_TEST_SFEQOF, 0 }, |
|---|
| 571 | { 0, INS_MOVCC, 0, ADDRMETH_E | OPTYPE_b | OP_W, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "seto" , "" , 0, 0, 0, INS_TEST_OFLOW, 0 }, |
|---|
| 572 | { 0, INS_MOVCC, 0, ADDRMETH_E | OPTYPE_b | OP_W, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "setno" , "" , 0, 0, 0, INS_TEST_OFLOW, 0 }, |
|---|
| 573 | { 0, INS_MOVCC, 0, ADDRMETH_E | OPTYPE_b | OP_W, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "setc" , "" , 0, 0, 0, INS_TEST_CARRY, 0 }, |
|---|
| 574 | { 0, INS_MOVCC, 0, ADDRMETH_E | OPTYPE_b | OP_W, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "setnc" , "" , 0, 0, 0, INS_TEST_NCARRY, 0 }, |
|---|
| 575 | { 0, INS_MOVCC, 0, ADDRMETH_E | OPTYPE_b | OP_W, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "setz" , "" , 0, 0, 0, INS_TEST_ZERO, 0 }, |
|---|
| 576 | { 0, INS_MOVCC, 0, ADDRMETH_E | OPTYPE_b | OP_W, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "setnz" , "" , 0, 0, 0, INS_TEST_NZERO, 0 }, |
|---|
| 577 | { 0, INS_MOVCC, 0, ADDRMETH_E | OPTYPE_b | OP_W, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "setbe" , "" , 0, 0, 0, INS_TEST_CARRY|INS_TEST_OR|INS_TEST_ZERO, 0 }, |
|---|
| 578 | { 0, INS_MOVCC, 0, ADDRMETH_E | OPTYPE_b | OP_W, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "seta" , "" , 0, 0, 0, INS_TEST_NCARRY|INS_TEST_NZERO, 0 }, |
|---|
| 579 | { 0, INS_MOVCC, 0, ADDRMETH_E | OPTYPE_b | OP_W, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "sets" , "" , 0, 0, 0, INS_TEST_SIGN, 0 }, |
|---|
| 580 | { 0, INS_MOVCC, 0, ADDRMETH_E | OPTYPE_b | OP_W, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "setns" , "" , 0, 0, 0, INS_TEST_NSIGN, 0 }, |
|---|
| 581 | { 0, INS_MOVCC, 0, ADDRMETH_E | OPTYPE_b | OP_W, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "setpe" , "" , 0, 0, 0, INS_TEST_PARITY, 0 }, |
|---|
| 582 | { 0, INS_MOVCC, 0, ADDRMETH_E | OPTYPE_b | OP_W, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "setpo" , "" , 0, 0, 0, INS_TEST_NPARITY, 0 }, |
|---|
| 583 | { 0, INS_MOVCC, 0, ADDRMETH_E | OPTYPE_b | OP_W, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "setl" , "" , 0, 0, 0, INS_TEST_SFNEOF, 0 }, |
|---|
| 584 | { 0, INS_MOVCC, 0, ADDRMETH_E | OPTYPE_b | OP_W, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "setge" , "" , 0, 0, 0, INS_TEST_SFEQOF, 0 }, |
|---|
| 585 | { 0, INS_MOVCC, 0, ADDRMETH_E | OPTYPE_b | OP_W, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "setle" , "" , 0, 0, 0, INS_TEST_ZERO|INS_TEST_OR|INS_TEST_SFNEOF, 0 }, |
|---|
| 586 | { 0, INS_MOVCC, 0, ADDRMETH_E | OPTYPE_b | OP_W, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "setg" , "" , 0, 0, 0, INS_TEST_NZERO|INS_TEST_SFEQOF, 0 }, |
|---|
| 587 | { 0, INS_PUSH, 0, ADDRMETH_RS | OPTYPE_w | OP_R, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "push" , "" , 4, 0, 0, 0 , 33 }, |
|---|
| 588 | { 0, INS_POP, 0, ADDRMETH_RS | OPTYPE_w | OP_W, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "pop" , "" , 4, 0, 0, 0 , 33 }, |
|---|
| 589 | { 0, INS_CPUID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM | isa_GP, "cpuid" , "" , 0, 0, 0, 0 , 10 }, |
|---|
| 590 | { 0, INS_BITTEST, 0, ADDRMETH_E | OPTYPE_v | OP_R, ADDRMETH_G | OPTYPE_v | OP_R, ARG_NONE, cpu_80386 | isa_GP, "bt" , "" , 0, 0, 0, INS_SET_CARRY, 0 }, |
|---|
| 591 | { 0, INS_SHL, 0, ADDRMETH_E | OPTYPE_v | OP_W | OP_R, ADDRMETH_G | OPTYPE_v | OP_R, ADDRMETH_I | OPTYPE_b | OP_R, cpu_80386 | isa_GP, "shld" , "" , 0, 0, 0, INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY, 0 }, |
|---|
| 592 | //{ 0, INS_SHL, 0, ADDRMETH_E | OPTYPE_v | OP_W | OP_R, ADDRMETH_G | OPTYPE_v | OP_R, ADDRMETH_I | OP_R | OPTYPE_b | ADDRMETH_RR, cpu_80386 | isa_GP, "shld", "", 0, 0, 1, INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY, 0 }, |
|---|
| 593 | { 0, INS_SHL, 0, ADDRMETH_E | OPTYPE_v | OP_W | OP_R, ADDRMETH_G | OPTYPE_v | OP_R, ADDRMETH_RR | OP_R | OPTYPE_b, cpu_80386 | isa_GP, "shld" , "" , 0, 0, 1, INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY, 0 }, |
|---|
| 594 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 595 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 596 | { 0, INS_PUSH, 0, ADDRMETH_RS | OPTYPE_w | OP_R, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "push" , "" , 5, 0, 0, 0 , 33 }, |
|---|
| 597 | { 0, INS_POP, 0, ADDRMETH_RS | OPTYPE_w | OP_W, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "pop" , "" , 5, 0, 0, 0 , 33 }, |
|---|
| 598 | { 0, INS_SYSTEM, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "rsm" , "" , 0, 0, 0, INS_SET_ALL|INS_SET_DIR, 42 }, |
|---|
| 599 | { 0, INS_BITTEST, 0, ADDRMETH_E | OPTYPE_v | OP_R, ADDRMETH_G | OPTYPE_v | OP_R, ARG_NONE, cpu_80386 | isa_GP, "bts" , "" , 0, 0, 0, INS_SET_CARRY, 0 }, |
|---|
| 600 | { 0, INS_SHR, 0, ADDRMETH_E | OPTYPE_v | OP_W | OP_R, ADDRMETH_G | OPTYPE_v | OP_R, ADDRMETH_I | OPTYPE_b | OP_R, cpu_80386 | isa_GP, "shrd" , "" , 0, 0, 0, INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY, 0 }, |
|---|
| 601 | { 0, INS_SHR, 0, ADDRMETH_E | OPTYPE_v | OP_W | OP_R, ADDRMETH_G | OPTYPE_v | OP_R, ADDRMETH_RR | OP_R | OPTYPE_b , cpu_80386 | isa_GP, "shrd" , "" , 0, 0, 1, INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY, 0 }, |
|---|
| 602 | { idx_0FAE, 0, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM2 | isa_GP, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 603 | { 0, INS_MUL, 0, ADDRMETH_G | OPTYPE_v | OP_SIGNED | OP_R | OP_W, ADDRMETH_E | OPTYPE_v | OP_SIGNED | OP_R, ARG_NONE, cpu_80386 | isa_GP, "imul" , "" , 0, 0, 0, INS_SET_OFLOW|INS_SET_CARRY, }, |
|---|
| 604 | { 0, INS_XCHGCC, 0, ADDRMETH_E | OPTYPE_b | OP_W | OP_R, ADDRMETH_G | OPTYPE_b | OP_W, ARG_NONE, cpu_80486 | isa_GP, "cmpxchg" , "" , 0, 0, 0, INS_SET_ALL, 8 }, |
|---|
| 605 | { 0, INS_XCHGCC, 0, ADDRMETH_E | OPTYPE_v | OP_W | OP_R, ADDRMETH_G | OPTYPE_v | OP_W, ARG_NONE, cpu_80486 | isa_GP, "cmpxchg" , "" , 0, 0, 0, INS_SET_ALL, 7 }, |
|---|
| 606 | { 0, INS_MOV, 0, ADDRMETH_G | OPTYPE_v | OP_W, ADDRMETH_M | OPTYPE_p | OP_W, ARG_NONE, cpu_80386 | isa_GP, "lss" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 607 | { 0, INS_BITTEST, 0, ADDRMETH_E | OPTYPE_v | OP_R, ADDRMETH_G | OPTYPE_v | OP_R, ARG_NONE, cpu_80386 | isa_GP, "btr" , "" , 0, 0, 0, INS_SET_CARRY, 0 }, |
|---|
| 608 | { 0, INS_MOV, 0, ADDRMETH_G | OPTYPE_v | OP_W, ADDRMETH_M | OPTYPE_p | OP_W, ARG_NONE, cpu_80386 | isa_GP, "lfs" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 609 | { 0, INS_MOV, 0, ADDRMETH_G | OPTYPE_v | OP_W, ADDRMETH_M | OPTYPE_p | OP_W, ARG_NONE, cpu_80386 | isa_GP, "lgs" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 610 | { 0, INS_MOV, 0, ADDRMETH_G | OPTYPE_v | OP_W, ADDRMETH_E | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "movzx" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 611 | { 0, INS_MOV, 0, ADDRMETH_G | OPTYPE_v | OP_W, ADDRMETH_E | OPTYPE_w | OP_R, ARG_NONE, cpu_80386 | isa_GP, "movzx" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 612 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 613 | { 0, INS_UNKNOWN, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "ud1" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 614 | { idx_0FBA, 0, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 615 | { 0, INS_BITTEST, 0, ADDRMETH_E | OPTYPE_v | OP_R, ADDRMETH_G | OPTYPE_v | OP_R, ARG_NONE, cpu_80386 | isa_GP, "btc" , "" , 0, 0, 0, INS_SET_CARRY, 0 }, |
|---|
| 616 | { 0, INS_BITTEST, 0, ADDRMETH_G | OPTYPE_v | OP_R | OP_W, ADDRMETH_E | OPTYPE_v | OP_R, ARG_NONE, cpu_80386 | isa_GP, "bsf" , "" , 0, 0, 0, INS_SET_ZERO, 0 }, |
|---|
| 617 | { 0, INS_BITTEST, 0, ADDRMETH_G | OPTYPE_v | OP_R | OP_W, ADDRMETH_E | OPTYPE_v | OP_R, ARG_NONE, cpu_80386 | isa_GP, "bsr" , "" , 0, 0, 0, INS_SET_ZERO, 0 }, |
|---|
| 618 | { 0, INS_MOV, 0, ADDRMETH_G | OPTYPE_v | OP_W, ADDRMETH_E | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "movsx" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 619 | { 0, INS_MOV, 0, ADDRMETH_G | OPTYPE_v | OP_W, ADDRMETH_E | OPTYPE_w | OP_R, ARG_NONE, cpu_80386 | isa_GP, "movsx" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 620 | { 0, INS_ADD, 0, ADDRMETH_E | OPTYPE_b | OP_W | OP_R, ADDRMETH_G | OPTYPE_b | OP_W, ARG_NONE, cpu_80486 | isa_GP, "xadd" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
|---|
| 621 | { 0, INS_ADD, 0, ADDRMETH_E | OPTYPE_v | OP_W | OP_R, ADDRMETH_G | OPTYPE_v | OP_W, ARG_NONE, cpu_80486 | isa_GP, "xadd" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
|---|
| 622 | { 0, INS_CMP, 0, ADDRMETH_V | OPTYPE_ps | OP_R, ADDRMETH_W | OPTYPE_ps | OP_R, ADDRMETH_I | OPTYPE_b | OP_R, cpu_PENTIUM4 | isa_GP, "cmpps" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 623 | { 0, INS_MOV, 0, ADDRMETH_M | OPTYPE_d | OP_W, ADDRMETH_G | OPTYPE_d | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "movnti" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 624 | { 0, INS_OTHER, 0, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_E | OPTYPE_d | OP_R, ADDRMETH_I | OPTYPE_b | OP_R, cpu_PENTIUM2 | isa_GP, "pinsrw" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 625 | { 0, INS_OTHER, 0, ADDRMETH_G | OPTYPE_d | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ADDRMETH_I | OPTYPE_b | OP_R, cpu_PENTIUM2 | isa_GP, "pextrw" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 626 | { 0, INS_OTHER, 0, ADDRMETH_V | OPTYPE_ps | OP_W, ADDRMETH_W | OPTYPE_ps | OP_R, ADDRMETH_I | OPTYPE_b | OP_R, cpu_PENTIUM2 | isa_GP, "shufps" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 627 | { 0, INS_XCHGCC, 0, ADDRMETH_M | OPTYPE_q | OP_R | OP_W, ARG_NONE, ARG_NONE, cpu_PENTIUM | isa_GP, "cmpxchg8b" , "" , 0, 0, 0, 0, 9 }, |
|---|
| 628 | { 0, INS_XCHG, 0, ADDRMETH_RR | OPTYPE_d | OP_W | OP_R, ARG_NONE, ARG_NONE, cpu_80486 | isa_GP, "bswap" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 629 | { 0, INS_XCHG, 0, ADDRMETH_RR | OPTYPE_d | OP_W | OP_R, ARG_NONE, ARG_NONE, cpu_80486 | isa_GP, "bswap" , "" , 1, 0, 0, 0 , 0 }, |
|---|
| 630 | { 0, INS_XCHG, 0, ADDRMETH_RR | OPTYPE_d | OP_W | OP_R, ARG_NONE, ARG_NONE, cpu_80486 | isa_GP, "bswap" , "" , 2, 0, 0, 0 , 0 }, |
|---|
| 631 | { 0, INS_XCHG, 0, ADDRMETH_RR | OPTYPE_d | OP_W | OP_R, ARG_NONE, ARG_NONE, cpu_80486 | isa_GP, "bswap" , "" , 3, 0, 0, 0 , 0 }, |
|---|
| 632 | { 0, INS_XCHG, 0, ADDRMETH_RR | OPTYPE_d | OP_W | OP_R, ARG_NONE, ARG_NONE, cpu_80486 | isa_GP, "bswap" , "" , 4, 0, 0, 0 , 0 }, |
|---|
| 633 | { 0, INS_XCHG, 0, ADDRMETH_RR | OPTYPE_d | OP_W | OP_R, ARG_NONE, ARG_NONE, cpu_80486 | isa_GP, "bswap" , "" , 5, 0, 0, 0 , 0 }, |
|---|
| 634 | { 0, INS_XCHG, 0, ADDRMETH_RR | OPTYPE_d | OP_W | OP_R, ARG_NONE, ARG_NONE, cpu_80486 | isa_GP, "bswap" , "" , 6, 0, 0, 0 , 0 }, |
|---|
| 635 | { 0, INS_XCHG, 0, ADDRMETH_RR | OPTYPE_d | OP_W | OP_R, ARG_NONE, ARG_NONE, cpu_80486 | isa_GP, "bswap" , "" , 7, 0, 0, 0 , 0 }, |
|---|
| 636 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 637 | { 0, INS_OTHER, 0, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM | isa_MMX, "psrlw" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 638 | { 0, INS_OTHER, 0, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM | isa_MMX, "psrld" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 639 | { 0, INS_OTHER, 0, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM | isa_MMX, "psrlq" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 640 | { 0, INS_ADD, 0, ADDRMETH_P | OPTYPE_q | OP_R | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "paddq" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 641 | { 0, INS_OTHER, 0, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM | isa_MMX, "pmullw" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 642 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 643 | { 0, INS_OTHER, 0, ADDRMETH_G | OPTYPE_d | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM2 | isa_GP, "pmovmskb" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 644 | { 0, INS_OTHER, 0, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM | isa_MMX, "psubusb" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 645 | { 0, INS_OTHER, 0, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM | isa_MMX, "psubusw" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 646 | { 0, INS_OTHER, 0, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM2 | isa_GP, "pminub" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 647 | { 0, INS_AND, 0, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM | isa_MMX, "pand" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 648 | { 0, INS_ADD, 0, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM | isa_MMX, "paddusb" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 649 | { 0, INS_ADD, 0, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM | isa_MMX, "paddusw" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 650 | { 0, INS_ARITH, 0, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM2 | isa_GP, "pmaxub" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 651 | { 0, INS_AND, 0, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM | isa_MMX, "pandn" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 652 | { 0, INS_OTHER, 0, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM2 | isa_GP, "pavgb" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 653 | { 0, INS_OTHER, 0, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM | isa_MMX, "psraw" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 654 | { 0, INS_OTHER, 0, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM | isa_MMX, "psrad" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 655 | { 0, INS_OTHER, 0, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM2 | isa_GP, "pavgw" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 656 | { 0, INS_MUL, 0, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM2 | isa_GP, "pmulhuw" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 657 | { 0, INS_MUL, 0, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM | isa_MMX, "pmulhw" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 658 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 659 | { 0, INS_MOV, INS_NOTE_NOSUFFIX, ADDRMETH_W | OPTYPE_q | OP_W, ADDRMETH_V | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM2 | isa_GP, "movntq" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 660 | { 0, INS_SUB, 0, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM | isa_MMX, "psubsb" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 661 | { 0, INS_SUB, 0, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM | isa_MMX, "psubsw" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 662 | { 0, INS_ARITH, 0, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM2 | isa_GP, "pminsw" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 663 | { 0, INS_OR, 0, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM | isa_MMX, "por" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 664 | { 0, INS_ADD, 0, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM | isa_MMX, "paddsb" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 665 | { 0, INS_ADD, 0, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM | isa_MMX, "paddsw" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 666 | { 0, INS_ARITH, 0, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM2 | isa_GP, "pmaxsw" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 667 | { 0, INS_XOR, 0, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM | isa_MMX, "pxor" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 668 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 669 | { 0, INS_OTHER, 0, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM | isa_MMX, "psllw" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 670 | { 0, INS_OTHER, 0, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM | isa_MMX, "pslld" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 671 | { 0, INS_OTHER, 0, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM | isa_MMX, "psllq" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 672 | { 0, INS_MUL, 0, ADDRMETH_P | OPTYPE_q | OP_R | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "pmuludq" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 673 | { 0, INS_ADD, 0, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM | isa_MMX, "pmaddwd" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 674 | { 0, INS_OTHER, 0, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM2 | isa_GP, "psadbw" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 675 | { 0, INS_MOV, 0, ADDRMETH_P | OPTYPE_pi | OP_W, ADDRMETH_Q | OPTYPE_pi | OP_R, ARG_NONE, cpu_PENTIUM2 | isa_GP, "maskmovq" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 676 | { 0, INS_SUB, 0, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM | isa_MMX, "psubb" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 677 | { 0, INS_SUB, 0, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM | isa_MMX, "psubw" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 678 | { 0, INS_SUB, 0, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM | isa_MMX, "psubd" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 679 | { 0, INS_SUB, 0, ADDRMETH_P | OPTYPE_q | OP_R | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "psubq" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 680 | { 0, INS_ADD, 0, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM | isa_MMX, "paddb" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 681 | { 0, INS_ADD, 0, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM | isa_MMX, "paddw" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 682 | { 0, INS_ADD, 0, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM | isa_MMX, "paddd" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 683 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 } |
|---|
| 684 | }; |
|---|
| 685 | |
|---|
| 686 | |
|---|
| 687 | static ia32_insn_t tbl_660F[] = { /* SIMD 66 Two-byte Opcodes */ |
|---|
| 688 | { 0, INS_MOV, 0, ADDRMETH_V | OPTYPE_pd | OP_R, ADDRMETH_W | OPTYPE_pd | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "movupd" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 689 | { 0, INS_MOV, 0, ADDRMETH_W | OPTYPE_pd | OP_R, ADDRMETH_V | OPTYPE_pd | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "movupd" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 690 | { 0, INS_MOV, INS_NOTE_NOSUFFIX, ADDRMETH_V | OPTYPE_q | OP_R, ADDRMETH_M | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "movlpd" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 691 | { 0, INS_MOV, INS_NOTE_NOSUFFIX, ADDRMETH_M | OPTYPE_q | OP_R, ADDRMETH_V | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "movlpd" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 692 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_pd | OP_R, ADDRMETH_W | OPTYPE_pd | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "unpcklpd" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 693 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_pd | OP_R, ADDRMETH_W | OPTYPE_pd | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "unpckhpd" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 694 | { 0, INS_MOV, INS_NOTE_NOSUFFIX, ADDRMETH_V | OPTYPE_q | OP_R, ADDRMETH_M | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "movhpd" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 695 | { 0, INS_MOV, INS_NOTE_NOSUFFIX, ADDRMETH_M | OPTYPE_q | OP_R, ADDRMETH_V | OPTYPE_pd | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "movhpd" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 696 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 697 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 698 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 699 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 700 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 701 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 702 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 703 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 704 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 705 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 706 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 707 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 708 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 709 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 710 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 711 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 712 | { 0, INS_MOV, 0, ADDRMETH_V | OPTYPE_pd | OP_R, ADDRMETH_W | OPTYPE_pd | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "movapd" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 713 | { 0, INS_MOV, 0, ADDRMETH_W | OPTYPE_pd | OP_R, ADDRMETH_V | OPTYPE_pd | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "movapd" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 714 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_pd | OP_R, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "cvtpi2pd" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 715 | { 0, INS_UNKNOWN, 0, ADDRMETH_M | OPTYPE_pd | OP_R, ADDRMETH_V | OPTYPE_pd | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "movntpd" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 716 | { 0, INS_UNKNOWN, 0, ADDRMETH_P | OPTYPE_q | OP_R, ADDRMETH_W | OPTYPE_pd | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "cvttpd2pi" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 717 | { 0, INS_UNKNOWN, 0, ADDRMETH_P | OPTYPE_q | OP_R, ADDRMETH_W | OPTYPE_pd | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "cvtpd2pi" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 718 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_sd | OP_R, ADDRMETH_W | OPTYPE_sd | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "ucomisd" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 719 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_sd | OP_R, ADDRMETH_W | OPTYPE_sd | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "comisd" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 720 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 721 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 722 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 723 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 724 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 725 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 726 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 727 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 728 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 729 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 730 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 731 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 732 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 733 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 734 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 735 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 736 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 737 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 738 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 739 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 740 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 741 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 742 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 743 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 744 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 745 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 746 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 747 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 748 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 749 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 750 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 751 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 752 | { 0, INS_UNKNOWN, 0, ADDRMETH_G | OPTYPE_d | OP_R, ADDRMETH_W | OPTYPE_pd | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "movmskpd" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 753 | { 0, INS_FSQRT, 0, ADDRMETH_V | OPTYPE_pd | OP_R, ADDRMETH_W | OPTYPE_pd | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "sqrtpd" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 754 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 755 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 756 | { 0, INS_AND, 0, ADDRMETH_V | OPTYPE_pd | OP_R, ADDRMETH_W | OPTYPE_pd | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "andpd" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 757 | { 0, INS_AND, 0, ADDRMETH_V | OPTYPE_pd | OP_R, ADDRMETH_W | OPTYPE_pd | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "andnpd" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 758 | { 0, INS_OR, 0, ADDRMETH_V | OPTYPE_pd | OP_R, ADDRMETH_W | OPTYPE_pd | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "orpd" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 759 | { 0, INS_XOR, 0, ADDRMETH_V | OPTYPE_pd | OP_R, ADDRMETH_W | OPTYPE_pd | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "xorpd" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 760 | { 0, INS_ADD, 0, ADDRMETH_V | OPTYPE_pd | OP_R, ADDRMETH_W | OPTYPE_pd | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "addpd" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 761 | { 0, INS_MUL, 0, ADDRMETH_V | OPTYPE_pd | OP_R, ADDRMETH_W | OPTYPE_pd | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "mulpd" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 762 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_ps | OP_R, ADDRMETH_W | OPTYPE_pd | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "cvtpd2ps" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 763 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_dq | OP_R, ADDRMETH_W | OPTYPE_ps | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "cvtps2dq" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 764 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_pd | OP_R, ADDRMETH_W | OPTYPE_pd | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "subpd" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 765 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_pd | OP_R, ADDRMETH_W | OPTYPE_pd | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "minpd" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 766 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_pd | OP_R, ADDRMETH_W | OPTYPE_pd | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "divpd" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 767 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_pd | OP_R, ADDRMETH_W | OPTYPE_pd | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "maxpd" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 768 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_dq | OP_R, ADDRMETH_W | OPTYPE_dq | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "punpcklbw" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 769 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_dq | OP_R, ADDRMETH_W | OPTYPE_dq | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "punpcklwd" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 770 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_dq | OP_R, ADDRMETH_W | OPTYPE_dq | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "punpckldq" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 771 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_dq | OP_R, ADDRMETH_W | OPTYPE_dq | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "packsswb" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 772 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_dq | OP_R, ADDRMETH_W | OPTYPE_dq | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "pcmpgtb" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 773 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_dq | OP_R, ADDRMETH_W | OPTYPE_dq | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "pcmpgtw" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 774 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_dq | OP_R, ADDRMETH_W | OPTYPE_dq | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "pcmpgtd" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 775 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_dq | OP_R, ADDRMETH_W | OPTYPE_dq | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "packuswb" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 776 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_dq | OP_R, ADDRMETH_W | OPTYPE_dq | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "punpckhbw" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 777 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_dq | OP_R, ADDRMETH_W | OPTYPE_dq | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "punpckhwd" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 778 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_dq | OP_R, ADDRMETH_W | OPTYPE_dq | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "punpckhdq" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 779 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_dq | OP_R, ADDRMETH_W | OPTYPE_dq | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "packssdw" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 780 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_dq | OP_R, ADDRMETH_W | OPTYPE_dq | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "punpcklqdq" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 781 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_dq | OP_R, ADDRMETH_W | OPTYPE_dq | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "punpckhqdq" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 782 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_d | OP_R, ADDRMETH_E | OPTYPE_d | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "movd" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 783 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_dq | OP_R, ADDRMETH_W | OPTYPE_dq | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "movdqa" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 784 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_dq | OP_R, ADDRMETH_W | OPTYPE_dq | OP_R, ADDRMETH_I | OPTYPE_b | OP_R, cpu_PENTIUM4 | isa_GP, "pshufd" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 785 | { idx_660F71, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 786 | { idx_660F72, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 787 | { idx_660F73, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 788 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_dq | OP_R, ADDRMETH_W | OPTYPE_dq | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "pcmpeqb" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 789 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_dq | OP_R, ADDRMETH_W | OPTYPE_dq | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "pcmpeqw" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 790 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_dq | OP_R, ADDRMETH_W | OPTYPE_dq | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "pcmpeqd" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 791 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 792 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 793 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 794 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 795 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 796 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_pd | OP_R, ADDRMETH_W | OPTYPE_pd | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "haddpd" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 797 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_pd | OP_R, ADDRMETH_W | OPTYPE_pd | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "hsubpd" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 798 | { 0, INS_UNKNOWN, 0, ADDRMETH_E | OPTYPE_d | OP_R, ADDRMETH_V | OPTYPE_d | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "movd" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 799 | { 0, INS_UNKNOWN, 0, ADDRMETH_W | OPTYPE_dq | OP_R, ADDRMETH_V | OPTYPE_dq | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "movdqa" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 800 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 801 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 802 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 803 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 804 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 805 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 806 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 807 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 808 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 809 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 810 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 811 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 812 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 813 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 814 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 815 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 816 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 817 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 818 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 819 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 820 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 821 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 822 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 823 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 824 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 825 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 826 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 827 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 828 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 829 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 830 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 831 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 832 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 833 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 834 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 835 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 836 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 837 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 838 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 839 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 840 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 841 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 842 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 843 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 844 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 845 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 846 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 847 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 848 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 849 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 850 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 851 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 852 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 853 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 854 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 855 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 856 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 857 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 858 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 859 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 860 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 861 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 862 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 863 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 864 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 865 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 866 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_pd | OP_R, ADDRMETH_W | OPTYPE_pd | OP_R, ADDRMETH_I | OPTYPE_b | OP_R, cpu_PENTIUM4 | isa_GP, "cmppd" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 867 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 868 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_w | OP_R, ADDRMETH_E | OPTYPE_d | OP_R, ADDRMETH_I | OPTYPE_b | OP_R, cpu_PENTIUM4 | isa_GP, "pinsrw" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 869 | { 0, INS_UNKNOWN, 0, ADDRMETH_G | OPTYPE_d | OP_R, ADDRMETH_W | OPTYPE_w | OP_R, ADDRMETH_I | OPTYPE_b | OP_R, cpu_PENTIUM4 | isa_GP, "pextrw" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 870 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_pd | OP_R, ADDRMETH_W | OPTYPE_pd | OP_R, ADDRMETH_I | OPTYPE_b | OP_R, cpu_PENTIUM4 | isa_GP, "shufpd" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 871 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 872 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 873 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 874 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 875 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 876 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 877 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 878 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 879 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 880 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_pd | OP_R, ADDRMETH_W | OPTYPE_pd | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "addsubpd" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 881 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_dq | OP_R, ADDRMETH_W | OPTYPE_dq | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "psrlw" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 882 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_dq | OP_R, ADDRMETH_W | OPTYPE_dq | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "psrld" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 883 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_dq | OP_R, ADDRMETH_W | OPTYPE_dq | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "psrlq" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 884 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_dq | OP_R, ADDRMETH_W | OPTYPE_dq | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "paddq" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 885 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_dq | OP_R, ADDRMETH_W | OPTYPE_dq | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "pmullw" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 886 | { 0, INS_UNKNOWN, 0, ADDRMETH_W | OPTYPE_q | OP_R, ADDRMETH_V | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "movq" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 887 | { 0, INS_UNKNOWN, 0, ADDRMETH_G | OPTYPE_d | OP_R, ADDRMETH_W | OPTYPE_dq | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "pmovmskb" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 888 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_dq | OP_R, ADDRMETH_W | OPTYPE_dq | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "psubusb" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 889 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_dq | OP_R, ADDRMETH_W | OPTYPE_dq | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "psubusw" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 890 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_dq | OP_R, ADDRMETH_W | OPTYPE_dq | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "pminub" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 891 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_dq | OP_R, ADDRMETH_W | OPTYPE_dq | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "pand" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 892 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_dq | OP_R, ADDRMETH_W | OPTYPE_dq | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "paddusb" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 893 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_dq | OP_R, ADDRMETH_W | OPTYPE_dq | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "paddusw" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 894 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_dq | OP_R, ADDRMETH_W | OPTYPE_dq | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "pmaxub" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 895 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_dq | OP_R, ADDRMETH_W | OPTYPE_dq | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "pandn" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 896 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_dq | OP_R, ADDRMETH_W | OPTYPE_dq | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "pavgb" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 897 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_dq | OP_R, ADDRMETH_W | OPTYPE_dq | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "psraw" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 898 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_dq | OP_R, ADDRMETH_W | OPTYPE_dq | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "psrad" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 899 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_dq | OP_R, ADDRMETH_W | OPTYPE_dq | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "pavgw" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 900 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_dq | OP_R, ADDRMETH_W | OPTYPE_dq | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "pmulhuw" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 901 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_dq | OP_R, ADDRMETH_W | OPTYPE_dq | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "pmulhw" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 902 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_dq | OP_R, ADDRMETH_W | OPTYPE_pd | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "cvttpd2dq" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 903 | { 0, INS_UNKNOWN, 0, ADDRMETH_M | OPTYPE_dq | OP_R, ADDRMETH_V | OPTYPE_dq | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "movntdq" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 904 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_dq | OP_R, ADDRMETH_W | OPTYPE_dq | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "psubsb" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 905 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_dq | OP_R, ADDRMETH_W | OPTYPE_dq | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "psubsw" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 906 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_dq | OP_R, ADDRMETH_W | OPTYPE_dq | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "pminsw" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 907 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_dq | OP_R, ADDRMETH_W | OPTYPE_dq | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "por" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 908 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_dq | OP_R, ADDRMETH_W | OPTYPE_dq | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "paddsb" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 909 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_dq | OP_R, ADDRMETH_W | OPTYPE_dq | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "paddsw" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 910 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_dq | OP_R, ADDRMETH_W | OPTYPE_dq | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "pmaxsw" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 911 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_dq | OP_R, ADDRMETH_W | OPTYPE_dq | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "pxor" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 912 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 913 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_dq | OP_R, ADDRMETH_W | OPTYPE_dq | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "psllw" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 914 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_dq | OP_R, ADDRMETH_W | OPTYPE_dq | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "pslld" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 915 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_dq | OP_R, ADDRMETH_W | OPTYPE_dq | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "psllq" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 916 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_dq | OP_R, ADDRMETH_W | OPTYPE_dq | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "pmuludq" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 917 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_dq | OP_R, ADDRMETH_W | OPTYPE_dq | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "pmaddwd" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 918 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_dq | OP_R, ADDRMETH_W | OPTYPE_dq | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "psadbw" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 919 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_dq | OP_R, ADDRMETH_W | OPTYPE_dq | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "maskmovdqu" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 920 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_dq | OP_R, ADDRMETH_W | OPTYPE_dq | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "psubb" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 921 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_dq | OP_R, ADDRMETH_W | OPTYPE_dq | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "psubw" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 922 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_dq | OP_R, ADDRMETH_W | OPTYPE_dq | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "psubd" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 923 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_dq | OP_R, ADDRMETH_W | OPTYPE_dq | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "psubq" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 924 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_dq | OP_R, ADDRMETH_W | OPTYPE_dq | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "paddb" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 925 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_dq | OP_R, ADDRMETH_W | OPTYPE_dq | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "paddw" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 926 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_dq | OP_R, ADDRMETH_W | OPTYPE_dq | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "paddd" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 927 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 } |
|---|
| 928 | }; |
|---|
| 929 | |
|---|
| 930 | |
|---|
| 931 | static ia32_insn_t tbl_F20F[] = { /* SIMD F2 Two-byte Opcodes */ |
|---|
| 932 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_sd | OP_R, ADDRMETH_W | OPTYPE_sd | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "movsd" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 933 | { 0, INS_UNKNOWN, 0, ADDRMETH_W | OPTYPE_sd | OP_R, ADDRMETH_V | OPTYPE_sd | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "movsd" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 934 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_q | OP_R, ADDRMETH_W | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "movddup" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 935 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 936 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 937 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 938 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 939 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 940 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 941 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 942 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 943 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 944 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 945 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 946 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 947 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 948 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 949 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 950 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 951 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 952 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 953 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 954 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 955 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 956 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 957 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 958 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_sd | OP_R, ADDRMETH_E | OPTYPE_d | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "cvtsi2sd" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 959 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 960 | { 0, INS_UNKNOWN, 0, ADDRMETH_G | OPTYPE_d | OP_R, ADDRMETH_W | OPTYPE_sd | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "cvttsd2si" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 961 | { 0, INS_UNKNOWN, 0, ADDRMETH_G | OPTYPE_d | OP_R, ADDRMETH_W | OPTYPE_sd | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "cvtsd2si" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 962 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 963 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 964 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 965 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 966 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 967 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 968 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 969 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 970 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 971 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 972 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 973 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 974 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 975 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 976 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 977 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 978 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 979 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 980 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 981 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 982 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 983 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 984 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 985 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 986 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 987 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 988 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 989 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 990 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 991 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 992 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 993 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 994 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 995 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 996 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 997 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_sd | OP_R, ADDRMETH_W | OPTYPE_sd | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "sqrtsd" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 998 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 999 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1000 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1001 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1002 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1003 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1004 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_sd | OP_R, ADDRMETH_W | OPTYPE_sd | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "addsd" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1005 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_sd | OP_R, ADDRMETH_W | OPTYPE_sd | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "mulsd" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1006 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_ss | OP_R, ADDRMETH_W | OPTYPE_sd | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "cvtsd2ss" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1007 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1008 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_sd | OP_R, ADDRMETH_W | OPTYPE_sd | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "subsd" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1009 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_sd | OP_R, ADDRMETH_W | OPTYPE_sd | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "minsd" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1010 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_sd | OP_R, ADDRMETH_W | OPTYPE_sd | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "divsd" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1011 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_sd | OP_R, ADDRMETH_W | OPTYPE_sd | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "maxsd" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1012 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1013 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1014 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1015 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1016 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1017 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1018 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1019 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1020 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1021 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1022 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1023 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1024 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1025 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1026 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1027 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1028 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_dq | OP_R, ADDRMETH_W | OPTYPE_dq | OP_R, ADDRMETH_I | OPTYPE_b | OP_R, cpu_PENTIUM4 | isa_GP, "pshuflw" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1029 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1030 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1031 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1032 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1033 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1034 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1035 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1036 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1037 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1038 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1039 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1040 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_ps | OP_R, ADDRMETH_W | OPTYPE_ps | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "haddps" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1041 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_ps | OP_R, ADDRMETH_W | OPTYPE_ps | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "hsubps" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1042 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1043 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1044 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1045 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1046 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1047 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1048 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1049 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1050 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1051 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1052 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1053 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1054 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1055 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1056 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1057 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1058 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1059 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1060 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1061 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1062 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1063 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1064 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1065 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1066 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1067 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1068 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1069 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1070 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1071 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1072 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1073 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1074 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1075 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1076 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1077 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1078 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1079 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1080 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1081 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1082 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1083 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1084 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1085 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1086 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1087 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1088 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1089 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1090 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1091 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1092 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1093 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1094 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1095 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1096 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1097 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1098 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1099 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1100 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1101 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1102 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1103 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1104 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1105 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1106 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1107 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1108 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1109 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1110 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_sd | OP_R, ADDRMETH_W | OPTYPE_sd | OP_R, ADDRMETH_I | OPTYPE_b | OP_R, cpu_PENTIUM4 | isa_GP, "cmpsd" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1111 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1112 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1113 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1114 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1115 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1116 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1117 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1118 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1119 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1120 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1121 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1122 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1123 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1124 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_ps | OP_R, ADDRMETH_W | OPTYPE_ps | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "addsubps" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1125 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1126 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1127 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1128 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1129 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1130 | { 0, INS_UNKNOWN, 0, ADDRMETH_P | OPTYPE_q | OP_R, ADDRMETH_W | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "movdq2q" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1131 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1132 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1133 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1134 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1135 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1136 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1137 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1138 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1139 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1140 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1141 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1142 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1143 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1144 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1145 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1146 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_dq | OP_R, ADDRMETH_W | OPTYPE_pd | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "cvtpd2dq" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1147 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1148 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1149 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1150 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1151 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1152 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1153 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1154 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1155 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1156 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_dq | OP_R, ADDRMETH_M | OPTYPE_dq | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "lddqu" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1157 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1158 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1159 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1160 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1161 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1162 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1163 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1164 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1165 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1166 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1167 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1168 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1169 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1170 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1171 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 } |
|---|
| 1172 | }; |
|---|
| 1173 | |
|---|
| 1174 | |
|---|
| 1175 | static ia32_insn_t tbl_F30F[] = { /* SIMD F3 Two-byte Opcodes */ |
|---|
| 1176 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_ss | OP_R, ADDRMETH_W | OPTYPE_ss | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "movss" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1177 | { 0, INS_UNKNOWN, 0, ADDRMETH_W | OPTYPE_ss | OP_R, ADDRMETH_V | OPTYPE_ss | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "movss" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1178 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_ps | OP_R, ADDRMETH_W | OPTYPE_ps | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "movsldup" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1179 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1180 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1181 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1182 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_ps | OP_R, ADDRMETH_W | OPTYPE_ps | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "movshdup" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1183 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1184 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1185 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1186 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1187 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1188 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1189 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1190 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1191 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1192 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1193 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1194 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1195 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1196 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1197 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1198 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1199 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1200 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1201 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1202 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_ss | OP_R, ADDRMETH_E | OPTYPE_d | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "cvtsi2ss" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1203 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1204 | { 0, INS_UNKNOWN, 0, ADDRMETH_G | OPTYPE_d | OP_R, ADDRMETH_W | OPTYPE_ss | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "cvttss2si" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1205 | { 0, INS_UNKNOWN, 0, ADDRMETH_G | OPTYPE_d | OP_R, ADDRMETH_W | OPTYPE_ss | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "cvtss2si" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1206 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1207 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1208 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1209 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1210 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1211 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1212 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1213 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1214 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1215 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1216 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1217 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1218 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1219 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1220 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1221 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1222 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1223 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1224 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1225 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1226 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1227 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1228 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1229 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1230 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1231 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1232 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1233 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1234 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1235 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1236 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1237 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1238 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1239 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1240 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1241 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_ss | OP_R, ADDRMETH_W | OPTYPE_ss | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "sqrtss" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1242 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_ss | OP_R, ADDRMETH_W | OPTYPE_ss | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "rsqrtss" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1243 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_ss | OP_R, ADDRMETH_W | OPTYPE_ss | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "rcpss" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1244 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1245 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1246 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1247 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1248 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_ss | OP_R, ADDRMETH_W | OPTYPE_ss | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "addss" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1249 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_ss | OP_R, ADDRMETH_W | OPTYPE_ss | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "mulss" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1250 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_sd | OP_R, ADDRMETH_W | OPTYPE_ss | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "cvtss2sd" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1251 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_dq | OP_R, ADDRMETH_W | OPTYPE_ps | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "cvttps2dq" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1252 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_ss | OP_R, ADDRMETH_W | OPTYPE_ss | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "subss" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1253 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_ss | OP_R, ADDRMETH_W | OPTYPE_ss | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "minss" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1254 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_ss | OP_R, ADDRMETH_W | OPTYPE_ss | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "divss" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1255 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_ss | OP_R, ADDRMETH_W | OPTYPE_ss | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "maxss" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1256 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1257 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1258 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1259 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1260 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1261 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1262 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1263 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1264 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1265 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1266 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1267 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1268 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1269 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1270 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1271 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_dq | OP_R, ADDRMETH_W | OPTYPE_dq | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "movdqu" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1272 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_dq | OP_R, ADDRMETH_W | OPTYPE_dq | OP_R, ADDRMETH_I | OPTYPE_b | OP_R, cpu_PENTIUM4 | isa_GP, "pshufhw" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1273 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1274 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1275 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1276 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1277 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1278 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1279 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1280 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1281 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1282 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1283 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1284 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1285 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1286 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_q | OP_R, ADDRMETH_W | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "movq" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1287 | { 0, INS_UNKNOWN, 0, ADDRMETH_W | OPTYPE_dq | OP_R, ADDRMETH_V | OPTYPE_dq | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "movdqu" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1288 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1289 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1290 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1291 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1292 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1293 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1294 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1295 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1296 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1297 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1298 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1299 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1300 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1301 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1302 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1303 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1304 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1305 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1306 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1307 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1308 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1309 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1310 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1311 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1312 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1313 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1314 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1315 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1316 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1317 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1318 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1319 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1320 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1321 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1322 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1323 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1324 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1325 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1326 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1327 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1328 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1329 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1330 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1331 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1332 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1333 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1334 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1335 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1336 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1337 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1338 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1339 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1340 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1341 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1342 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1343 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1344 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1345 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1346 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1347 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1348 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1349 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1350 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1351 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1352 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1353 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1354 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_ss | OP_R, ADDRMETH_W | OPTYPE_ss | OP_R, ADDRMETH_I | OPTYPE_b | OP_R, cpu_PENTIUM4 | isa_GP, "cmpss" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1355 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1356 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1357 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1358 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1359 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1360 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1361 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1362 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1363 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1364 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1365 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1366 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1367 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1368 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1369 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1370 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1371 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1372 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1373 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1374 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_dq | OP_R, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "movq2dq" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1375 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1376 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1377 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1378 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1379 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1380 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1381 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1382 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1383 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1384 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1385 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1386 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1387 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1388 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1389 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1390 | { 0, INS_UNKNOWN, 0, ADDRMETH_V | OPTYPE_pd | OP_R, ADDRMETH_W | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM4 | isa_GP, "cvtdq2pd" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1391 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1392 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1393 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1394 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1395 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1396 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1397 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1398 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1399 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1400 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1401 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1402 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1403 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1404 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1405 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1406 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1407 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1408 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1409 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1410 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1411 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1412 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1413 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1414 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1415 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "" , "" , 0, 0, 0, 0, 0 } |
|---|
| 1416 | }; |
|---|
| 1417 | |
|---|
| 1418 | |
|---|
| 1419 | static ia32_insn_t tbl_0F00[] = { /* Group 6 */ |
|---|
| 1420 | { 0, INS_SYSTEM, 0, ADDRMETH_E | OPTYPE_w | OP_R, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "sldt" , "" , 0, 0, 0, 0 , 46 }, |
|---|
| 1421 | { 0, INS_SYSTEM, 0, ADDRMETH_E | OPTYPE_w | OP_W, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "str" , "" , 0, 0, 0, 0 , 49 }, |
|---|
| 1422 | { 0, INS_SYSTEM, 0, ADDRMETH_E | OPTYPE_w | OP_W, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "lldt" , "" , 0, 0, 0, 0 , 29 }, |
|---|
| 1423 | { 0, INS_SYSTEM, 0, ADDRMETH_E | OPTYPE_w | OP_W, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "ltr" , "" , 0, 0, 0, 0 , 32 }, |
|---|
| 1424 | { 0, INS_SYSTEM, 0, ADDRMETH_E | OPTYPE_w | OP_R, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "verr" , "" , 0, 0, 0, INS_SET_ZERO, 0 }, |
|---|
| 1425 | { 0, INS_SYSTEM, 0, ADDRMETH_E | OPTYPE_w | OP_R, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "verw" , "" , 0, 0, 0, INS_SET_ZERO, 0 }, |
|---|
| 1426 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1427 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 } |
|---|
| 1428 | }; |
|---|
| 1429 | |
|---|
| 1430 | |
|---|
| 1431 | static ia32_insn_t tbl_0F01[] = { /* Group 7 */ |
|---|
| 1432 | { 0, INS_SYSTEM, 0, ADDRMETH_M | OPTYPE_s | OP_R, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "sgdt" , "" , 0, 0, 0, 0 , 44 }, |
|---|
| 1433 | { 0, INS_SYSTEM, 0, ADDRMETH_M | OPTYPE_s | OP_R, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "sidt" , "" , 0, 0, 0, 0 , 45 }, |
|---|
| 1434 | { 0, INS_SYSTEM, 0, ADDRMETH_M | OPTYPE_s | OP_W, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "lgdt" , "" , 0, 0, 0, 0 , 27 }, |
|---|
| 1435 | { 0, INS_SYSTEM, 0, ADDRMETH_M | OPTYPE_s | OP_W, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "lidt" , "" , 0, 0, 0, 0 , 28 }, |
|---|
| 1436 | { 0, INS_SYSTEM, 0, ADDRMETH_E | OPTYPE_w | OP_W, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "smsw" , "" , 0, 0, 0, 0 , 47 }, |
|---|
| 1437 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1438 | { 0, INS_SYSTEM, 0, ADDRMETH_E | OPTYPE_w | OP_W, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "lmsw" , "" , 0, 0, 0, 0 , 30 }, |
|---|
| 1439 | { 0, INS_SYSTEM, 0, ADDRMETH_M | OPTYPE_none | OP_R, ARG_NONE, ARG_NONE, cpu_80486 | isa_GP, "invlpg" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1440 | { 0, INS_SYSTEM, 0, ADDRMETH_M | OPTYPE_s | OP_R, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "sgdt" , "" , 0, 0, 0, 0 , 44 }, |
|---|
| 1441 | { 0, INS_SYSTEM, 0, ADDRMETH_M | OPTYPE_s | OP_R, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "sidt" , "" , 0, 0, 0, 0 , 45 }, |
|---|
| 1442 | { 0, INS_SYSTEM, 0, ADDRMETH_M | OPTYPE_s | OP_W, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "lgdt" , "" , 0, 0, 0, 0 , 27 }, |
|---|
| 1443 | { 0, INS_SYSTEM, 0, ADDRMETH_M | OPTYPE_s | OP_W, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "lidt" , "" , 0, 0, 0, 0 , 28 }, |
|---|
| 1444 | { 0, INS_SYSTEM, 0, ADDRMETH_E | OPTYPE_w | OP_W, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "smsw" , "" , 0, 0, 0, 0 , 47 }, |
|---|
| 1445 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1446 | { 0, INS_SYSTEM, 0, ADDRMETH_E | OPTYPE_w | OP_W, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "lmsw" , "" , 0, 0, 0, 0 , 30 }, |
|---|
| 1447 | { 0, INS_SYSTEM, 0, ADDRMETH_M | OPTYPE_none | OP_R, ARG_NONE, ARG_NONE, cpu_80486 | isa_GP, "invlpg" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1448 | { 0, INS_SYSTEM, 0, ADDRMETH_M | OPTYPE_s | OP_R, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "sgdt" , "" , 0, 0, 0, 0 , 44 }, |
|---|
| 1449 | { 0, INS_SYSTEM, 0, ADDRMETH_M | OPTYPE_s | OP_R, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "sidt" , "" , 0, 0, 0, 0 , 45 }, |
|---|
| 1450 | { 0, INS_SYSTEM, 0, ADDRMETH_M | OPTYPE_s | OP_W, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "lgdt" , "" , 0, 0, 0, 0 , 27 }, |
|---|
| 1451 | { 0, INS_SYSTEM, 0, ADDRMETH_M | OPTYPE_s | OP_W, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "lidt" , "" , 0, 0, 0, 0 , 28 }, |
|---|
| 1452 | { 0, INS_SYSTEM, 0, ADDRMETH_E | OPTYPE_w | OP_W, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "smsw" , "" , 0, 0, 0, 0 , 47 }, |
|---|
| 1453 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1454 | { 0, INS_SYSTEM, 0, ADDRMETH_E | OPTYPE_w | OP_W, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "lmsw" , "" , 0, 0, 0, 0 , 30 }, |
|---|
| 1455 | { 0, INS_SYSTEM, 0, ADDRMETH_M | OPTYPE_none | OP_R, ARG_NONE, ARG_NONE, cpu_80486 | isa_GP, "invlpg" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1456 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1457 | { idx_0F0111, 0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1458 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1459 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1460 | { 0, INS_SYSTEM, 0, ADDRMETH_E | OPTYPE_w | OP_W, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "smsw" , "" , 0, 0, 0, 0 , 47 }, |
|---|
| 1461 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1462 | { 0, INS_SYSTEM, 0, ADDRMETH_E | OPTYPE_w | OP_W, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "lmsw" , "" , 0, 0, 0, 0 , 30 }, |
|---|
| 1463 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 } |
|---|
| 1464 | }; |
|---|
| 1465 | |
|---|
| 1466 | |
|---|
| 1467 | static ia32_insn_t tbl_0F0111[] = { /* Monitor/MWait opcode */ |
|---|
| 1468 | { 0, INS_SYSTEM, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "monitor" , "" , 0, 0, 0, 0, 54 }, |
|---|
| 1469 | { 0, INS_SYSTEM, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "mwait" , "" , 0, 0, 0, 0, 55 } |
|---|
| 1470 | }; |
|---|
| 1471 | |
|---|
| 1472 | |
|---|
| 1473 | static ia32_insn_t tbl_0F12[] = { /* Movlps Opcode */ |
|---|
| 1474 | { 0, INS_MOV, INS_NOTE_NOSUFFIX, ADDRMETH_V | OPTYPE_q | OP_W, ADDRMETH_M | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM2 | isa_GP, "movlps" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1475 | { 0, INS_MOV, INS_NOTE_NOSUFFIX, ADDRMETH_V | OPTYPE_q | OP_W, ADDRMETH_M | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM2 | isa_GP, "movlps" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1476 | { 0, INS_MOV, INS_NOTE_NOSUFFIX, ADDRMETH_V | OPTYPE_q | OP_W, ADDRMETH_M | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM2 | isa_GP, "movlps" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1477 | { 0, INS_MOV, 0, ADDRMETH_V | OPTYPE_ps | OP_R | OP_W, ADDRMETH_W | OPTYPE_ps | OP_R , ARG_NONE, cpu_PENTIUM4 | isa_GP, "movhlps" , "" , 0, 0, 0, 0, 0 } |
|---|
| 1478 | }; |
|---|
| 1479 | |
|---|
| 1480 | |
|---|
| 1481 | static ia32_insn_t tbl_0F16[] = { /* Movhps Opcode */ |
|---|
| 1482 | { 0, INS_OTHER, 0, ADDRMETH_V | OPTYPE_q | OP_W, ADDRMETH_M | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM2 | isa_GP, "movhps" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1483 | { 0, INS_OTHER, 0, ADDRMETH_V | OPTYPE_q | OP_W, ADDRMETH_M | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM2 | isa_GP, "movhps" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1484 | { 0, INS_OTHER, 0, ADDRMETH_V | OPTYPE_q | OP_W, ADDRMETH_M | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM2 | isa_GP, "movhps" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1485 | { 0, INS_MOV, 0, ADDRMETH_V | OPTYPE_ps | OP_R | OP_W, ADDRMETH_W | OPTYPE_ps | OP_R , ARG_NONE, cpu_PENTIUM4 | isa_GP, "movlhps" , "" , 0, 0, 0, 0, 0 } |
|---|
| 1486 | }; |
|---|
| 1487 | |
|---|
| 1488 | |
|---|
| 1489 | static ia32_insn_t tbl_0F18[] = { /* Group 16 */ |
|---|
| 1490 | { 0, INS_SYSTEM, 0, OP_W | OPTYPE_b | ADDRMETH_M, ARG_NONE, ARG_NONE, cpu_PENTIUM2 | isa_GP, "prefetchnta" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1491 | { 0, INS_SYSTEM, 0, ADDRMETH_RT | OPTYPE_d | OP_W, ARG_NONE, ARG_NONE, cpu_PENTIUM2 | isa_GP, "prefetcht0" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1492 | { 0, INS_SYSTEM, 0, ADDRMETH_RT | OPTYPE_d | OP_W, ARG_NONE, ARG_NONE, cpu_PENTIUM2 | isa_GP, "prefetcht1" , "" , 1, 0, 0, 0 , 0 }, |
|---|
| 1493 | { 0, INS_SYSTEM, 0, ADDRMETH_RT | OPTYPE_d | OP_W, ARG_NONE, ARG_NONE, cpu_PENTIUM2 | isa_GP, "prefetcht2" , "" , 2, 0, 0, 0 , 0 }, |
|---|
| 1494 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1495 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1496 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1497 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1498 | { 0, INS_SYSTEM, 0, OP_W | OPTYPE_b | ADDRMETH_M, ARG_NONE, ARG_NONE, cpu_PENTIUM2 | isa_GP, "prefetchnta" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1499 | { 0, INS_SYSTEM, 0, ADDRMETH_RT | OPTYPE_d | OP_W, ARG_NONE, ARG_NONE, cpu_PENTIUM2 | isa_GP, "prefetcht0" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1500 | { 0, INS_SYSTEM, 0, ADDRMETH_RT | OPTYPE_d | OP_W, ARG_NONE, ARG_NONE, cpu_PENTIUM2 | isa_GP, "prefetcht1" , "" , 1, 0, 0, 0 , 0 }, |
|---|
| 1501 | { 0, INS_SYSTEM, 0, ADDRMETH_RT | OPTYPE_d | OP_W, ARG_NONE, ARG_NONE, cpu_PENTIUM2 | isa_GP, "prefetcht2" , "" , 2, 0, 0, 0 , 0 }, |
|---|
| 1502 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1503 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1504 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1505 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1506 | { 0, INS_SYSTEM, 0, OP_W | OPTYPE_b | ADDRMETH_M, ARG_NONE, ARG_NONE, cpu_PENTIUM2 | isa_GP, "prefetchnta" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1507 | { 0, INS_SYSTEM, 0, ADDRMETH_RT | OPTYPE_d | OP_W, ARG_NONE, ARG_NONE, cpu_PENTIUM2 | isa_GP, "prefetcht0" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1508 | { 0, INS_SYSTEM, 0, ADDRMETH_RT | OPTYPE_d | OP_W, ARG_NONE, ARG_NONE, cpu_PENTIUM2 | isa_GP, "prefetcht1" , "" , 1, 0, 0, 0 , 0 }, |
|---|
| 1509 | { 0, INS_SYSTEM, 0, ADDRMETH_RT | OPTYPE_d | OP_W, ARG_NONE, ARG_NONE, cpu_PENTIUM2 | isa_GP, "prefetcht2" , "" , 2, 0, 0, 0 , 0 } |
|---|
| 1510 | }; |
|---|
| 1511 | |
|---|
| 1512 | |
|---|
| 1513 | static ia32_insn_t tbl_0F71[] = { /* Group 12 */ |
|---|
| 1514 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1515 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1516 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1517 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1518 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1519 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1520 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1521 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1522 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1523 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1524 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1525 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1526 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1527 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1528 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1529 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1530 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1531 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1532 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1533 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1534 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1535 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1536 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1537 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1538 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1539 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1540 | { 0, INS_OTHER, 0, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_PENTIUM | isa_MMX, "psrlw" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1541 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1542 | { 0, INS_OTHER, 0, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_PENTIUM | isa_MMX, "psraw" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1543 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1544 | { 0, INS_OTHER, 0, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_PENTIUM | isa_MMX, "psllw" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1545 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 } |
|---|
| 1546 | }; |
|---|
| 1547 | |
|---|
| 1548 | |
|---|
| 1549 | static ia32_insn_t tbl_660F71[] = { /* Group 12 SSE */ |
|---|
| 1550 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1551 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1552 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1553 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1554 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1555 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1556 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1557 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1558 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1559 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1560 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1561 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1562 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1563 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1564 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1565 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1566 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1567 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1568 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1569 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1570 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1571 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1572 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1573 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1574 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1575 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1576 | { 0, INS_OTHER, 0, ADDRMETH_P | OPTYPE_dq | OP_W, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_PENTIUM | isa_MMX, "psrlw" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1577 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1578 | { 0, INS_OTHER, 0, ADDRMETH_P | OPTYPE_dq | OP_W, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_PENTIUM | isa_MMX, "psraw" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1579 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1580 | { 0, INS_OTHER, 0, ADDRMETH_P | OPTYPE_dq | OP_W, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_PENTIUM | isa_MMX, "psllw" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1581 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 } |
|---|
| 1582 | }; |
|---|
| 1583 | |
|---|
| 1584 | |
|---|
| 1585 | static ia32_insn_t tbl_0F72[] = { /* Group 13 */ |
|---|
| 1586 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1587 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1588 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1589 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1590 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1591 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1592 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1593 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1594 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1595 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1596 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1597 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1598 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1599 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1600 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1601 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1602 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1603 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1604 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1605 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1606 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1607 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1608 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1609 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1610 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1611 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1612 | { 0, INS_OTHER, 0, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_PENTIUM | isa_MMX, "psrld" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1613 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1614 | { 0, INS_OTHER, 0, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_PENTIUM | isa_MMX, "psrad" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1615 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1616 | { 0, INS_OTHER, 0, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_PENTIUM | isa_MMX, "pslld" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1617 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 } |
|---|
| 1618 | }; |
|---|
| 1619 | |
|---|
| 1620 | |
|---|
| 1621 | static ia32_insn_t tbl_660F72[] = { /* Group 13 SSE */ |
|---|
| 1622 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1623 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1624 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1625 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1626 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1627 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1628 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1629 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1630 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1631 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1632 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1633 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1634 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1635 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1636 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1637 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1638 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1639 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1640 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1641 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1642 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1643 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1644 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1645 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1646 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1647 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1648 | { 0, INS_OTHER, 0, ADDRMETH_W | OPTYPE_dq | OP_W, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_PENTIUM | isa_MMX, "psrld" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1649 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1650 | { 0, INS_OTHER, 0, ADDRMETH_W | OPTYPE_dq | OP_W, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_PENTIUM | isa_MMX, "psrad" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1651 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1652 | { 0, INS_OTHER, 0, ADDRMETH_W | OPTYPE_dq | OP_W, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_PENTIUM | isa_MMX, "pslld" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1653 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 } |
|---|
| 1654 | }; |
|---|
| 1655 | |
|---|
| 1656 | |
|---|
| 1657 | static ia32_insn_t tbl_0F73[] = { /* Group 14 */ |
|---|
| 1658 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1659 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1660 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1661 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1662 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1663 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1664 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1665 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1666 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1667 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1668 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1669 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1670 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1671 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1672 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1673 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1674 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1675 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1676 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1677 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1678 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1679 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1680 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1681 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1682 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1683 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1684 | { 0, INS_OTHER, 0, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_PENTIUM | isa_MMX, "psrlq" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1685 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1686 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1687 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1688 | { 0, INS_OTHER, 0, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_PENTIUM | isa_MMX, "psllq" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1689 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 } |
|---|
| 1690 | }; |
|---|
| 1691 | |
|---|
| 1692 | |
|---|
| 1693 | static ia32_insn_t tbl_660F73[] = { /* Group 14 SSE */ |
|---|
| 1694 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1695 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1696 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1697 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1698 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1699 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1700 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1701 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1702 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1703 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1704 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1705 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1706 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1707 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1708 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1709 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1710 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1711 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1712 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1713 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1714 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1715 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1716 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1717 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1718 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1719 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1720 | { 0, INS_OTHER, 0, ADDRMETH_W | OPTYPE_dq | OP_W, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_PENTIUM | isa_MMX, "psrlq" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1721 | { 0, INS_OTHER, 0, ADDRMETH_W | OPTYPE_dq | OP_W, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_PENTIUM | isa_MMX, "psrldq" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1722 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1723 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1724 | { 0, INS_OTHER, 0, ADDRMETH_W | OPTYPE_dq | OP_W, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_PENTIUM | isa_MMX, "psllq" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1725 | { 0, INS_OTHER, 0, ADDRMETH_W | OPTYPE_dq | OP_W, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_PENTIUM | isa_MMX, "pslldq" , "" , 0, 0, 0, 0 , 0 } |
|---|
| 1726 | }; |
|---|
| 1727 | |
|---|
| 1728 | |
|---|
| 1729 | static ia32_insn_t tbl_0FAE[] = { /* Group 15 */ |
|---|
| 1730 | { 0, INS_FPU, 0, ADDRMETH_E | OPTYPE_fx | OP_W, ARG_NONE, ARG_NONE, cpu_PENTIUM | isa_MMX, "fxsave" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1731 | { 0, INS_FPU, 0, ADDRMETH_E | OPTYPE_fx | OP_R, ARG_NONE, ARG_NONE, cpu_PENTIUM | isa_MMX, "fxrstor" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1732 | { 0, INS_SYSTEM, 0, ADDRMETH_E | OPTYPE_d | OP_R, ARG_NONE, ARG_NONE, cpu_PENTIUM2, "ldmxcsr" , "" , 0, 0, 0, 0 , 25 }, |
|---|
| 1733 | { 0, INS_SYSTEM, 0, ADDRMETH_E | OPTYPE_d | OP_W, ARG_NONE, ARG_NONE, cpu_PENTIUM2, "stmxcsr" , "" , 0, 0, 0 , 0, 48 }, |
|---|
| 1734 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1735 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1736 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1737 | { 0, INS_SYSTEM, 0, ADDRMETH_M | OPTYPE_b | OP_R, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "clflush" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1738 | { 0, INS_FPU, 0, ADDRMETH_E | OPTYPE_fx | OP_W, ARG_NONE, ARG_NONE, cpu_PENTIUM | isa_MMX, "fxsave" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1739 | { 0, INS_FPU, 0, ADDRMETH_E | OPTYPE_fx | OP_R, ARG_NONE, ARG_NONE, cpu_PENTIUM | isa_MMX, "fxrstor" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1740 | { 0, INS_SYSTEM, 0, ADDRMETH_E | OPTYPE_d | OP_R, ARG_NONE, ARG_NONE, cpu_PENTIUM2, "ldmxcsr" , "" , 0, 0, 0, 0 , 25 }, |
|---|
| 1741 | { 0, INS_SYSTEM, 0, ADDRMETH_E | OPTYPE_d | OP_W, ARG_NONE, ARG_NONE, cpu_PENTIUM2, "stmxcsr" , "" , 0, 0, 0 , 0, 48 }, |
|---|
| 1742 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1743 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1744 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1745 | { 0, INS_SYSTEM, 0, ADDRMETH_M | OPTYPE_b | OP_R, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "clflush" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1746 | { 0, INS_FPU, 0, ADDRMETH_E | OPTYPE_fx | OP_W, ARG_NONE, ARG_NONE, cpu_PENTIUM | isa_MMX, "fxsave" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1747 | { 0, INS_FPU, 0, ADDRMETH_E | OPTYPE_fx | OP_R, ARG_NONE, ARG_NONE, cpu_PENTIUM | isa_MMX, "fxrstor" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1748 | { 0, INS_SYSTEM, 0, ADDRMETH_E | OPTYPE_d | OP_R, ARG_NONE, ARG_NONE, cpu_PENTIUM2, "ldmxcsr" , "" , 0, 0, 0, 0 , 25 }, |
|---|
| 1749 | { 0, INS_SYSTEM, 0, ADDRMETH_E | OPTYPE_d | OP_W, ARG_NONE, ARG_NONE, cpu_PENTIUM2, "stmxcsr" , "" , 0, 0, 0 , 0, 48 }, |
|---|
| 1750 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1751 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1752 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1753 | { 0, INS_SYSTEM, 0, ADDRMETH_M | OPTYPE_b | OP_R, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "clflush" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 1754 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1755 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1756 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1757 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1758 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1759 | { 0, INS_SYSTEM, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "lfence" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1760 | { 0, INS_SYSTEM, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "mfence" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1761 | { 0, INS_SYSTEM, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "sfence" , "" , 0, 0, 0, 0 , 0 } |
|---|
| 1762 | }; |
|---|
| 1763 | |
|---|
| 1764 | |
|---|
| 1765 | static ia32_insn_t tbl_0FBA[] = { /* Group 8 */ |
|---|
| 1766 | { 0, INS_BITTEST, 0, ADDRMETH_E | OPTYPE_v | OP_R, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "bt" , "" , 0, 0, 0, INS_SET_CARRY, 0 }, |
|---|
| 1767 | { 0, INS_BITTEST, 0, ADDRMETH_E | OPTYPE_v | OP_R, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "bts" , "" , 0, 0, 0, INS_SET_CARRY, 0 }, |
|---|
| 1768 | { 0, INS_BITTEST, 0, ADDRMETH_E | OPTYPE_v | OP_R, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "btr" , "" , 0, 0, 0, INS_SET_CARRY, 0 }, |
|---|
| 1769 | { 0, INS_BITTEST, 0, ADDRMETH_E | OPTYPE_v | OP_R, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "btc" , "" , 0, 0, 0 , INS_SET_CARRY, 0 } |
|---|
| 1770 | }; |
|---|
| 1771 | |
|---|
| 1772 | |
|---|
| 1773 | static ia32_insn_t tbl_0FC7[] = { /* Group 9 */ |
|---|
| 1774 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1775 | { 0, INS_XCHGCC, 0, ADDRMETH_M | OPTYPE_q | OP_W, ARG_NONE, ARG_NONE, cpu_PENTIUM | isa_GP, "cmpxch8b" , "" , 0, 0, 0 , 0 , 9 }, |
|---|
| 1776 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1777 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1778 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1779 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1780 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1781 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1782 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1783 | { 0, INS_XCHGCC, 0, ADDRMETH_M | OPTYPE_q | OP_W, ARG_NONE, ARG_NONE, cpu_PENTIUM | isa_GP, "cmpxch8b" , "" , 0, 0, 0 , 0 , 9 }, |
|---|
| 1784 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1785 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1786 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1787 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1788 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1789 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1790 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1791 | { 0, INS_XCHGCC, 0, ADDRMETH_M | OPTYPE_q | OP_W, ARG_NONE, ARG_NONE, cpu_PENTIUM | isa_GP, "cmpxch8b" , "" , 0, 0, 0 , 0 , 9 } |
|---|
| 1792 | }; |
|---|
| 1793 | |
|---|
| 1794 | |
|---|
| 1795 | static ia32_insn_t tbl_0FB9[] = { /* Group 10 */ |
|---|
| 1796 | { 0, INS_SYSTEM, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, "fxsave" , "" , 0, 0, 0, 0 , 0 } |
|---|
| 1797 | }; |
|---|
| 1798 | |
|---|
| 1799 | |
|---|
| 1800 | static ia32_insn_t tbl_C6[] = { /* Group 11a */ |
|---|
| 1801 | { 0, INS_MOV, 0, ADDRMETH_E | OPTYPE_b | OP_W, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "mov" , "" , 0, 0, 0, 0 , 0 } |
|---|
| 1802 | }; |
|---|
| 1803 | |
|---|
| 1804 | |
|---|
| 1805 | static ia32_insn_t tbl_C7[] = { /* Group 11b */ |
|---|
| 1806 | { 0, INS_MOV, 0, ADDRMETH_E | OPTYPE_v | OP_W, ADDRMETH_I | OPTYPE_v | OP_R, ARG_NONE, cpu_80386 | isa_GP, "mov" , "" , 0, 0, 0, 0 , 0 } |
|---|
| 1807 | }; |
|---|
| 1808 | |
|---|
| 1809 | |
|---|
| 1810 | static ia32_insn_t tbl_80[] = { /* Group 1a */ |
|---|
| 1811 | { 0, INS_ADD, 0, ADDRMETH_E | OPTYPE_b | OP_W | OP_R, ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R, ARG_NONE, cpu_80386 | isa_GP, "add" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
|---|
| 1812 | { 0, INS_OR, 0, ADDRMETH_E | OPTYPE_b | OP_W | OP_R, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "or" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
|---|
| 1813 | { 0, INS_ADD, 0, ADDRMETH_E | OPTYPE_b | OP_W | OP_R, ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R, ARG_NONE, cpu_80386 | isa_GP, "adc" , "" , 0, 0, 0, INS_SET_ALL|INS_TEST_CARRY, 0 }, |
|---|
| 1814 | { 0, INS_SUB, 0, ADDRMETH_E | OPTYPE_b | OP_SIGNED | OP_W | OP_R, ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R, ARG_NONE, cpu_80386 | isa_GP, "sbb" , "" , 0, 0, 0, INS_SET_ALL|INS_TEST_CARRY, 0 }, |
|---|
| 1815 | { 0, INS_AND, 0, ADDRMETH_E | OPTYPE_b | OP_W | OP_R, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "and" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
|---|
| 1816 | { 0, INS_SUB, 0, ADDRMETH_E | OPTYPE_b | OP_SIGNED | OP_W | OP_R, ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R, ARG_NONE, cpu_80386 | isa_GP, "sub" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
|---|
| 1817 | { 0, INS_XOR, 0, ADDRMETH_E | OPTYPE_b | OP_W | OP_R, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "xor" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
|---|
| 1818 | { 0, INS_CMP, 0, ADDRMETH_E | OPTYPE_b | OP_R, ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R, ARG_NONE, cpu_80386 | isa_GP, "cmp" , "" , 0, 0, 0 , INS_SET_ALL, 0 } |
|---|
| 1819 | }; |
|---|
| 1820 | |
|---|
| 1821 | |
|---|
| 1822 | static ia32_insn_t tbl_81[] = { /* Group 1b */ |
|---|
| 1823 | { 0, INS_ADD, 0, ADDRMETH_E | OPTYPE_v | OP_W | OP_R, ADDRMETH_I | OPTYPE_v | OP_SIGNED | OP_R, ARG_NONE, cpu_80386 | isa_GP, "add" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
|---|
| 1824 | { 0, INS_OR, 0, ADDRMETH_E | OPTYPE_v | OP_W | OP_R, ADDRMETH_I | OPTYPE_v | OP_R, ARG_NONE, cpu_80386 | isa_GP, "or" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
|---|
| 1825 | { 0, INS_ADD, 0, ADDRMETH_E | OPTYPE_v | OP_W | OP_R, ADDRMETH_I | OPTYPE_v | OP_SIGNED | OP_R, ARG_NONE, cpu_80386 | isa_GP, "adc" , "" , 0, 0, 0, INS_SET_ALL|INS_TEST_CARRY, 0 }, |
|---|
| 1826 | { 0, INS_SUB, 0, ADDRMETH_E | OPTYPE_v | OP_SIGNED | OP_W | OP_R, ADDRMETH_I | OPTYPE_v | OP_SIGNED | OP_R, ARG_NONE, cpu_80386 | isa_GP, "sbb" , "" , 0, 0, 0, INS_SET_ALL|INS_TEST_CARRY, 0 }, |
|---|
| 1827 | { 0, INS_AND, 0, ADDRMETH_E | OPTYPE_v | OP_W | OP_R, ADDRMETH_I | OPTYPE_v | OP_R, ARG_NONE, cpu_80386 | isa_GP, "and" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
|---|
| 1828 | { 0, INS_SUB, 0, ADDRMETH_E | OPTYPE_v | OP_SIGNED | OP_W | OP_R, ADDRMETH_I | OPTYPE_v | OP_SIGNED | OP_R, ARG_NONE, cpu_80386 | isa_GP, "sub" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
|---|
| 1829 | { 0, INS_XOR, 0, ADDRMETH_E | OPTYPE_v | OP_W | OP_R, ADDRMETH_I | OPTYPE_v | OP_R, ARG_NONE, cpu_80386 | isa_GP, "xor" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
|---|
| 1830 | { 0, INS_CMP, 0, ADDRMETH_E | OPTYPE_v | OP_R, ADDRMETH_I | OPTYPE_v | OP_SIGNED | OP_R, ARG_NONE, cpu_80386 | isa_GP, "cmp" , "" , 0, 0, 0 , INS_SET_ALL, 0 } |
|---|
| 1831 | }; |
|---|
| 1832 | |
|---|
| 1833 | |
|---|
| 1834 | static ia32_insn_t tbl_82[] = { /* Group 1c */ |
|---|
| 1835 | { 0, INS_ADD, 0, ADDRMETH_E | OPTYPE_b | OP_W | OP_R, ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R, ARG_NONE, cpu_80386 | isa_GP, "add" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
|---|
| 1836 | { 0, INS_OR, 0, ADDRMETH_E | OPTYPE_b | OP_W | OP_R, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "or" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
|---|
| 1837 | { 0, INS_ADD, 0, ADDRMETH_E | OPTYPE_b | OP_W | OP_R, ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R, ARG_NONE, cpu_80386 | isa_GP, "adc" , "" , 0, 0, 0, INS_SET_ALL|INS_TEST_CARRY, 0 }, |
|---|
| 1838 | { 0, INS_SUB, 0, ADDRMETH_E | OPTYPE_b | OP_SIGNED | OP_W | OP_R, ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R, ARG_NONE, cpu_80386 | isa_GP, "sbb" , "" , 0, 0, 0, INS_SET_ALL|INS_TEST_CARRY, 0 }, |
|---|
| 1839 | { 0, INS_AND, 0, ADDRMETH_E | OPTYPE_b | OP_W | OP_R, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "and" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
|---|
| 1840 | { 0, INS_SUB, 0, ADDRMETH_E | OPTYPE_b | OP_SIGNED | OP_W | OP_R, ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R, ARG_NONE, cpu_80386 | isa_GP, "sub" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
|---|
| 1841 | { 0, INS_XOR, 0, ADDRMETH_E | OPTYPE_b | OP_W | OP_R, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "xor" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
|---|
| 1842 | { 0, INS_CMP, 0, ADDRMETH_E | OPTYPE_b | OP_R, ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R, ARG_NONE, cpu_80386 | isa_GP, "cmp" , "" , 0, 0, 0 , INS_SET_ALL, 0 } |
|---|
| 1843 | }; |
|---|
| 1844 | |
|---|
| 1845 | |
|---|
| 1846 | static ia32_insn_t tbl_83[] = { /* Group 1d */ |
|---|
| 1847 | { 0, INS_ADD, 0, ADDRMETH_E | OPTYPE_v | OP_W | OP_R, ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R, ARG_NONE, cpu_80386 | isa_GP, "add" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
|---|
| 1848 | { 0, INS_OR, 0, ADDRMETH_E | OPTYPE_v | OP_W | OP_R, ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R, ARG_NONE, cpu_80386 | isa_GP, "or" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
|---|
| 1849 | { 0, INS_ADD, 0, ADDRMETH_E | OPTYPE_v | OP_W | OP_R, ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R, ARG_NONE, cpu_80386 | isa_GP, "adc" , "" , 0, 0, 0, INS_SET_ALL|INS_TEST_CARRY, 0 }, |
|---|
| 1850 | { 0, INS_SUB, 0, ADDRMETH_E | OPTYPE_v | OP_SIGNED | OP_W | OP_R, ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R, ARG_NONE, cpu_80386 | isa_GP, "sbb" , "" , 0, 0, 0, INS_SET_ALL|INS_TEST_CARRY, 0 }, |
|---|
| 1851 | { 0, INS_AND, 0, ADDRMETH_E | OPTYPE_v | OP_W | OP_R, ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R, ARG_NONE, cpu_80386 | isa_GP, "and" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
|---|
| 1852 | { 0, INS_SUB, 0, ADDRMETH_E | OPTYPE_v | OP_SIGNED | OP_W | OP_R, ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R, ARG_NONE, cpu_80386 | isa_GP, "sub" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
|---|
| 1853 | { 0, INS_XOR, 0, ADDRMETH_E | OPTYPE_v | OP_W | OP_R, ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R, ARG_NONE, cpu_80386 | isa_GP, "xor" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
|---|
| 1854 | { 0, INS_CMP, 0, ADDRMETH_E | OPTYPE_v | OP_R, ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R, ARG_NONE, cpu_80386 | isa_GP, "cmp" , "" , 0, 0, 0 , INS_SET_ALL, 0 } |
|---|
| 1855 | }; |
|---|
| 1856 | |
|---|
| 1857 | |
|---|
| 1858 | static ia32_insn_t tbl_C0[] = { /* Group 2a */ |
|---|
| 1859 | { 0, INS_ROL, 0, ADDRMETH_E | OPTYPE_b | OP_W | OP_R, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "rol" , "" , 0, 0, 0, INS_SET_CARRY|INS_SET_OFLOW, 0 }, |
|---|
| 1860 | { 0, INS_ROR, 0, ADDRMETH_E | OPTYPE_b | OP_W | OP_R, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "ror" , "" , 0, 0, 0, INS_SET_CARRY|INS_SET_OFLOW, 0 }, |
|---|
| 1861 | { 0, INS_ROL, 0, ADDRMETH_E | OPTYPE_b | OP_W | OP_R, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "rcl" , "" , 0, 0, 0, INS_SET_CARRY|INS_SET_OFLOW|INS_TEST_CARRY, 0 }, |
|---|
| 1862 | { 0, INS_ROR, 0, ADDRMETH_E | OPTYPE_b | OP_W | OP_R, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "rcr" , "" , 0, 0, 0, INS_SET_CARRY|INS_SET_OFLOW|INS_TEST_CARRY, 0 }, |
|---|
| 1863 | { 0, INS_SHL, 0, ADDRMETH_E | OPTYPE_b | OP_W | OP_R, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "shl" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
|---|
| 1864 | { 0, INS_SHR, 0, ADDRMETH_E | OPTYPE_b | OP_W | OP_R, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "shr" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
|---|
| 1865 | { 0, INS_SHL, 0, ADDRMETH_E | OPTYPE_b | OP_W | OP_R, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "sal" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
|---|
| 1866 | { 0, INS_SHR, 0, ADDRMETH_E | OPTYPE_b | OP_W | OP_R, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "sar" , "" , 0, 0, 0 , INS_SET_ALL, 0 } |
|---|
| 1867 | }; |
|---|
| 1868 | |
|---|
| 1869 | |
|---|
| 1870 | static ia32_insn_t tbl_C1[] = { /* Group 2b */ |
|---|
| 1871 | { 0, INS_ROL, 0, ADDRMETH_E | OPTYPE_v | OP_W | OP_R, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "rol" , "" , 0, 0, 0, INS_SET_CARRY|INS_SET_OFLOW, 0 }, |
|---|
| 1872 | { 0, INS_ROR, 0, ADDRMETH_E | OPTYPE_v | OP_W | OP_R, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "ror" , "" , 0, 0, 0, INS_SET_CARRY|INS_SET_OFLOW, 0 }, |
|---|
| 1873 | { 0, INS_ROL, 0, ADDRMETH_E | OPTYPE_v | OP_W | OP_R, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "rcl" , "" , 0, 0, 0, INS_SET_CARRY|INS_SET_OFLOW|INS_TEST_CARRY, 0 }, |
|---|
| 1874 | { 0, INS_ROR, 0, ADDRMETH_E | OPTYPE_v | OP_W | OP_R, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "rcr" , "" , 0, 0, 0, INS_SET_CARRY|INS_SET_OFLOW|INS_TEST_CARRY, 0 }, |
|---|
| 1875 | { 0, INS_SHL, 0, ADDRMETH_E | OPTYPE_v | OP_W | OP_R, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "shl" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
|---|
| 1876 | { 0, INS_SHR, 0, ADDRMETH_E | OPTYPE_v | OP_W | OP_R, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "shr" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
|---|
| 1877 | { 0, INS_SHL, 0, ADDRMETH_E | OPTYPE_v | OP_W | OP_R, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "sal" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
|---|
| 1878 | { 0, INS_SHR, 0, ADDRMETH_E | OPTYPE_v | OP_W | OP_R, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "sar" , "" , 0, 0, 0 , INS_SET_ALL, 0 } |
|---|
| 1879 | }; |
|---|
| 1880 | |
|---|
| 1881 | |
|---|
| 1882 | static ia32_insn_t tbl_D0[] = { /* Group 2c */ |
|---|
| 1883 | { 0, INS_ROL, 0, ADDRMETH_E | OPTYPE_b | OP_W | OP_R, ADDRMETH_II | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "rol" , "" , 0, 1, 0, INS_SET_CARRY|INS_SET_OFLOW, 0 }, |
|---|
| 1884 | { 0, INS_ROR, 0, ADDRMETH_E | OPTYPE_b | OP_W | OP_R, ADDRMETH_II | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "ror" , "" , 0, 1, 0, INS_SET_CARRY|INS_SET_OFLOW, 0 }, |
|---|
| 1885 | { 0, INS_ROL, 0, ADDRMETH_E | OPTYPE_b | OP_W | OP_R, ADDRMETH_II | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "rcl" , "" , 0, 1, 0, INS_SET_CARRY|INS_SET_OFLOW|INS_TEST_CARRY, 0 }, |
|---|
| 1886 | { 0, INS_ROR, 0, ADDRMETH_E | OPTYPE_b | OP_W | OP_R, ADDRMETH_II | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "rcr" , "" , 0, 1, 0, INS_SET_CARRY|INS_SET_OFLOW|INS_TEST_CARRY, 0 }, |
|---|
| 1887 | { 0, INS_SHL, 0, ADDRMETH_E | OPTYPE_b | OP_W | OP_R, ADDRMETH_II | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "shl" , "" , 0, 1, 0, INS_SET_ALL, 0 }, |
|---|
| 1888 | { 0, INS_SHR, 0, ADDRMETH_E | OPTYPE_b | OP_W | OP_R, ADDRMETH_II | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "shr" , "" , 0, 1, 0, INS_SET_ALL, 0 }, |
|---|
| 1889 | { 0, INS_SHL, 0, ADDRMETH_E | OPTYPE_b | OP_W | OP_R, ADDRMETH_II | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "sal" , "" , 0, 1, 0, INS_SET_ALL, 0 }, |
|---|
| 1890 | { 0, INS_SHR, 0, ADDRMETH_E | OPTYPE_b | OP_W | OP_R, ADDRMETH_II | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "sar" , "" , 0, 1, 0 , INS_SET_ALL, 0 } |
|---|
| 1891 | }; |
|---|
| 1892 | |
|---|
| 1893 | |
|---|
| 1894 | static ia32_insn_t tbl_D1[] = { /* Group 2d */ |
|---|
| 1895 | { 0, INS_ROL, 0, ADDRMETH_E | OPTYPE_v | OP_W | OP_R, ADDRMETH_II | OPTYPE_v | OP_R, ARG_NONE, cpu_80386 | isa_GP, "rol" , "" , 0, 1, 0, INS_SET_CARRY|INS_SET_OFLOW, 0 }, |
|---|
| 1896 | { 0, INS_ROR, 0, ADDRMETH_E | OPTYPE_v | OP_W | OP_R, ADDRMETH_II | OPTYPE_v | OP_R, ARG_NONE, cpu_80386 | isa_GP, "ror" , "" , 0, 1, 0, INS_SET_CARRY|INS_SET_OFLOW, 0 }, |
|---|
| 1897 | { 0, INS_ROL, 0, ADDRMETH_E | OPTYPE_v | OP_W | OP_R, ADDRMETH_II | OPTYPE_v | OP_R, ARG_NONE, cpu_80386 | isa_GP, "rcl" , "" , 0, 1, 0, INS_SET_CARRY|INS_SET_OFLOW|INS_TEST_CARRY, 0 }, |
|---|
| 1898 | { 0, INS_ROR, 0, ADDRMETH_E | OPTYPE_v | OP_W | OP_R, ADDRMETH_II | OPTYPE_v | OP_R, ARG_NONE, cpu_80386 | isa_GP, "rcr" , "" , 0, 1, 0, INS_SET_CARRY|INS_SET_OFLOW|INS_TEST_CARRY, 0 }, |
|---|
| 1899 | { 0, INS_SHL, 0, ADDRMETH_E | OPTYPE_v | OP_W | OP_R, ADDRMETH_II | OPTYPE_v | OP_R, ARG_NONE, cpu_80386 | isa_GP, "shl" , "" , 0, 1, 0, INS_SET_ALL, 0 }, |
|---|
| 1900 | { 0, INS_SHR, 0, ADDRMETH_E | OPTYPE_v | OP_W | OP_R, ADDRMETH_II | OPTYPE_v | OP_R, ARG_NONE, cpu_80386 | isa_GP, "shr" , "" , 0, 1, 0, INS_SET_ALL, 0 }, |
|---|
| 1901 | { 0, INS_SHL, 0, ADDRMETH_E | OPTYPE_v | OP_W | OP_R, ADDRMETH_II | OPTYPE_v | OP_R, ARG_NONE, cpu_80386 | isa_GP, "sal" , "" , 0, 1, 0, INS_SET_ALL, 0 }, |
|---|
| 1902 | { 0, INS_SHR, 0, ADDRMETH_E | OPTYPE_v | OP_W | OP_R, ADDRMETH_II | OPTYPE_v | OP_R, ARG_NONE, cpu_80386 | isa_GP, "sar" , "" , 0, 1, 0 , INS_SET_ALL, 0 } |
|---|
| 1903 | }; |
|---|
| 1904 | |
|---|
| 1905 | |
|---|
| 1906 | static ia32_insn_t tbl_D2[] = { /* Group 2e */ |
|---|
| 1907 | { 0, INS_ROL, 0, ADDRMETH_E | OPTYPE_b | OP_W | OP_R, ADDRMETH_RR | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "rol" , "" , 0, 1, 0, INS_SET_CARRY|INS_SET_OFLOW, 0 }, |
|---|
| 1908 | { 0, INS_ROR, 0, ADDRMETH_E | OPTYPE_b | OP_W | OP_R, ADDRMETH_RR | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "ror" , "" , 0, 1, 0, INS_SET_CARRY|INS_SET_OFLOW, 0 }, |
|---|
| 1909 | { 0, INS_ROL, 0, ADDRMETH_E | OPTYPE_b | OP_W | OP_R, ADDRMETH_RR | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "rcl" , "" , 0, 1, 0, INS_SET_CARRY|INS_SET_OFLOW|INS_TEST_CARRY, 0 }, |
|---|
| 1910 | { 0, INS_ROR, 0, ADDRMETH_E | OPTYPE_b | OP_W | OP_R, ADDRMETH_RR | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "rcr" , "" , 0, 1, 0, INS_SET_CARRY|INS_SET_OFLOW|INS_TEST_CARRY, 0 }, |
|---|
| 1911 | { 0, INS_SHL, 0, ADDRMETH_E | OPTYPE_b | OP_W | OP_R, ADDRMETH_RR | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "shl" , "" , 0, 1, 0, INS_SET_ALL, 0 }, |
|---|
| 1912 | { 0, INS_SHR, 0, ADDRMETH_E | OPTYPE_b | OP_W | OP_R, ADDRMETH_RR | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "shr" , "" , 0, 1, 0, INS_SET_ALL, 0 }, |
|---|
| 1913 | { 0, INS_SHL, 0, ADDRMETH_E | OPTYPE_b | OP_W | OP_R, ADDRMETH_RR | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "sal" , "" , 0, 1, 0, INS_SET_ALL, 0 }, |
|---|
| 1914 | { 0, INS_SHR, 0, ADDRMETH_E | OPTYPE_b | OP_W | OP_R, ADDRMETH_RR | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "sar" , "" , 0, 1, 0 , INS_SET_ALL, 0 } |
|---|
| 1915 | }; |
|---|
| 1916 | |
|---|
| 1917 | |
|---|
| 1918 | static ia32_insn_t tbl_D3[] = { /* Group 2f */ |
|---|
| 1919 | { 0, INS_ROL, 0, ADDRMETH_E | OPTYPE_v | OP_W | OP_R, ADDRMETH_RR | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "rol" , "" , 0, 1, 0, INS_SET_CARRY|INS_SET_OFLOW, 0 }, |
|---|
| 1920 | { 0, INS_ROR, 0, ADDRMETH_E | OPTYPE_v | OP_W | OP_R, ADDRMETH_RR | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "ror" , "" , 0, 1, 0, INS_SET_CARRY|INS_SET_OFLOW, 0 }, |
|---|
| 1921 | { 0, INS_ROL, 0, ADDRMETH_E | OPTYPE_v | OP_W | OP_R, ADDRMETH_RR | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "rcl" , "" , 0, 1, 0, INS_SET_CARRY|INS_SET_OFLOW|INS_TEST_CARRY, 0 }, |
|---|
| 1922 | { 0, INS_ROR, 0, ADDRMETH_E | OPTYPE_v | OP_W | OP_R, ADDRMETH_RR | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "rcr" , "" , 0, 1, 0, INS_SET_CARRY|INS_SET_OFLOW|INS_TEST_CARRY, 0 }, |
|---|
| 1923 | { 0, INS_SHL, 0, ADDRMETH_E | OPTYPE_v | OP_W | OP_R, ADDRMETH_RR | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "shl" , "" , 0, 1, 0, INS_SET_ALL, 0 }, |
|---|
| 1924 | { 0, INS_SHR, 0, ADDRMETH_E | OPTYPE_v | OP_W | OP_R, ADDRMETH_RR | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "shr" , "" , 0, 1, 0, INS_SET_ALL, 0 }, |
|---|
| 1925 | { 0, INS_SHL, 0, ADDRMETH_E | OPTYPE_v | OP_W | OP_R, ADDRMETH_RR | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "sal" , "" , 0, 1, 0, INS_SET_ALL, 0 }, |
|---|
| 1926 | { 0, INS_SHR, 0, ADDRMETH_E | OPTYPE_v | OP_W | OP_R, ADDRMETH_RR | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "sar" , "" , 0, 1, 0 , INS_SET_ALL, 0 } |
|---|
| 1927 | }; |
|---|
| 1928 | |
|---|
| 1929 | |
|---|
| 1930 | static ia32_insn_t tbl_F6[] = { /* Group 3a */ |
|---|
| 1931 | { 0, INS_TEST, 0, ADDRMETH_E | OPTYPE_b | OP_R, ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R, ARG_NONE, cpu_80386 | isa_GP, "test" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
|---|
| 1932 | { 0, INS_TEST, 0, ADDRMETH_E | OPTYPE_b | OP_R, ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R, ARG_NONE, cpu_80386 | isa_GP, "test" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
|---|
| 1933 | { 0, INS_NOT, 0, ADDRMETH_E | OPTYPE_b | OP_W | OP_R, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "not" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1934 | { 0, INS_NEG, 0, ADDRMETH_E | OPTYPE_b | OP_W | OP_R, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "neg" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
|---|
| 1935 | { 0, INS_MUL, 0, OPTYPE_b | ADDRMETH_RR | OP_W | OP_R, ADDRMETH_E | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "mul" , "" , 0, 0, 0, INS_SET_OFLOW|INS_SET_CARRY, 22 }, |
|---|
| 1936 | { 0, INS_MUL, 0, OPTYPE_b | ADDRMETH_RR | OP_W | OP_SIGNED | OP_R, ADDRMETH_E | OPTYPE_b | OP_SIGNED | OP_R, ARG_NONE, cpu_80386 | isa_GP, "imul" , "" , 0, 0, 0, INS_SET_OFLOW|INS_SET_CARRY, 22 }, |
|---|
| 1937 | { 0, INS_DIV, 0, ADDRMETH_RR | OPTYPE_b | OP_W | OP_R, ADDRMETH_E | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "div" , "" , 0, 0, 0, 0 , 13 }, |
|---|
| 1938 | { 0, INS_DIV, 0, ADDRMETH_RR | OPTYPE_b | OP_W | OP_R, ADDRMETH_E | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "idiv" , "" , 0, 0, 0 , 0 , 13 } |
|---|
| 1939 | }; |
|---|
| 1940 | |
|---|
| 1941 | |
|---|
| 1942 | static ia32_insn_t tbl_F7[] = { /* Group 3b */ |
|---|
| 1943 | { 0, INS_TEST, 0, ADDRMETH_E | OPTYPE_v | OP_R, ADDRMETH_I | OPTYPE_v | OP_SIGNED | OP_R, ARG_NONE, cpu_80386 | isa_GP, "test" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
|---|
| 1944 | { 0, INS_TEST, 0, ADDRMETH_E | OPTYPE_v | OP_R, ADDRMETH_I | OPTYPE_v | OP_SIGNED | OP_R, ARG_NONE, cpu_80386 | isa_GP, "test" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
|---|
| 1945 | { 0, INS_NOT, 0, ADDRMETH_E | OPTYPE_v | OP_W | OP_R, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "not" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1946 | { 0, INS_NEG, 0, ADDRMETH_E | OPTYPE_v | OP_W | OP_R, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "neg" , "" , 0, 0, 0, INS_SET_ALL, 0 }, |
|---|
| 1947 | { 0, INS_MUL, 0, ADDRMETH_RR | OPTYPE_v | OP_W | OP_R, ADDRMETH_E | OPTYPE_v | OP_R, ARG_NONE, cpu_80386 | isa_GP, "mul" , "" , 0, 0, 0, INS_SET_OFLOW|INS_SET_CARRY, 23 }, |
|---|
| 1948 | { 0, INS_MUL, 0, ADDRMETH_RR | OPTYPE_v | OP_SIGNED | OP_W | OP_R, ADDRMETH_E | OPTYPE_v | OP_SIGNED | OP_R, ARG_NONE, cpu_80386 | isa_GP, "imul" , "" , 0, 0, 0, INS_SET_OFLOW|INS_SET_CARRY, 23 }, |
|---|
| 1949 | { 0, INS_DIV, 0, ADDRMETH_RR | OPTYPE_v | OP_W | OP_R, ADDRMETH_E | OPTYPE_v | OP_R, ARG_NONE, cpu_80386 | isa_GP, "div" , "" , 0, 0, 0, 0 , 14 }, |
|---|
| 1950 | { 0, INS_DIV, 0, ADDRMETH_RR | OPTYPE_v | OP_W | OP_R, ADDRMETH_E | OPTYPE_v | OP_R, ARG_NONE, cpu_80386 | isa_GP, "idiv" , "" , 0, 0, 0, 0 , 14 } |
|---|
| 1951 | }; |
|---|
| 1952 | |
|---|
| 1953 | |
|---|
| 1954 | static ia32_insn_t tbl_FE[] = { /* Group 4 */ |
|---|
| 1955 | { 0, INS_INC, 0, ADDRMETH_E | OPTYPE_b | OP_W | OP_R, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "inc" , "" , 0, 0, 0, INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY, 0 }, |
|---|
| 1956 | { 0, INS_DEC, 0, ADDRMETH_E | OPTYPE_b | OP_W | OP_R, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "dec" , "" , 0, 0, 0 , INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY, 0 } |
|---|
| 1957 | }; |
|---|
| 1958 | |
|---|
| 1959 | |
|---|
| 1960 | static ia32_insn_t tbl_FF[] = { /* Group 5 */ |
|---|
| 1961 | { 0, INS_INC, 0, ADDRMETH_E | OPTYPE_v | OP_W | OP_R, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "inc" , "" , 0, 0, 0, INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY, 0 }, |
|---|
| 1962 | { 0, INS_DEC, 0, ADDRMETH_E | OPTYPE_v | OP_W | OP_R, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "dec" , "" , 0, 0, 0, INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY, 0 }, |
|---|
| 1963 | { 0, INS_CALL, 0, ADDRMETH_E | OPTYPE_v | OP_X, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "call" , "" , 0, 0, 0, 0 , 3 }, |
|---|
| 1964 | { 0, INS_CALL, 0, ADDRMETH_M | OPTYPE_p | OP_X, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "call" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1965 | { 0, INS_BRANCH, 0, ADDRMETH_E | OPTYPE_v | OP_X, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "jmp" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1966 | { 0, INS_BRANCH, 0, ADDRMETH_M | OPTYPE_p | OP_X, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "jmp" , "" , 0, 0, 0, 0 , 0 }, |
|---|
| 1967 | { 0, INS_PUSH, 0, ADDRMETH_E | OPTYPE_v | OP_R, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "push" , "" , 0, 0, 0, 0 , 33 } |
|---|
| 1968 | }; |
|---|
| 1969 | |
|---|
| 1970 | |
|---|
| 1971 | static ia32_insn_t tbl_D8[] = { /* FPU D8 */ |
|---|
| 1972 | { 0, INS_FPU, 0, ADDRMETH_M|OPTYPE_fs|OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fadd" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 1973 | { 0, INS_FPU, 0, ADDRMETH_M|OPTYPE_fs|OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fmul" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 1974 | { 0, INS_FPU, 0, ADDRMETH_M|OPTYPE_fs|OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fcom" , "" , 0, 0, 0 , INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY, 17 }, |
|---|
| 1975 | { 0, INS_FPU, 0, ADDRMETH_M|OPTYPE_fs|OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fcomp" , "" , 0, 0, 0 , INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY, 0 }, |
|---|
| 1976 | { 0, INS_FPU, 0, ADDRMETH_M|OPTYPE_fs|OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fsub" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 1977 | { 0, INS_FPU, 0, ADDRMETH_M|OPTYPE_fs|OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fsubr" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 1978 | { 0, INS_FPU, 0, ADDRMETH_M|OPTYPE_fs|OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fdiv" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 1979 | { 0, INS_FPU, 0, ADDRMETH_M|OPTYPE_fs|OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fdivr" , "" , 0, 0, 0 , 0 , 0 } |
|---|
| 1980 | }; |
|---|
| 1981 | |
|---|
| 1982 | |
|---|
| 1983 | static ia32_insn_t tbl_D8C0[] = { /* FPU D8 C0 */ |
|---|
| 1984 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fadd" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 1985 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fadd" , "" , 0, 1, 0 , 0 , 0 }, |
|---|
| 1986 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fadd" , "" , 0, 2, 0 , 0 , 0 }, |
|---|
| 1987 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fadd" , "" , 0, 3, 0 , 0 , 0 }, |
|---|
| 1988 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fadd" , "" , 0, 4, 0 , 0 , 0 }, |
|---|
| 1989 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fadd" , "" , 0, 5, 0 , 0 , 0 }, |
|---|
| 1990 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fadd" , "" , 0, 6, 0 , 0 , 0 }, |
|---|
| 1991 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fadd" , "" , 0, 7, 0 , 0 , 0 }, |
|---|
| 1992 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fmul" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 1993 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fmul" , "" , 0, 1, 0 , 0 , 0 }, |
|---|
| 1994 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fmul" , "" , 0, 2, 0 , 0 , 0 }, |
|---|
| 1995 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fmul" , "" , 0, 3, 0 , 0 , 0 }, |
|---|
| 1996 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fmul" , "" , 0, 4, 0 , 0 , 0 }, |
|---|
| 1997 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fmul" , "" , 0, 5, 0 , 0 , 0 }, |
|---|
| 1998 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fmul" , "" , 0, 6, 0 , 0 , 0 }, |
|---|
| 1999 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fmul" , "" , 0, 7, 0 , 0 , 0 }, |
|---|
| 2000 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fcom" , "" , 0, 0, 0 , INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY, 17 }, |
|---|
| 2001 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fcom" , "" , 0, 1, 0 , INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY, 17 }, |
|---|
| 2002 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fcom" , "" , 0, 2, 0 , INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY, 17 }, |
|---|
| 2003 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fcom" , "" , 0, 3, 0 , INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY, 17 }, |
|---|
| 2004 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fcom" , "" , 0, 4, 0 , INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY, 17 }, |
|---|
| 2005 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fcom" , "" , 0, 5, 0 , INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY, 17 }, |
|---|
| 2006 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fcom" , "" , 0, 6, 0 , INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY, 17 }, |
|---|
| 2007 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fcom" , "" , 0, 7, 0 , INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY, 17 }, |
|---|
| 2008 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fcomp" , "" , 0, 0, 0 , INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY, 0 }, |
|---|
| 2009 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fcomp" , "" , 0, 1, 0 , INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY, 0 }, |
|---|
| 2010 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fcomp" , "" , 0, 2, 0 , INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY, 0 }, |
|---|
| 2011 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fcomp" , "" , 0, 3, 0 , INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY, 0 }, |
|---|
| 2012 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fcomp" , "" , 0, 4, 0 , INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY, 0 }, |
|---|
| 2013 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fcomp" , "" , 0, 5, 0 , INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY, 0 }, |
|---|
| 2014 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fcomp" , "" , 0, 6, 0 , INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY, 0 }, |
|---|
| 2015 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fcomp" , "" , 0, 7, 0 , INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY, 0 }, |
|---|
| 2016 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fsub" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2017 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fsub" , "" , 0, 1, 0 , 0 , 0 }, |
|---|
| 2018 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fsub" , "" , 0, 2, 0 , 0 , 0 }, |
|---|
| 2019 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fsub" , "" , 0, 3, 0 , 0 , 0 }, |
|---|
| 2020 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fsub" , "" , 0, 4, 0 , 0 , 0 }, |
|---|
| 2021 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fsub" , "" , 0, 5, 0 , 0 , 0 }, |
|---|
| 2022 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fsub" , "" , 0, 6, 0 , 0 , 0 }, |
|---|
| 2023 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fsub" , "" , 0, 7, 0 , 0 , 0 }, |
|---|
| 2024 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fsubr" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2025 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fsubr" , "" , 0, 1, 0 , 0 , 0 }, |
|---|
| 2026 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fsubr" , "" , 0, 2, 0 , 0 , 0 }, |
|---|
| 2027 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fsubr" , "" , 0, 3, 0 , 0 , 0 }, |
|---|
| 2028 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fsubr" , "" , 0, 4, 0 , 0 , 0 }, |
|---|
| 2029 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fsubr" , "" , 0, 5, 0 , 0 , 0 }, |
|---|
| 2030 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fsubr" , "" , 0, 6, 0 , 0 , 0 }, |
|---|
| 2031 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fsubr" , "" , 0, 7, 0 , 0 , 0 }, |
|---|
| 2032 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fdiv" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2033 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fdiv" , "" , 0, 1, 0 , 0 , 0 }, |
|---|
| 2034 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fdiv" , "" , 0, 2, 0 , 0 , 0 }, |
|---|
| 2035 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fdiv" , "" , 0, 3, 0 , 0 , 0 }, |
|---|
| 2036 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fdiv" , "" , 0, 4, 0 , 0 , 0 }, |
|---|
| 2037 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fdiv" , "" , 0, 5, 0 , 0 , 0 }, |
|---|
| 2038 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fdiv" , "" , 0, 6, 0 , 0 , 0 }, |
|---|
| 2039 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fdiv" , "" , 0, 7, 0 , 0 , 0 }, |
|---|
| 2040 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fdivr" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2041 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fdivr" , "" , 0, 1, 0 , 0 , 0 }, |
|---|
| 2042 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fdivr" , "" , 0, 2, 0 , 0 , 0 }, |
|---|
| 2043 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fdivr" , "" , 0, 3, 0 , 0 , 0 }, |
|---|
| 2044 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fdivr" , "" , 0, 4, 0 , 0 , 0 }, |
|---|
| 2045 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fdivr" , "" , 0, 5, 0 , 0 , 0 }, |
|---|
| 2046 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fdivr" , "" , 0, 6, 0 , 0 , 0 }, |
|---|
| 2047 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fdivr" , "" , 0, 7, 0 , 0 , 0 } |
|---|
| 2048 | }; |
|---|
| 2049 | |
|---|
| 2050 | |
|---|
| 2051 | static ia32_insn_t tbl_D9[] = { /* FPU D9 */ |
|---|
| 2052 | { 0, INS_FPU, 0, ADDRMETH_M|OPTYPE_fs|OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fld" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2053 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2054 | { 0, INS_FPU, 0, ADDRMETH_M|OPTYPE_fs|OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fst" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2055 | { 0, INS_FPU, 0, ADDRMETH_M|OPTYPE_fs|OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fstp" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2056 | { 0, INS_FPU, 0, ADDRMETH_M|OPTYPE_fv|OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fldenv" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2057 | { 0, INS_FPU, 0, ADDRMETH_M|OPTYPE_w|OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fldcw" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2058 | { 0, INS_FPU, 0, ADDRMETH_M|OPTYPE_fv|OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fnstenv" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2059 | { 0, INS_FPU, 0, ADDRMETH_M|OPTYPE_w|OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fnstcw" , "" , 0, 0, 0 , 0 , 0 } |
|---|
| 2060 | }; |
|---|
| 2061 | |
|---|
| 2062 | |
|---|
| 2063 | static ia32_insn_t tbl_D9C0[] = { /* FPU D9 C0 */ |
|---|
| 2064 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fld" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2065 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fld" , "" , 0, 1, 0 , 0 , 0 }, |
|---|
| 2066 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fld" , "" , 0, 2, 0 , 0 , 0 }, |
|---|
| 2067 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fld" , "" , 0, 3, 0 , 0 , 0 }, |
|---|
| 2068 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fld" , "" , 0, 4, 0 , 0 , 0 }, |
|---|
| 2069 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fld" , "" , 0, 5, 0 , 0 , 0 }, |
|---|
| 2070 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fld" , "" , 0, 6, 0 , 0 , 0 }, |
|---|
| 2071 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fld" , "" , 0, 7, 0 , 0 , 0 }, |
|---|
| 2072 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fxch" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2073 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fxch" , "" , 0, 1, 0 , 0 , 0 }, |
|---|
| 2074 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fxch" , "" , 0, 2, 0 , 0 , 0 }, |
|---|
| 2075 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fxch" , "" , 0, 3, 0 , 0 , 0 }, |
|---|
| 2076 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fxch" , "" , 0, 4, 0 , 0 , 0 }, |
|---|
| 2077 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fxch" , "" , 0, 5, 0 , 0 , 0 }, |
|---|
| 2078 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fxch" , "" , 0, 6, 0 , 0 , 0 }, |
|---|
| 2079 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fxch" , "" , 0, 7, 0 , 0 , 0 }, |
|---|
| 2080 | { 0, INS_FPU, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fnop" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2081 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2082 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2083 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2084 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2085 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2086 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2087 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2088 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2089 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2090 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2091 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2092 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2093 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2094 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2095 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2096 | { 0, INS_FPU, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fchs" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2097 | { 0, INS_FPU, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fabs" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2098 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2099 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2100 | { 0, INS_FPU, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "ftst" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2101 | { 0, INS_FPU, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fxam" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2102 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2103 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2104 | { 0, INS_FPU, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fld1" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2105 | { 0, INS_FPU, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fldl2t" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2106 | { 0, INS_FPU, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fldl2e" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2107 | { 0, INS_FPU, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fldpi" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2108 | { 0, INS_FPU, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fldlg2" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2109 | { 0, INS_FPU, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fldln2" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2110 | { 0, INS_FPU, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fldz" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2111 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2112 | { 0, INS_FPU, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "f2xm1" , "" , 0, 0, 0 , 0 , 16 }, |
|---|
| 2113 | { 0, INS_FPU, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fyl2x" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2114 | { 0, INS_FPU, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fptan" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2115 | { 0, INS_FPU, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fpatan" , "" , 0, 0, 0 , 0 , 18 }, |
|---|
| 2116 | { 0, INS_FPU, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fxtract" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2117 | { 0, INS_FPU, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fprem1" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2118 | { 0, INS_FPU, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fdecstp" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2119 | { 0, INS_FPU, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fincstp" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2120 | { 0, INS_FPU, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fprem" , "" , 0, 0, 0 , 0 , 19 }, |
|---|
| 2121 | { 0, INS_FPU, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fyl2xp1" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2122 | { 0, INS_FPU, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fsqrt" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2123 | { 0, INS_FPU, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fsincos" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2124 | { 0, INS_FPU, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "frndint" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2125 | { 0, INS_FPU, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fscale" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2126 | { 0, INS_FPU, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fsin" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2127 | { 0, INS_FPU, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fcos" , "" , 0, 0, 0 , 0 , 0 } |
|---|
| 2128 | }; |
|---|
| 2129 | |
|---|
| 2130 | |
|---|
| 2131 | static ia32_insn_t tbl_DA[] = { /* FPU DA */ |
|---|
| 2132 | { 0, INS_FPU, 0, ADDRMETH_M|OPTYPE_d|OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fiadd" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2133 | { 0, INS_FPU, 0, ADDRMETH_M|OPTYPE_d|OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fimul" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2134 | { 0, INS_FPU, 0, ADDRMETH_M|OPTYPE_d|OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "ficom" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2135 | { 0, INS_FPU, 0, ADDRMETH_M|OPTYPE_d|OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "ficomp" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2136 | { 0, INS_FPU, 0, ADDRMETH_M|OPTYPE_d|OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fisub" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2137 | { 0, INS_FPU, 0, ADDRMETH_M|OPTYPE_d|OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fisubr" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2138 | { 0, INS_FPU, 0, ADDRMETH_M|OPTYPE_d|OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fidiv" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2139 | { 0, INS_FPU, 0, ADDRMETH_M|OPTYPE_d|OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fidivr" , "" , 0, 0, 0 , 0 , 0 } |
|---|
| 2140 | }; |
|---|
| 2141 | |
|---|
| 2142 | |
|---|
| 2143 | static ia32_insn_t tbl_DAC0[] = { /* FPU DA C0 */ |
|---|
| 2144 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_PENTPRO | isa_GP, "fcmovb" , "" , 0, 0, 0 , INS_TEST_CARRY, 0 }, |
|---|
| 2145 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_PENTPRO | isa_GP, "fcmovb" , "" , 0, 1, 0 , INS_TEST_CARRY, 0 }, |
|---|
| 2146 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_PENTPRO | isa_GP, "fcmovb" , "" , 0, 2, 0 , INS_TEST_CARRY, 0 }, |
|---|
| 2147 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_PENTPRO | isa_GP, "fcmovb" , "" , 0, 3, 0 , INS_TEST_CARRY, 0 }, |
|---|
| 2148 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_PENTPRO | isa_GP, "fcmovb" , "" , 0, 4, 0 , INS_TEST_CARRY, 0 }, |
|---|
| 2149 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_PENTPRO | isa_GP, "fcmovb" , "" , 0, 5, 0 , INS_TEST_CARRY, 0 }, |
|---|
| 2150 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_PENTPRO | isa_GP, "fcmovb" , "" , 0, 6, 0 , INS_TEST_CARRY, 0 }, |
|---|
| 2151 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_PENTPRO | isa_GP, "fcmovb" , "" , 0, 7, 0 , INS_TEST_CARRY, 0 }, |
|---|
| 2152 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_PENTPRO | isa_GP, "fcmove" , "" , 0, 0, 0 , INS_TEST_ZERO, 0 }, |
|---|
| 2153 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_PENTPRO | isa_GP, "fcmove" , "" , 0, 1, 0 , INS_TEST_ZERO, 0 }, |
|---|
| 2154 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_PENTPRO | isa_GP, "fcmove" , "" , 0, 2, 0 , INS_TEST_ZERO, 0 }, |
|---|
| 2155 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_PENTPRO | isa_GP, "fcmove" , "" , 0, 3, 0 , INS_TEST_ZERO, 0 }, |
|---|
| 2156 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_PENTPRO | isa_GP, "fcmove" , "" , 0, 4, 0 , INS_TEST_ZERO, 0 }, |
|---|
| 2157 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_PENTPRO | isa_GP, "fcmove" , "" , 0, 5, 0 , INS_TEST_ZERO, 0 }, |
|---|
| 2158 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_PENTPRO | isa_GP, "fcmove" , "" , 0, 6, 0 , INS_TEST_ZERO, 0 }, |
|---|
| 2159 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_PENTPRO | isa_GP, "fcmove" , "" , 0, 7, 0 , INS_TEST_ZERO, 0 }, |
|---|
| 2160 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_PENTPRO | isa_GP, "fcmovbe" , "" , 0, 0, 0 , INS_TEST_CARRY|INS_TEST_OR|INS_TEST_ZERO, 0 }, |
|---|
| 2161 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_PENTPRO | isa_GP, "fcmovbe" , "" , 0, 1, 0 , INS_TEST_CARRY|INS_TEST_OR|INS_TEST_ZERO, 0 }, |
|---|
| 2162 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_PENTPRO | isa_GP, "fcmovbe" , "" , 0, 2, 0 , INS_TEST_CARRY|INS_TEST_OR|INS_TEST_ZERO, 0 }, |
|---|
| 2163 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_PENTPRO | isa_GP, "fcmovbe" , "" , 0, 3, 0 , INS_TEST_CARRY|INS_TEST_OR|INS_TEST_ZERO, 0 }, |
|---|
| 2164 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_PENTPRO | isa_GP, "fcmovbe" , "" , 0, 4, 0 , INS_TEST_CARRY|INS_TEST_OR|INS_TEST_ZERO, 0 }, |
|---|
| 2165 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_PENTPRO | isa_GP, "fcmovbe" , "" , 0, 5, 0 , INS_TEST_CARRY|INS_TEST_OR|INS_TEST_ZERO, 0 }, |
|---|
| 2166 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_PENTPRO | isa_GP, "fcmovbe" , "" , 0, 6, 0 , INS_TEST_CARRY|INS_TEST_OR|INS_TEST_ZERO, 0 }, |
|---|
| 2167 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_PENTPRO | isa_GP, "fcmovbe" , "" , 0, 7, 0 , INS_TEST_CARRY|INS_TEST_OR|INS_TEST_ZERO, 0 }, |
|---|
| 2168 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_PENTPRO | isa_GP, "fcmovu" , "" , 0, 0, 0 , INS_TEST_PARITY, 0 }, |
|---|
| 2169 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_PENTPRO | isa_GP, "fcmovu" , "" , 0, 1, 0 , INS_TEST_PARITY, 0 }, |
|---|
| 2170 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_PENTPRO | isa_GP, "fcmovu" , "" , 0, 2, 0 , INS_TEST_PARITY, 0 }, |
|---|
| 2171 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_PENTPRO | isa_GP, "fcmovu" , "" , 0, 3, 0 , INS_TEST_PARITY, 0 }, |
|---|
| 2172 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_PENTPRO | isa_GP, "fcmovu" , "" , 0, 4, 0 , INS_TEST_PARITY, 0 }, |
|---|
| 2173 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_PENTPRO | isa_GP, "fcmovu" , "" , 0, 5, 0 , INS_TEST_PARITY, 0 }, |
|---|
| 2174 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_PENTPRO | isa_GP, "fcmovu" , "" , 0, 6, 0 , INS_TEST_PARITY, 0 }, |
|---|
| 2175 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_PENTPRO | isa_GP, "fcmovu" , "" , 0, 7, 0 , INS_TEST_PARITY, 0 }, |
|---|
| 2176 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2177 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2178 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2179 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2180 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2181 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2182 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2183 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2184 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2185 | { 0, INS_FPU, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fucompp" , "" , 0, 0, 0 , 0 , 21 }, |
|---|
| 2186 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2187 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2188 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2189 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2190 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2191 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2192 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2193 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2194 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2195 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2196 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2197 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2198 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2199 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2200 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2201 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2202 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2203 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2204 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2205 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2206 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2207 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 } |
|---|
| 2208 | }; |
|---|
| 2209 | |
|---|
| 2210 | |
|---|
| 2211 | static ia32_insn_t tbl_DB[] = { /* FPU DB */ |
|---|
| 2212 | { 0, INS_FPU, 0, ADDRMETH_M|OPTYPE_d|OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fild" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2213 | { 0, INS_FPU, 0, ADDRMETH_M|OPTYPE_d|OP_W, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "fisttp" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2214 | { 0, INS_FPU, 0, ADDRMETH_M|OPTYPE_d|OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fist" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2215 | { 0, INS_FPU, 0, ADDRMETH_M|OPTYPE_d|OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fistp" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2216 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2217 | { 0, INS_FPU, 0, ADDRMETH_M|OPTYPE_fe|OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fld" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2218 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2219 | { 0, INS_FPU, 0, ADDRMETH_M|OPTYPE_fe|OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fstp" , "" , 0, 0, 0 , 0 , 0 } |
|---|
| 2220 | }; |
|---|
| 2221 | |
|---|
| 2222 | |
|---|
| 2223 | static ia32_insn_t tbl_DBC0[] = { /* FPU DB C0 */ |
|---|
| 2224 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fcmovnb" , "" , 0, 0, 0 , INS_TEST_NCARRY, 0 }, |
|---|
| 2225 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fcmovnb" , "" , 0, 1, 0 , INS_TEST_NCARRY, 0 }, |
|---|
| 2226 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fcmovnb" , "" , 0, 2, 0 , INS_TEST_NCARRY, 0 }, |
|---|
| 2227 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fcmovnb" , "" , 0, 3, 0 , INS_TEST_NCARRY, 0 }, |
|---|
| 2228 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fcmovnb" , "" , 0, 4, 0 , INS_TEST_NCARRY, 0 }, |
|---|
| 2229 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fcmovnb" , "" , 0, 5, 0 , INS_TEST_NCARRY, 0 }, |
|---|
| 2230 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fcmovnb" , "" , 0, 6, 0 , INS_TEST_NCARRY, 0 }, |
|---|
| 2231 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fcmovnb" , "" , 0, 7, 0 , INS_TEST_NCARRY, 0 }, |
|---|
| 2232 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fcmovne" , "" , 0, 0, 0 , INS_TEST_NZERO, 0 }, |
|---|
| 2233 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fcmovne" , "" , 0, 1, 0 , INS_TEST_NZERO, 0 }, |
|---|
| 2234 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fcmovne" , "" , 0, 2, 0 , INS_TEST_NZERO, 0 }, |
|---|
| 2235 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fcmovne" , "" , 0, 3, 0 , INS_TEST_NZERO, 0 }, |
|---|
| 2236 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fcmovne" , "" , 0, 4, 0 , INS_TEST_NZERO, 0 }, |
|---|
| 2237 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fcmovne" , "" , 0, 5, 0 , INS_TEST_NZERO, 0 }, |
|---|
| 2238 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fcmovne" , "" , 0, 6, 0 , INS_TEST_NZERO, 0 }, |
|---|
| 2239 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fcmovne" , "" , 0, 7, 0 , INS_TEST_NZERO, 0 }, |
|---|
| 2240 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fcmovnbe" , "" , 0, 0, 0 , INS_TEST_NCARRY|INS_TEST_NZERO, 0 }, |
|---|
| 2241 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fcmovnbe" , "" , 0, 1, 0 , INS_TEST_NCARRY|INS_TEST_NZERO, 0 }, |
|---|
| 2242 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fcmovnbe" , "" , 0, 2, 0 , INS_TEST_NCARRY|INS_TEST_NZERO, 0 }, |
|---|
| 2243 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fcmovnbe" , "" , 0, 3, 0 , INS_TEST_NCARRY|INS_TEST_NZERO, 0 }, |
|---|
| 2244 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fcmovnbe" , "" , 0, 4, 0 , INS_TEST_NCARRY|INS_TEST_NZERO, 0 }, |
|---|
| 2245 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fcmovnbe" , "" , 0, 5, 0 , INS_TEST_NCARRY|INS_TEST_NZERO, 0 }, |
|---|
| 2246 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fcmovnbe" , "" , 0, 6, 0 , INS_TEST_NCARRY|INS_TEST_NZERO, 0 }, |
|---|
| 2247 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fcmovnbe" , "" , 0, 7, 0 , INS_TEST_NCARRY|INS_TEST_NZERO, 0 }, |
|---|
| 2248 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fcmovnu" , "" , 0, 0, 0 , INS_TEST_NPARITY, 0 }, |
|---|
| 2249 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fcmovnu" , "" , 0, 1, 0 , INS_TEST_NPARITY, 0 }, |
|---|
| 2250 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fcmovnu" , "" , 0, 2, 0 , INS_TEST_NPARITY, 0 }, |
|---|
| 2251 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fcmovnu" , "" , 0, 3, 0 , INS_TEST_NPARITY, 0 }, |
|---|
| 2252 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fcmovnu" , "" , 0, 4, 0 , INS_TEST_NPARITY, 0 }, |
|---|
| 2253 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fcmovnu" , "" , 0, 5, 0 , INS_TEST_NPARITY, 0 }, |
|---|
| 2254 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fcmovnu" , "" , 0, 6, 0 , INS_TEST_NPARITY, 0 }, |
|---|
| 2255 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fcmovnu" , "" , 0, 7, 0 , INS_TEST_NPARITY, 0 }, |
|---|
| 2256 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2257 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2258 | { 0, INS_FPU, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fnclex" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2259 | { 0, INS_FPU, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fninit" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2260 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2261 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2262 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2263 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2264 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fucomi" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2265 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fucomi" , "" , 0, 1, 0 , 0 , 0 }, |
|---|
| 2266 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fucomi" , "" , 0, 2, 0 , 0 , 0 }, |
|---|
| 2267 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fucomi" , "" , 0, 3, 0 , 0 , 0 }, |
|---|
| 2268 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fucomi" , "" , 0, 4, 0 , 0 , 0 }, |
|---|
| 2269 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fucomi" , "" , 0, 5, 0 , 0 , 0 }, |
|---|
| 2270 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fucomi" , "" , 0, 6, 0 , 0 , 0 }, |
|---|
| 2271 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fucomi" , "" , 0, 7, 0 , 0 , 0 }, |
|---|
| 2272 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_PENTPRO | isa_GP, "fcomi" , "" , 0, 0, 0 , INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY, 0, }, |
|---|
| 2273 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_PENTPRO | isa_GP, "fcomi" , "" , 0, 1, 0 , INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY, 0 }, |
|---|
| 2274 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_PENTPRO | isa_GP, "fcomi" , "" , 0, 2, 0 , INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY, 0 }, |
|---|
| 2275 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_PENTPRO | isa_GP, "fcomi" , "" , 0, 3, 0 , INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY, 0 }, |
|---|
| 2276 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_PENTPRO | isa_GP, "fcomi" , "" , 0, 4, 0 , INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY, 0 }, |
|---|
| 2277 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_PENTPRO | isa_GP, "fcomi" , "" , 0, 5, 0 , INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY, 0 }, |
|---|
| 2278 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_PENTPRO | isa_GP, "fcomi" , "" , 0, 6, 0 , INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY, 0 }, |
|---|
| 2279 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_PENTPRO | isa_GP, "fcomi" , "" , 0, 7, 0 , INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY, 0 }, |
|---|
| 2280 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2281 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2282 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2283 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2284 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2285 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2286 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2287 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 } |
|---|
| 2288 | }; |
|---|
| 2289 | |
|---|
| 2290 | |
|---|
| 2291 | static ia32_insn_t tbl_DC[] = { /* FPU DC */ |
|---|
| 2292 | { 0, INS_FPU, 0, ADDRMETH_M|OPTYPE_fd|OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fadd" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2293 | { 0, INS_FPU, 0, ADDRMETH_M|OPTYPE_fd|OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fmul" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2294 | { 0, INS_FPU, 0, ADDRMETH_M|OPTYPE_fd|OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fcom" , "" , 0, 0, 0 , INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY, 17 }, |
|---|
| 2295 | { 0, INS_FPU, 0, ADDRMETH_M|OPTYPE_fd|OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fcomp" , "" , 0, 0, 0 , INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY, 0 }, |
|---|
| 2296 | { 0, INS_FPU, 0, ADDRMETH_M|OPTYPE_fd|OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fsub" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2297 | { 0, INS_FPU, 0, ADDRMETH_M|OPTYPE_fd|OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fsubr" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2298 | { 0, INS_FPU, 0, ADDRMETH_M|OPTYPE_fd|OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fdiv" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2299 | { 0, INS_FPU, 0, ADDRMETH_M|OPTYPE_fd|OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fdivr" , "" , 0, 0, 0, 0 , 0 } |
|---|
| 2300 | }; |
|---|
| 2301 | |
|---|
| 2302 | |
|---|
| 2303 | static ia32_insn_t tbl_DCC0[] = { /* FPU DC C0 */ |
|---|
| 2304 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fadd" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2305 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fadd" , "" , 1, 0, 0 , 0 , 0 }, |
|---|
| 2306 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fadd" , "" , 2, 0, 0 , 0 , 0 }, |
|---|
| 2307 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fadd" , "" , 3, 0, 0 , 0 , 0 }, |
|---|
| 2308 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fadd" , "" , 4, 0, 0 , 0 , 0 }, |
|---|
| 2309 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fadd" , "" , 5, 0, 0 , 0 , 0 }, |
|---|
| 2310 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fadd" , "" , 6, 0, 0 , 0 , 0 }, |
|---|
| 2311 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fadd" , "" , 7, 0, 0 , 0 , 0 }, |
|---|
| 2312 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fmul" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2313 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fmul" , "" , 1, 0, 0 , 0 , 0 }, |
|---|
| 2314 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fmul" , "" , 2, 0, 0 , 0 , 0 }, |
|---|
| 2315 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fmul" , "" , 3, 0, 0 , 0 , 0 }, |
|---|
| 2316 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fmul" , "" , 4, 0, 0 , 0 , 0 }, |
|---|
| 2317 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fmul" , "" , 5, 0, 0 , 0 , 0 }, |
|---|
| 2318 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fmul" , "" , 6, 0, 0 , 0 , 0 }, |
|---|
| 2319 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fmul" , "" , 7, 0, 0 , 0 , 0 }, |
|---|
| 2320 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2321 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2322 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2323 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2324 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2325 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2326 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2327 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2328 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2329 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2330 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2331 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2332 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2333 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2334 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2335 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2336 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fsubr" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2337 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fsubr" , "" , 1, 0, 0 , 0 , 0 }, |
|---|
| 2338 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fsubr" , "" , 2, 0, 0 , 0 , 0 }, |
|---|
| 2339 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fsubr" , "" , 3, 0, 0 , 0 , 0 }, |
|---|
| 2340 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fsubr" , "" , 4, 0, 0 , 0 , 0 }, |
|---|
| 2341 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fsubr" , "" , 5, 0, 0 , 0 , 0 }, |
|---|
| 2342 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fsubr" , "" , 6, 0, 0 , 0 , 0 }, |
|---|
| 2343 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fsubr" , "" , 7, 0, 0 , 0 , 0 }, |
|---|
| 2344 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fsub" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2345 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fsub" , "" , 1, 0, 0 , 0 , 0 }, |
|---|
| 2346 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fsub" , "" , 2, 0, 0 , 0 , 0 }, |
|---|
| 2347 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fsub" , "" , 3, 0, 0 , 0 , 0 }, |
|---|
| 2348 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fsub" , "" , 4, 0, 0 , 0 , 0 }, |
|---|
| 2349 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fsub" , "" , 5, 0, 0 , 0 , 0 }, |
|---|
| 2350 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fsub" , "" , 6, 0, 0 , 0 , 0 }, |
|---|
| 2351 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fsub" , "" , 7, 0, 0 , 0 , 0 }, |
|---|
| 2352 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fdivr" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2353 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fdivr" , "" , 1, 0, 0 , 0 , 0 }, |
|---|
| 2354 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fdivr" , "" , 2, 0, 0 , 0 , 0 }, |
|---|
| 2355 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fdivr" , "" , 3, 0, 0 , 0 , 0 }, |
|---|
| 2356 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fdivr" , "" , 4, 0, 0 , 0 , 0 }, |
|---|
| 2357 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fdivr" , "" , 5, 0, 0 , 0 , 0 }, |
|---|
| 2358 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fdivr" , "" , 6, 0, 0 , 0 , 0 }, |
|---|
| 2359 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fdivr" , "" , 7, 0, 0 , 0 , 0 }, |
|---|
| 2360 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fdiv" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2361 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fdiv" , "" , 1, 0, 0 , 0 , 0 }, |
|---|
| 2362 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fdiv" , "" , 2, 0, 0 , 0 , 0 }, |
|---|
| 2363 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fdiv" , "" , 3, 0, 0 , 0 , 0 }, |
|---|
| 2364 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fdiv" , "" , 4, 0, 0 , 0 , 0 }, |
|---|
| 2365 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fdiv" , "" , 5, 0, 0 , 0 , 0 }, |
|---|
| 2366 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fdiv" , "" , 6, 0, 0 , 0 , 0 }, |
|---|
| 2367 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fdiv" , "" , 7, 0, 0 , 0 , 0 } |
|---|
| 2368 | }; |
|---|
| 2369 | |
|---|
| 2370 | |
|---|
| 2371 | static ia32_insn_t tbl_DD[] = { /* FPU DD */ |
|---|
| 2372 | { 0, INS_FPU, 0, ADDRMETH_M|OPTYPE_fd|OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fld" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2373 | { 0, INS_FPU, 0, ADDRMETH_M|OPTYPE_q|OP_W, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "fisttp" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2374 | { 0, INS_FPU, 0, ADDRMETH_M|OPTYPE_fd|OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fst" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2375 | { 0, INS_FPU, 0, ADDRMETH_M|OPTYPE_fd|OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fstp" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2376 | { 0, INS_FPU, 0, ADDRMETH_M|OPTYPE_ft|OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "frstor" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2377 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2378 | { 0, INS_FPU, 0, ADDRMETH_M|OPTYPE_ft|OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fnsave" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2379 | { 0, INS_FPU, 0, ADDRMETH_M|OPTYPE_w|OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fnstsw" , "" , 0, 0, 0 , 0 , 0 } |
|---|
| 2380 | }; |
|---|
| 2381 | |
|---|
| 2382 | |
|---|
| 2383 | static ia32_insn_t tbl_DDC0[] = { /* FPU DD C0 */ |
|---|
| 2384 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "ffree" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2385 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "ffree" , "" , 1, 0, 0 , 0 , 0 }, |
|---|
| 2386 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "ffree" , "" , 2, 0, 0 , 0 , 0 }, |
|---|
| 2387 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "ffree" , "" , 3, 0, 0 , 0 , 0 }, |
|---|
| 2388 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "ffree" , "" , 4, 0, 0 , 0 , 0 }, |
|---|
| 2389 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "ffree" , "" , 5, 0, 0 , 0 , 0 }, |
|---|
| 2390 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "ffree" , "" , 6, 0, 0 , 0 , 0 }, |
|---|
| 2391 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "ffree" , "" , 7, 0, 0 , 0 , 0 }, |
|---|
| 2392 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2393 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2394 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2395 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2396 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2397 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2398 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2399 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2400 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fst" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2401 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fst" , "" , 1, 0, 0 , 0 , 0 }, |
|---|
| 2402 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fst" , "" , 2, 0, 0 , 0 , 0 }, |
|---|
| 2403 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fst" , "" , 3, 0, 0 , 0 , 0 }, |
|---|
| 2404 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fst" , "" , 4, 0, 0 , 0 , 0 }, |
|---|
| 2405 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fst" , "" , 5, 0, 0 , 0 , 0 }, |
|---|
| 2406 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fst" , "" , 6, 0, 0 , 0 , 0 }, |
|---|
| 2407 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fst" , "" , 7, 0, 0 , 0 , 0 }, |
|---|
| 2408 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fstp" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2409 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fstp" , "" , 1, 0, 0 , 0 , 0 }, |
|---|
| 2410 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fstp" , "" , 2, 0, 0 , 0 , 0 }, |
|---|
| 2411 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fstp" , "" , 3, 0, 0 , 0 , 0 }, |
|---|
| 2412 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fstp" , "" , 4, 0, 0 , 0 , 0 }, |
|---|
| 2413 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fstp" , "" , 5, 0, 0 , 0 , 0 }, |
|---|
| 2414 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fstp" , "" , 6, 0, 0 , 0 , 0 }, |
|---|
| 2415 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fstp" , "" , 7, 0, 0 , 0 , 0 }, |
|---|
| 2416 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fucom" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2417 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fucom" , "" , 1, 0, 0 , 0 , 0 }, |
|---|
| 2418 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fucom" , "" , 2, 0, 0 , 0 , 0 }, |
|---|
| 2419 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fucom" , "" , 3, 0, 0 , 0 , 0 }, |
|---|
| 2420 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fucom" , "" , 4, 0, 0 , 0 , 0 }, |
|---|
| 2421 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fucom" , "" , 5, 0, 0 , 0 , 0 }, |
|---|
| 2422 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fucom" , "" , 6, 0, 0 , 0 , 0 }, |
|---|
| 2423 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fucom" , "" , 7, 0, 0 , 0 , 0 }, |
|---|
| 2424 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fucomp" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2425 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fucomp" , "" , 1, 0, 0 , 0 , 0 }, |
|---|
| 2426 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fucomp" , "" , 2, 0, 0 , 0 , 0 }, |
|---|
| 2427 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fucomp" , "" , 3, 0, 0 , 0 , 0 }, |
|---|
| 2428 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fucomp" , "" , 4, 0, 0 , 0 , 0 }, |
|---|
| 2429 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fucomp" , "" , 5, 0, 0 , 0 , 0 }, |
|---|
| 2430 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fucomp" , "" , 6, 0, 0 , 0 , 0 }, |
|---|
| 2431 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fucomp" , "" , 7, 0, 0 , 0 , 0 }, |
|---|
| 2432 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2433 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2434 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2435 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2436 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2437 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2438 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2439 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2440 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2441 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2442 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2443 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2444 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2445 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2446 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2447 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 } |
|---|
| 2448 | }; |
|---|
| 2449 | |
|---|
| 2450 | |
|---|
| 2451 | static ia32_insn_t tbl_DE[] = { /* FPU DE */ |
|---|
| 2452 | { 0, INS_FPU, 0, ADDRMETH_M|OPTYPE_w|OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fiadd" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2453 | { 0, INS_FPU, 0, ADDRMETH_M|OPTYPE_w|OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fimul" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2454 | { 0, INS_FPU, 0, ADDRMETH_M|OPTYPE_w|OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "ficom" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2455 | { 0, INS_FPU, 0, ADDRMETH_M|OPTYPE_w|OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "ficomp" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2456 | { 0, INS_FPU, 0, ADDRMETH_M|OPTYPE_w|OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fisub" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2457 | { 0, INS_FPU, 0, ADDRMETH_M|OPTYPE_w|OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fisubr" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2458 | { 0, INS_FPU, 0, ADDRMETH_M|OPTYPE_w|OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fidiv" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2459 | { 0, INS_FPU, 0, ADDRMETH_M|OPTYPE_w|OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fidivr" , "" , 0, 0, 0, 0 , 0 } |
|---|
| 2460 | }; |
|---|
| 2461 | |
|---|
| 2462 | |
|---|
| 2463 | static ia32_insn_t tbl_DEC0[] = { /* FPU DE C0 */ |
|---|
| 2464 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "faddp" , "" , 0, 0, 0 , 0 , 20 }, |
|---|
| 2465 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "faddp" , "" , 1, 0, 0 , 0 , 20 }, |
|---|
| 2466 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "faddp" , "" , 2, 0, 0 , 0 , 20 }, |
|---|
| 2467 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "faddp" , "" , 3, 0, 0 , 0 , 20 }, |
|---|
| 2468 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "faddp" , "" , 4, 0, 0 , 0 , 20 }, |
|---|
| 2469 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "faddp" , "" , 5, 0, 0 , 0 , 20 }, |
|---|
| 2470 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "faddp" , "" , 6, 0, 0 , 0 , 20 }, |
|---|
| 2471 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "faddp" , "" , 7, 0, 0 , 0 , 20 }, |
|---|
| 2472 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fmulp" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2473 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fmulp" , "" , 1, 0, 0 , 0 , 0 }, |
|---|
| 2474 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fmulp" , "" , 2, 0, 0 , 0 , 0 }, |
|---|
| 2475 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fmulp" , "" , 3, 0, 0 , 0 , 0 }, |
|---|
| 2476 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fmulp" , "" , 4, 0, 0 , 0 , 0 }, |
|---|
| 2477 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fmulp" , "" , 5, 0, 0 , 0 , 0 }, |
|---|
| 2478 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fmulp" , "" , 6, 0, 0 , 0 , 0 }, |
|---|
| 2479 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fmulp" , "" , 7, 0, 0 , 0 , 0 }, |
|---|
| 2480 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2481 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2482 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2483 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2484 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2485 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2486 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2487 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2488 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2489 | { 0, INS_FPU, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fcompp" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2490 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2491 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2492 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2493 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2494 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2495 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2496 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fsubrp" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2497 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fsubrp" , "" , 1, 0, 0 , 0 , 0 }, |
|---|
| 2498 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fsubrp" , "" , 2, 0, 0 , 0 , 0 }, |
|---|
| 2499 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fsubrp" , "" , 3, 0, 0 , 0 , 0 }, |
|---|
| 2500 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fsubrp" , "" , 4, 0, 0 , 0 , 0 }, |
|---|
| 2501 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fsubrp" , "" , 5, 0, 0 , 0 , 0 }, |
|---|
| 2502 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fsubrp" , "" , 6, 0, 0 , 0 , 0 }, |
|---|
| 2503 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fsubrp" , "" , 7, 0, 0 , 0 , 0 }, |
|---|
| 2504 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fsubp" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2505 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fsubp" , "" , 1, 0, 0 , 0 , 0 }, |
|---|
| 2506 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fsubp" , "" , 2, 0, 0 , 0 , 0 }, |
|---|
| 2507 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fsubp" , "" , 3, 0, 0 , 0 , 0 }, |
|---|
| 2508 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fsubp" , "" , 4, 0, 0 , 0 , 0 }, |
|---|
| 2509 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fsubp" , "" , 5, 0, 0 , 0 , 0 }, |
|---|
| 2510 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fsubp" , "" , 6, 0, 0 , 0 , 0 }, |
|---|
| 2511 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fsubp" , "" , 7, 0, 0 , 0 , 0 }, |
|---|
| 2512 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fdivrp" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2513 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fdivrp" , "" , 1, 0, 0 , 0 , 0 }, |
|---|
| 2514 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fdivrp" , "" , 2, 0, 0 , 0 , 0 }, |
|---|
| 2515 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fdivrp" , "" , 3, 0, 0 , 0 , 0 }, |
|---|
| 2516 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fdivrp" , "" , 4, 0, 0 , 0 , 0 }, |
|---|
| 2517 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fdivrp" , "" , 5, 0, 0 , 0 , 0 }, |
|---|
| 2518 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fdivrp" , "" , 6, 0, 0 , 0 , 0 }, |
|---|
| 2519 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fdivrp" , "" , 7, 0, 0 , 0 , 0 }, |
|---|
| 2520 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fdivp" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2521 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fdivp" , "" , 1, 0, 0 , 0 , 0 }, |
|---|
| 2522 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fdivp" , "" , 2, 0, 0 , 0 , 0 }, |
|---|
| 2523 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fdivp" , "" , 3, 0, 0 , 0 , 0 }, |
|---|
| 2524 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fdivp" , "" , 4, 0, 0 , 0 , 0 }, |
|---|
| 2525 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fdivp" , "" , 5, 0, 0 , 0 , 0 }, |
|---|
| 2526 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fdivp" , "" , 6, 0, 0 , 0 , 0 }, |
|---|
| 2527 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fdivp" , "" , 7, 0, 0 , 0 , 0 } |
|---|
| 2528 | }; |
|---|
| 2529 | |
|---|
| 2530 | |
|---|
| 2531 | static ia32_insn_t tbl_DF[] = { /* FPU DF */ |
|---|
| 2532 | { 0, INS_FPU, 0, ADDRMETH_M|OPTYPE_w|OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fild" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2533 | { 0, INS_FPU, 0, ADDRMETH_M|OPTYPE_w|OP_W, ARG_NONE, ARG_NONE, cpu_PENTIUM4 | isa_GP, "fisttp" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2534 | { 0, INS_FPU, 0, ADDRMETH_M|OPTYPE_w|OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fist" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2535 | { 0, INS_FPU, 0, ADDRMETH_M|OPTYPE_w|OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fistp" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2536 | { 0, INS_FPU, 0, ADDRMETH_M|OPTYPE_fb|OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fbld" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2537 | { 0, INS_FPU, 0, ADDRMETH_M|OPTYPE_q|OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fild" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2538 | { 0, INS_FPU, 0, ADDRMETH_M|OPTYPE_fb|OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fbstp" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2539 | { 0, INS_FPU, 0, ADDRMETH_M|OPTYPE_q|OP_W, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fistp" , "" , 0, 0, 0 , 0 , 0 } |
|---|
| 2540 | }; |
|---|
| 2541 | |
|---|
| 2542 | |
|---|
| 2543 | static ia32_insn_t tbl_DFC0[] = { /* FPU DF C0 */ |
|---|
| 2544 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2545 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2546 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2547 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2548 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2549 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2550 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2551 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2552 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2553 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2554 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2555 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2556 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2557 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2558 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2559 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2560 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2561 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2562 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2563 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2564 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2565 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2566 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2567 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2568 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2569 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2570 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2571 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2572 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2573 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2574 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2575 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2576 | { 0, INS_FPU, 0, ADDRMETH_RR | OPTYPE_w | OP_R, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "fnstsw" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2577 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2578 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2579 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2580 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2581 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2582 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2583 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2584 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fucomip" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2585 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fucomip" , "" , 0, 1, 0 , 0 , 0 }, |
|---|
| 2586 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fucomip" , "" , 0, 2, 0 , 0 , 0 }, |
|---|
| 2587 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fucomip" , "" , 0, 3, 0 , 0 , 0 }, |
|---|
| 2588 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fucomip" , "" , 0, 4, 0 , 0 , 0 }, |
|---|
| 2589 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fucomip" , "" , 0, 5, 0 , 0 , 0 }, |
|---|
| 2590 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fucomip" , "" , 0, 6, 0 , 0 , 0 }, |
|---|
| 2591 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fucomip" , "" , 0, 7, 0 , 0 , 0 }, |
|---|
| 2592 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fcomip" , "" , 0, 0, 0 , INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY, 0 }, |
|---|
| 2593 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fcomip" , "" , 0, 1, 0 , INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY, 0 }, |
|---|
| 2594 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fcomip" , "" , 0, 2, 0 , INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY, 0 }, |
|---|
| 2595 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fcomip" , "" , 0, 3, 0 , INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY, 0 }, |
|---|
| 2596 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fcomip" , "" , 0, 4, 0 , INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY, 0 }, |
|---|
| 2597 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fcomip" , "" , 0, 5, 0 , INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY, 0 }, |
|---|
| 2598 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fcomip" , "" , 0, 6, 0 , INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY, 0 }, |
|---|
| 2599 | { 0, INS_FPU, 0, ADDRMETH_RF | OPTYPE_fp | OP_W, ADDRMETH_RF | OPTYPE_fp | OP_R, ARG_NONE, cpu_80387 | isa_FPU, "fcomip" , "" , 0, 7, 0 , INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY, 0 }, |
|---|
| 2600 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2601 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2602 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2603 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2604 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2605 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2606 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 }, |
|---|
| 2607 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387 | isa_FPU, "" , "" , 0, 0, 0 , 0 , 0 } |
|---|
| 2608 | }; |
|---|
| 2609 | |
|---|
| 2610 | |
|---|
| 2611 | static ia32_insn_t tbl_0F0F[] = { /* 3D Now! 0F Suffix */ |
|---|
| 2612 | /* 00 */ { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2613 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2614 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2615 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2616 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2617 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2618 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2619 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2620 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2621 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2622 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2623 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2624 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2625 | { 0, INS_CONV, 0, ADDRMETH_P | OPTYPE_pi | OP_R | OP_W, ADDRMETH_Q | OPTYPE_q |OP_R, ARG_NONE, cpu_K6 | isa_3DNOW, "pi2fd" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2626 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2627 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2628 | /* 10 */ { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2629 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2630 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2631 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2632 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2633 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2634 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2635 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2636 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2637 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2638 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2639 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2640 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2641 | { 0, INS_CONV, 0, ADDRMETH_P | OPTYPE_pi | OP_R | OP_W, ADDRMETH_Q | OPTYPE_q |OP_R, ARG_NONE, cpu_K6 | isa_3DNOW, "pf2id" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2642 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2643 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2644 | /* 20 */ { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2645 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2646 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2647 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2648 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2649 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2650 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2651 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2652 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2653 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2654 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2655 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2656 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2657 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2658 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2659 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2660 | /* 30 */ { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2661 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2662 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2663 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2664 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2665 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2666 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2667 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2668 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2669 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2670 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2671 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2672 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2673 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2674 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2675 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2676 | /* 40 */ { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2677 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2678 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2679 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2680 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2681 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2682 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2683 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2684 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2685 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2686 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2687 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2688 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2689 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2690 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2691 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2692 | /* 50 */ { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2693 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2694 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2695 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2696 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2697 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2698 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2699 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2700 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2701 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2702 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2703 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2704 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2705 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2706 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2707 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2708 | /* 60 */ { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2709 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2710 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2711 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2712 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2713 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2714 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2715 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2716 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2717 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2718 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2719 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2720 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2721 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2722 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2723 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2724 | /* 70 */ { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2725 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2726 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2727 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2728 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2729 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2730 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2731 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2732 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2733 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2734 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2735 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2736 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2737 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2738 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2739 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2740 | /* 80 */ { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2741 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2742 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2743 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2744 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2745 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2746 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2747 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2748 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2749 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2750 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2751 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2752 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2753 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2754 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2755 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2756 | { 0, INS_CMP, 0, ADDRMETH_P | OPTYPE_pi | OP_R | OP_W, ADDRMETH_Q | OPTYPE_q |OP_R, ARG_NONE, cpu_K6 | isa_3DNOW, "pfcmpge" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2757 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2758 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2759 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2760 | { 0, INS_MIN, 0, ADDRMETH_P | OPTYPE_pi | OP_R | OP_W, ADDRMETH_Q | OPTYPE_q |OP_R, ARG_NONE, cpu_K6 | isa_3DNOW, "pfmin" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2761 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2762 | { 0, INS_ARITH, 0, ADDRMETH_P | OPTYPE_pi | OP_R | OP_W, ADDRMETH_Q | OPTYPE_q |OP_R, ARG_NONE, cpu_K6 | isa_3DNOW, "pfrcp" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2763 | { 0, INS_ARITH, 0, ADDRMETH_P | OPTYPE_pi | OP_R | OP_W, ADDRMETH_Q | OPTYPE_q |OP_R, ARG_NONE, cpu_K6 | isa_3DNOW, "pfrsqrt" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2764 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2765 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2766 | { 0, INS_SUB, 0, ADDRMETH_P | OPTYPE_pi | OP_R | OP_W, ADDRMETH_Q | OPTYPE_q |OP_R, ARG_NONE, cpu_K6 | isa_3DNOW, "pfsub" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2767 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2768 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2769 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2770 | { 0, INS_ADD, 0, ADDRMETH_P | OPTYPE_pi | OP_R | OP_W, ADDRMETH_Q | OPTYPE_q |OP_R, ARG_NONE, cpu_K6 | isa_3DNOW, "pfadd" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2771 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2772 | { 0, INS_CMP, 0, ADDRMETH_P | OPTYPE_pi | OP_R | OP_W, ADDRMETH_Q | OPTYPE_q |OP_R, ARG_NONE, cpu_K6 | isa_3DNOW, "pfcmpgt" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2773 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2774 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2775 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2776 | { 0, INS_MAX, 0, ADDRMETH_P | OPTYPE_pi | OP_R | OP_W, ADDRMETH_Q | OPTYPE_q |OP_R, ARG_NONE, cpu_K6 | isa_3DNOW, "pfmax" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2777 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2778 | { 0, INS_ARITH, 0, ADDRMETH_P | OPTYPE_pi | OP_R | OP_W, ADDRMETH_Q | OPTYPE_q |OP_R, ARG_NONE, cpu_K6 | isa_3DNOW, "pfrcpit1" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2779 | { 0, INS_ARITH, 0, ADDRMETH_P | OPTYPE_pi | OP_R | OP_W, ADDRMETH_Q | OPTYPE_q |OP_R, ARG_NONE, cpu_K6 | isa_3DNOW, "pfrsqit1" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2780 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2781 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2782 | { 0, INS_SUB, 0, ADDRMETH_P | OPTYPE_pi | OP_R | OP_W, ADDRMETH_Q | OPTYPE_q |OP_R, ARG_NONE, cpu_K6 | isa_3DNOW, "pfsubr" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2783 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2784 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2785 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2786 | { 0, INS_ADD, 0, ADDRMETH_P | OPTYPE_pi | OP_R | OP_W, ADDRMETH_Q | OPTYPE_q |OP_R, ARG_NONE, cpu_K6 | isa_3DNOW, "pfacc" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2787 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2788 | { 0, INS_CMP, 0, ADDRMETH_P | OPTYPE_pi | OP_R | OP_W, ADDRMETH_Q | OPTYPE_q |OP_R, ARG_NONE, cpu_K6 | isa_3DNOW, "pfcmpeq" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2789 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2790 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2791 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2792 | { 0, INS_MUL, 0, ADDRMETH_P | OPTYPE_pi | OP_R | OP_W, ADDRMETH_Q | OPTYPE_q |OP_R, ARG_NONE, cpu_K6 | isa_3DNOW, "pfmul" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2793 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2794 | { 0, INS_ARITH, 0, ADDRMETH_P | OPTYPE_pi | OP_R | OP_W, ADDRMETH_Q | OPTYPE_q |OP_R, ARG_NONE, cpu_K6 | isa_3DNOW, "pfrcpit2" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2795 | { 0, INS_MUL, 0, ADDRMETH_P | OPTYPE_pi | OP_R | OP_W, ADDRMETH_Q | OPTYPE_q |OP_R, ARG_NONE, cpu_K6 | isa_3DNOW, "pmulhrw" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2796 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2797 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2798 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2799 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2800 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2801 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2802 | { 0, INS_INVALID, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_K6 | isa_3DNOW, "" , "" , 0, 0, 0, 0, 0 }, |
|---|
| 2803 | { 0, INS_AVG, 0, ADDRMETH_P | OPTYPE_pi | OP_R | OP_W, ADDRMETH_Q | OPTYPE_q |OP_R, ARG_NONE, cpu_K6 | isa_3DNOW, "pavgusb" , "" , 0, 0, 0, 0, 0 } |
|---|
| 2804 | }; |
|---|
| 2805 | |
|---|
| 2806 | |
|---|
| 2807 | |
|---|
| 2808 | /* ================== Table of Opcode Tables ================== */ |
|---|
| 2809 | ia32_table_desc_t ia32_tables[] = { |
|---|
| 2810 | /* table, prefix table, type, shift, mask, min, max */ |
|---|
| 2811 | { tbl_Main, tbl_opcode, 0x00, 0xFF, 0x00, 0xFF }, |
|---|
| 2812 | { tbl_66, tbl_prefix, 0x00, 0xFF, 0x0F, 0x0F }, |
|---|
| 2813 | { tbl_F2, tbl_prefix, 0x00, 0xFF, 0x0F, 0x0F }, |
|---|
| 2814 | { tbl_F3, tbl_prefix, 0x00, 0xFF, 0x0F, 0x90 }, |
|---|
| 2815 | { tbl_0F, tbl_opcode, 0x00, 0xFF, 0x00, 0xFF }, |
|---|
| 2816 | /* 5 */ |
|---|
| 2817 | { tbl_660F, tbl_prefix, 0x00, 0xFF, 0x10, 0xFF }, |
|---|
| 2818 | { tbl_F20F, tbl_prefix, 0x00, 0xFF, 0x10, 0xFF }, |
|---|
| 2819 | { tbl_F30F, tbl_prefix, 0x00, 0xFF, 0x10, 0xFF }, |
|---|
| 2820 | { tbl_0F00, tbl_extension, 0x03, 0x07, 0x00, 0x07 }, |
|---|
| 2821 | { tbl_0F01, tbl_extension, 0x03, 0x1F, 0x00, 0x1F }, |
|---|
| 2822 | /* 10 */ |
|---|
| 2823 | { tbl_0F0111, tbl_ext_ext, 0x00, 0x01, 0x00, 0x01 }, |
|---|
| 2824 | { tbl_0F12, tbl_extension, 0x06, 0x03, 0x00, 0x03 }, |
|---|
| 2825 | { tbl_0F16, tbl_extension, 0x06, 0x03, 0x00, 0x03 }, |
|---|
| 2826 | { tbl_0F18, tbl_extension, 0x03, 0x1F, 0x00, 0x13 }, |
|---|
| 2827 | { tbl_0F71, tbl_extension, 0x03, 0x1F, 0x00, 0x1F }, |
|---|
| 2828 | /* 15 */ |
|---|
| 2829 | { tbl_660F71, tbl_extension, 0x03, 0x1F, 0x00, 0x1F }, |
|---|
| 2830 | { tbl_0F72, tbl_extension, 0x03, 0x1F, 0x00, 0x1F }, |
|---|
| 2831 | { tbl_660F72, tbl_extension, 0x03, 0x1F, 0x00, 0x1F }, |
|---|
| 2832 | { tbl_0F73, tbl_extension, 0x00, 0x00, 0x00, 0x00 }, |
|---|
| 2833 | { tbl_660F73, tbl_extension, 0x03, 0x1F, 0x00, 0x1F }, |
|---|
| 2834 | /* 20 */ |
|---|
| 2835 | { tbl_0FAE, tbl_extension, 0x03, 0x1F, 0x00, 0x1F }, |
|---|
| 2836 | { tbl_0FBA, tbl_extension, 0x03, 0x07, 0x04, 0x07 }, |
|---|
| 2837 | { tbl_0FC7, tbl_extension, 0x03, 0x1F, 0x00, 0x11 }, |
|---|
| 2838 | { tbl_0FB9, tbl_extension, 0x03, 0x07, 0x00, 0x00 }, |
|---|
| 2839 | { tbl_C6, tbl_extension, 0x03, 0x07, 0x00, 0x00 }, |
|---|
| 2840 | /* 25 */ |
|---|
| 2841 | { tbl_C7, tbl_extension, 0x03, 0x07, 0x00, 0x00 }, |
|---|
| 2842 | { tbl_80, tbl_extension, 0x03, 0x07, 0x00, 0x07 }, |
|---|
| 2843 | { tbl_81, tbl_extension, 0x03, 0x07, 0x00, 0x07 }, |
|---|
| 2844 | { tbl_82, tbl_extension, 0x03, 0x07, 0x00, 0x07 }, |
|---|
| 2845 | { tbl_83, tbl_extension, 0x03, 0x07, 0x00, 0x07 }, |
|---|
| 2846 | /* 30 */ |
|---|
| 2847 | { tbl_C0, tbl_extension, 0x03, 0x07, 0x00, 0x07 }, |
|---|
| 2848 | { tbl_C1, tbl_extension, 0x03, 0x07, 0x00, 0x07 }, |
|---|
| 2849 | { tbl_D0, tbl_extension, 0x03, 0x07, 0x00, 0x07 }, |
|---|
| 2850 | { tbl_D1, tbl_extension, 0x03, 0x07, 0x00, 0x07 }, |
|---|
| 2851 | { tbl_D2, tbl_extension, 0x03, 0x07, 0x00, 0x07 }, |
|---|
| 2852 | /* 35 */ |
|---|
| 2853 | { tbl_D3, tbl_extension, 0x03, 0x07, 0x00, 0x07 }, |
|---|
| 2854 | { tbl_F6, tbl_extension, 0x03, 0x07, 0x00, 0x07 }, |
|---|
| 2855 | { tbl_F7, tbl_extension, 0x03, 0x07, 0x00, 0x07 }, |
|---|
| 2856 | { tbl_FE, tbl_extension, 0x03, 0x07, 0x00, 0x01 }, |
|---|
| 2857 | { tbl_FF, tbl_extension, 0x03, 0x07, 0x00, 0x06 }, |
|---|
| 2858 | /* 40 */ |
|---|
| 2859 | { tbl_D8, tbl_fpu, 0x03, 0x07, 0x00, 0xBF }, |
|---|
| 2860 | { tbl_D8C0, tbl_fpu_ext, 0x00, 0xFF, 0xC0, 0xFF }, |
|---|
| 2861 | { tbl_D9, tbl_fpu, 0x03, 0x07, 0x00, 0xBF }, |
|---|
| 2862 | { tbl_D9C0, tbl_fpu_ext, 0x00, 0xFF, 0xC0, 0xFF }, |
|---|
| 2863 | { tbl_DA, tbl_fpu, 0x03, 0x07, 0x00, 0xBF }, |
|---|
| 2864 | /* 45 */ |
|---|
| 2865 | { tbl_DAC0, tbl_fpu_ext, 0x00, 0xFF, 0xC0, 0xFF }, |
|---|
| 2866 | { tbl_DB, tbl_fpu, 0x03, 0x07, 0x00, 0xBF }, |
|---|
| 2867 | { tbl_DBC0, tbl_fpu_ext, 0x00, 0xFF, 0xC0, 0xFF }, |
|---|
| 2868 | { tbl_DC, tbl_fpu, 0x03, 0x07, 0x00, 0xBF }, |
|---|
| 2869 | { tbl_DCC0, tbl_fpu_ext, 0x00, 0xFF, 0xC0, 0xFF }, |
|---|
| 2870 | /* 50 */ |
|---|
| 2871 | { tbl_DD, tbl_fpu, 0x03, 0x07, 0x00, 0xBF }, |
|---|
| 2872 | { tbl_DDC0, tbl_fpu_ext, 0x00, 0xFF, 0xC0, 0xFF }, |
|---|
| 2873 | { tbl_DE, tbl_fpu, 0x03, 0x07, 0x00, 0xBF }, |
|---|
| 2874 | { tbl_DEC0, tbl_fpu_ext, 0x00, 0xFF, 0xC0, 0xFF }, |
|---|
| 2875 | { tbl_DF, tbl_fpu, 0x03, 0x07, 0x00, 0xBF }, |
|---|
| 2876 | /* 55 */ |
|---|
| 2877 | { tbl_DFC0, tbl_fpu_ext, 0x00, 0xFF, 0xC0, 0xFF }, |
|---|
| 2878 | { tbl_0F0F, tbl_suffix, 0x00, 0xFF, 0x00, 0xBF } |
|---|
| 2879 | }; |
|---|
| 2880 | /* ia32_opcode_tables.h */ |
|---|
| 2881 | /* Table index constants: |
|---|
| 2882 | #define idx_Main 0 |
|---|
| 2883 | #define idx_66 1 |
|---|
| 2884 | #define idx_F2 2 |
|---|
| 2885 | #define idx_F3 3 |
|---|
| 2886 | #define idx_0F 4 |
|---|
| 2887 | #define idx_660F 5 |
|---|
| 2888 | #define idx_F20F 6 |
|---|
| 2889 | #define idx_F30F 7 |
|---|
| 2890 | #define idx_0F00 8 |
|---|
| 2891 | #define idx_0F01 9 |
|---|
| 2892 | #define idx_0F0111 10 |
|---|
| 2893 | #define idx_0F12 11 |
|---|
| 2894 | #define idx_0F16 12 |
|---|
| 2895 | #define idx_0F18 13 |
|---|
| 2896 | #define idx_0F71 14 |
|---|
| 2897 | #define idx_660F71 15 |
|---|
| 2898 | #define idx_0F72 16 |
|---|
| 2899 | #define idx_660F72 17 |
|---|
| 2900 | #define idx_0F73 18 |
|---|
| 2901 | #define idx_660F73 19 |
|---|
| 2902 | #define idx_0FAE 20 |
|---|
| 2903 | #define idx_0FBA 21 |
|---|
| 2904 | #define idx_0FC7 22 |
|---|
| 2905 | #define idx_0FB9 23 |
|---|
| 2906 | #define idx_C6 24 |
|---|
| 2907 | #define idx_C7 25 |
|---|
| 2908 | #define idx_80 26 |
|---|
| 2909 | #define idx_81 27 |
|---|
| 2910 | #define idx_82 28 |
|---|
| 2911 | #define idx_83 29 |
|---|
| 2912 | #define idx_C0 30 |
|---|
| 2913 | #define idx_C1 31 |
|---|
| 2914 | #define idx_D0 32 |
|---|
| 2915 | #define idx_D1 33 |
|---|
| 2916 | #define idx_D2 34 |
|---|
| 2917 | #define idx_D3 35 |
|---|
| 2918 | #define idx_F6 36 |
|---|
| 2919 | #define idx_F7 37 |
|---|
| 2920 | #define idx_FE 38 |
|---|
| 2921 | #define idx_FF 39 |
|---|
| 2922 | #define idx_D8 40 |
|---|
| 2923 | #define idx_D8C0 41 |
|---|
| 2924 | #define idx_D9 42 |
|---|
| 2925 | #define idx_D9C0 43 |
|---|
| 2926 | #define idx_DA 44 |
|---|
| 2927 | #define idx_DAC0 45 |
|---|
| 2928 | #define idx_DB 46 |
|---|
| 2929 | #define idx_DBC0 47 |
|---|
| 2930 | #define idx_DC 48 |
|---|
| 2931 | #define idx_DCC0 49 |
|---|
| 2932 | #define idx_DD 50 |
|---|
| 2933 | #define idx_DDC0 51 |
|---|
| 2934 | #define idx_DE 52 |
|---|
| 2935 | #define idx_DEC0 53 |
|---|
| 2936 | #define idx_DF 54 |
|---|
| 2937 | #define idx_DFC0 55 |
|---|
| 2938 | #define idx_0F0F 56 |
|---|
| 2939 | */ |
|---|
| 2940 | |
|---|
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