1/* Copyright (C) 2017 Povilas Kanapickas <povilas@radix.lt>
2
3 Distributed under the Boost Software License, Version 1.0.
4 (See accompanying file LICENSE_1_0.txt or copy at
5 http://www.boost.org/LICENSE_1_0.txt)
6*/
7
8#ifndef LIBSIMDPP_SIMD_CAPABILITIES_H
9#define LIBSIMDPP_SIMD_CAPABILITIES_H
10
11#ifndef LIBSIMDPP_SIMD_H
12 #error "This file must be included through simd.h"
13#endif
14#include <simdpp/setup_arch.h>
15
16#if SIMDPP_USE_SSE2 || SIMDPP_USE_NEON || SIMDPP_USE_ALTIVEC || SIMDPP_USE_MSA
17#define SIMDPP_HAS_INT8_SIMD 1
18#define SIMDPP_HAS_INT16_SIMD 1
19#define SIMDPP_HAS_INT32_SIMD 1
20#else
21#define SIMDPP_HAS_INT8_SIMD 0
22#define SIMDPP_HAS_INT16_SIMD 0
23#define SIMDPP_HAS_INT32_SIMD 0
24#endif
25
26#if SIMDPP_USE_SSE2 || SIMDPP_USE_NEON || SIMDPP_USE_VSX_207 || SIMDPP_USE_MSA
27#define SIMDPP_HAS_INT64_SIMD 1
28#else
29#define SIMDPP_HAS_INT64_SIMD 0
30#endif
31
32#if SIMDPP_USE_SSE2 || SIMDPP_USE_NEON_FLT_SP || (SIMDPP_USE_NEON && SIMDPP_64_BITS) || SIMDPP_USE_ALTIVEC || SIMDPP_USE_MSA
33#define SIMDPP_HAS_FLOAT32_SIMD 1
34#else
35#define SIMDPP_HAS_FLOAT32_SIMD 0
36#endif
37
38#if SIMDPP_USE_SSE2 || (SIMDPP_USE_NEON && SIMDPP_64_BITS) || SIMDPP_USE_VSX_206 || SIMDPP_USE_MSA
39#define SIMDPP_HAS_FLOAT64_SIMD 1
40#else
41#define SIMDPP_HAS_FLOAT64_SIMD 0
42#endif
43
44#if SIMDPP_USE_NULL || SIMDPP_USE_AVX512F || (SIMDPP_USE_NEON && SIMDPP_64_BITS) || SIMDPP_USE_VSX_206 || SIMDPP_USE_MSA
45#define SIMDPP_HAS_FLOAT64_TO_UINT32_CONVERSION 1
46#else
47#define SIMDPP_HAS_FLOAT64_TO_UINT32_CONVERSION 0
48#endif
49
50#if SIMDPP_USE_NULL || SIMDPP_USE_AVX512DQ || (SIMDPP_USE_NEON && SIMDPP_64_BITS) || SIMDPP_USE_VSX_207 || SIMDPP_USE_MSA
51#define SIMDPP_HAS_INT64_TO_FLOAT64_CONVERSION 1
52#define SIMDPP_HAS_INT64_TO_FLOAT32_CONVERSION 1
53#define SIMDPP_HAS_UINT64_TO_FLOAT64_CONVERSION 1
54#define SIMDPP_HAS_UINT64_TO_FLOAT32_CONVERSION 1
55
56#define SIMDPP_HAS_FLOAT32_TO_INT64_CONVERSION 1
57#define SIMDPP_HAS_FLOAT32_TO_UINT64_CONVERSION 1
58
59#define SIMDPP_HAS_FLOAT64_TO_INT64_CONVERSION 1
60#define SIMDPP_HAS_FLOAT64_TO_UINT64_CONVERSION 1
61#else
62#define SIMDPP_HAS_INT64_TO_FLOAT64_CONVERSION 0
63#define SIMDPP_HAS_INT64_TO_FLOAT32_CONVERSION 0
64#define SIMDPP_HAS_UINT64_TO_FLOAT64_CONVERSION 0
65#define SIMDPP_HAS_UINT64_TO_FLOAT32_CONVERSION 0
66
67#define SIMDPP_HAS_FLOAT32_TO_INT64_CONVERSION 0
68#define SIMDPP_HAS_FLOAT32_TO_UINT64_CONVERSION 0
69
70#define SIMDPP_HAS_FLOAT64_TO_INT64_CONVERSION 0
71#define SIMDPP_HAS_FLOAT64_TO_UINT64_CONVERSION 0
72#endif
73
74#if SIMDPP_USE_NULL || SIMDPP_USE_SSSE3 || SIMDPP_USE_NEON || SIMDPP_USE_ALTIVEC || SIMDPP_USE_MSA
75#define SIMDPP_HAS_INT8_SHIFT_L_BY_VECTOR 1
76#define SIMDPP_HAS_UINT8_SHIFT_L_BY_VECTOR 1
77#define SIMDPP_HAS_INT16_SHIFT_L_BY_VECTOR 1
78#define SIMDPP_HAS_UINT16_SHIFT_L_BY_VECTOR 1
79#else
80#define SIMDPP_HAS_INT8_SHIFT_L_BY_VECTOR 0
81#define SIMDPP_HAS_UINT8_SHIFT_L_BY_VECTOR 0
82#define SIMDPP_HAS_INT16_SHIFT_L_BY_VECTOR 0
83#define SIMDPP_HAS_UINT16_SHIFT_L_BY_VECTOR 0
84#endif
85
86#if SIMDPP_USE_NULL || SIMDPP_USE_SSE2 || SIMDPP_USE_NEON || SIMDPP_USE_ALTIVEC || SIMDPP_USE_MSA
87#define SIMDPP_HAS_INT32_SHIFT_L_BY_VECTOR 1
88#define SIMDPP_HAS_UINT32_SHIFT_L_BY_VECTOR 1
89#else
90#define SIMDPP_HAS_INT32_SHIFT_L_BY_VECTOR 0
91#define SIMDPP_HAS_UINT32_SHIFT_L_BY_VECTOR 0
92#endif
93
94#if SIMDPP_USE_NULL || SIMDPP_USE_SSSE3 || SIMDPP_USE_NEON || SIMDPP_USE_ALTIVEC || SIMDPP_USE_MSA
95#define SIMDPP_HAS_INT8_SHIFT_R_BY_VECTOR 1
96#define SIMDPP_HAS_UINT8_SHIFT_R_BY_VECTOR 1
97#define SIMDPP_HAS_UINT16_SHIFT_R_BY_VECTOR 1
98#else
99#define SIMDPP_HAS_INT8_SHIFT_R_BY_VECTOR 0
100#define SIMDPP_HAS_UINT8_SHIFT_R_BY_VECTOR 0
101#define SIMDPP_HAS_UINT16_SHIFT_R_BY_VECTOR 0
102#endif
103
104#if SIMDPP_USE_NULL || SIMDPP_USE_AVX512BW || SIMDPP_USE_NEON || SIMDPP_USE_ALTIVEC || SIMDPP_USE_MSA
105#define SIMDPP_HAS_INT16_SHIFT_R_BY_VECTOR 1
106#else
107#define SIMDPP_HAS_INT16_SHIFT_R_BY_VECTOR 0
108#endif
109
110#if SIMDPP_USE_NULL || SIMDPP_USE_SSE2 || SIMDPP_USE_NEON || SIMDPP_USE_ALTIVEC || SIMDPP_USE_MSA
111#define SIMDPP_HAS_INT32_SHIFT_R_BY_VECTOR 1
112#define SIMDPP_HAS_UINT32_SHIFT_R_BY_VECTOR 1
113#else
114#define SIMDPP_HAS_INT32_SHIFT_R_BY_VECTOR 0
115#define SIMDPP_HAS_UINT32_SHIFT_R_BY_VECTOR 0
116#endif
117
118#endif
119