1/* Copyright (C) 2013-2014 Povilas Kanapickas <povilas@radix.lt>
2
3 Distributed under the Boost Software License, Version 1.0.
4 (See accompanying file LICENSE_1_0.txt or copy at
5 http://www.boost.org/LICENSE_1_0.txt)
6*/
7
8#ifndef LIBSIMDPP_SIMDPP_CORE_CMP_GT_H
9#define LIBSIMDPP_SIMDPP_CORE_CMP_GT_H
10
11#ifndef LIBSIMDPP_SIMD_H
12 #error "This file must be included through simd.h"
13#endif
14
15#include <simdpp/types.h>
16#include <simdpp/detail/insn/cmp_gt.h>
17#include <simdpp/core/detail/scalar_arg_impl.h>
18
19namespace simdpp {
20namespace SIMDPP_ARCH_NAMESPACE {
21
22/** Compares the values of two signed int16x8 vectors for greater-than
23
24 @code
25 r0 = (a0 > b0) ? 0xff : 0x0
26 ...
27 rN = (aN > bN) ? 0xff : 0x0
28 @endcode
29
30 @par 256-bit version:
31 @icost{SSE2-AVX, NEON, ALTIVEC, 2}
32*/
33template<unsigned N, class E1, class E2> SIMDPP_INL
34mask_int8<N,expr_empty> cmp_gt(const int8<N,E1>& a,
35 const int8<N,E2>& b)
36{
37 return detail::insn::i_cmp_gt(a.eval(), b.eval());
38}
39
40SIMDPP_SCALAR_ARG_IMPL_VEC(cmp_gt, mask_int8, int8)
41
42
43/** Compares the values of two unsigned int16x8 vectors for greater-than
44
45 @code
46 r0 = (a0 > b0) ? 0xff : 0x0
47 ...
48 rN = (aN > bN) ? 0xff : 0x0
49 @endcode
50
51 @par 128-bit version:
52 @icost{SSE2-AVX2, 3-4}
53 @icost{XOP, 1}
54
55 @par 256-bit version:
56 @icost{SSE2-AVX, 6-7}
57 @icost{AVX2, 3-4}
58 @icost{XOP, 2}
59 @icost{NEON, ALTIVEC, 2}
60*/
61template<unsigned N, class E1, class E2> SIMDPP_INL
62mask_int8<N,expr_empty> cmp_gt(const uint8<N,E1>& a,
63 const uint8<N,E2>& b)
64{
65 return detail::insn::i_cmp_gt(a.eval(), b.eval());
66}
67
68SIMDPP_SCALAR_ARG_IMPL_VEC(cmp_gt, mask_int8, uint8)
69
70/** Compares the values of two signed int16x8 vectors for greater-than
71
72 @code
73 r0 = (a0 > b0) ? 0xffff : 0x0
74 ...
75 rN = (aN > bN) ? 0xffff : 0x0
76 @endcode
77
78 @par 256-bit version:
79 @icost{SSE2-AVX, NEON, ALTIVEC, 2}
80*/
81template<unsigned N, class E1, class E2> SIMDPP_INL
82mask_int16<N,expr_empty> cmp_gt(const int16<N,E1>& a,
83 const int16<N,E2>& b)
84{
85 return detail::insn::i_cmp_gt(a.eval(), b.eval());
86}
87
88SIMDPP_SCALAR_ARG_IMPL_VEC(cmp_gt, mask_int16, int16)
89
90/** Compares the values of two unsigned int16x8 vectors for greater-than
91
92 @code
93 r0 = (a0 > b0) ? 0xffff : 0x0
94 ...
95 rN = (aN > bN) ? 0xffff : 0x0
96 @endcode
97
98 @par 128-bit version:
99 @icost{SSE2-AVX2, 3-4}
100 @icost{XOP, 1}
101
102 @par 256-bit version:
103 @icost{SSE2-AVX, 6-7}
104 @icost{AVX2, 3-4}
105 @icost{XOP, NEON, ALTIVEC, 2}
106*/
107template<unsigned N, class E1, class E2> SIMDPP_INL
108mask_int16<N,expr_empty> cmp_gt(const uint16<N,E1>& a,
109 const uint16<N,E2>& b)
110{
111 return detail::insn::i_cmp_gt(a.eval(), b.eval());
112}
113
114SIMDPP_SCALAR_ARG_IMPL_VEC(cmp_gt, mask_int16, uint16)
115
116/** Compares the values of two signed int32x4 vectors for greater-than
117
118 @code
119 r0 = (a0 > b0) ? 0xffffffff : 0x0
120 ...
121 rN = (aN > bN) ? 0xffffffff : 0x0
122 @endcode
123
124 @par 256-bit version:
125 @icost{SSE2-AVX, NEON, ALTIVEC, 2}
126*/
127template<unsigned N, class E1, class E2> SIMDPP_INL
128mask_int32<N,expr_empty> cmp_gt(const int32<N,E1>& a,
129 const int32<N,E2>& b)
130{
131 return detail::insn::i_cmp_gt(a.eval(), b.eval());
132}
133
134SIMDPP_SCALAR_ARG_IMPL_VEC(cmp_gt, mask_int32, int32)
135
136/** Compares the values of two unsigned int32x4 vectors for greater-than
137
138 @code
139 r0 = (a0 > b0) ? 0xffffffff : 0x0
140 ...
141 rN = (aN > bN) ? 0xffffffff : 0x0
142 @endcode
143
144 @par 128-bit version:
145 @icost{SSE2-AVX2, 3-4}
146 @icost{XOP, 1}
147
148 @par 256-bit version:
149 @icost{SSE2-AVX, 6-7}
150 @icost{AVX2, 3-4}
151 @icost{XOP, NEON, ALTIVEC, 2}
152*/
153template<unsigned N, class E1, class E2> SIMDPP_INL
154mask_int32<N,expr_empty> cmp_gt(const uint32<N,E1>& a,
155 const uint32<N,E2>& b)
156{
157 return detail::insn::i_cmp_gt(a.eval(), b.eval());
158}
159
160SIMDPP_SCALAR_ARG_IMPL_VEC(cmp_gt, mask_int32, uint32)
161
162/** Compares the values of two signed int64 vectors for greater-than
163
164 @code
165 r0 = (a0 > b0) ? 0xffffffffffff : 0x0
166 ...
167 rN = (aN > bN) ? 0xffffffffffff : 0x0
168 @endcode
169
170 Supported since AVX2, NEON64. Not supported on ALTIVEC.
171*/
172template<unsigned N, class E1, class E2> SIMDPP_INL
173mask_int64<N,expr_empty> cmp_gt(const int64<N,E1>& a,
174 const int64<N,E2>& b)
175{
176 return detail::insn::i_cmp_gt(a.eval(), b.eval());
177}
178
179SIMDPP_SCALAR_ARG_IMPL_VEC(cmp_gt, mask_int64, int64)
180
181/** Compares the values of two unsigned int64 vectors for greater-than
182
183 @code
184 r0 = (a0 > b0) ? 0xffffffffffff : 0x0
185 ...
186 rN = (aN > bN) ? 0xffffffffffff : 0x0
187 @endcode
188
189 Supported since AVX2, NEON64. Not supported on ALTIVEC.
190*/
191template<unsigned N, class E1, class E2> SIMDPP_INL
192mask_int64<N,expr_empty> cmp_gt(const uint64<N,E1>& a,
193 const uint64<N,E2>& b)
194{
195 return detail::insn::i_cmp_gt(a.eval(), b.eval());
196}
197
198SIMDPP_SCALAR_ARG_IMPL_VEC(cmp_gt, mask_int64, uint64)
199
200/** Compares the values of two float32x4 vectors for greater-than
201
202 @code
203 r0 = (a0 > b0) ? 0xffffffff : 0x0
204 ...
205 rN = (aN > bN) ? 0xffffffff : 0x0
206 @endcode
207
208 @par 256-bit version:
209 @icost{SSE2-SSE4.1, NEON, ALTIVEC, 2}
210*/
211template<unsigned N, class E1, class E2>
212mask_float32<N,expr_empty> cmp_gt(const float32<N,E1>& a,
213 const float32<N,E2>& b)
214{
215 return detail::insn::i_cmp_gt(a.eval(), b.eval());
216}
217
218SIMDPP_SCALAR_ARG_IMPL_VEC(cmp_gt, mask_float32, float32)
219
220/** Compares the values of two float64x2 vectors for greater-than
221
222 @code
223 r0 = (a0 > b0) ? 0xffffffffffffffff : 0x0
224 ...
225 rN = (aN > bN) ? 0xffffffffffffffff : 0x0
226 @endcode
227
228 @par 128-bit version:
229 @novec{NEON, ALTIVEC}
230
231 @par 256-bit version:
232 @novec{NEON, ALTIVEC}
233 @icost{SSE2-SSE4.1, 2}
234*/
235template<unsigned N, class E1, class E2> SIMDPP_INL
236mask_float64<N,expr_empty> cmp_gt(const float64<N,E1>& a,
237 const float64<N,E2>& b)
238{
239 return detail::insn::i_cmp_gt(a.eval(), b.eval());
240}
241
242SIMDPP_SCALAR_ARG_IMPL_VEC(cmp_gt, mask_float64, float64)
243
244} // namespace SIMDPP_ARCH_NAMESPACE
245} // namespace simdpp
246
247#endif
248
249