1/* Copyright (C) 2013-2014 Povilas Kanapickas <povilas@radix.lt>
2
3 Distributed under the Boost Software License, Version 1.0.
4 (See accompanying file LICENSE_1_0.txt or copy at
5 http://www.boost.org/LICENSE_1_0.txt)
6*/
7
8#ifndef LIBSIMDPP_SIMDPP_CORE_CMP_LT_H
9#define LIBSIMDPP_SIMDPP_CORE_CMP_LT_H
10
11#ifndef LIBSIMDPP_SIMD_H
12 #error "This file must be included through simd.h"
13#endif
14
15#include <simdpp/types.h>
16#include <simdpp/detail/insn/cmp_lt.h>
17#include <simdpp/core/detail/scalar_arg_impl.h>
18
19namespace simdpp {
20namespace SIMDPP_ARCH_NAMESPACE {
21
22/** Compares the values of two signed int8x16 vectors for less-than
23
24 @code
25 r0 = (a0 < b0) ? 0xff : 0x0
26 ...
27 rN = (aN < bN) ? 0xff : 0x0
28 @endcode
29
30 @par 256-bit version:
31 @icost{SSE2-AVX, NEON, ALTIVEC, 2}
32*/
33template<unsigned N, class E1, class E2> SIMDPP_INL
34mask_int8<N,expr_empty> cmp_lt(const int8<N,E1>& a,
35 const int8<N,E2>& b)
36{
37 return detail::insn::i_cmp_lt(a.eval(), b.eval());
38}
39
40SIMDPP_SCALAR_ARG_IMPL_VEC(cmp_lt, mask_int8, int8)
41
42/** Compares the values of two unsigned int8x16 vectors for less-than
43
44 @code
45 r0 = (a0 < b0) ? 0xff : 0x0
46 ...
47 rN = (aN < bN) ? 0xff : 0x0
48 @endcode
49
50 @par 128-bit version:
51 @icost{SSE2-AVX2, 3-4}
52 @icost{XOP, 1}
53
54 @par 256-bit version:
55 @icost{SSE2-AVX, 6-7}
56 @icost{AVX2, 3-4}
57 @icost{XOP, NEON, ALTIVEC, 2}
58*/
59template<unsigned N, class E1, class E2> SIMDPP_INL
60mask_int8<N,expr_empty> cmp_lt(const uint8<N,E1>& a,
61 const uint8<N,E2>& b)
62{
63 return detail::insn::i_cmp_lt(a.eval(), b.eval());
64}
65
66SIMDPP_SCALAR_ARG_IMPL_VEC(cmp_lt, mask_int8, uint8)
67
68/** Compares the values of two signed int16x8 vectors for less-than
69
70 @code
71 r0 = (a0 < b0) ? 0xffff : 0x0
72 ...
73 rN = (aN < bN) ? 0xffff : 0x0
74 @endcode
75
76 @par 256-bit version:
77 @icost{SSE2-AVX, NEON, ALTIVEC, 2}
78*/
79template<unsigned N, class E1, class E2> SIMDPP_INL
80mask_int16<N,expr_empty> cmp_lt(const int16<N,E1>& a,
81 const int16<N,E2>& b)
82{
83 return detail::insn::i_cmp_lt(a.eval(), b.eval());
84}
85
86SIMDPP_SCALAR_ARG_IMPL_VEC(cmp_lt, mask_int16, int16)
87
88/** Compares the values of two unsigned int16x8 vectors for less-than
89
90 @code
91 r0 = (a0 < b0) ? 0xffff : 0x0
92 ...
93 rN = (aN < bN) ? 0xffff : 0x0
94 @endcode
95
96 @par 128-bit version:
97 @icost{SSE2-AVX2, 3-4}
98 @icost{XOP, 1}
99
100 @par 256-bit version:
101 @icost{SSE2-AVX, 6-7}
102 @icost{AVX2, 3-4}
103 @icost{XOP, NEON, ALTIVEC, 2}
104*/
105template<unsigned N, class E1, class E2> SIMDPP_INL
106mask_int16<N,expr_empty> cmp_lt(const uint16<N,E1>& a,
107 const uint16<N,E2>& b)
108{
109 return detail::insn::i_cmp_lt(a.eval(), b.eval());
110}
111
112SIMDPP_SCALAR_ARG_IMPL_VEC(cmp_lt, mask_int16, uint16)
113
114/** Compares the values of two signed int32x4 vectors for less-than
115
116 @code
117 r0 = (a0 < b0) ? 0xffffffff : 0x0
118 ...
119 rN = (aN < bN) ? 0xffffffff : 0x0
120 @endcode
121
122 @par 256-bit version:
123 @icost{SSE2-AVX, NEON, ALTIVEC, 2}
124*/
125template<unsigned N, class E1, class E2> SIMDPP_INL
126mask_int32<N,expr_empty> cmp_lt(const int32<N,E1>& a,
127 const int32<N,E2>& b)
128{
129 return detail::insn::i_cmp_lt(a.eval(), b.eval());
130}
131
132SIMDPP_SCALAR_ARG_IMPL_VEC(cmp_lt, mask_int32, int32)
133
134/** Compares the values of two unsigned int32x4 vectors for less-than
135
136 @code
137 r0 = (a0 < b0) ? 0xffffffff : 0x0
138 ...
139 rN = (aN < bN) ? 0xffffffff : 0x0
140 @endcode
141
142 @par 128-bit version:
143 @icost{SSE2-AVX2, 3-4}
144 @icost{XOP, 1}
145
146 @par 256-bit version:
147 @icost{SSE2-AVX, 6-7}
148 @icost{AVX2, 3-4}
149 @icost{XOP, NEON, ALTIVEC, 2}
150*/
151template<unsigned N, class E1, class E2> SIMDPP_INL
152mask_int32<N,expr_empty> cmp_lt(const uint32<N,E1>& a,
153 const uint32<N,E2>& b)
154{
155 return detail::insn::i_cmp_lt(a.eval(), b.eval());
156}
157
158SIMDPP_SCALAR_ARG_IMPL_VEC(cmp_lt, mask_int32, uint32)
159
160/** Compares the values of two signed int64 vectors for less-than
161
162 @code
163 r0 = (a0 > b0) ? 0xffffffffffff : 0x0
164 ...
165 rN = (aN > bN) ? 0xffffffffffff : 0x0
166 @endcode
167
168 Supported since AVX2, NEON64. Not supported on ALTIVEC.
169*/
170template<unsigned N, class E1, class E2> SIMDPP_INL
171mask_int64<N,expr_empty> cmp_lt(const int64<N,E1>& a,
172 const int64<N,E2>& b)
173{
174 return detail::insn::i_cmp_lt(a.eval(), b.eval());
175}
176
177SIMDPP_SCALAR_ARG_IMPL_VEC(cmp_lt, mask_int64, int64)
178
179/** Compares the values of two unsigned int64 vectors for less-than
180
181 @code
182 r0 = (a0 > b0) ? 0xffffffffffff : 0x0
183 ...
184 rN = (aN > bN) ? 0xffffffffffff : 0x0
185 @endcode
186
187 Supported since AVX2, NEON64. Not supported on ALTIVEC.
188*/
189template<unsigned N, class E1, class E2> SIMDPP_INL
190mask_int64<N,expr_empty> cmp_lt(const uint64<N,E1>& a,
191 const uint64<N,E2>& b)
192{
193 return detail::insn::i_cmp_lt(a.eval(), b.eval());
194}
195
196SIMDPP_SCALAR_ARG_IMPL_VEC(cmp_lt, mask_int64, uint64)
197
198/** Compares the values of two float32x4 vectors for less-than
199
200 @code
201 r0 = (a0 < b0) ? 0xffffffff : 0x0
202 ...
203 rN = (aN < bN) ? 0xffffffff : 0x0
204 @endcode
205
206 @par 256-bit version:
207 @icost{SSE2-AVX, NEON, ALTIVEC, 2}
208*/
209template<unsigned N, class E1, class E2> SIMDPP_INL
210mask_float32<N,expr_empty> cmp_lt(const float32<N,E1>& a,
211 const float32<N,E2>& b)
212{
213 return detail::insn::i_cmp_lt(a.eval(), b.eval());
214}
215
216SIMDPP_SCALAR_ARG_IMPL_VEC(cmp_lt, mask_float32, float32)
217
218/** Compares the values of two float64x2 vectors for less-than
219
220 @code
221 r0 = (a0 < b0) ? 0xffffffffffffffff : 0x0
222 ...
223 rN = (aN < bN) ? 0xffffffffffffffff : 0x0
224 @endcode
225
226 @par 128-bit version:
227 @novec{NEON, ALTIVEC}
228
229 @par 256-bit version:
230 @novec{NEON, ALTIVEC}
231 @icost{SSE2-SSE4.1, 2}
232*/
233template<unsigned N, class E1, class E2> SIMDPP_INL
234mask_float64<N,expr_empty> cmp_lt(const float64<N,E1>& a,
235 const float64<N,E2>& b)
236{
237 return detail::insn::i_cmp_lt(a.eval(), b.eval());
238}
239
240SIMDPP_SCALAR_ARG_IMPL_VEC(cmp_lt, mask_float64, float64)
241
242} // namespace SIMDPP_ARCH_NAMESPACE
243} // namespace simdpp
244
245#endif
246
247