1/* Copyright (C) 2013-2014 Povilas Kanapickas <povilas@radix.lt>
2
3 Distributed under the Boost Software License, Version 1.0.
4 (See accompanying file LICENSE_1_0.txt or copy at
5 http://www.boost.org/LICENSE_1_0.txt)
6*/
7
8#ifndef LIBSIMDPP_SIMDPP_CORE_ZIP_LO_H
9#define LIBSIMDPP_SIMDPP_CORE_ZIP_LO_H
10
11#ifndef LIBSIMDPP_SIMD_H
12 #error "This file must be included through simd.h"
13#endif
14
15#include <simdpp/types.h>
16#include <simdpp/detail/insn/zip_lo.h>
17#include <simdpp/detail/get_expr.h>
18
19namespace simdpp {
20namespace SIMDPP_ARCH_NAMESPACE {
21
22/** Interleaves the lower halves of two vectors.
23
24 @code
25 | 0 1 2 3 4 5 ... N-2 N-1 |
26 r = [ a0 b0 a1 b1 a2 b2 ... a(N/2-1) b(N/2-1) ]
27 @endcode
28
29 @par 256-bit version:
30 The lower and higher 128-bit halves are processed as if 128-bit instruction
31 was applied to each of them separately.
32
33 @icost{SSE2-AVX, NEON, ALTIVEC, 2}
34*/
35template<unsigned N, class V1, class V2> SIMDPP_INL
36typename detail::get_expr2_nomask<V1, V2>::empty
37 zip16_lo(const any_vec8<N,V1>& a, const any_vec8<N,V2>& b)
38{
39 typename detail::get_expr2_nomask_nosign<V1, V2>::type ra, rb;
40 ra = a.wrapped().eval();
41 rb = b.wrapped().eval();
42 return detail::insn::i_zip16_lo(ra, rb);
43}
44
45template<unsigned N, class V1, class V2> SIMDPP_INL
46typename detail::get_expr2_nomask<V1, V2>::empty
47 zip8_lo(const any_vec16<N,V1>& a, const any_vec16<N,V2>& b)
48{
49 typename detail::get_expr2_nomask_nosign<V1, V2>::type ra, rb;
50 ra = a.wrapped().eval();
51 rb = b.wrapped().eval();
52 return detail::insn::i_zip8_lo(ra, rb);
53}
54
55template<unsigned N, class V1, class V2> SIMDPP_INL
56typename detail::get_expr2_nomask<V1, V2>::empty
57 zip4_lo(const any_vec32<N,V1>& a, const any_vec32<N,V2>& b)
58{
59 typename detail::get_expr2_nomask_nosign<V1, V2>::type ra, rb;
60 ra = a.wrapped().eval();
61 rb = b.wrapped().eval();
62 return detail::insn::i_zip4_lo(ra, rb);
63}
64
65template<unsigned N, class V1, class V2> SIMDPP_INL
66typename detail::get_expr2_nomask<V1, V2>::empty
67 zip2_lo(const any_vec64<N,V1>& a, const any_vec64<N,V2>& b)
68{
69 typename detail::get_expr2_nomask_nosign<V1, V2>::type ra, rb;
70 ra = a.wrapped().eval();
71 rb = b.wrapped().eval();
72 return detail::insn::i_zip2_lo(ra, rb);
73}
74
75} // namespace SIMDPP_ARCH_NAMESPACE
76} // namespace simdpp
77
78#endif
79