1/* Copyright (C) 2015-2017 Povilas Kanapickas <povilas@radix.lt>
2
3 Distributed under the Boost Software License, Version 1.0.
4 (See accompanying file LICENSE_1_0.txt or copy at
5 http://www.boost.org/LICENSE_1_0.txt)
6*/
7
8#ifndef LIBSIMDPP_SIMDPP_DETAIL_INSN_ID_H
9#define LIBSIMDPP_SIMDPP_DETAIL_INSN_ID_H
10
11// Instruction set ids used when constructing architecture id. The architecture
12// id is then used to define SIMDPP_ARCH_NAMESPACE
13#define SIMDPP_INSN_ID_NULL _null
14#define SIMDPP_INSN_ID_SSE2 _sse2
15#define SIMDPP_INSN_ID_SSE3 _sse3
16#define SIMDPP_INSN_ID_SSSE3 _ssse3
17#define SIMDPP_INSN_ID_SSE4_1 _sse4p1
18#define SIMDPP_INSN_ID_POPCNT_INSN _popcnt
19#define SIMDPP_INSN_ID_AVX _avx
20#define SIMDPP_INSN_ID_AVX2 _avx2
21#define SIMDPP_INSN_ID_FMA3 _fma3
22#define SIMDPP_INSN_ID_FMA4 _fma4
23#define SIMDPP_INSN_ID_XOP _xop
24#define SIMDPP_INSN_ID_AVX512F _avx512f
25#define SIMDPP_INSN_ID_AVX512BW _avx512bw
26#define SIMDPP_INSN_ID_AVX512DQ _avx512dq
27#define SIMDPP_INSN_ID_AVX512VL _avx512vl
28#define SIMDPP_INSN_ID_NEON _neon
29#define SIMDPP_INSN_ID_NEON_FLT_SP _neonfltsp
30#define SIMDPP_INSN_ID_ALTIVEC _altivec
31#define SIMDPP_INSN_ID_VSX_206 _vsx_206
32#define SIMDPP_INSN_ID_VSX_207 _vsx_207
33#define SIMDPP_INSN_ID_MSA _msa
34
35// Arbitrary masks used to simplify architecture processing
36// (used in preprocess_single_arch.h)
37#define SIMDPP_INSN_MASK_NULL 0x00000001
38#define SIMDPP_INSN_MASK_SSE2 0x00000002
39#define SIMDPP_INSN_MASK_SSE3 0x00000004
40#define SIMDPP_INSN_MASK_SSSE3 0x00000008
41#define SIMDPP_INSN_MASK_SSE4_1 0x00000010
42#define SIMDPP_INSN_MASK_POPCNT_INSN 0x00000020
43#define SIMDPP_INSN_MASK_AVX 0x00000040
44#define SIMDPP_INSN_MASK_AVX2 0x00000080
45#define SIMDPP_INSN_MASK_FMA3 0x00000100
46#define SIMDPP_INSN_MASK_FMA4 0x00000200
47#define SIMDPP_INSN_MASK_XOP 0x00000400
48#define SIMDPP_INSN_MASK_AVX512F 0x00000800
49#define SIMDPP_INSN_MASK_AVX512BW 0x00001000
50#define SIMDPP_INSN_MASK_AVX512DQ 0x00002000
51#define SIMDPP_INSN_MASK_AVX512VL 0x00004000
52#define SIMDPP_INSN_MASK_NEON 0x00008000
53#define SIMDPP_INSN_MASK_NEON_FLT_SP 0x00010000
54#define SIMDPP_INSN_MASK_ALTIVEC 0x00020000
55#define SIMDPP_INSN_MASK_VSX_206 0x00040000
56#define SIMDPP_INSN_MASK_VSX_207 0x00080000
57#define SIMDPP_INSN_MASK_MSA 0x00100000
58
59#define SIMDPP_PREFIX_SIMDPP_ARCH_X86_NULL SIMDPP_INSN_MASK_NULL
60#define SIMDPP_PREFIX_SIMDPP_ARCH_X86_SSE2 SIMDPP_INSN_MASK_SSE2
61#define SIMDPP_PREFIX_SIMDPP_ARCH_X86_SSE3 SIMDPP_INSN_MASK_SSE3
62#define SIMDPP_PREFIX_SIMDPP_ARCH_X86_SSSE3 SIMDPP_INSN_MASK_SSSE3
63#define SIMDPP_PREFIX_SIMDPP_ARCH_X86_SSE4_1 SIMDPP_INSN_MASK_SSE4_1
64#define SIMDPP_PREFIX_SIMDPP_ARCH_X86_POPCNT_INSN SIMDPP_INSN_MASK_POPCNT_INSN
65#define SIMDPP_PREFIX_SIMDPP_ARCH_X86_AVX SIMDPP_INSN_MASK_AVX
66#define SIMDPP_PREFIX_SIMDPP_ARCH_X86_AVX2 SIMDPP_INSN_MASK_AVX2
67#define SIMDPP_PREFIX_SIMDPP_ARCH_X86_FMA3 SIMDPP_INSN_MASK_FMA3
68#define SIMDPP_PREFIX_SIMDPP_ARCH_X86_FMA4 SIMDPP_INSN_MASK_FMA4
69#define SIMDPP_PREFIX_SIMDPP_ARCH_X86_XOP SIMDPP_INSN_MASK_XOP
70#define SIMDPP_PREFIX_SIMDPP_ARCH_X86_AVX512F SIMDPP_INSN_MASK_AVX512F
71#define SIMDPP_PREFIX_SIMDPP_ARCH_X86_AVX512BW SIMDPP_INSN_MASK_AVX512BW
72#define SIMDPP_PREFIX_SIMDPP_ARCH_X86_AVX512DQ SIMDPP_INSN_MASK_AVX512DQ
73#define SIMDPP_PREFIX_SIMDPP_ARCH_X86_AVX512VL SIMDPP_INSN_MASK_AVX512VL
74#define SIMDPP_PREFIX_SIMDPP_ARCH_ARM_NEON SIMDPP_INSN_MASK_NEON
75#define SIMDPP_PREFIX_SIMDPP_ARCH_ARM_NEON_FLT_SP SIMDPP_INSN_MASK_NEON_FLT_SP
76#define SIMDPP_PREFIX_SIMDPP_ARCH_POWER_ALTIVEC SIMDPP_INSN_MASK_ALTIVEC
77#define SIMDPP_PREFIX_SIMDPP_ARCH_POWER_VSX_206 SIMDPP_INSN_MASK_VSX_206
78#define SIMDPP_PREFIX_SIMDPP_ARCH_POWER_VSX_207 SIMDPP_INSN_MASK_VSX_207
79#define SIMDPP_PREFIX_SIMDPP_ARCH_MIPS_MSA SIMDPP_INSN_MASK_MSA
80
81#endif
82
83