1// This file is generated by tools/gen_operators.pl. CHANGES WILL BE OVERWRITTEN
2/* Copyright (C) 2013-2014 Povilas Kanapickas <povilas@radix.lt>
3
4 Distributed under the Boost Software License, Version 1.0.
5 (See accompanying file LICENSE_1_0.txt or copy at
6 http://www.boost.org/LICENSE_1_0.txt)
7*/
8
9#ifndef LIBSIMDPP_SIMDPP_CORE_CMP_EQ_OPERATOR_H
10#define LIBSIMDPP_SIMDPP_CORE_CMP_EQ_OPERATOR_H
11
12#ifndef LIBSIMDPP_SIMD_H
13 #error "This file must be included through simd.h"
14#endif
15
16#include <simdpp/types.h>
17#include <simdpp/detail/insn/cmp_eq.h>
18#include <simdpp/core/detail/scalar_arg_impl.h>
19
20namespace simdpp {
21namespace SIMDPP_ARCH_NAMESPACE {
22
23
24/** Compares 8-bit values for equality.
25
26 @code
27 r0 = (a0 == b0) ? 0xff : 0x0
28 ...
29 rN = (aN == bN) ? 0xff : 0x0
30 @endcode
31
32 @par 256-bit version:
33 @icost{SSE2-AVX, NEON, ALTIVEC, 2}
34*/
35template<unsigned N, class V1, class V2> SIMDPP_INL
36mask_int8<N,expr_empty> operator==(const any_int8<N,V1>& a,
37 const any_int8<N,V2>& b)
38{
39 typename detail::get_expr2_nosign<V1, V2>::type ra, rb;
40 ra = a.wrapped().eval();
41 rb = b.wrapped().eval();
42 return detail::insn::i_cmp_eq(ra, rb);
43}
44
45SIMDPP_SCALAR_ARG_IMPL_VEC_EXPR(operator==, mask_int8, any_int8)
46
47/** Compares 16-bit values for equality.
48
49 @code
50 r0 = (a0 == b0) ? 0xffff : 0x0
51 ...
52 rN = (aN == bN) ? 0xffff : 0x0
53 @endcode
54
55 @par 256-bit version:
56 @icost{SSE2-AVX, NEON, ALTIVEC, 2}
57*/
58template<unsigned N, class V1, class V2> SIMDPP_INL
59mask_int16<N,expr_empty> operator==(const any_int16<N,V1>& a,
60 const any_int16<N,V2>& b)
61{
62 typename detail::get_expr2_nosign<V1, V2>::type ra, rb;
63 ra = a.wrapped().eval();
64 rb = b.wrapped().eval();
65 return detail::insn::i_cmp_eq(ra, rb);
66}
67
68SIMDPP_SCALAR_ARG_IMPL_VEC_EXPR(operator==, mask_int16, any_int16)
69
70/** Compares the values of two int32x4 vectors for equality
71
72 @code
73 r0 = (a0 == b0) ? 0xffffffff : 0x0
74 ...
75 rN = (aN == bN) ? 0xffffffff : 0x0
76 @endcode
77
78 @par 256-bit version:
79 @icost{SSE2-AVX, NEON, ALTIVEC, 2}
80*/
81template<unsigned N, class V1, class V2> SIMDPP_INL
82mask_int32<N,expr_empty> operator==(const any_int32<N,V1>& a,
83 const any_int32<N,V2>& b)
84{
85 typename detail::get_expr2_nosign<V1, V2>::type ra, rb;
86 ra = a.wrapped().eval();
87 rb = b.wrapped().eval();
88 return detail::insn::i_cmp_eq(ra, rb);
89}
90
91SIMDPP_SCALAR_ARG_IMPL_VEC_EXPR(operator==, mask_int32, any_int32)
92
93/** Compares the values of two int64x2 vectors for equality
94
95 @code
96 r0 = (a0 == b0) ? 0xffffffffffffffff : 0x0
97 ...
98 rN = (aN == bN) ? 0xffffffffffffffff : 0x0
99 @endcode
100
101 @par 128-bit version:
102 @icost{SSE2-SSSE3, 5}
103 @icost{XOP, 1}
104 @icost{NEON, 3}
105 @icost{ALTIVEC, 3-4}
106
107 @par 256-bit version:
108 @icost{SSE2-SSSE3, AVX, 10}
109 @icost{XOP, SSE4.1, 2}
110 @icost{NEON, 6}
111 @icost{ALTIVEC, 6-7}
112*/
113template<unsigned N, class V1, class V2> SIMDPP_INL
114mask_int64<N,expr_empty> operator==(const any_int64<N,V1>& a,
115 const any_int64<N,V2>& b)
116{
117 typename detail::get_expr2_nosign<V1, V2>::type ra, rb;
118 ra = a.wrapped().eval();
119 rb = b.wrapped().eval();
120 return detail::insn::i_cmp_eq(ra, rb);
121}
122
123SIMDPP_SCALAR_ARG_IMPL_VEC_EXPR(operator==, mask_int64, any_int64)
124
125/** Compares the values of two float32x4 vectors for equality
126
127 @code
128 r0 = (a0 == b0) ? 0xffffffff : 0x0
129 ...
130 rN = (aN == bN) ? 0xffffffff : 0x0
131 @endcode
132
133 @par 256-bit version:
134 @icost{SSE2-SSE4.1, NEON, ALTIVEC, 2}
135*/
136template<unsigned N, class V1, class V2> SIMDPP_INL
137mask_float32<N,expr_empty> operator==(const any_float32<N,V1>& a,
138 const any_float32<N,V2>& b)
139{
140 return detail::insn::i_cmp_eq(a.wrapped().eval(), b.wrapped().eval());
141}
142
143SIMDPP_SCALAR_ARG_IMPL_VEC_EXPR(operator==, mask_float32, any_float32)
144
145/** Compares the values of two float64x2 vectors for equality
146
147 @code
148 r0 = (a0 == b0) ? 0xffffffffffffffff : 0x0
149 ...
150 rN = (aN == bN) ? 0xffffffffffffffff : 0x0
151 @endcode
152
153 @par 128-bit version:
154 @novec{NEON, ALTIVEC}
155
156 @par 256-bit version:
157 @novec{NEON, ALTIVEC}
158 @icost{SSE2-SSE4.1, 2}
159*/
160template<unsigned N, class V1, class V2> SIMDPP_INL
161mask_float64<N,expr_empty> operator==(const any_float64<N,V1>& a,
162 const any_float64<N,V2>& b)
163{
164 return detail::insn::i_cmp_eq(a.wrapped().eval(), b.wrapped().eval());
165}
166
167SIMDPP_SCALAR_ARG_IMPL_VEC_EXPR(operator==, mask_float64, any_float64)
168
169
170} // namespace SIMDPP_ARCH_NAMESPACE
171} // namespace simdpp
172
173#endif
174
175