1// This file is generated by tools/gen_operators.pl. CHANGES WILL BE OVERWRITTEN
2/* Copyright (C) 2013-2014 Povilas Kanapickas <povilas@radix.lt>
3
4 Distributed under the Boost Software License, Version 1.0.
5 (See accompanying file LICENSE_1_0.txt or copy at
6 http://www.boost.org/LICENSE_1_0.txt)
7*/
8
9#ifndef LIBSIMDPP_SIMDPP_CORE_CMP_GT_OPERATOR_H
10#define LIBSIMDPP_SIMDPP_CORE_CMP_GT_OPERATOR_H
11
12#ifndef LIBSIMDPP_SIMD_H
13 #error "This file must be included through simd.h"
14#endif
15
16#include <simdpp/types.h>
17#include <simdpp/detail/insn/cmp_gt.h>
18#include <simdpp/core/detail/scalar_arg_impl.h>
19
20namespace simdpp {
21namespace SIMDPP_ARCH_NAMESPACE {
22
23/** Compares the values of two signed int16x8 vectors for greater-than
24
25 @code
26 r0 = (a0 > b0) ? 0xff : 0x0
27 ...
28 rN = (aN > bN) ? 0xff : 0x0
29 @endcode
30
31 @par 256-bit version:
32 @icost{SSE2-AVX, NEON, ALTIVEC, 2}
33*/
34template<unsigned N, class E1, class E2> SIMDPP_INL
35mask_int8<N,expr_empty> operator>(const int8<N,E1>& a,
36 const int8<N,E2>& b)
37{
38 return detail::insn::i_cmp_gt(a.eval(), b.eval());
39}
40
41SIMDPP_SCALAR_ARG_IMPL_VEC(operator>, mask_int8, int8)
42
43
44/** Compares the values of two unsigned int16x8 vectors for greater-than
45
46 @code
47 r0 = (a0 > b0) ? 0xff : 0x0
48 ...
49 rN = (aN > bN) ? 0xff : 0x0
50 @endcode
51
52 @par 128-bit version:
53 @icost{SSE2-AVX2, 3-4}
54 @icost{XOP, 1}
55
56 @par 256-bit version:
57 @icost{SSE2-AVX, 6-7}
58 @icost{AVX2, 3-4}
59 @icost{XOP, 2}
60 @icost{NEON, ALTIVEC, 2}
61*/
62template<unsigned N, class E1, class E2> SIMDPP_INL
63mask_int8<N,expr_empty> operator>(const uint8<N,E1>& a,
64 const uint8<N,E2>& b)
65{
66 return detail::insn::i_cmp_gt(a.eval(), b.eval());
67}
68
69SIMDPP_SCALAR_ARG_IMPL_VEC(operator>, mask_int8, uint8)
70
71/** Compares the values of two signed int16x8 vectors for greater-than
72
73 @code
74 r0 = (a0 > b0) ? 0xffff : 0x0
75 ...
76 rN = (aN > bN) ? 0xffff : 0x0
77 @endcode
78
79 @par 256-bit version:
80 @icost{SSE2-AVX, NEON, ALTIVEC, 2}
81*/
82template<unsigned N, class E1, class E2> SIMDPP_INL
83mask_int16<N,expr_empty> operator>(const int16<N,E1>& a,
84 const int16<N,E2>& b)
85{
86 return detail::insn::i_cmp_gt(a.eval(), b.eval());
87}
88
89SIMDPP_SCALAR_ARG_IMPL_VEC(operator>, mask_int16, int16)
90
91/** Compares the values of two unsigned int16x8 vectors for greater-than
92
93 @code
94 r0 = (a0 > b0) ? 0xffff : 0x0
95 ...
96 rN = (aN > bN) ? 0xffff : 0x0
97 @endcode
98
99 @par 128-bit version:
100 @icost{SSE2-AVX2, 3-4}
101 @icost{XOP, 1}
102
103 @par 256-bit version:
104 @icost{SSE2-AVX, 6-7}
105 @icost{AVX2, 3-4}
106 @icost{XOP, NEON, ALTIVEC, 2}
107*/
108template<unsigned N, class E1, class E2> SIMDPP_INL
109mask_int16<N,expr_empty> operator>(const uint16<N,E1>& a,
110 const uint16<N,E2>& b)
111{
112 return detail::insn::i_cmp_gt(a.eval(), b.eval());
113}
114
115SIMDPP_SCALAR_ARG_IMPL_VEC(operator>, mask_int16, uint16)
116
117/** Compares the values of two signed int32x4 vectors for greater-than
118
119 @code
120 r0 = (a0 > b0) ? 0xffffffff : 0x0
121 ...
122 rN = (aN > bN) ? 0xffffffff : 0x0
123 @endcode
124
125 @par 256-bit version:
126 @icost{SSE2-AVX, NEON, ALTIVEC, 2}
127*/
128template<unsigned N, class E1, class E2> SIMDPP_INL
129mask_int32<N,expr_empty> operator>(const int32<N,E1>& a,
130 const int32<N,E2>& b)
131{
132 return detail::insn::i_cmp_gt(a.eval(), b.eval());
133}
134
135SIMDPP_SCALAR_ARG_IMPL_VEC(operator>, mask_int32, int32)
136
137/** Compares the values of two unsigned int32x4 vectors for greater-than
138
139 @code
140 r0 = (a0 > b0) ? 0xffffffff : 0x0
141 ...
142 rN = (aN > bN) ? 0xffffffff : 0x0
143 @endcode
144
145 @par 128-bit version:
146 @icost{SSE2-AVX2, 3-4}
147 @icost{XOP, 1}
148
149 @par 256-bit version:
150 @icost{SSE2-AVX, 6-7}
151 @icost{AVX2, 3-4}
152 @icost{XOP, NEON, ALTIVEC, 2}
153*/
154template<unsigned N, class E1, class E2> SIMDPP_INL
155mask_int32<N,expr_empty> operator>(const uint32<N,E1>& a,
156 const uint32<N,E2>& b)
157{
158 return detail::insn::i_cmp_gt(a.eval(), b.eval());
159}
160
161SIMDPP_SCALAR_ARG_IMPL_VEC(operator>, mask_int32, uint32)
162
163/** Compares the values of two signed int64 vectors for greater-than
164
165 @code
166 r0 = (a0 > b0) ? 0xffffffffffff : 0x0
167 ...
168 rN = (aN > bN) ? 0xffffffffffff : 0x0
169 @endcode
170
171 Supported since AVX2, NEON64. Not supported on ALTIVEC.
172*/
173template<unsigned N, class E1, class E2> SIMDPP_INL
174mask_int64<N,expr_empty> operator>(const int64<N,E1>& a,
175 const int64<N,E2>& b)
176{
177 return detail::insn::i_cmp_gt(a.eval(), b.eval());
178}
179
180SIMDPP_SCALAR_ARG_IMPL_VEC(operator>, mask_int64, int64)
181
182/** Compares the values of two unsigned int64 vectors for greater-than
183
184 @code
185 r0 = (a0 > b0) ? 0xffffffffffff : 0x0
186 ...
187 rN = (aN > bN) ? 0xffffffffffff : 0x0
188 @endcode
189
190 Supported since AVX2, NEON64. Not supported on ALTIVEC.
191*/
192template<unsigned N, class E1, class E2> SIMDPP_INL
193mask_int64<N,expr_empty> operator>(const uint64<N,E1>& a,
194 const uint64<N,E2>& b)
195{
196 return detail::insn::i_cmp_gt(a.eval(), b.eval());
197}
198
199SIMDPP_SCALAR_ARG_IMPL_VEC(operator>, mask_int64, uint64)
200
201/** Compares the values of two float32x4 vectors for greater-than
202
203 @code
204 r0 = (a0 > b0) ? 0xffffffff : 0x0
205 ...
206 rN = (aN > bN) ? 0xffffffff : 0x0
207 @endcode
208
209 @par 256-bit version:
210 @icost{SSE2-SSE4.1, NEON, ALTIVEC, 2}
211*/
212template<unsigned N, class E1, class E2>
213mask_float32<N,expr_empty> operator>(const float32<N,E1>& a,
214 const float32<N,E2>& b)
215{
216 return detail::insn::i_cmp_gt(a.eval(), b.eval());
217}
218
219SIMDPP_SCALAR_ARG_IMPL_VEC(operator>, mask_float32, float32)
220
221/** Compares the values of two float64x2 vectors for greater-than
222
223 @code
224 r0 = (a0 > b0) ? 0xffffffffffffffff : 0x0
225 ...
226 rN = (aN > bN) ? 0xffffffffffffffff : 0x0
227 @endcode
228
229 @par 128-bit version:
230 @novec{NEON, ALTIVEC}
231
232 @par 256-bit version:
233 @novec{NEON, ALTIVEC}
234 @icost{SSE2-SSE4.1, 2}
235*/
236template<unsigned N, class E1, class E2> SIMDPP_INL
237mask_float64<N,expr_empty> operator>(const float64<N,E1>& a,
238 const float64<N,E2>& b)
239{
240 return detail::insn::i_cmp_gt(a.eval(), b.eval());
241}
242
243SIMDPP_SCALAR_ARG_IMPL_VEC(operator>, mask_float64, float64)
244
245} // namespace SIMDPP_ARCH_NAMESPACE
246} // namespace simdpp
247
248#endif
249
250