1// This file is generated by tools/gen_operators.pl. CHANGES WILL BE OVERWRITTEN
2/* Copyright (C) 2013-2014 Povilas Kanapickas <povilas@radix.lt>
3
4 Distributed under the Boost Software License, Version 1.0.
5 (See accompanying file LICENSE_1_0.txt or copy at
6 http://www.boost.org/LICENSE_1_0.txt)
7*/
8
9#ifndef LIBSIMDPP_SIMDPP_CORE_CMP_LE_OPERATOR_H
10#define LIBSIMDPP_SIMDPP_CORE_CMP_LE_OPERATOR_H
11
12#ifndef LIBSIMDPP_SIMD_H
13 #error "This file must be included through simd.h"
14#endif
15
16#include <simdpp/types.h>
17#include <simdpp/detail/insn/cmp_le.h>
18#include <simdpp/core/detail/scalar_arg_impl.h>
19
20namespace simdpp {
21namespace SIMDPP_ARCH_NAMESPACE {
22
23template<unsigned N, class E1, class E2> SIMDPP_INL
24mask_int8<N,expr_empty> operator<=(const int8<N,E1>& a,
25 const int8<N,E2>& b)
26{
27 return detail::insn::i_cmp_le(a.eval(), b.eval());
28}
29
30SIMDPP_SCALAR_ARG_IMPL_VEC(operator<=, mask_int8, int8)
31
32template<unsigned N, class E1, class E2> SIMDPP_INL
33mask_int8<N,expr_empty> operator<=(const uint8<N,E1>& a,
34 const uint8<N,E2>& b)
35{
36 return detail::insn::i_cmp_le(a.eval(), b.eval());
37}
38
39SIMDPP_SCALAR_ARG_IMPL_VEC(operator<=, mask_int8, uint8)
40
41template<unsigned N, class E1, class E2> SIMDPP_INL
42mask_int16<N,expr_empty> operator<=(const int16<N,E1>& a,
43 const int16<N,E2>& b)
44{
45 return detail::insn::i_cmp_le(a.eval(), b.eval());
46}
47
48SIMDPP_SCALAR_ARG_IMPL_VEC(operator<=, mask_int16, int16)
49
50template<unsigned N, class E1, class E2> SIMDPP_INL
51mask_int16<N,expr_empty> operator<=(const uint16<N,E1>& a,
52 const uint16<N,E2>& b)
53{
54 return detail::insn::i_cmp_le(a.eval(), b.eval());
55}
56
57SIMDPP_SCALAR_ARG_IMPL_VEC(operator<=, mask_int16, uint16)
58
59template<unsigned N, class E1, class E2> SIMDPP_INL
60mask_int32<N,expr_empty> operator<=(const int32<N,E1>& a,
61 const int32<N,E2>& b)
62{
63 return detail::insn::i_cmp_le(a.eval(), b.eval());
64}
65
66SIMDPP_SCALAR_ARG_IMPL_VEC(operator<=, mask_int32, int32)
67
68template<unsigned N, class E1, class E2> SIMDPP_INL
69mask_int32<N,expr_empty> operator<=(const uint32<N,E1>& a,
70 const uint32<N,E2>& b)
71{
72 return detail::insn::i_cmp_le(a.eval(), b.eval());
73}
74
75SIMDPP_SCALAR_ARG_IMPL_VEC(operator<=, mask_int32, uint32)
76
77template<unsigned N, class E1, class E2> SIMDPP_INL
78mask_int64<N,expr_empty> operator<=(const int64<N,E1>& a,
79 const int64<N,E2>& b)
80{
81 return detail::insn::i_cmp_le(a.eval(), b.eval());
82}
83
84SIMDPP_SCALAR_ARG_IMPL_VEC(operator<=, mask_int64, int64)
85
86template<unsigned N, class E1, class E2> SIMDPP_INL
87mask_int64<N,expr_empty> operator<=(const uint64<N,E1>& a,
88 const uint64<N,E2>& b)
89{
90 return detail::insn::i_cmp_le(a.eval(), b.eval());
91}
92SIMDPP_SCALAR_ARG_IMPL_VEC(operator<=, mask_int64, uint64)
93
94/** Compares the values of two float32x4 vectors for less-than or equal
95
96 @code
97 r0 = (a0 <= b0) ? 0xffffffff : 0x0
98 ...
99 rN = (aN <= bN) ? 0xffffffff : 0x0
100 @endcode
101
102 @par 256-bit version:
103 @icost{SSE2-AVX, NEON, ALTIVEC, 2}
104*/
105template<unsigned N, class E1, class E2> SIMDPP_INL
106mask_float32<N,expr_empty> operator<=(const float32<N,E1>& a,
107 const float32<N,E2>& b)
108{
109 return detail::insn::i_cmp_le(a.eval(), b.eval());
110}
111
112SIMDPP_SCALAR_ARG_IMPL_VEC(operator<=, mask_float32, float32)
113
114/** Compares the values of two float64x2 vectors for less-than or equal
115
116 @code
117 r0 = (a0 <= b0) ? 0xffffffffffffffff : 0x0
118 ...
119 rN = (aN <= bN) ? 0xffffffffffffffff : 0x0
120 @endcode
121
122 @par 128-bit version:
123 @novec{NEON, ALTIVEC}
124
125 @par 256-bit version:
126 @novec{NEON, ALTIVEC}
127 @icost{SSE2-SSE4.1, 2}
128*/
129template<unsigned N, class E1, class E2> SIMDPP_INL
130mask_float64<N,expr_empty> operator<=(const float64<N,E1>& a,
131 const float64<N,E2>& b)
132{
133 return detail::insn::i_cmp_le(a.eval(), b.eval());
134}
135
136SIMDPP_SCALAR_ARG_IMPL_VEC(operator<=, mask_float64, float64)
137
138} // namespace SIMDPP_ARCH_NAMESPACE
139} // namespace simdpp
140
141#endif
142
143