1// This file is generated by tools/gen_operators.pl. CHANGES WILL BE OVERWRITTEN
2/* Copyright (C) 2013-2014 Povilas Kanapickas <povilas@radix.lt>
3
4 Distributed under the Boost Software License, Version 1.0.
5 (See accompanying file LICENSE_1_0.txt or copy at
6 http://www.boost.org/LICENSE_1_0.txt)
7*/
8
9#ifndef LIBSIMDPP_SIMDPP_CORE_CMP_LT_OPERATOR_H
10#define LIBSIMDPP_SIMDPP_CORE_CMP_LT_OPERATOR_H
11
12#ifndef LIBSIMDPP_SIMD_H
13 #error "This file must be included through simd.h"
14#endif
15
16#include <simdpp/types.h>
17#include <simdpp/detail/insn/cmp_lt.h>
18#include <simdpp/core/detail/scalar_arg_impl.h>
19
20namespace simdpp {
21namespace SIMDPP_ARCH_NAMESPACE {
22
23/** Compares the values of two signed int8x16 vectors for less-than
24
25 @code
26 r0 = (a0 < b0) ? 0xff : 0x0
27 ...
28 rN = (aN < bN) ? 0xff : 0x0
29 @endcode
30
31 @par 256-bit version:
32 @icost{SSE2-AVX, NEON, ALTIVEC, 2}
33*/
34template<unsigned N, class E1, class E2> SIMDPP_INL
35mask_int8<N,expr_empty> operator<(const int8<N,E1>& a,
36 const int8<N,E2>& b)
37{
38 return detail::insn::i_cmp_lt(a.eval(), b.eval());
39}
40
41SIMDPP_SCALAR_ARG_IMPL_VEC(operator<, mask_int8, int8)
42
43/** Compares the values of two unsigned int8x16 vectors for less-than
44
45 @code
46 r0 = (a0 < b0) ? 0xff : 0x0
47 ...
48 rN = (aN < bN) ? 0xff : 0x0
49 @endcode
50
51 @par 128-bit version:
52 @icost{SSE2-AVX2, 3-4}
53 @icost{XOP, 1}
54
55 @par 256-bit version:
56 @icost{SSE2-AVX, 6-7}
57 @icost{AVX2, 3-4}
58 @icost{XOP, NEON, ALTIVEC, 2}
59*/
60template<unsigned N, class E1, class E2> SIMDPP_INL
61mask_int8<N,expr_empty> operator<(const uint8<N,E1>& a,
62 const uint8<N,E2>& b)
63{
64 return detail::insn::i_cmp_lt(a.eval(), b.eval());
65}
66
67SIMDPP_SCALAR_ARG_IMPL_VEC(operator<, mask_int8, uint8)
68
69/** Compares the values of two signed int16x8 vectors for less-than
70
71 @code
72 r0 = (a0 < b0) ? 0xffff : 0x0
73 ...
74 rN = (aN < bN) ? 0xffff : 0x0
75 @endcode
76
77 @par 256-bit version:
78 @icost{SSE2-AVX, NEON, ALTIVEC, 2}
79*/
80template<unsigned N, class E1, class E2> SIMDPP_INL
81mask_int16<N,expr_empty> operator<(const int16<N,E1>& a,
82 const int16<N,E2>& b)
83{
84 return detail::insn::i_cmp_lt(a.eval(), b.eval());
85}
86
87SIMDPP_SCALAR_ARG_IMPL_VEC(operator<, mask_int16, int16)
88
89/** Compares the values of two unsigned int16x8 vectors for less-than
90
91 @code
92 r0 = (a0 < b0) ? 0xffff : 0x0
93 ...
94 rN = (aN < bN) ? 0xffff : 0x0
95 @endcode
96
97 @par 128-bit version:
98 @icost{SSE2-AVX2, 3-4}
99 @icost{XOP, 1}
100
101 @par 256-bit version:
102 @icost{SSE2-AVX, 6-7}
103 @icost{AVX2, 3-4}
104 @icost{XOP, NEON, ALTIVEC, 2}
105*/
106template<unsigned N, class E1, class E2> SIMDPP_INL
107mask_int16<N,expr_empty> operator<(const uint16<N,E1>& a,
108 const uint16<N,E2>& b)
109{
110 return detail::insn::i_cmp_lt(a.eval(), b.eval());
111}
112
113SIMDPP_SCALAR_ARG_IMPL_VEC(operator<, mask_int16, uint16)
114
115/** Compares the values of two signed int32x4 vectors for less-than
116
117 @code
118 r0 = (a0 < b0) ? 0xffffffff : 0x0
119 ...
120 rN = (aN < bN) ? 0xffffffff : 0x0
121 @endcode
122
123 @par 256-bit version:
124 @icost{SSE2-AVX, NEON, ALTIVEC, 2}
125*/
126template<unsigned N, class E1, class E2> SIMDPP_INL
127mask_int32<N,expr_empty> operator<(const int32<N,E1>& a,
128 const int32<N,E2>& b)
129{
130 return detail::insn::i_cmp_lt(a.eval(), b.eval());
131}
132
133SIMDPP_SCALAR_ARG_IMPL_VEC(operator<, mask_int32, int32)
134
135/** Compares the values of two unsigned int32x4 vectors for less-than
136
137 @code
138 r0 = (a0 < b0) ? 0xffffffff : 0x0
139 ...
140 rN = (aN < bN) ? 0xffffffff : 0x0
141 @endcode
142
143 @par 128-bit version:
144 @icost{SSE2-AVX2, 3-4}
145 @icost{XOP, 1}
146
147 @par 256-bit version:
148 @icost{SSE2-AVX, 6-7}
149 @icost{AVX2, 3-4}
150 @icost{XOP, NEON, ALTIVEC, 2}
151*/
152template<unsigned N, class E1, class E2> SIMDPP_INL
153mask_int32<N,expr_empty> operator<(const uint32<N,E1>& a,
154 const uint32<N,E2>& b)
155{
156 return detail::insn::i_cmp_lt(a.eval(), b.eval());
157}
158
159SIMDPP_SCALAR_ARG_IMPL_VEC(operator<, mask_int32, uint32)
160
161/** Compares the values of two signed int64 vectors for less-than
162
163 @code
164 r0 = (a0 > b0) ? 0xffffffffffff : 0x0
165 ...
166 rN = (aN > bN) ? 0xffffffffffff : 0x0
167 @endcode
168
169 Supported since AVX2, NEON64. Not supported on ALTIVEC.
170*/
171template<unsigned N, class E1, class E2> SIMDPP_INL
172mask_int64<N,expr_empty> operator<(const int64<N,E1>& a,
173 const int64<N,E2>& b)
174{
175 return detail::insn::i_cmp_lt(a.eval(), b.eval());
176}
177
178SIMDPP_SCALAR_ARG_IMPL_VEC(operator<, mask_int64, int64)
179
180/** Compares the values of two unsigned int64 vectors for less-than
181
182 @code
183 r0 = (a0 > b0) ? 0xffffffffffff : 0x0
184 ...
185 rN = (aN > bN) ? 0xffffffffffff : 0x0
186 @endcode
187
188 Supported since AVX2, NEON64. Not supported on ALTIVEC.
189*/
190template<unsigned N, class E1, class E2> SIMDPP_INL
191mask_int64<N,expr_empty> operator<(const uint64<N,E1>& a,
192 const uint64<N,E2>& b)
193{
194 return detail::insn::i_cmp_lt(a.eval(), b.eval());
195}
196
197SIMDPP_SCALAR_ARG_IMPL_VEC(operator<, mask_int64, uint64)
198
199/** Compares the values of two float32x4 vectors for less-than
200
201 @code
202 r0 = (a0 < b0) ? 0xffffffff : 0x0
203 ...
204 rN = (aN < bN) ? 0xffffffff : 0x0
205 @endcode
206
207 @par 256-bit version:
208 @icost{SSE2-AVX, NEON, ALTIVEC, 2}
209*/
210template<unsigned N, class E1, class E2> SIMDPP_INL
211mask_float32<N,expr_empty> operator<(const float32<N,E1>& a,
212 const float32<N,E2>& b)
213{
214 return detail::insn::i_cmp_lt(a.eval(), b.eval());
215}
216
217SIMDPP_SCALAR_ARG_IMPL_VEC(operator<, mask_float32, float32)
218
219/** Compares the values of two float64x2 vectors for less-than
220
221 @code
222 r0 = (a0 < b0) ? 0xffffffffffffffff : 0x0
223 ...
224 rN = (aN < bN) ? 0xffffffffffffffff : 0x0
225 @endcode
226
227 @par 128-bit version:
228 @novec{NEON, ALTIVEC}
229
230 @par 256-bit version:
231 @novec{NEON, ALTIVEC}
232 @icost{SSE2-SSE4.1, 2}
233*/
234template<unsigned N, class E1, class E2> SIMDPP_INL
235mask_float64<N,expr_empty> operator<(const float64<N,E1>& a,
236 const float64<N,E2>& b)
237{
238 return detail::insn::i_cmp_lt(a.eval(), b.eval());
239}
240
241SIMDPP_SCALAR_ARG_IMPL_VEC(operator<, mask_float64, float64)
242
243} // namespace SIMDPP_ARCH_NAMESPACE
244} // namespace simdpp
245
246#endif
247
248