1// This file is generated by tools/gen_operators.pl. CHANGES WILL BE OVERWRITTEN
2/* Copyright (C) 2013-2014 Povilas Kanapickas <povilas@radix.lt>
3
4 Distributed under the Boost Software License, Version 1.0.
5 (See accompanying file LICENSE_1_0.txt or copy at
6 http://www.boost.org/LICENSE_1_0.txt)
7*/
8
9#ifndef LIBSIMDPP_SIMDPP_CORE_CMP_NEQ_OPERATOR_H
10#define LIBSIMDPP_SIMDPP_CORE_CMP_NEQ_OPERATOR_H
11
12#ifndef LIBSIMDPP_SIMD_H
13 #error "This file must be included through simd.h"
14#endif
15
16#include <simdpp/types.h>
17#include <simdpp/detail/insn/cmp_neq.h>
18#include <simdpp/core/detail/scalar_arg_impl.h>
19
20namespace simdpp {
21namespace SIMDPP_ARCH_NAMESPACE {
22
23
24/** Compares the values of two int8x16 vectors for inequality
25
26 @code
27 r0 = (a0 != b0) ? 0xff : 0x0
28 ...
29 rN = (aN != bN) ? 0xff : 0x0
30 @endcode
31
32 @par 128-bit version:
33 @icost{SSE2-AVX, NEON, ALTIVEC, 2}
34 @icost{XOP, 1}
35
36 @par 256-bit version
37 @icost{SSE2-AVX, NEON, ALTIVEC, 4}
38 @icost{AVX2, 2}
39 @icost{XOP, 2}
40*/
41template<unsigned N, class V1, class V2> SIMDPP_INL
42mask_int8<N,expr_empty> operator!=(const any_int8<N,V1>& a,
43 const any_int8<N,V2>& b)
44{
45 typename detail::get_expr2_nosign<V1, V2>::type ra, rb;
46 ra = a.wrapped().eval();
47 rb = b.wrapped().eval();
48 return detail::insn::i_cmp_neq(ra, rb);
49}
50
51SIMDPP_SCALAR_ARG_IMPL_VEC_EXPR(operator!=, mask_int8, any_int8)
52
53/** Compares the values of two int16x8 vectors for inequality
54
55 @code
56 r0 = (a0 != b0) ? 0xffff : 0x0
57 ...
58 rN = (aN != bN) ? 0xffff : 0x0
59 @endcode
60
61 @par 128-bit version:
62 @icost{SSE2-AVX, NEON, ALTIVEC, 2}
63 @icost{XOP, 1}
64
65 @par 256-bit version
66 @icost{SSE2-AVX, NEON, ALTIVEC, 4}
67 @icost{AVX2, 2}
68 @icost{XOP, 2}
69*/
70template<unsigned N, class V1, class V2> SIMDPP_INL
71mask_int16<N,expr_empty> operator!=(const any_int16<N,V1>& a,
72 const any_int16<N,V2>& b)
73{
74 typename detail::get_expr2_nosign<V1, V2>::type ra, rb;
75 ra = a.wrapped().eval();
76 rb = b.wrapped().eval();
77 return detail::insn::i_cmp_neq(ra, rb);
78}
79
80SIMDPP_SCALAR_ARG_IMPL_VEC_EXPR(operator!=, mask_int16, any_int16)
81
82/** Compares the values of two int32x4 vectors for inequality
83
84 @code
85 r0 = (a0 != b0) ? 0xffffffff : 0x0
86 ...
87 rN = (aN != bN) ? 0xffffffff : 0x0
88 @endcode
89
90 @par 128-bit version:
91 @icost{SSE2-AVX, NEON, ALTIVEC, 2}
92 @icost{XOP, 1}
93
94 @par 256-bit version
95 @icost{SSE2-AVX, NEON, ALTIVEC, 4}
96 @icost{AVX2, 2}
97 @icost{XOP, 2}
98*/
99template<unsigned N, class V1, class V2> SIMDPP_INL
100mask_int32<N,expr_empty> operator!=(const any_int32<N,V1>& a,
101 const any_int32<N,V2>& b)
102{
103 typename detail::get_expr2_nosign<V1, V2>::type ra, rb;
104 ra = a.wrapped().eval();
105 rb = b.wrapped().eval();
106 return detail::insn::i_cmp_neq(ra, rb);
107}
108
109SIMDPP_SCALAR_ARG_IMPL_VEC_EXPR(operator!=, mask_int32, any_int32)
110
111/** Compares the values of two int64x2 vectors for inequality
112
113 @code
114 r0 = (a0 != b0) ? 0xffffffffffffffff : 0x0
115 ...
116 rN = (aN != bN) ? 0xffffffffffffffff : 0x0
117 @endcode
118
119 @par 128-bit version:
120 @icost{SSE2-SSSE3, 5}
121 @icost{SSE4.1, AVX, 2}
122 @icost{XOP, 1}
123 @icost{NEON, 4}
124 @icost{ALTIVEC, 3-5}
125
126 @par 256-bit version:
127 @icost{SSE2-SSSE3, AVX, 10}
128 @icost{SSE4.1, NEON, 4}
129 @icost{AVX2, XOP, 2}
130 @icost{NEON, 8}
131 @icost{ALTIVEC, 6-8}
132*/
133template<unsigned N, class V1, class V2> SIMDPP_INL
134mask_int64<N,expr_empty> operator!=(const any_int64<N,V1>& a,
135 const any_int64<N,V2>& b)
136{
137 typename detail::get_expr2_nosign<V1, V2>::type ra, rb;
138 ra = a.wrapped().eval();
139 rb = b.wrapped().eval();
140 return detail::insn::i_cmp_neq(ra, rb);
141}
142
143SIMDPP_SCALAR_ARG_IMPL_VEC_EXPR(operator!=, mask_int64, any_int64)
144
145/** Compares the values of two float32x4 vectors for inequality
146
147 @code
148 r0 = (a0 != b0) ? 0xffffffff : 0x0
149 ...
150 rN = (aN != bN) ? 0xffffffff : 0x0
151 @endcode
152
153 @par 128-bit version:
154 @icost{NEON, ALTIVEC, 2}
155
156 @par 256-bit version
157 @icost{SSE2-SSE4.1, 2}
158 @icost{NEON, ALTIVEC, 4}
159*/
160template<unsigned N, class V1, class V2> SIMDPP_INL
161mask_float32<N,expr_empty> operator!=(const any_float32<N,V1>& a,
162 const any_float32<N,V2>& b)
163{
164 return detail::insn::i_cmp_neq(a.wrapped().eval(), b.wrapped().eval());
165}
166
167SIMDPP_SCALAR_ARG_IMPL_VEC_EXPR(operator!=, mask_float32, any_float32)
168
169/** Compares the values of two float64x2 vectors for inequality
170
171 @code
172 r0 = (a0 != b0) ? 0xffffffffffffffff : 0x0
173 ...
174 rN = (aN != bN) ? 0xffffffffffffffff : 0x0
175 @endcode
176
177 @par 128-bit version:
178 @novec{NEON, ALTIVEC}
179
180 @par 256-bit version:
181 @novec{NEON, ALTIVEC}
182 @icost{SSE2-SSE4.1, 2}
183*/
184template<unsigned N, class V1, class V2> SIMDPP_INL
185mask_float64<N,expr_empty> operator!=(const any_float64<N,V1>& a,
186 const any_float64<N,V2>& b)
187{
188 return detail::insn::i_cmp_neq(a.wrapped().eval(), b.wrapped().eval());
189}
190
191SIMDPP_SCALAR_ARG_IMPL_VEC_EXPR(operator!=, mask_float64, any_float64)
192
193} // namespace SIMDPP_ARCH_NAMESPACE
194} // namespace simdpp
195
196#endif
197
198