1// This file is generated by tools/gen_operators.pl. CHANGES WILL BE OVERWRITTEN
2/* Copyright (C) 2013-2014 Povilas Kanapickas <povilas@radix.lt>
3
4 Distributed under the Boost Software License, Version 1.0.
5 (See accompanying file LICENSE_1_0.txt or copy at
6 http://www.boost.org/LICENSE_1_0.txt)
7*/
8
9#ifndef LIBSIMDPP_SIMDPP_CORE_I_ADD_OPERATOR_H
10#define LIBSIMDPP_SIMDPP_CORE_I_ADD_OPERATOR_H
11
12#ifndef LIBSIMDPP_SIMD_H
13 #error "This file must be included through simd.h"
14#endif
15
16#include <simdpp/types.h>
17#include <simdpp/detail/expr/i_add.h>
18#include <simdpp/core/detail/get_expr_uint.h>
19#include <simdpp/core/detail/scalar_arg_impl.h>
20#include <simdpp/core/detail/get_expr_uint.h>
21
22namespace simdpp {
23namespace SIMDPP_ARCH_NAMESPACE {
24
25
26/** Adds 8-bit integer values.
27
28 @code
29 r0 = a0 + b0
30 ...
31 rN = aN + bN
32 @endcode
33
34 @par 256-bit version:
35 @icost{SSE2-AVX, NEON, ALTIVEC, 2}
36*/
37template<unsigned N, class V1, class V2> SIMDPP_INL
38typename detail::get_expr_uint<expr_iadd, V1, V2>::type
39 operator+(const any_int8<N,V1>& a,
40 const any_int8<N,V2>& b)
41{
42 return { { a.wrapped(), b.wrapped() } };
43}
44
45SIMDPP_SCALAR_ARG_IMPL_INT_UNSIGNED(operator+, expr_iadd, any_int8, int8)
46
47/** Adds 16-bit integer values.
48
49 @code
50 r0 = a0 + b0
51 ...
52 rN = aN + bN
53 @endcode
54
55 @par 256-bit version:
56 @icost{SSE2-AVX, NEON, ALTIVEC, 2}
57*/
58template<unsigned N, class V1, class V2> SIMDPP_INL
59typename detail::get_expr_uint<expr_iadd, V1, V2>::type
60 operator+(const any_int16<N,V1>& a,
61 const any_int16<N,V2>& b)
62{
63 return { { a.wrapped(), b.wrapped() } };
64}
65
66SIMDPP_SCALAR_ARG_IMPL_INT_UNSIGNED(operator+, expr_iadd, any_int16, int16)
67
68/** Adds 32-bit integer values.
69
70 @code
71 r0 = a0 + b0
72 ...
73 rN = aN + bN
74 @endcode
75
76 @par 256-bit version:
77 @icost{SSE2-AVX, NEON, ALTIVEC, 2}
78*/
79template<unsigned N, class V1, class V2> SIMDPP_INL
80typename detail::get_expr_uint<expr_iadd, V1, V2>::type
81 operator+(const any_int32<N,V1>& a,
82 const any_int32<N,V2>& b)
83{
84 return { { a.wrapped(), b.wrapped() } };
85}
86
87SIMDPP_SCALAR_ARG_IMPL_INT_UNSIGNED(operator+, expr_iadd, any_int32, int32)
88
89/** Adds 64-bit integer values.
90
91 @code
92 r0 = a0 + b0
93 ...
94 rN = aN + bN
95 @endcode
96
97 @par 128-bit version:
98 @icost{ALTIVEC, 5-6}
99
100 @par 256-bit version:
101 @icost{SSE2-AVX, NEON, 2}
102 @icost{ALTIVEC, 10-11}
103*/
104template<unsigned N, class V1, class V2> SIMDPP_INL
105typename detail::get_expr_uint<expr_iadd, V1, V2>::type
106 operator+(const any_int64<N,V1>& a,
107 const any_int64<N,V2>& b)
108{
109 return { { a.wrapped(), b.wrapped() } };
110}
111
112SIMDPP_SCALAR_ARG_IMPL_INT_UNSIGNED(operator+, expr_iadd, any_int64, int64)
113
114} // namespace SIMDPP_ARCH_NAMESPACE
115} // namespace simdpp
116
117#endif
118
119