| 1 | /* |
| 2 | * Copyright (c) 2017, Intel Corporation |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * * Redistributions of source code must retain the above copyright notice, |
| 8 | * this list of conditions and the following disclaimer. |
| 9 | * * Redistributions in binary form must reproduce the above copyright |
| 10 | * notice, this list of conditions and the following disclaimer in the |
| 11 | * documentation and/or other materials provided with the distribution. |
| 12 | * * Neither the name of Intel Corporation nor the names of its contributors |
| 13 | * may be used to endorse or promote products derived from this software |
| 14 | * without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 17 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 18 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
| 20 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 23 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 24 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 25 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 26 | * POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
| 28 | |
| 29 | /** \file |
| 30 | * \brief Per-platform architecture definitions |
| 31 | */ |
| 32 | |
| 33 | #ifndef UTIL_ARCH_H_ |
| 34 | #define UTIL_ARCH_H_ |
| 35 | |
| 36 | #if defined(__SSE2__) || defined(_M_X64) || (_M_IX86_FP >= 2) |
| 37 | #define HAVE_SSE2 |
| 38 | #endif |
| 39 | |
| 40 | #if defined(__SSE4_1__) || (defined(_WIN32) && defined(__AVX__)) |
| 41 | #define HAVE_SSE41 |
| 42 | #endif |
| 43 | |
| 44 | #if defined(__SSE4_2__) || (defined(_WIN32) && defined(__AVX__)) |
| 45 | #define HAVE_SSE42 |
| 46 | #endif |
| 47 | |
| 48 | #if defined(__AVX__) |
| 49 | #define HAVE_AVX |
| 50 | #endif |
| 51 | |
| 52 | #if defined(__AVX2__) |
| 53 | #define HAVE_AVX2 |
| 54 | #endif |
| 55 | |
| 56 | #if defined(__AVX512BW__) |
| 57 | #define HAVE_AVX512 |
| 58 | #endif |
| 59 | |
| 60 | /* |
| 61 | * ICC and MSVC don't break out POPCNT or BMI/2 as separate pre-def macros |
| 62 | */ |
| 63 | #if defined(__POPCNT__) || \ |
| 64 | (defined(__INTEL_COMPILER) && defined(__SSE4_2__)) || \ |
| 65 | (defined(_WIN32) && defined(__AVX__)) |
| 66 | #define HAVE_POPCOUNT_INSTR |
| 67 | #endif |
| 68 | |
| 69 | #if defined(__BMI__) || (defined(_WIN32) && defined(__AVX2__)) || \ |
| 70 | (defined(__INTEL_COMPILER) && defined(__AVX2__)) |
| 71 | #define HAVE_BMI |
| 72 | #endif |
| 73 | |
| 74 | #if defined(__BMI2__) || (defined(_WIN32) && defined(__AVX2__)) || \ |
| 75 | (defined(__INTEL_COMPILER) && defined(__AVX2__)) |
| 76 | #define HAVE_BMI2 |
| 77 | #endif |
| 78 | |
| 79 | /* |
| 80 | * MSVC uses a different form of inline asm |
| 81 | */ |
| 82 | #if defined(_WIN32) && defined(_MSC_VER) |
| 83 | #define NO_ASM |
| 84 | #endif |
| 85 | |
| 86 | #endif // UTIL_ARCH_H_ |
| 87 | |