1 | //===---------------------------- libunwind.h -----------------------------===// |
2 | // |
3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | // See https://llvm.org/LICENSE.txt for license information. |
5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | // |
7 | // |
8 | // Compatible with libunwind API documented at: |
9 | // http://www.nongnu.org/libunwind/man/libunwind(3).html |
10 | // |
11 | //===----------------------------------------------------------------------===// |
12 | |
13 | #ifndef __LIBUNWIND__ |
14 | #define __LIBUNWIND__ |
15 | |
16 | #include <__libunwind_config.h> |
17 | |
18 | #include <stdint.h> |
19 | #include <stddef.h> |
20 | |
21 | #ifdef __APPLE__ |
22 | #if __clang__ |
23 | #if __has_include(<Availability.h>) |
24 | #include <Availability.h> |
25 | #endif |
26 | #elif __ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__ >= 1050 |
27 | #include <Availability.h> |
28 | #endif |
29 | |
30 | #ifdef __arm__ |
31 | #define LIBUNWIND_AVAIL __attribute__((unavailable)) |
32 | #elif defined(__OSX_AVAILABLE_STARTING) |
33 | #define LIBUNWIND_AVAIL __OSX_AVAILABLE_STARTING(__MAC_10_6, __IPHONE_5_0) |
34 | #else |
35 | #include <AvailabilityMacros.h> |
36 | #ifdef AVAILABLE_MAC_OS_X_VERSION_10_6_AND_LATER |
37 | #define LIBUNWIND_AVAIL AVAILABLE_MAC_OS_X_VERSION_10_6_AND_LATER |
38 | #else |
39 | #define LIBUNWIND_AVAIL __attribute__((unavailable)) |
40 | #endif |
41 | #endif |
42 | #else |
43 | #define LIBUNWIND_AVAIL |
44 | #endif |
45 | |
46 | #define LIBUNWIND_MAX_STACK_SIZE 1024 |
47 | |
48 | /* error codes */ |
49 | enum { |
50 | UNW_ESUCCESS = 0, /* no error */ |
51 | UNW_EUNSPEC = -6540, /* unspecified (general) error */ |
52 | UNW_ENOMEM = -6541, /* out of memory */ |
53 | UNW_EBADREG = -6542, /* bad register number */ |
54 | UNW_EREADONLYREG = -6543, /* attempt to write read-only register */ |
55 | UNW_ESTOPUNWIND = -6544, /* stop unwinding */ |
56 | UNW_EINVALIDIP = -6545, /* invalid IP */ |
57 | UNW_EBADFRAME = -6546, /* bad frame */ |
58 | UNW_EINVAL = -6547, /* unsupported operation or bad value */ |
59 | UNW_EBADVERSION = -6548, /* unwind info has unsupported version */ |
60 | UNW_ENOINFO = -6549 /* no unwind info found */ |
61 | #if defined(_LIBUNWIND_TARGET_AARCH64) && !defined(_LIBUNWIND_IS_NATIVE_ONLY) |
62 | , UNW_ECROSSRASIGNING = -6550 /* cross unwind with return address signing */ |
63 | #endif |
64 | }; |
65 | |
66 | struct unw_context_t { |
67 | uint64_t data[_LIBUNWIND_CONTEXT_SIZE]; |
68 | }; |
69 | typedef struct unw_context_t unw_context_t; |
70 | |
71 | struct unw_cursor_t { |
72 | uint64_t data[_LIBUNWIND_CURSOR_SIZE]; |
73 | }; |
74 | typedef struct unw_cursor_t unw_cursor_t; |
75 | |
76 | typedef struct unw_addr_space *unw_addr_space_t; |
77 | |
78 | typedef int unw_regnum_t; |
79 | typedef uintptr_t unw_word_t; |
80 | #if defined(__arm__) && !defined(__ARM_DWARF_EH__) |
81 | typedef uint64_t unw_fpreg_t; |
82 | #else |
83 | typedef double unw_fpreg_t; |
84 | #endif |
85 | |
86 | struct unw_proc_info_t { |
87 | unw_word_t start_ip; /* start address of function */ |
88 | unw_word_t end_ip; /* address after end of function */ |
89 | unw_word_t lsda; /* address of language specific data area, */ |
90 | /* or zero if not used */ |
91 | unw_word_t handler; /* personality routine, or zero if not used */ |
92 | unw_word_t gp; /* not used */ |
93 | unw_word_t flags; /* not used */ |
94 | uint32_t format; /* compact unwind encoding, or zero if none */ |
95 | uint32_t unwind_info_size; /* size of DWARF unwind info, or zero if none */ |
96 | unw_word_t unwind_info; /* address of DWARF unwind info, or zero */ |
97 | unw_word_t ; /* mach_header of mach-o image containing func */ |
98 | }; |
99 | typedef struct unw_proc_info_t unw_proc_info_t; |
100 | |
101 | #ifdef __cplusplus |
102 | extern "C" { |
103 | #endif |
104 | |
105 | extern int unw_getcontext(unw_context_t *) LIBUNWIND_AVAIL; |
106 | extern int unw_init_local(unw_cursor_t *, unw_context_t *) LIBUNWIND_AVAIL; |
107 | extern int unw_step(unw_cursor_t *) LIBUNWIND_AVAIL; |
108 | extern int unw_get_reg(unw_cursor_t *, unw_regnum_t, unw_word_t *) LIBUNWIND_AVAIL; |
109 | extern int unw_get_fpreg(unw_cursor_t *, unw_regnum_t, unw_fpreg_t *) LIBUNWIND_AVAIL; |
110 | extern int unw_set_reg(unw_cursor_t *, unw_regnum_t, unw_word_t) LIBUNWIND_AVAIL; |
111 | extern int unw_set_fpreg(unw_cursor_t *, unw_regnum_t, unw_fpreg_t) LIBUNWIND_AVAIL; |
112 | extern int unw_resume(unw_cursor_t *) LIBUNWIND_AVAIL; |
113 | |
114 | #ifdef __arm__ |
115 | /* Save VFP registers in FSTMX format (instead of FSTMD). */ |
116 | extern void unw_save_vfp_as_X(unw_cursor_t *) LIBUNWIND_AVAIL; |
117 | #endif |
118 | |
119 | |
120 | extern const char *unw_regname(unw_cursor_t *, unw_regnum_t) LIBUNWIND_AVAIL; |
121 | extern int unw_get_proc_info(unw_cursor_t *, unw_proc_info_t *) LIBUNWIND_AVAIL; |
122 | extern int unw_is_fpreg(unw_cursor_t *, unw_regnum_t) LIBUNWIND_AVAIL; |
123 | extern int unw_is_signal_frame(unw_cursor_t *) LIBUNWIND_AVAIL; |
124 | extern int unw_get_proc_name(unw_cursor_t *, char *, size_t, unw_word_t *) LIBUNWIND_AVAIL; |
125 | //extern int unw_get_save_loc(unw_cursor_t*, int, unw_save_loc_t*); |
126 | extern int unw_backtrace(void **, int) LIBUNWIND_AVAIL; |
127 | |
128 | extern unw_addr_space_t unw_local_addr_space; |
129 | |
130 | #ifdef __cplusplus |
131 | } |
132 | #endif |
133 | |
134 | // architecture independent register numbers |
135 | enum { |
136 | UNW_REG_IP = -1, // instruction pointer |
137 | UNW_REG_SP = -2, // stack pointer |
138 | }; |
139 | |
140 | // 32-bit x86 registers |
141 | enum { |
142 | UNW_X86_EAX = 0, |
143 | UNW_X86_ECX = 1, |
144 | UNW_X86_EDX = 2, |
145 | UNW_X86_EBX = 3, |
146 | UNW_X86_EBP = 4, |
147 | UNW_X86_ESP = 5, |
148 | UNW_X86_ESI = 6, |
149 | UNW_X86_EDI = 7 |
150 | }; |
151 | |
152 | // 64-bit x86_64 registers |
153 | enum { |
154 | UNW_X86_64_RAX = 0, |
155 | UNW_X86_64_RDX = 1, |
156 | UNW_X86_64_RCX = 2, |
157 | UNW_X86_64_RBX = 3, |
158 | UNW_X86_64_RSI = 4, |
159 | UNW_X86_64_RDI = 5, |
160 | UNW_X86_64_RBP = 6, |
161 | UNW_X86_64_RSP = 7, |
162 | UNW_X86_64_R8 = 8, |
163 | UNW_X86_64_R9 = 9, |
164 | UNW_X86_64_R10 = 10, |
165 | UNW_X86_64_R11 = 11, |
166 | UNW_X86_64_R12 = 12, |
167 | UNW_X86_64_R13 = 13, |
168 | UNW_X86_64_R14 = 14, |
169 | UNW_X86_64_R15 = 15, |
170 | UNW_X86_64_RIP = 16, |
171 | UNW_X86_64_XMM0 = 17, |
172 | UNW_X86_64_XMM1 = 18, |
173 | UNW_X86_64_XMM2 = 19, |
174 | UNW_X86_64_XMM3 = 20, |
175 | UNW_X86_64_XMM4 = 21, |
176 | UNW_X86_64_XMM5 = 22, |
177 | UNW_X86_64_XMM6 = 23, |
178 | UNW_X86_64_XMM7 = 24, |
179 | UNW_X86_64_XMM8 = 25, |
180 | UNW_X86_64_XMM9 = 26, |
181 | UNW_X86_64_XMM10 = 27, |
182 | UNW_X86_64_XMM11 = 28, |
183 | UNW_X86_64_XMM12 = 29, |
184 | UNW_X86_64_XMM13 = 30, |
185 | UNW_X86_64_XMM14 = 31, |
186 | UNW_X86_64_XMM15 = 32, |
187 | }; |
188 | |
189 | |
190 | // 32-bit ppc register numbers |
191 | enum { |
192 | UNW_PPC_R0 = 0, |
193 | UNW_PPC_R1 = 1, |
194 | UNW_PPC_R2 = 2, |
195 | UNW_PPC_R3 = 3, |
196 | UNW_PPC_R4 = 4, |
197 | UNW_PPC_R5 = 5, |
198 | UNW_PPC_R6 = 6, |
199 | UNW_PPC_R7 = 7, |
200 | UNW_PPC_R8 = 8, |
201 | UNW_PPC_R9 = 9, |
202 | UNW_PPC_R10 = 10, |
203 | UNW_PPC_R11 = 11, |
204 | UNW_PPC_R12 = 12, |
205 | UNW_PPC_R13 = 13, |
206 | UNW_PPC_R14 = 14, |
207 | UNW_PPC_R15 = 15, |
208 | UNW_PPC_R16 = 16, |
209 | UNW_PPC_R17 = 17, |
210 | UNW_PPC_R18 = 18, |
211 | UNW_PPC_R19 = 19, |
212 | UNW_PPC_R20 = 20, |
213 | UNW_PPC_R21 = 21, |
214 | UNW_PPC_R22 = 22, |
215 | UNW_PPC_R23 = 23, |
216 | UNW_PPC_R24 = 24, |
217 | UNW_PPC_R25 = 25, |
218 | UNW_PPC_R26 = 26, |
219 | UNW_PPC_R27 = 27, |
220 | UNW_PPC_R28 = 28, |
221 | UNW_PPC_R29 = 29, |
222 | UNW_PPC_R30 = 30, |
223 | UNW_PPC_R31 = 31, |
224 | UNW_PPC_F0 = 32, |
225 | UNW_PPC_F1 = 33, |
226 | UNW_PPC_F2 = 34, |
227 | UNW_PPC_F3 = 35, |
228 | UNW_PPC_F4 = 36, |
229 | UNW_PPC_F5 = 37, |
230 | UNW_PPC_F6 = 38, |
231 | UNW_PPC_F7 = 39, |
232 | UNW_PPC_F8 = 40, |
233 | UNW_PPC_F9 = 41, |
234 | UNW_PPC_F10 = 42, |
235 | UNW_PPC_F11 = 43, |
236 | UNW_PPC_F12 = 44, |
237 | UNW_PPC_F13 = 45, |
238 | UNW_PPC_F14 = 46, |
239 | UNW_PPC_F15 = 47, |
240 | UNW_PPC_F16 = 48, |
241 | UNW_PPC_F17 = 49, |
242 | UNW_PPC_F18 = 50, |
243 | UNW_PPC_F19 = 51, |
244 | UNW_PPC_F20 = 52, |
245 | UNW_PPC_F21 = 53, |
246 | UNW_PPC_F22 = 54, |
247 | UNW_PPC_F23 = 55, |
248 | UNW_PPC_F24 = 56, |
249 | UNW_PPC_F25 = 57, |
250 | UNW_PPC_F26 = 58, |
251 | UNW_PPC_F27 = 59, |
252 | UNW_PPC_F28 = 60, |
253 | UNW_PPC_F29 = 61, |
254 | UNW_PPC_F30 = 62, |
255 | UNW_PPC_F31 = 63, |
256 | UNW_PPC_MQ = 64, |
257 | UNW_PPC_LR = 65, |
258 | UNW_PPC_CTR = 66, |
259 | UNW_PPC_AP = 67, |
260 | UNW_PPC_CR0 = 68, |
261 | UNW_PPC_CR1 = 69, |
262 | UNW_PPC_CR2 = 70, |
263 | UNW_PPC_CR3 = 71, |
264 | UNW_PPC_CR4 = 72, |
265 | UNW_PPC_CR5 = 73, |
266 | UNW_PPC_CR6 = 74, |
267 | UNW_PPC_CR7 = 75, |
268 | UNW_PPC_XER = 76, |
269 | UNW_PPC_V0 = 77, |
270 | UNW_PPC_V1 = 78, |
271 | UNW_PPC_V2 = 79, |
272 | UNW_PPC_V3 = 80, |
273 | UNW_PPC_V4 = 81, |
274 | UNW_PPC_V5 = 82, |
275 | UNW_PPC_V6 = 83, |
276 | UNW_PPC_V7 = 84, |
277 | UNW_PPC_V8 = 85, |
278 | UNW_PPC_V9 = 86, |
279 | UNW_PPC_V10 = 87, |
280 | UNW_PPC_V11 = 88, |
281 | UNW_PPC_V12 = 89, |
282 | UNW_PPC_V13 = 90, |
283 | UNW_PPC_V14 = 91, |
284 | UNW_PPC_V15 = 92, |
285 | UNW_PPC_V16 = 93, |
286 | UNW_PPC_V17 = 94, |
287 | UNW_PPC_V18 = 95, |
288 | UNW_PPC_V19 = 96, |
289 | UNW_PPC_V20 = 97, |
290 | UNW_PPC_V21 = 98, |
291 | UNW_PPC_V22 = 99, |
292 | UNW_PPC_V23 = 100, |
293 | UNW_PPC_V24 = 101, |
294 | UNW_PPC_V25 = 102, |
295 | UNW_PPC_V26 = 103, |
296 | UNW_PPC_V27 = 104, |
297 | UNW_PPC_V28 = 105, |
298 | UNW_PPC_V29 = 106, |
299 | UNW_PPC_V30 = 107, |
300 | UNW_PPC_V31 = 108, |
301 | UNW_PPC_VRSAVE = 109, |
302 | UNW_PPC_VSCR = 110, |
303 | UNW_PPC_SPE_ACC = 111, |
304 | UNW_PPC_SPEFSCR = 112 |
305 | }; |
306 | |
307 | // 64-bit ppc register numbers |
308 | enum { |
309 | UNW_PPC64_R0 = 0, |
310 | UNW_PPC64_R1 = 1, |
311 | UNW_PPC64_R2 = 2, |
312 | UNW_PPC64_R3 = 3, |
313 | UNW_PPC64_R4 = 4, |
314 | UNW_PPC64_R5 = 5, |
315 | UNW_PPC64_R6 = 6, |
316 | UNW_PPC64_R7 = 7, |
317 | UNW_PPC64_R8 = 8, |
318 | UNW_PPC64_R9 = 9, |
319 | UNW_PPC64_R10 = 10, |
320 | UNW_PPC64_R11 = 11, |
321 | UNW_PPC64_R12 = 12, |
322 | UNW_PPC64_R13 = 13, |
323 | UNW_PPC64_R14 = 14, |
324 | UNW_PPC64_R15 = 15, |
325 | UNW_PPC64_R16 = 16, |
326 | UNW_PPC64_R17 = 17, |
327 | UNW_PPC64_R18 = 18, |
328 | UNW_PPC64_R19 = 19, |
329 | UNW_PPC64_R20 = 20, |
330 | UNW_PPC64_R21 = 21, |
331 | UNW_PPC64_R22 = 22, |
332 | UNW_PPC64_R23 = 23, |
333 | UNW_PPC64_R24 = 24, |
334 | UNW_PPC64_R25 = 25, |
335 | UNW_PPC64_R26 = 26, |
336 | UNW_PPC64_R27 = 27, |
337 | UNW_PPC64_R28 = 28, |
338 | UNW_PPC64_R29 = 29, |
339 | UNW_PPC64_R30 = 30, |
340 | UNW_PPC64_R31 = 31, |
341 | UNW_PPC64_F0 = 32, |
342 | UNW_PPC64_F1 = 33, |
343 | UNW_PPC64_F2 = 34, |
344 | UNW_PPC64_F3 = 35, |
345 | UNW_PPC64_F4 = 36, |
346 | UNW_PPC64_F5 = 37, |
347 | UNW_PPC64_F6 = 38, |
348 | UNW_PPC64_F7 = 39, |
349 | UNW_PPC64_F8 = 40, |
350 | UNW_PPC64_F9 = 41, |
351 | UNW_PPC64_F10 = 42, |
352 | UNW_PPC64_F11 = 43, |
353 | UNW_PPC64_F12 = 44, |
354 | UNW_PPC64_F13 = 45, |
355 | UNW_PPC64_F14 = 46, |
356 | UNW_PPC64_F15 = 47, |
357 | UNW_PPC64_F16 = 48, |
358 | UNW_PPC64_F17 = 49, |
359 | UNW_PPC64_F18 = 50, |
360 | UNW_PPC64_F19 = 51, |
361 | UNW_PPC64_F20 = 52, |
362 | UNW_PPC64_F21 = 53, |
363 | UNW_PPC64_F22 = 54, |
364 | UNW_PPC64_F23 = 55, |
365 | UNW_PPC64_F24 = 56, |
366 | UNW_PPC64_F25 = 57, |
367 | UNW_PPC64_F26 = 58, |
368 | UNW_PPC64_F27 = 59, |
369 | UNW_PPC64_F28 = 60, |
370 | UNW_PPC64_F29 = 61, |
371 | UNW_PPC64_F30 = 62, |
372 | UNW_PPC64_F31 = 63, |
373 | // 64: reserved |
374 | UNW_PPC64_LR = 65, |
375 | UNW_PPC64_CTR = 66, |
376 | // 67: reserved |
377 | UNW_PPC64_CR0 = 68, |
378 | UNW_PPC64_CR1 = 69, |
379 | UNW_PPC64_CR2 = 70, |
380 | UNW_PPC64_CR3 = 71, |
381 | UNW_PPC64_CR4 = 72, |
382 | UNW_PPC64_CR5 = 73, |
383 | UNW_PPC64_CR6 = 74, |
384 | UNW_PPC64_CR7 = 75, |
385 | UNW_PPC64_XER = 76, |
386 | UNW_PPC64_V0 = 77, |
387 | UNW_PPC64_V1 = 78, |
388 | UNW_PPC64_V2 = 79, |
389 | UNW_PPC64_V3 = 80, |
390 | UNW_PPC64_V4 = 81, |
391 | UNW_PPC64_V5 = 82, |
392 | UNW_PPC64_V6 = 83, |
393 | UNW_PPC64_V7 = 84, |
394 | UNW_PPC64_V8 = 85, |
395 | UNW_PPC64_V9 = 86, |
396 | UNW_PPC64_V10 = 87, |
397 | UNW_PPC64_V11 = 88, |
398 | UNW_PPC64_V12 = 89, |
399 | UNW_PPC64_V13 = 90, |
400 | UNW_PPC64_V14 = 91, |
401 | UNW_PPC64_V15 = 92, |
402 | UNW_PPC64_V16 = 93, |
403 | UNW_PPC64_V17 = 94, |
404 | UNW_PPC64_V18 = 95, |
405 | UNW_PPC64_V19 = 96, |
406 | UNW_PPC64_V20 = 97, |
407 | UNW_PPC64_V21 = 98, |
408 | UNW_PPC64_V22 = 99, |
409 | UNW_PPC64_V23 = 100, |
410 | UNW_PPC64_V24 = 101, |
411 | UNW_PPC64_V25 = 102, |
412 | UNW_PPC64_V26 = 103, |
413 | UNW_PPC64_V27 = 104, |
414 | UNW_PPC64_V28 = 105, |
415 | UNW_PPC64_V29 = 106, |
416 | UNW_PPC64_V30 = 107, |
417 | UNW_PPC64_V31 = 108, |
418 | // 109, 111-113: OpenPOWER ELF V2 ABI: reserved |
419 | // Borrowing VRSAVE number from PPC32. |
420 | UNW_PPC64_VRSAVE = 109, |
421 | UNW_PPC64_VSCR = 110, |
422 | UNW_PPC64_TFHAR = 114, |
423 | UNW_PPC64_TFIAR = 115, |
424 | UNW_PPC64_TEXASR = 116, |
425 | UNW_PPC64_VS0 = UNW_PPC64_F0, |
426 | UNW_PPC64_VS1 = UNW_PPC64_F1, |
427 | UNW_PPC64_VS2 = UNW_PPC64_F2, |
428 | UNW_PPC64_VS3 = UNW_PPC64_F3, |
429 | UNW_PPC64_VS4 = UNW_PPC64_F4, |
430 | UNW_PPC64_VS5 = UNW_PPC64_F5, |
431 | UNW_PPC64_VS6 = UNW_PPC64_F6, |
432 | UNW_PPC64_VS7 = UNW_PPC64_F7, |
433 | UNW_PPC64_VS8 = UNW_PPC64_F8, |
434 | UNW_PPC64_VS9 = UNW_PPC64_F9, |
435 | UNW_PPC64_VS10 = UNW_PPC64_F10, |
436 | UNW_PPC64_VS11 = UNW_PPC64_F11, |
437 | UNW_PPC64_VS12 = UNW_PPC64_F12, |
438 | UNW_PPC64_VS13 = UNW_PPC64_F13, |
439 | UNW_PPC64_VS14 = UNW_PPC64_F14, |
440 | UNW_PPC64_VS15 = UNW_PPC64_F15, |
441 | UNW_PPC64_VS16 = UNW_PPC64_F16, |
442 | UNW_PPC64_VS17 = UNW_PPC64_F17, |
443 | UNW_PPC64_VS18 = UNW_PPC64_F18, |
444 | UNW_PPC64_VS19 = UNW_PPC64_F19, |
445 | UNW_PPC64_VS20 = UNW_PPC64_F20, |
446 | UNW_PPC64_VS21 = UNW_PPC64_F21, |
447 | UNW_PPC64_VS22 = UNW_PPC64_F22, |
448 | UNW_PPC64_VS23 = UNW_PPC64_F23, |
449 | UNW_PPC64_VS24 = UNW_PPC64_F24, |
450 | UNW_PPC64_VS25 = UNW_PPC64_F25, |
451 | UNW_PPC64_VS26 = UNW_PPC64_F26, |
452 | UNW_PPC64_VS27 = UNW_PPC64_F27, |
453 | UNW_PPC64_VS28 = UNW_PPC64_F28, |
454 | UNW_PPC64_VS29 = UNW_PPC64_F29, |
455 | UNW_PPC64_VS30 = UNW_PPC64_F30, |
456 | UNW_PPC64_VS31 = UNW_PPC64_F31, |
457 | UNW_PPC64_VS32 = UNW_PPC64_V0, |
458 | UNW_PPC64_VS33 = UNW_PPC64_V1, |
459 | UNW_PPC64_VS34 = UNW_PPC64_V2, |
460 | UNW_PPC64_VS35 = UNW_PPC64_V3, |
461 | UNW_PPC64_VS36 = UNW_PPC64_V4, |
462 | UNW_PPC64_VS37 = UNW_PPC64_V5, |
463 | UNW_PPC64_VS38 = UNW_PPC64_V6, |
464 | UNW_PPC64_VS39 = UNW_PPC64_V7, |
465 | UNW_PPC64_VS40 = UNW_PPC64_V8, |
466 | UNW_PPC64_VS41 = UNW_PPC64_V9, |
467 | UNW_PPC64_VS42 = UNW_PPC64_V10, |
468 | UNW_PPC64_VS43 = UNW_PPC64_V11, |
469 | UNW_PPC64_VS44 = UNW_PPC64_V12, |
470 | UNW_PPC64_VS45 = UNW_PPC64_V13, |
471 | UNW_PPC64_VS46 = UNW_PPC64_V14, |
472 | UNW_PPC64_VS47 = UNW_PPC64_V15, |
473 | UNW_PPC64_VS48 = UNW_PPC64_V16, |
474 | UNW_PPC64_VS49 = UNW_PPC64_V17, |
475 | UNW_PPC64_VS50 = UNW_PPC64_V18, |
476 | UNW_PPC64_VS51 = UNW_PPC64_V19, |
477 | UNW_PPC64_VS52 = UNW_PPC64_V20, |
478 | UNW_PPC64_VS53 = UNW_PPC64_V21, |
479 | UNW_PPC64_VS54 = UNW_PPC64_V22, |
480 | UNW_PPC64_VS55 = UNW_PPC64_V23, |
481 | UNW_PPC64_VS56 = UNW_PPC64_V24, |
482 | UNW_PPC64_VS57 = UNW_PPC64_V25, |
483 | UNW_PPC64_VS58 = UNW_PPC64_V26, |
484 | UNW_PPC64_VS59 = UNW_PPC64_V27, |
485 | UNW_PPC64_VS60 = UNW_PPC64_V28, |
486 | UNW_PPC64_VS61 = UNW_PPC64_V29, |
487 | UNW_PPC64_VS62 = UNW_PPC64_V30, |
488 | UNW_PPC64_VS63 = UNW_PPC64_V31 |
489 | }; |
490 | |
491 | // 64-bit ARM64 registers |
492 | enum { |
493 | UNW_ARM64_X0 = 0, |
494 | UNW_ARM64_X1 = 1, |
495 | UNW_ARM64_X2 = 2, |
496 | UNW_ARM64_X3 = 3, |
497 | UNW_ARM64_X4 = 4, |
498 | UNW_ARM64_X5 = 5, |
499 | UNW_ARM64_X6 = 6, |
500 | UNW_ARM64_X7 = 7, |
501 | UNW_ARM64_X8 = 8, |
502 | UNW_ARM64_X9 = 9, |
503 | UNW_ARM64_X10 = 10, |
504 | UNW_ARM64_X11 = 11, |
505 | UNW_ARM64_X12 = 12, |
506 | UNW_ARM64_X13 = 13, |
507 | UNW_ARM64_X14 = 14, |
508 | UNW_ARM64_X15 = 15, |
509 | UNW_ARM64_X16 = 16, |
510 | UNW_ARM64_X17 = 17, |
511 | UNW_ARM64_X18 = 18, |
512 | UNW_ARM64_X19 = 19, |
513 | UNW_ARM64_X20 = 20, |
514 | UNW_ARM64_X21 = 21, |
515 | UNW_ARM64_X22 = 22, |
516 | UNW_ARM64_X23 = 23, |
517 | UNW_ARM64_X24 = 24, |
518 | UNW_ARM64_X25 = 25, |
519 | UNW_ARM64_X26 = 26, |
520 | UNW_ARM64_X27 = 27, |
521 | UNW_ARM64_X28 = 28, |
522 | UNW_ARM64_X29 = 29, |
523 | UNW_ARM64_FP = 29, |
524 | UNW_ARM64_X30 = 30, |
525 | UNW_ARM64_LR = 30, |
526 | UNW_ARM64_X31 = 31, |
527 | UNW_ARM64_SP = 31, |
528 | // reserved block |
529 | UNW_ARM64_RA_SIGN_STATE = 34, |
530 | // reserved block |
531 | UNW_ARM64_D0 = 64, |
532 | UNW_ARM64_D1 = 65, |
533 | UNW_ARM64_D2 = 66, |
534 | UNW_ARM64_D3 = 67, |
535 | UNW_ARM64_D4 = 68, |
536 | UNW_ARM64_D5 = 69, |
537 | UNW_ARM64_D6 = 70, |
538 | UNW_ARM64_D7 = 71, |
539 | UNW_ARM64_D8 = 72, |
540 | UNW_ARM64_D9 = 73, |
541 | UNW_ARM64_D10 = 74, |
542 | UNW_ARM64_D11 = 75, |
543 | UNW_ARM64_D12 = 76, |
544 | UNW_ARM64_D13 = 77, |
545 | UNW_ARM64_D14 = 78, |
546 | UNW_ARM64_D15 = 79, |
547 | UNW_ARM64_D16 = 80, |
548 | UNW_ARM64_D17 = 81, |
549 | UNW_ARM64_D18 = 82, |
550 | UNW_ARM64_D19 = 83, |
551 | UNW_ARM64_D20 = 84, |
552 | UNW_ARM64_D21 = 85, |
553 | UNW_ARM64_D22 = 86, |
554 | UNW_ARM64_D23 = 87, |
555 | UNW_ARM64_D24 = 88, |
556 | UNW_ARM64_D25 = 89, |
557 | UNW_ARM64_D26 = 90, |
558 | UNW_ARM64_D27 = 91, |
559 | UNW_ARM64_D28 = 92, |
560 | UNW_ARM64_D29 = 93, |
561 | UNW_ARM64_D30 = 94, |
562 | UNW_ARM64_D31 = 95, |
563 | }; |
564 | |
565 | // 32-bit ARM registers. Numbers match DWARF for ARM spec #3.1 Table 1. |
566 | // Naming scheme uses recommendations given in Note 4 for VFP-v2 and VFP-v3. |
567 | // In this scheme, even though the 64-bit floating point registers D0-D31 |
568 | // overlap physically with the 32-bit floating pointer registers S0-S31, |
569 | // they are given a non-overlapping range of register numbers. |
570 | // |
571 | // Commented out ranges are not preserved during unwinding. |
572 | enum { |
573 | UNW_ARM_R0 = 0, |
574 | UNW_ARM_R1 = 1, |
575 | UNW_ARM_R2 = 2, |
576 | UNW_ARM_R3 = 3, |
577 | UNW_ARM_R4 = 4, |
578 | UNW_ARM_R5 = 5, |
579 | UNW_ARM_R6 = 6, |
580 | UNW_ARM_R7 = 7, |
581 | UNW_ARM_R8 = 8, |
582 | UNW_ARM_R9 = 9, |
583 | UNW_ARM_R10 = 10, |
584 | UNW_ARM_R11 = 11, |
585 | UNW_ARM_R12 = 12, |
586 | UNW_ARM_SP = 13, // Logical alias for UNW_REG_SP |
587 | UNW_ARM_R13 = 13, |
588 | UNW_ARM_LR = 14, |
589 | UNW_ARM_R14 = 14, |
590 | UNW_ARM_IP = 15, // Logical alias for UNW_REG_IP |
591 | UNW_ARM_R15 = 15, |
592 | // 16-63 -- OBSOLETE. Used in VFP1 to represent both S0-S31 and D0-D31. |
593 | UNW_ARM_S0 = 64, |
594 | UNW_ARM_S1 = 65, |
595 | UNW_ARM_S2 = 66, |
596 | UNW_ARM_S3 = 67, |
597 | UNW_ARM_S4 = 68, |
598 | UNW_ARM_S5 = 69, |
599 | UNW_ARM_S6 = 70, |
600 | UNW_ARM_S7 = 71, |
601 | UNW_ARM_S8 = 72, |
602 | UNW_ARM_S9 = 73, |
603 | UNW_ARM_S10 = 74, |
604 | UNW_ARM_S11 = 75, |
605 | UNW_ARM_S12 = 76, |
606 | UNW_ARM_S13 = 77, |
607 | UNW_ARM_S14 = 78, |
608 | UNW_ARM_S15 = 79, |
609 | UNW_ARM_S16 = 80, |
610 | UNW_ARM_S17 = 81, |
611 | UNW_ARM_S18 = 82, |
612 | UNW_ARM_S19 = 83, |
613 | UNW_ARM_S20 = 84, |
614 | UNW_ARM_S21 = 85, |
615 | UNW_ARM_S22 = 86, |
616 | UNW_ARM_S23 = 87, |
617 | UNW_ARM_S24 = 88, |
618 | UNW_ARM_S25 = 89, |
619 | UNW_ARM_S26 = 90, |
620 | UNW_ARM_S27 = 91, |
621 | UNW_ARM_S28 = 92, |
622 | UNW_ARM_S29 = 93, |
623 | UNW_ARM_S30 = 94, |
624 | UNW_ARM_S31 = 95, |
625 | // 96-103 -- OBSOLETE. F0-F7. Used by the FPA system. Superseded by VFP. |
626 | // 104-111 -- wCGR0-wCGR7, ACC0-ACC7 (Intel wireless MMX) |
627 | UNW_ARM_WR0 = 112, |
628 | UNW_ARM_WR1 = 113, |
629 | UNW_ARM_WR2 = 114, |
630 | UNW_ARM_WR3 = 115, |
631 | UNW_ARM_WR4 = 116, |
632 | UNW_ARM_WR5 = 117, |
633 | UNW_ARM_WR6 = 118, |
634 | UNW_ARM_WR7 = 119, |
635 | UNW_ARM_WR8 = 120, |
636 | UNW_ARM_WR9 = 121, |
637 | UNW_ARM_WR10 = 122, |
638 | UNW_ARM_WR11 = 123, |
639 | UNW_ARM_WR12 = 124, |
640 | UNW_ARM_WR13 = 125, |
641 | UNW_ARM_WR14 = 126, |
642 | UNW_ARM_WR15 = 127, |
643 | // 128-133 -- SPSR, SPSR_{FIQ|IRQ|ABT|UND|SVC} |
644 | // 134-143 -- Reserved |
645 | // 144-150 -- R8_USR-R14_USR |
646 | // 151-157 -- R8_FIQ-R14_FIQ |
647 | // 158-159 -- R13_IRQ-R14_IRQ |
648 | // 160-161 -- R13_ABT-R14_ABT |
649 | // 162-163 -- R13_UND-R14_UND |
650 | // 164-165 -- R13_SVC-R14_SVC |
651 | // 166-191 -- Reserved |
652 | UNW_ARM_WC0 = 192, |
653 | UNW_ARM_WC1 = 193, |
654 | UNW_ARM_WC2 = 194, |
655 | UNW_ARM_WC3 = 195, |
656 | // 196-199 -- wC4-wC7 (Intel wireless MMX control) |
657 | // 200-255 -- Reserved |
658 | UNW_ARM_D0 = 256, |
659 | UNW_ARM_D1 = 257, |
660 | UNW_ARM_D2 = 258, |
661 | UNW_ARM_D3 = 259, |
662 | UNW_ARM_D4 = 260, |
663 | UNW_ARM_D5 = 261, |
664 | UNW_ARM_D6 = 262, |
665 | UNW_ARM_D7 = 263, |
666 | UNW_ARM_D8 = 264, |
667 | UNW_ARM_D9 = 265, |
668 | UNW_ARM_D10 = 266, |
669 | UNW_ARM_D11 = 267, |
670 | UNW_ARM_D12 = 268, |
671 | UNW_ARM_D13 = 269, |
672 | UNW_ARM_D14 = 270, |
673 | UNW_ARM_D15 = 271, |
674 | UNW_ARM_D16 = 272, |
675 | UNW_ARM_D17 = 273, |
676 | UNW_ARM_D18 = 274, |
677 | UNW_ARM_D19 = 275, |
678 | UNW_ARM_D20 = 276, |
679 | UNW_ARM_D21 = 277, |
680 | UNW_ARM_D22 = 278, |
681 | UNW_ARM_D23 = 279, |
682 | UNW_ARM_D24 = 280, |
683 | UNW_ARM_D25 = 281, |
684 | UNW_ARM_D26 = 282, |
685 | UNW_ARM_D27 = 283, |
686 | UNW_ARM_D28 = 284, |
687 | UNW_ARM_D29 = 285, |
688 | UNW_ARM_D30 = 286, |
689 | UNW_ARM_D31 = 287, |
690 | // 288-319 -- Reserved for VFP/Neon |
691 | // 320-8191 -- Reserved |
692 | // 8192-16383 -- Unspecified vendor co-processor register. |
693 | }; |
694 | |
695 | // OpenRISC1000 register numbers |
696 | enum { |
697 | UNW_OR1K_R0 = 0, |
698 | UNW_OR1K_R1 = 1, |
699 | UNW_OR1K_R2 = 2, |
700 | UNW_OR1K_R3 = 3, |
701 | UNW_OR1K_R4 = 4, |
702 | UNW_OR1K_R5 = 5, |
703 | UNW_OR1K_R6 = 6, |
704 | UNW_OR1K_R7 = 7, |
705 | UNW_OR1K_R8 = 8, |
706 | UNW_OR1K_R9 = 9, |
707 | UNW_OR1K_R10 = 10, |
708 | UNW_OR1K_R11 = 11, |
709 | UNW_OR1K_R12 = 12, |
710 | UNW_OR1K_R13 = 13, |
711 | UNW_OR1K_R14 = 14, |
712 | UNW_OR1K_R15 = 15, |
713 | UNW_OR1K_R16 = 16, |
714 | UNW_OR1K_R17 = 17, |
715 | UNW_OR1K_R18 = 18, |
716 | UNW_OR1K_R19 = 19, |
717 | UNW_OR1K_R20 = 20, |
718 | UNW_OR1K_R21 = 21, |
719 | UNW_OR1K_R22 = 22, |
720 | UNW_OR1K_R23 = 23, |
721 | UNW_OR1K_R24 = 24, |
722 | UNW_OR1K_R25 = 25, |
723 | UNW_OR1K_R26 = 26, |
724 | UNW_OR1K_R27 = 27, |
725 | UNW_OR1K_R28 = 28, |
726 | UNW_OR1K_R29 = 29, |
727 | UNW_OR1K_R30 = 30, |
728 | UNW_OR1K_R31 = 31, |
729 | UNW_OR1K_EPCR = 32, |
730 | }; |
731 | |
732 | // MIPS registers |
733 | enum { |
734 | UNW_MIPS_R0 = 0, |
735 | UNW_MIPS_R1 = 1, |
736 | UNW_MIPS_R2 = 2, |
737 | UNW_MIPS_R3 = 3, |
738 | UNW_MIPS_R4 = 4, |
739 | UNW_MIPS_R5 = 5, |
740 | UNW_MIPS_R6 = 6, |
741 | UNW_MIPS_R7 = 7, |
742 | UNW_MIPS_R8 = 8, |
743 | UNW_MIPS_R9 = 9, |
744 | UNW_MIPS_R10 = 10, |
745 | UNW_MIPS_R11 = 11, |
746 | UNW_MIPS_R12 = 12, |
747 | UNW_MIPS_R13 = 13, |
748 | UNW_MIPS_R14 = 14, |
749 | UNW_MIPS_R15 = 15, |
750 | UNW_MIPS_R16 = 16, |
751 | UNW_MIPS_R17 = 17, |
752 | UNW_MIPS_R18 = 18, |
753 | UNW_MIPS_R19 = 19, |
754 | UNW_MIPS_R20 = 20, |
755 | UNW_MIPS_R21 = 21, |
756 | UNW_MIPS_R22 = 22, |
757 | UNW_MIPS_R23 = 23, |
758 | UNW_MIPS_R24 = 24, |
759 | UNW_MIPS_R25 = 25, |
760 | UNW_MIPS_R26 = 26, |
761 | UNW_MIPS_R27 = 27, |
762 | UNW_MIPS_R28 = 28, |
763 | UNW_MIPS_R29 = 29, |
764 | UNW_MIPS_R30 = 30, |
765 | UNW_MIPS_R31 = 31, |
766 | UNW_MIPS_F0 = 32, |
767 | UNW_MIPS_F1 = 33, |
768 | UNW_MIPS_F2 = 34, |
769 | UNW_MIPS_F3 = 35, |
770 | UNW_MIPS_F4 = 36, |
771 | UNW_MIPS_F5 = 37, |
772 | UNW_MIPS_F6 = 38, |
773 | UNW_MIPS_F7 = 39, |
774 | UNW_MIPS_F8 = 40, |
775 | UNW_MIPS_F9 = 41, |
776 | UNW_MIPS_F10 = 42, |
777 | UNW_MIPS_F11 = 43, |
778 | UNW_MIPS_F12 = 44, |
779 | UNW_MIPS_F13 = 45, |
780 | UNW_MIPS_F14 = 46, |
781 | UNW_MIPS_F15 = 47, |
782 | UNW_MIPS_F16 = 48, |
783 | UNW_MIPS_F17 = 49, |
784 | UNW_MIPS_F18 = 50, |
785 | UNW_MIPS_F19 = 51, |
786 | UNW_MIPS_F20 = 52, |
787 | UNW_MIPS_F21 = 53, |
788 | UNW_MIPS_F22 = 54, |
789 | UNW_MIPS_F23 = 55, |
790 | UNW_MIPS_F24 = 56, |
791 | UNW_MIPS_F25 = 57, |
792 | UNW_MIPS_F26 = 58, |
793 | UNW_MIPS_F27 = 59, |
794 | UNW_MIPS_F28 = 60, |
795 | UNW_MIPS_F29 = 61, |
796 | UNW_MIPS_F30 = 62, |
797 | UNW_MIPS_F31 = 63, |
798 | UNW_MIPS_HI = 64, |
799 | UNW_MIPS_LO = 65, |
800 | }; |
801 | |
802 | // SPARC registers |
803 | enum { |
804 | UNW_SPARC_G0 = 0, |
805 | UNW_SPARC_G1 = 1, |
806 | UNW_SPARC_G2 = 2, |
807 | UNW_SPARC_G3 = 3, |
808 | UNW_SPARC_G4 = 4, |
809 | UNW_SPARC_G5 = 5, |
810 | UNW_SPARC_G6 = 6, |
811 | UNW_SPARC_G7 = 7, |
812 | UNW_SPARC_O0 = 8, |
813 | UNW_SPARC_O1 = 9, |
814 | UNW_SPARC_O2 = 10, |
815 | UNW_SPARC_O3 = 11, |
816 | UNW_SPARC_O4 = 12, |
817 | UNW_SPARC_O5 = 13, |
818 | UNW_SPARC_O6 = 14, |
819 | UNW_SPARC_O7 = 15, |
820 | UNW_SPARC_L0 = 16, |
821 | UNW_SPARC_L1 = 17, |
822 | UNW_SPARC_L2 = 18, |
823 | UNW_SPARC_L3 = 19, |
824 | UNW_SPARC_L4 = 20, |
825 | UNW_SPARC_L5 = 21, |
826 | UNW_SPARC_L6 = 22, |
827 | UNW_SPARC_L7 = 23, |
828 | UNW_SPARC_I0 = 24, |
829 | UNW_SPARC_I1 = 25, |
830 | UNW_SPARC_I2 = 26, |
831 | UNW_SPARC_I3 = 27, |
832 | UNW_SPARC_I4 = 28, |
833 | UNW_SPARC_I5 = 29, |
834 | UNW_SPARC_I6 = 30, |
835 | UNW_SPARC_I7 = 31, |
836 | }; |
837 | |
838 | #endif |
839 | |