1//===------------------------------- dwarf2.h -----------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9
10/*
11 These constants were taken from version 3 of the DWARF standard,
12 which is Copyright (c) 2005 Free Standards Group, and
13 Copyright (c) 1992, 1993 UNIX International, Inc.
14*/
15
16#ifndef __DWARF2__
17#define __DWARF2__
18
19// DWARF unwind instructions
20enum {
21 DW_CFA_nop = 0x0,
22 DW_CFA_set_loc = 0x1,
23 DW_CFA_advance_loc1 = 0x2,
24 DW_CFA_advance_loc2 = 0x3,
25 DW_CFA_advance_loc4 = 0x4,
26 DW_CFA_offset_extended = 0x5,
27 DW_CFA_restore_extended = 0x6,
28 DW_CFA_undefined = 0x7,
29 DW_CFA_same_value = 0x8,
30 DW_CFA_register = 0x9,
31 DW_CFA_remember_state = 0xA,
32 DW_CFA_restore_state = 0xB,
33 DW_CFA_def_cfa = 0xC,
34 DW_CFA_def_cfa_register = 0xD,
35 DW_CFA_def_cfa_offset = 0xE,
36 DW_CFA_def_cfa_expression = 0xF,
37 DW_CFA_expression = 0x10,
38 DW_CFA_offset_extended_sf = 0x11,
39 DW_CFA_def_cfa_sf = 0x12,
40 DW_CFA_def_cfa_offset_sf = 0x13,
41 DW_CFA_val_offset = 0x14,
42 DW_CFA_val_offset_sf = 0x15,
43 DW_CFA_val_expression = 0x16,
44 DW_CFA_advance_loc = 0x40, // high 2 bits are 0x1, lower 6 bits are delta
45 DW_CFA_offset = 0x80, // high 2 bits are 0x2, lower 6 bits are register
46 DW_CFA_restore = 0xC0, // high 2 bits are 0x3, lower 6 bits are register
47
48 // GNU extensions
49 DW_CFA_GNU_window_save = 0x2D,
50 DW_CFA_GNU_args_size = 0x2E,
51 DW_CFA_GNU_negative_offset_extended = 0x2F,
52
53 // AARCH64 extensions
54 DW_CFA_AARCH64_negate_ra_state = 0x2D
55};
56
57
58// FSF exception handling Pointer-Encoding constants
59// Used in CFI augmentation by GCC
60enum {
61 DW_EH_PE_ptr = 0x00,
62 DW_EH_PE_uleb128 = 0x01,
63 DW_EH_PE_udata2 = 0x02,
64 DW_EH_PE_udata4 = 0x03,
65 DW_EH_PE_udata8 = 0x04,
66 DW_EH_PE_signed = 0x08,
67 DW_EH_PE_sleb128 = 0x09,
68 DW_EH_PE_sdata2 = 0x0A,
69 DW_EH_PE_sdata4 = 0x0B,
70 DW_EH_PE_sdata8 = 0x0C,
71 DW_EH_PE_absptr = 0x00,
72 DW_EH_PE_pcrel = 0x10,
73 DW_EH_PE_textrel = 0x20,
74 DW_EH_PE_datarel = 0x30,
75 DW_EH_PE_funcrel = 0x40,
76 DW_EH_PE_aligned = 0x50,
77 DW_EH_PE_indirect = 0x80,
78 DW_EH_PE_omit = 0xFF
79};
80
81
82// DWARF expressions
83enum {
84 DW_OP_addr = 0x03, // constant address (size target specific)
85 DW_OP_deref = 0x06,
86 DW_OP_const1u = 0x08, // 1-byte constant
87 DW_OP_const1s = 0x09, // 1-byte constant
88 DW_OP_const2u = 0x0A, // 2-byte constant
89 DW_OP_const2s = 0x0B, // 2-byte constant
90 DW_OP_const4u = 0x0C, // 4-byte constant
91 DW_OP_const4s = 0x0D, // 4-byte constant
92 DW_OP_const8u = 0x0E, // 8-byte constant
93 DW_OP_const8s = 0x0F, // 8-byte constant
94 DW_OP_constu = 0x10, // ULEB128 constant
95 DW_OP_consts = 0x11, // SLEB128 constant
96 DW_OP_dup = 0x12,
97 DW_OP_drop = 0x13,
98 DW_OP_over = 0x14,
99 DW_OP_pick = 0x15, // 1-byte stack index
100 DW_OP_swap = 0x16,
101 DW_OP_rot = 0x17,
102 DW_OP_xderef = 0x18,
103 DW_OP_abs = 0x19,
104 DW_OP_and = 0x1A,
105 DW_OP_div = 0x1B,
106 DW_OP_minus = 0x1C,
107 DW_OP_mod = 0x1D,
108 DW_OP_mul = 0x1E,
109 DW_OP_neg = 0x1F,
110 DW_OP_not = 0x20,
111 DW_OP_or = 0x21,
112 DW_OP_plus = 0x22,
113 DW_OP_plus_uconst = 0x23, // ULEB128 addend
114 DW_OP_shl = 0x24,
115 DW_OP_shr = 0x25,
116 DW_OP_shra = 0x26,
117 DW_OP_xor = 0x27,
118 DW_OP_skip = 0x2F, // signed 2-byte constant
119 DW_OP_bra = 0x28, // signed 2-byte constant
120 DW_OP_eq = 0x29,
121 DW_OP_ge = 0x2A,
122 DW_OP_gt = 0x2B,
123 DW_OP_le = 0x2C,
124 DW_OP_lt = 0x2D,
125 DW_OP_ne = 0x2E,
126 DW_OP_lit0 = 0x30, // Literal 0
127 DW_OP_lit1 = 0x31, // Literal 1
128 DW_OP_lit2 = 0x32, // Literal 2
129 DW_OP_lit3 = 0x33, // Literal 3
130 DW_OP_lit4 = 0x34, // Literal 4
131 DW_OP_lit5 = 0x35, // Literal 5
132 DW_OP_lit6 = 0x36, // Literal 6
133 DW_OP_lit7 = 0x37, // Literal 7
134 DW_OP_lit8 = 0x38, // Literal 8
135 DW_OP_lit9 = 0x39, // Literal 9
136 DW_OP_lit10 = 0x3A, // Literal 10
137 DW_OP_lit11 = 0x3B, // Literal 11
138 DW_OP_lit12 = 0x3C, // Literal 12
139 DW_OP_lit13 = 0x3D, // Literal 13
140 DW_OP_lit14 = 0x3E, // Literal 14
141 DW_OP_lit15 = 0x3F, // Literal 15
142 DW_OP_lit16 = 0x40, // Literal 16
143 DW_OP_lit17 = 0x41, // Literal 17
144 DW_OP_lit18 = 0x42, // Literal 18
145 DW_OP_lit19 = 0x43, // Literal 19
146 DW_OP_lit20 = 0x44, // Literal 20
147 DW_OP_lit21 = 0x45, // Literal 21
148 DW_OP_lit22 = 0x46, // Literal 22
149 DW_OP_lit23 = 0x47, // Literal 23
150 DW_OP_lit24 = 0x48, // Literal 24
151 DW_OP_lit25 = 0x49, // Literal 25
152 DW_OP_lit26 = 0x4A, // Literal 26
153 DW_OP_lit27 = 0x4B, // Literal 27
154 DW_OP_lit28 = 0x4C, // Literal 28
155 DW_OP_lit29 = 0x4D, // Literal 29
156 DW_OP_lit30 = 0x4E, // Literal 30
157 DW_OP_lit31 = 0x4F, // Literal 31
158 DW_OP_reg0 = 0x50, // Contents of reg0
159 DW_OP_reg1 = 0x51, // Contents of reg1
160 DW_OP_reg2 = 0x52, // Contents of reg2
161 DW_OP_reg3 = 0x53, // Contents of reg3
162 DW_OP_reg4 = 0x54, // Contents of reg4
163 DW_OP_reg5 = 0x55, // Contents of reg5
164 DW_OP_reg6 = 0x56, // Contents of reg6
165 DW_OP_reg7 = 0x57, // Contents of reg7
166 DW_OP_reg8 = 0x58, // Contents of reg8
167 DW_OP_reg9 = 0x59, // Contents of reg9
168 DW_OP_reg10 = 0x5A, // Contents of reg10
169 DW_OP_reg11 = 0x5B, // Contents of reg11
170 DW_OP_reg12 = 0x5C, // Contents of reg12
171 DW_OP_reg13 = 0x5D, // Contents of reg13
172 DW_OP_reg14 = 0x5E, // Contents of reg14
173 DW_OP_reg15 = 0x5F, // Contents of reg15
174 DW_OP_reg16 = 0x60, // Contents of reg16
175 DW_OP_reg17 = 0x61, // Contents of reg17
176 DW_OP_reg18 = 0x62, // Contents of reg18
177 DW_OP_reg19 = 0x63, // Contents of reg19
178 DW_OP_reg20 = 0x64, // Contents of reg20
179 DW_OP_reg21 = 0x65, // Contents of reg21
180 DW_OP_reg22 = 0x66, // Contents of reg22
181 DW_OP_reg23 = 0x67, // Contents of reg23
182 DW_OP_reg24 = 0x68, // Contents of reg24
183 DW_OP_reg25 = 0x69, // Contents of reg25
184 DW_OP_reg26 = 0x6A, // Contents of reg26
185 DW_OP_reg27 = 0x6B, // Contents of reg27
186 DW_OP_reg28 = 0x6C, // Contents of reg28
187 DW_OP_reg29 = 0x6D, // Contents of reg29
188 DW_OP_reg30 = 0x6E, // Contents of reg30
189 DW_OP_reg31 = 0x6F, // Contents of reg31
190 DW_OP_breg0 = 0x70, // base register 0 + SLEB128 offset
191 DW_OP_breg1 = 0x71, // base register 1 + SLEB128 offset
192 DW_OP_breg2 = 0x72, // base register 2 + SLEB128 offset
193 DW_OP_breg3 = 0x73, // base register 3 + SLEB128 offset
194 DW_OP_breg4 = 0x74, // base register 4 + SLEB128 offset
195 DW_OP_breg5 = 0x75, // base register 5 + SLEB128 offset
196 DW_OP_breg6 = 0x76, // base register 6 + SLEB128 offset
197 DW_OP_breg7 = 0x77, // base register 7 + SLEB128 offset
198 DW_OP_breg8 = 0x78, // base register 8 + SLEB128 offset
199 DW_OP_breg9 = 0x79, // base register 9 + SLEB128 offset
200 DW_OP_breg10 = 0x7A, // base register 10 + SLEB128 offset
201 DW_OP_breg11 = 0x7B, // base register 11 + SLEB128 offset
202 DW_OP_breg12 = 0x7C, // base register 12 + SLEB128 offset
203 DW_OP_breg13 = 0x7D, // base register 13 + SLEB128 offset
204 DW_OP_breg14 = 0x7E, // base register 14 + SLEB128 offset
205 DW_OP_breg15 = 0x7F, // base register 15 + SLEB128 offset
206 DW_OP_breg16 = 0x80, // base register 16 + SLEB128 offset
207 DW_OP_breg17 = 0x81, // base register 17 + SLEB128 offset
208 DW_OP_breg18 = 0x82, // base register 18 + SLEB128 offset
209 DW_OP_breg19 = 0x83, // base register 19 + SLEB128 offset
210 DW_OP_breg20 = 0x84, // base register 20 + SLEB128 offset
211 DW_OP_breg21 = 0x85, // base register 21 + SLEB128 offset
212 DW_OP_breg22 = 0x86, // base register 22 + SLEB128 offset
213 DW_OP_breg23 = 0x87, // base register 23 + SLEB128 offset
214 DW_OP_breg24 = 0x88, // base register 24 + SLEB128 offset
215 DW_OP_breg25 = 0x89, // base register 25 + SLEB128 offset
216 DW_OP_breg26 = 0x8A, // base register 26 + SLEB128 offset
217 DW_OP_breg27 = 0x8B, // base register 27 + SLEB128 offset
218 DW_OP_breg28 = 0x8C, // base register 28 + SLEB128 offset
219 DW_OP_breg29 = 0x8D, // base register 29 + SLEB128 offset
220 DW_OP_breg30 = 0x8E, // base register 30 + SLEB128 offset
221 DW_OP_breg31 = 0x8F, // base register 31 + SLEB128 offset
222 DW_OP_regx = 0x90, // ULEB128 register
223 DW_OP_fbreg = 0x91, // SLEB128 offset
224 DW_OP_bregx = 0x92, // ULEB128 register followed by SLEB128 offset
225 DW_OP_piece = 0x93, // ULEB128 size of piece addressed
226 DW_OP_deref_size = 0x94, // 1-byte size of data retrieved
227 DW_OP_xderef_size = 0x95, // 1-byte size of data retrieved
228 DW_OP_nop = 0x96,
229 DW_OP_push_object_addres = 0x97,
230 DW_OP_call2 = 0x98, // 2-byte offset of DIE
231 DW_OP_call4 = 0x99, // 4-byte offset of DIE
232 DW_OP_call_ref = 0x9A, // 4- or 8-byte offset of DIE
233 DW_OP_lo_user = 0xE0,
234 DW_OP_APPLE_uninit = 0xF0,
235 DW_OP_hi_user = 0xFF
236};
237
238
239#endif
240