1// Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
2// for details. All rights reserved. Use of this source code is governed by a
3// BSD-style license that can be found in the LICENSE file.
4
5#include <setjmp.h> // NOLINT
6#include <stdlib.h>
7
8#include "vm/globals.h"
9#if defined(TARGET_ARCH_ARM)
10
11// Only build the simulator if not compiling for real ARM hardware.
12#if defined(USING_SIMULATOR)
13
14#include "vm/simulator.h"
15
16#include "vm/compiler/assembler/disassembler.h"
17#include "vm/constants.h"
18#include "vm/cpu.h"
19#include "vm/native_arguments.h"
20#include "vm/os_thread.h"
21#include "vm/stack_frame.h"
22
23namespace dart {
24
25DEFINE_FLAG(uint64_t,
26 trace_sim_after,
27 ULLONG_MAX,
28 "Trace simulator execution after instruction count reached.");
29DEFINE_FLAG(uint64_t,
30 stop_sim_at,
31 ULLONG_MAX,
32 "Instruction address or instruction count to stop simulator at.");
33
34// This macro provides a platform independent use of sscanf. The reason for
35// SScanF not being implemented in a platform independent way through
36// OS in the same way as SNPrint is that the Windows C Run-Time
37// Library does not provide vsscanf.
38#define SScanF sscanf // NOLINT
39
40// SimulatorSetjmpBuffer are linked together, and the last created one
41// is referenced by the Simulator. When an exception is thrown, the exception
42// runtime looks at where to jump and finds the corresponding
43// SimulatorSetjmpBuffer based on the stack pointer of the exception handler.
44// The runtime then does a Longjmp on that buffer to return to the simulator.
45class SimulatorSetjmpBuffer {
46 public:
47 void Longjmp() {
48 // "This" is now the last setjmp buffer.
49 simulator_->set_last_setjmp_buffer(this);
50 longjmp(buffer_, 1);
51 }
52
53 explicit SimulatorSetjmpBuffer(Simulator* sim) {
54 simulator_ = sim;
55 link_ = sim->last_setjmp_buffer();
56 sim->set_last_setjmp_buffer(this);
57 sp_ = static_cast<uword>(sim->get_register(SP));
58 }
59
60 ~SimulatorSetjmpBuffer() {
61 ASSERT(simulator_->last_setjmp_buffer() == this);
62 simulator_->set_last_setjmp_buffer(link_);
63 }
64
65 SimulatorSetjmpBuffer* link() { return link_; }
66
67 uword sp() { return sp_; }
68
69 private:
70 uword sp_;
71 Simulator* simulator_;
72 SimulatorSetjmpBuffer* link_;
73 jmp_buf buffer_;
74
75 friend class Simulator;
76};
77
78// The SimulatorDebugger class is used by the simulator while debugging
79// simulated ARM code.
80class SimulatorDebugger {
81 public:
82 explicit SimulatorDebugger(Simulator* sim);
83 ~SimulatorDebugger();
84
85 void Stop(Instr* instr, const char* message);
86 void Debug();
87 char* ReadLine(const char* prompt);
88
89 private:
90 Simulator* sim_;
91
92 bool GetValue(char* desc, uint32_t* value);
93 bool GetFValue(char* desc, float* value);
94 bool GetDValue(char* desc, double* value);
95
96 static TokenPosition GetApproximateTokenIndex(const Code& code, uword pc);
97
98 static void PrintDartFrame(uword pc,
99 uword fp,
100 uword sp,
101 const Function& function,
102 TokenPosition token_pos,
103 bool is_optimized,
104 bool is_inlined);
105 void PrintBacktrace();
106
107 // Set or delete a breakpoint. Returns true if successful.
108 bool SetBreakpoint(Instr* breakpc);
109 bool DeleteBreakpoint(Instr* breakpc);
110
111 // Undo and redo all breakpoints. This is needed to bracket disassembly and
112 // execution to skip past breakpoints when run from the debugger.
113 void UndoBreakpoints();
114 void RedoBreakpoints();
115};
116
117SimulatorDebugger::SimulatorDebugger(Simulator* sim) {
118 sim_ = sim;
119}
120
121SimulatorDebugger::~SimulatorDebugger() {}
122
123void SimulatorDebugger::Stop(Instr* instr, const char* message) {
124 OS::PrintErr("Simulator hit %s\n", message);
125 Debug();
126}
127
128static Register LookupCpuRegisterByName(const char* name) {
129 static const char* kNames[] = {
130 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10",
131 "r11", "r12", "r13", "r14", "r15", "pc", "lr", "sp", "ip", "fp", "pp"};
132 static const Register kRegisters[] = {R0, R1, R2, R3, R4, R5, R6, R7,
133 R8, R9, R10, R11, R12, R13, R14, R15,
134 PC, LR, SP, IP, FP, PP};
135 ASSERT(ARRAY_SIZE(kNames) == ARRAY_SIZE(kRegisters));
136 for (unsigned i = 0; i < ARRAY_SIZE(kNames); i++) {
137 if (strcmp(kNames[i], name) == 0) {
138 return kRegisters[i];
139 }
140 }
141 return kNoRegister;
142}
143
144static SRegister LookupSRegisterByName(const char* name) {
145 int reg_nr = -1;
146 bool ok = SScanF(name, "s%d", &reg_nr);
147 if (ok && (0 <= reg_nr) && (reg_nr < kNumberOfSRegisters)) {
148 return static_cast<SRegister>(reg_nr);
149 }
150 return kNoSRegister;
151}
152
153static DRegister LookupDRegisterByName(const char* name) {
154 int reg_nr = -1;
155 bool ok = SScanF(name, "d%d", &reg_nr);
156 if (ok && (0 <= reg_nr) && (reg_nr < kNumberOfDRegisters)) {
157 return static_cast<DRegister>(reg_nr);
158 }
159 return kNoDRegister;
160}
161
162bool SimulatorDebugger::GetValue(char* desc, uint32_t* value) {
163 Register reg = LookupCpuRegisterByName(desc);
164 if (reg != kNoRegister) {
165 if (reg == PC) {
166 *value = sim_->get_pc();
167 } else {
168 *value = sim_->get_register(reg);
169 }
170 return true;
171 }
172 if (desc[0] == '*') {
173 uint32_t addr;
174 if (GetValue(desc + 1, &addr)) {
175 if (Simulator::IsIllegalAddress(addr)) {
176 return false;
177 }
178 *value = *(reinterpret_cast<uint32_t*>(addr));
179 return true;
180 }
181 }
182 bool retval = SScanF(desc, "0x%x", value) == 1;
183 if (!retval) {
184 retval = SScanF(desc, "%x", value) == 1;
185 }
186 return retval;
187}
188
189bool SimulatorDebugger::GetFValue(char* desc, float* value) {
190 SRegister sreg = LookupSRegisterByName(desc);
191 if (sreg != kNoSRegister) {
192 *value = sim_->get_sregister(sreg);
193 return true;
194 }
195 if (desc[0] == '*') {
196 uint32_t addr;
197 if (GetValue(desc + 1, &addr)) {
198 if (Simulator::IsIllegalAddress(addr)) {
199 return false;
200 }
201 *value = *(reinterpret_cast<float*>(addr));
202 return true;
203 }
204 }
205 return false;
206}
207
208bool SimulatorDebugger::GetDValue(char* desc, double* value) {
209 DRegister dreg = LookupDRegisterByName(desc);
210 if (dreg != kNoDRegister) {
211 *value = sim_->get_dregister(dreg);
212 return true;
213 }
214 if (desc[0] == '*') {
215 uint32_t addr;
216 if (GetValue(desc + 1, &addr)) {
217 if (Simulator::IsIllegalAddress(addr)) {
218 return false;
219 }
220 *value = *(reinterpret_cast<double*>(addr));
221 return true;
222 }
223 }
224 return false;
225}
226
227TokenPosition SimulatorDebugger::GetApproximateTokenIndex(const Code& code,
228 uword pc) {
229 TokenPosition token_pos = TokenPosition::kNoSource;
230 uword pc_offset = pc - code.PayloadStart();
231 const PcDescriptors& descriptors =
232 PcDescriptors::Handle(code.pc_descriptors());
233 PcDescriptors::Iterator iter(descriptors, PcDescriptorsLayout::kAnyKind);
234 while (iter.MoveNext()) {
235 if (iter.PcOffset() == pc_offset) {
236 return iter.TokenPos();
237 } else if (!token_pos.IsReal() && (iter.PcOffset() > pc_offset)) {
238 token_pos = iter.TokenPos();
239 }
240 }
241 return token_pos;
242}
243
244void SimulatorDebugger::PrintDartFrame(uword pc,
245 uword fp,
246 uword sp,
247 const Function& function,
248 TokenPosition token_pos,
249 bool is_optimized,
250 bool is_inlined) {
251 const Script& script = Script::Handle(function.script());
252 const String& func_name = String::Handle(function.QualifiedScrubbedName());
253 const String& url = String::Handle(script.url());
254 intptr_t line = -1;
255 intptr_t column = -1;
256 if (token_pos.IsReal()) {
257 script.GetTokenLocation(token_pos, &line, &column);
258 }
259 OS::PrintErr(
260 "pc=0x%" Px " fp=0x%" Px " sp=0x%" Px " %s%s (%s:%" Pd ":%" Pd ")\n", pc,
261 fp, sp, is_optimized ? (is_inlined ? "inlined " : "optimized ") : "",
262 func_name.ToCString(), url.ToCString(), line, column);
263}
264
265void SimulatorDebugger::PrintBacktrace() {
266 StackFrameIterator frames(
267 sim_->get_register(FP), sim_->get_register(SP), sim_->get_pc(),
268 ValidationPolicy::kDontValidateFrames, Thread::Current(),
269 StackFrameIterator::kNoCrossThreadIteration);
270 StackFrame* frame = frames.NextFrame();
271 ASSERT(frame != NULL);
272 Function& function = Function::Handle();
273 Function& inlined_function = Function::Handle();
274 Code& code = Code::Handle();
275 Code& unoptimized_code = Code::Handle();
276 while (frame != NULL) {
277 if (frame->IsDartFrame()) {
278 ASSERT(!frame->is_interpreted()); // Not yet supported.
279 code = frame->LookupDartCode();
280 function = code.function();
281 if (code.is_optimized()) {
282 // For optimized frames, extract all the inlined functions if any
283 // into the stack trace.
284 InlinedFunctionsIterator it(code, frame->pc());
285 while (!it.Done()) {
286 // Print each inlined frame with its pc in the corresponding
287 // unoptimized frame.
288 inlined_function = it.function();
289 unoptimized_code = it.code();
290 uword unoptimized_pc = it.pc();
291 it.Advance();
292 if (!it.Done()) {
293 PrintDartFrame(
294 unoptimized_pc, frame->fp(), frame->sp(), inlined_function,
295 GetApproximateTokenIndex(unoptimized_code, unoptimized_pc),
296 true, true);
297 }
298 }
299 // Print the optimized inlining frame below.
300 }
301 PrintDartFrame(frame->pc(), frame->fp(), frame->sp(), function,
302 GetApproximateTokenIndex(code, frame->pc()),
303 code.is_optimized(), false);
304 } else {
305 OS::PrintErr("pc=0x%" Px " fp=0x%" Px " sp=0x%" Px " %s frame\n",
306 frame->pc(), frame->fp(), frame->sp(),
307 frame->IsEntryFrame()
308 ? "entry"
309 : frame->IsExitFrame()
310 ? "exit"
311 : frame->IsStubFrame() ? "stub" : "invalid");
312 }
313 frame = frames.NextFrame();
314 }
315}
316
317bool SimulatorDebugger::SetBreakpoint(Instr* breakpc) {
318 // Check if a breakpoint can be set. If not return without any side-effects.
319 if (sim_->break_pc_ != NULL) {
320 return false;
321 }
322
323 // Set the breakpoint.
324 sim_->break_pc_ = breakpc;
325 sim_->break_instr_ = breakpc->InstructionBits();
326 // Not setting the breakpoint instruction in the code itself. It will be set
327 // when the debugger shell continues.
328 return true;
329}
330
331bool SimulatorDebugger::DeleteBreakpoint(Instr* breakpc) {
332 if (sim_->break_pc_ != NULL) {
333 sim_->break_pc_->SetInstructionBits(sim_->break_instr_);
334 }
335
336 sim_->break_pc_ = NULL;
337 sim_->break_instr_ = 0;
338 return true;
339}
340
341void SimulatorDebugger::UndoBreakpoints() {
342 if (sim_->break_pc_ != NULL) {
343 sim_->break_pc_->SetInstructionBits(sim_->break_instr_);
344 }
345}
346
347void SimulatorDebugger::RedoBreakpoints() {
348 if (sim_->break_pc_ != NULL) {
349 sim_->break_pc_->SetInstructionBits(Instr::kSimulatorBreakpointInstruction);
350 }
351}
352
353void SimulatorDebugger::Debug() {
354 intptr_t last_pc = -1;
355 bool done = false;
356
357#define COMMAND_SIZE 63
358#define ARG_SIZE 255
359
360#define STR(a) #a
361#define XSTR(a) STR(a)
362
363 char cmd[COMMAND_SIZE + 1];
364 char arg1[ARG_SIZE + 1];
365 char arg2[ARG_SIZE + 1];
366
367 // make sure to have a proper terminating character if reaching the limit
368 cmd[COMMAND_SIZE] = 0;
369 arg1[ARG_SIZE] = 0;
370 arg2[ARG_SIZE] = 0;
371
372 // Undo all set breakpoints while running in the debugger shell. This will
373 // make them invisible to all commands.
374 UndoBreakpoints();
375
376 while (!done) {
377 if (last_pc != sim_->get_pc()) {
378 last_pc = sim_->get_pc();
379 if (Simulator::IsIllegalAddress(last_pc)) {
380 OS::PrintErr("pc is out of bounds: 0x%" Px "\n", last_pc);
381 } else {
382 if (FLAG_support_disassembler) {
383 Disassembler::Disassemble(last_pc, last_pc + Instr::kInstrSize);
384 } else {
385 OS::PrintErr("Disassembler not supported in this mode.\n");
386 }
387 }
388 }
389 char* line = ReadLine("sim> ");
390 if (line == NULL) {
391 FATAL("ReadLine failed");
392 } else {
393 // Use sscanf to parse the individual parts of the command line. At the
394 // moment no command expects more than two parameters.
395 int args = SScanF(line,
396 "%" XSTR(COMMAND_SIZE) "s "
397 "%" XSTR(ARG_SIZE) "s "
398 "%" XSTR(ARG_SIZE) "s",
399 cmd, arg1, arg2);
400 if ((strcmp(cmd, "h") == 0) || (strcmp(cmd, "help") == 0)) {
401 OS::PrintErr(
402 "c/cont -- continue execution\n"
403 "disasm -- disassemble instrs at current pc location\n"
404 " other variants are:\n"
405 " disasm <address>\n"
406 " disasm <address> <number_of_instructions>\n"
407 " by default 10 instrs are disassembled\n"
408 "del -- delete breakpoints\n"
409 "flags -- print flag values\n"
410 "gdb -- transfer control to gdb\n"
411 "h/help -- print this help string\n"
412 "break <address> -- set break point at specified address\n"
413 "p/print <reg or icount or value or *addr> -- print integer\n"
414 "ps/printsingle <sreg or *addr> -- print float value\n"
415 "pd/printdouble <dreg or *addr> -- print double value\n"
416 "po/printobject <*reg or *addr> -- print object\n"
417 "si/stepi -- single step an instruction\n"
418 "trace -- toggle execution tracing mode\n"
419 "bt -- print backtrace\n"
420 "unstop -- if current pc is a stop instr make it a nop\n"
421 "q/quit -- Quit the debugger and exit the program\n");
422 } else if ((strcmp(cmd, "quit") == 0) || (strcmp(cmd, "q") == 0)) {
423 OS::PrintErr("Quitting\n");
424 OS::Exit(0);
425 } else if ((strcmp(cmd, "si") == 0) || (strcmp(cmd, "stepi") == 0)) {
426 sim_->InstructionDecode(reinterpret_cast<Instr*>(sim_->get_pc()));
427 } else if ((strcmp(cmd, "c") == 0) || (strcmp(cmd, "cont") == 0)) {
428 // Execute the one instruction we broke at with breakpoints disabled.
429 sim_->InstructionDecode(reinterpret_cast<Instr*>(sim_->get_pc()));
430 // Leave the debugger shell.
431 done = true;
432 } else if ((strcmp(cmd, "p") == 0) || (strcmp(cmd, "print") == 0)) {
433 if (args == 2) {
434 uint32_t value;
435 if (strcmp(arg1, "icount") == 0) {
436 const uint64_t icount = sim_->get_icount();
437 OS::PrintErr("icount: %" Pu64 " 0x%" Px64 "\n", icount, icount);
438 } else if (GetValue(arg1, &value)) {
439 OS::PrintErr("%s: %u 0x%x\n", arg1, value, value);
440 } else {
441 OS::PrintErr("%s unrecognized\n", arg1);
442 }
443 } else {
444 OS::PrintErr("print <reg or icount or value or *addr>\n");
445 }
446 } else if ((strcmp(cmd, "ps") == 0) ||
447 (strcmp(cmd, "printsingle") == 0)) {
448 if (args == 2) {
449 float fvalue;
450 if (GetFValue(arg1, &fvalue)) {
451 uint32_t value = bit_cast<uint32_t, float>(fvalue);
452 OS::PrintErr("%s: 0%u 0x%x %.8g\n", arg1, value, value, fvalue);
453 } else {
454 OS::PrintErr("%s unrecognized\n", arg1);
455 }
456 } else {
457 OS::PrintErr("printfloat <sreg or *addr>\n");
458 }
459 } else if ((strcmp(cmd, "pd") == 0) ||
460 (strcmp(cmd, "printdouble") == 0)) {
461 if (args == 2) {
462 double dvalue;
463 if (GetDValue(arg1, &dvalue)) {
464 uint64_t long_value = bit_cast<uint64_t, double>(dvalue);
465 OS::PrintErr("%s: %llu 0x%llx %.8g\n", arg1, long_value, long_value,
466 dvalue);
467 } else {
468 OS::PrintErr("%s unrecognized\n", arg1);
469 }
470 } else {
471 OS::PrintErr("printdouble <dreg or *addr>\n");
472 }
473 } else if ((strcmp(cmd, "po") == 0) ||
474 (strcmp(cmd, "printobject") == 0)) {
475 if (args == 2) {
476 uint32_t value;
477 // Make the dereferencing '*' optional.
478 if (((arg1[0] == '*') && GetValue(arg1 + 1, &value)) ||
479 GetValue(arg1, &value)) {
480 if (Isolate::Current()->heap()->Contains(value)) {
481 OS::PrintErr("%s: \n", arg1);
482#if defined(DEBUG)
483 const Object& obj = Object::Handle(static_cast<ObjectPtr>(value));
484 obj.Print();
485#endif // defined(DEBUG)
486 } else {
487 OS::PrintErr("0x%x is not an object reference\n", value);
488 }
489 } else {
490 OS::PrintErr("%s unrecognized\n", arg1);
491 }
492 } else {
493 OS::PrintErr("printobject <*reg or *addr>\n");
494 }
495 } else if (strcmp(cmd, "disasm") == 0) {
496 uint32_t start = 0;
497 uint32_t end = 0;
498 if (args == 1) {
499 start = sim_->get_pc();
500 end = start + (10 * Instr::kInstrSize);
501 } else if (args == 2) {
502 if (GetValue(arg1, &start)) {
503 // No length parameter passed, assume 10 instructions.
504 if (Simulator::IsIllegalAddress(start)) {
505 // If start isn't a valid address, warn and use PC instead.
506 OS::PrintErr("First argument yields invalid address: 0x%x\n",
507 start);
508 OS::PrintErr("Using PC instead\n");
509 start = sim_->get_pc();
510 }
511 end = start + (10 * Instr::kInstrSize);
512 }
513 } else {
514 uint32_t length;
515 if (GetValue(arg1, &start) && GetValue(arg2, &length)) {
516 if (Simulator::IsIllegalAddress(start)) {
517 // If start isn't a valid address, warn and use PC instead.
518 OS::PrintErr("First argument yields invalid address: 0x%x\n",
519 start);
520 OS::PrintErr("Using PC instead\n");
521 start = sim_->get_pc();
522 }
523 end = start + (length * Instr::kInstrSize);
524 }
525 }
526 if ((start > 0) && (end > start)) {
527 if (FLAG_support_disassembler) {
528 Disassembler::Disassemble(start, end);
529 } else {
530 OS::PrintErr("Disassembler not supported in this mode.\n");
531 }
532 } else {
533 OS::PrintErr("disasm [<address> [<number_of_instructions>]]\n");
534 }
535 } else if (strcmp(cmd, "gdb") == 0) {
536 OS::PrintErr("relinquishing control to gdb\n");
537 OS::DebugBreak();
538 OS::PrintErr("regaining control from gdb\n");
539 } else if (strcmp(cmd, "break") == 0) {
540 if (args == 2) {
541 uint32_t addr;
542 if (GetValue(arg1, &addr)) {
543 if (!SetBreakpoint(reinterpret_cast<Instr*>(addr))) {
544 OS::PrintErr("setting breakpoint failed\n");
545 }
546 } else {
547 OS::PrintErr("%s unrecognized\n", arg1);
548 }
549 } else {
550 OS::PrintErr("break <addr>\n");
551 }
552 } else if (strcmp(cmd, "del") == 0) {
553 if (!DeleteBreakpoint(NULL)) {
554 OS::PrintErr("deleting breakpoint failed\n");
555 }
556 } else if (strcmp(cmd, "flags") == 0) {
557 OS::PrintErr("APSR: ");
558 OS::PrintErr("N flag: %d; ", sim_->n_flag_);
559 OS::PrintErr("Z flag: %d; ", sim_->z_flag_);
560 OS::PrintErr("C flag: %d; ", sim_->c_flag_);
561 OS::PrintErr("V flag: %d\n", sim_->v_flag_);
562 OS::PrintErr("FPSCR: ");
563 OS::PrintErr("N flag: %d; ", sim_->fp_n_flag_);
564 OS::PrintErr("Z flag: %d; ", sim_->fp_z_flag_);
565 OS::PrintErr("C flag: %d; ", sim_->fp_c_flag_);
566 OS::PrintErr("V flag: %d\n", sim_->fp_v_flag_);
567 } else if (strcmp(cmd, "unstop") == 0) {
568 intptr_t stop_pc = sim_->get_pc() - Instr::kInstrSize;
569 Instr* stop_instr = reinterpret_cast<Instr*>(stop_pc);
570 if (stop_instr->IsSvc() || stop_instr->IsBkpt()) {
571 stop_instr->SetInstructionBits(Instr::kNopInstruction);
572 } else {
573 OS::PrintErr("Not at debugger stop.\n");
574 }
575 } else if (strcmp(cmd, "trace") == 0) {
576 if (FLAG_trace_sim_after == ULLONG_MAX) {
577 FLAG_trace_sim_after = sim_->get_icount();
578 OS::PrintErr("execution tracing on\n");
579 } else {
580 FLAG_trace_sim_after = ULLONG_MAX;
581 OS::PrintErr("execution tracing off\n");
582 }
583 } else if (strcmp(cmd, "bt") == 0) {
584 Thread* thread = reinterpret_cast<Thread*>(sim_->get_register(THR));
585 thread->set_execution_state(Thread::kThreadInVM);
586 PrintBacktrace();
587 thread->set_execution_state(Thread::kThreadInGenerated);
588 } else {
589 OS::PrintErr("Unknown command: %s\n", cmd);
590 }
591 }
592 delete[] line;
593 }
594
595 // Add all the breakpoints back to stop execution and enter the debugger
596 // shell when hit.
597 RedoBreakpoints();
598
599#undef COMMAND_SIZE
600#undef ARG_SIZE
601
602#undef STR
603#undef XSTR
604}
605
606char* SimulatorDebugger::ReadLine(const char* prompt) {
607 char* result = NULL;
608 char line_buf[256];
609 intptr_t offset = 0;
610 bool keep_going = true;
611 OS::PrintErr("%s", prompt);
612 while (keep_going) {
613 if (fgets(line_buf, sizeof(line_buf), stdin) == NULL) {
614 // fgets got an error. Just give up.
615 if (result != NULL) {
616 delete[] result;
617 }
618 return NULL;
619 }
620 intptr_t len = strlen(line_buf);
621 if (len > 1 && line_buf[len - 2] == '\\' && line_buf[len - 1] == '\n') {
622 // When we read a line that ends with a "\" we remove the escape and
623 // append the remainder.
624 line_buf[len - 2] = '\n';
625 line_buf[len - 1] = 0;
626 len -= 1;
627 } else if ((len > 0) && (line_buf[len - 1] == '\n')) {
628 // Since we read a new line we are done reading the line. This
629 // will exit the loop after copying this buffer into the result.
630 keep_going = false;
631 }
632 if (result == NULL) {
633 // Allocate the initial result and make room for the terminating '\0'
634 result = new char[len + 1];
635 if (result == NULL) {
636 // OOM, so cannot readline anymore.
637 return NULL;
638 }
639 } else {
640 // Allocate a new result with enough room for the new addition.
641 intptr_t new_len = offset + len + 1;
642 char* new_result = new char[new_len];
643 if (new_result == NULL) {
644 // OOM, free the buffer allocated so far and return NULL.
645 delete[] result;
646 return NULL;
647 } else {
648 // Copy the existing input into the new array and set the new
649 // array as the result.
650 memmove(new_result, result, offset);
651 delete[] result;
652 result = new_result;
653 }
654 }
655 // Copy the newly read line into the result.
656 memmove(result + offset, line_buf, len);
657 offset += len;
658 }
659 ASSERT(result != NULL);
660 result[offset] = '\0';
661 return result;
662}
663
664void Simulator::Init() {}
665
666Simulator::Simulator() : exclusive_access_addr_(0), exclusive_access_value_(0) {
667 // Setup simulator support first. Some of this information is needed to
668 // setup the architecture state.
669 // We allocate the stack here, the size is computed as the sum of
670 // the size specified by the user and the buffer space needed for
671 // handling stack overflow exceptions. To be safe in potential
672 // stack underflows we also add some underflow buffer space.
673 stack_ =
674 new char[(OSThread::GetSpecifiedStackSize() +
675 OSThread::kStackSizeBufferMax + kSimulatorStackUnderflowSize)];
676 // Low address.
677 stack_limit_ = reinterpret_cast<uword>(stack_);
678 // Limit for StackOverflowError.
679 overflow_stack_limit_ = stack_limit_ + OSThread::kStackSizeBufferMax;
680 // High address.
681 stack_base_ = overflow_stack_limit_ + OSThread::GetSpecifiedStackSize();
682
683 pc_modified_ = false;
684 icount_ = 0;
685 break_pc_ = NULL;
686 break_instr_ = 0;
687 last_setjmp_buffer_ = NULL;
688
689 // Setup architecture state.
690 // All registers are initialized to zero to start with.
691 for (int i = 0; i < kNumberOfCpuRegisters; i++) {
692 registers_[i] = 0;
693 }
694 n_flag_ = false;
695 z_flag_ = false;
696 c_flag_ = false;
697 v_flag_ = false;
698
699 // The sp is initialized to point to the bottom (high address) of the
700 // allocated stack area.
701 registers_[SP] = stack_base();
702 // The lr and pc are initialized to a known bad value that will cause an
703 // access violation if the simulator ever tries to execute it.
704 registers_[PC] = kBadLR;
705 registers_[LR] = kBadLR;
706
707 // All double-precision registers are initialized to zero.
708 for (int i = 0; i < kNumberOfDRegisters; i++) {
709 dregisters_[i] = 0;
710 }
711 // Since VFP registers are overlapping, single-precision registers should
712 // already be initialized.
713 ASSERT(2 * kNumberOfDRegisters >= kNumberOfSRegisters);
714 for (int i = 0; i < kNumberOfSRegisters; i++) {
715 ASSERT(sregisters_[i] == 0.0);
716 }
717 fp_n_flag_ = false;
718 fp_z_flag_ = false;
719 fp_c_flag_ = false;
720 fp_v_flag_ = false;
721}
722
723Simulator::~Simulator() {
724 delete[] stack_;
725 Isolate* isolate = Isolate::Current();
726 if (isolate != NULL) {
727 isolate->set_simulator(NULL);
728 }
729}
730
731// When the generated code calls an external reference we need to catch that in
732// the simulator. The external reference will be a function compiled for the
733// host architecture. We need to call that function instead of trying to
734// execute it with the simulator. We do that by redirecting the external
735// reference to a svc (supervisor call) instruction that is handled by
736// the simulator. We write the original destination of the jump just at a known
737// offset from the svc instruction so the simulator knows what to call.
738class Redirection {
739 public:
740 uword address_of_svc_instruction() {
741 return reinterpret_cast<uword>(&svc_instruction_);
742 }
743
744 uword external_function() const { return external_function_; }
745
746 Simulator::CallKind call_kind() const { return call_kind_; }
747
748 int argument_count() const { return argument_count_; }
749
750 static Redirection* Get(uword external_function,
751 Simulator::CallKind call_kind,
752 int argument_count) {
753 MutexLocker ml(mutex_);
754
755 Redirection* old_head = list_.load(std::memory_order_relaxed);
756 for (Redirection* current = old_head; current != nullptr;
757 current = current->next_) {
758 if (current->external_function_ == external_function) return current;
759 }
760
761 Redirection* redirection =
762 new Redirection(external_function, call_kind, argument_count);
763 redirection->next_ = old_head;
764
765 // Use a memory fence to ensure all pending writes are written at the time
766 // of updating the list head, so the profiling thread always has a valid
767 // list to look at.
768 list_.store(redirection, std::memory_order_release);
769
770 return redirection;
771 }
772
773 static Redirection* FromSvcInstruction(Instr* svc_instruction) {
774 char* addr_of_svc = reinterpret_cast<char*>(svc_instruction);
775 char* addr_of_redirection =
776 addr_of_svc - OFFSET_OF(Redirection, svc_instruction_);
777 return reinterpret_cast<Redirection*>(addr_of_redirection);
778 }
779
780 // Please note that this function is called by the signal handler of the
781 // profiling thread. It can therefore run at any point in time and is not
782 // allowed to hold any locks - which is precisely the reason why the list is
783 // prepend-only and a memory fence is used when writing the list head [list_]!
784 static uword FunctionForRedirect(uword address_of_svc) {
785 for (Redirection* current = list_.load(std::memory_order_acquire);
786 current != nullptr; current = current->next_) {
787 if (current->address_of_svc_instruction() == address_of_svc) {
788 return current->external_function_;
789 }
790 }
791 return 0;
792 }
793
794 private:
795 Redirection(uword external_function,
796 Simulator::CallKind call_kind,
797 int argument_count)
798 : external_function_(external_function),
799 call_kind_(call_kind),
800 argument_count_(argument_count),
801 svc_instruction_(Instr::kSimulatorRedirectInstruction),
802 next_(NULL) {}
803
804 uword external_function_;
805 Simulator::CallKind call_kind_;
806 int argument_count_;
807 uint32_t svc_instruction_;
808 Redirection* next_;
809 static std::atomic<Redirection*> list_;
810 static Mutex* mutex_;
811};
812
813std::atomic<Redirection*> Redirection::list_ = {nullptr};
814Mutex* Redirection::mutex_ = new Mutex();
815
816uword Simulator::RedirectExternalReference(uword function,
817 CallKind call_kind,
818 int argument_count) {
819 Redirection* redirection =
820 Redirection::Get(function, call_kind, argument_count);
821 return redirection->address_of_svc_instruction();
822}
823
824uword Simulator::FunctionForRedirect(uword redirect) {
825 return Redirection::FunctionForRedirect(redirect);
826}
827
828// Get the active Simulator for the current isolate.
829Simulator* Simulator::Current() {
830 Isolate* isolate = Isolate::Current();
831 Simulator* simulator = isolate->simulator();
832 if (simulator == NULL) {
833 NoSafepointScope no_safepoint;
834 simulator = new Simulator();
835 isolate->set_simulator(simulator);
836 }
837 return simulator;
838}
839
840// Sets the register in the architecture state. It will also deal with updating
841// Simulator internal state for special registers such as PC.
842DART_FORCE_INLINE void Simulator::set_register(Register reg, int32_t value) {
843 ASSERT((reg >= 0) && (reg < kNumberOfCpuRegisters));
844 if (reg == PC) {
845 pc_modified_ = true;
846 }
847 registers_[reg] = value;
848}
849
850// Raw access to the PC register.
851DART_FORCE_INLINE void Simulator::set_pc(int32_t value) {
852 pc_modified_ = true;
853 registers_[PC] = value;
854}
855
856// Accessors for VFP register state.
857DART_FORCE_INLINE void Simulator::set_sregister(SRegister reg, float value) {
858 ASSERT(TargetCPUFeatures::vfp_supported());
859 ASSERT((reg >= 0) && (reg < kNumberOfSRegisters));
860 sregisters_[reg] = bit_cast<int32_t, float>(value);
861}
862
863DART_FORCE_INLINE float Simulator::get_sregister(SRegister reg) const {
864 ASSERT(TargetCPUFeatures::vfp_supported());
865 ASSERT((reg >= 0) && (reg < kNumberOfSRegisters));
866 return bit_cast<float, int32_t>(sregisters_[reg]);
867}
868
869DART_FORCE_INLINE void Simulator::set_dregister(DRegister reg, double value) {
870 ASSERT(TargetCPUFeatures::vfp_supported());
871 ASSERT((reg >= 0) && (reg < kNumberOfDRegisters));
872 dregisters_[reg] = bit_cast<int64_t, double>(value);
873}
874
875DART_FORCE_INLINE double Simulator::get_dregister(DRegister reg) const {
876 ASSERT(TargetCPUFeatures::vfp_supported());
877 ASSERT((reg >= 0) && (reg < kNumberOfDRegisters));
878 return bit_cast<double, int64_t>(dregisters_[reg]);
879}
880
881void Simulator::set_qregister(QRegister reg, const simd_value_t& value) {
882 ASSERT(TargetCPUFeatures::neon_supported());
883 ASSERT((reg >= 0) && (reg < kNumberOfQRegisters));
884 qregisters_[reg].data_[0] = value.data_[0];
885 qregisters_[reg].data_[1] = value.data_[1];
886 qregisters_[reg].data_[2] = value.data_[2];
887 qregisters_[reg].data_[3] = value.data_[3];
888}
889
890void Simulator::get_qregister(QRegister reg, simd_value_t* value) const {
891 ASSERT(TargetCPUFeatures::neon_supported());
892 // TODO(zra): Replace this test with an assert after we support
893 // 16 Q registers.
894 if ((reg >= 0) && (reg < kNumberOfQRegisters)) {
895 *value = qregisters_[reg];
896 }
897}
898
899void Simulator::set_sregister_bits(SRegister reg, int32_t value) {
900 ASSERT(TargetCPUFeatures::vfp_supported());
901 ASSERT((reg >= 0) && (reg < kNumberOfSRegisters));
902 sregisters_[reg] = value;
903}
904
905int32_t Simulator::get_sregister_bits(SRegister reg) const {
906 ASSERT(TargetCPUFeatures::vfp_supported());
907 ASSERT((reg >= 0) && (reg < kNumberOfSRegisters));
908 return sregisters_[reg];
909}
910
911void Simulator::set_dregister_bits(DRegister reg, int64_t value) {
912 ASSERT(TargetCPUFeatures::vfp_supported());
913 ASSERT((reg >= 0) && (reg < kNumberOfDRegisters));
914 dregisters_[reg] = value;
915}
916
917int64_t Simulator::get_dregister_bits(DRegister reg) const {
918 ASSERT(TargetCPUFeatures::vfp_supported());
919 ASSERT((reg >= 0) && (reg < kNumberOfDRegisters));
920 return dregisters_[reg];
921}
922
923void Simulator::HandleIllegalAccess(uword addr, Instr* instr) {
924 uword fault_pc = get_pc();
925 // The debugger will not be able to single step past this instruction, but
926 // it will be possible to disassemble the code and inspect registers.
927 char buffer[128];
928 snprintf(buffer, sizeof(buffer),
929 "illegal memory access at 0x%" Px ", pc=0x%" Px "\n", addr,
930 fault_pc);
931 SimulatorDebugger dbg(this);
932 dbg.Stop(instr, buffer);
933 // The debugger will return control in non-interactive mode.
934 FATAL("Cannot continue execution after illegal memory access.");
935}
936
937void Simulator::UnimplementedInstruction(Instr* instr) {
938 char buffer[64];
939 snprintf(buffer, sizeof(buffer), "Unimplemented instruction: pc=%p\n", instr);
940 SimulatorDebugger dbg(this);
941 dbg.Stop(instr, buffer);
942 FATAL("Cannot continue execution after unimplemented instruction.");
943}
944
945DART_FORCE_INLINE intptr_t Simulator::ReadW(uword addr, Instr* instr) {
946 return *reinterpret_cast<intptr_t*>(addr);
947}
948
949DART_FORCE_INLINE void Simulator::WriteW(uword addr,
950 intptr_t value,
951 Instr* instr) {
952 *reinterpret_cast<intptr_t*>(addr) = value;
953}
954
955DART_FORCE_INLINE uint16_t Simulator::ReadHU(uword addr, Instr* instr) {
956 return *reinterpret_cast<uint16_t*>(addr);
957}
958
959DART_FORCE_INLINE int16_t Simulator::ReadH(uword addr, Instr* instr) {
960 return *reinterpret_cast<int16_t*>(addr);
961}
962
963DART_FORCE_INLINE void Simulator::WriteH(uword addr,
964 uint16_t value,
965 Instr* instr) {
966 *reinterpret_cast<uint16_t*>(addr) = value;
967}
968
969DART_FORCE_INLINE uint8_t Simulator::ReadBU(uword addr) {
970 return *reinterpret_cast<uint8_t*>(addr);
971}
972
973DART_FORCE_INLINE int8_t Simulator::ReadB(uword addr) {
974 return *reinterpret_cast<int8_t*>(addr);
975}
976
977DART_FORCE_INLINE void Simulator::WriteB(uword addr, uint8_t value) {
978 *reinterpret_cast<uint8_t*>(addr) = value;
979}
980
981void Simulator::ClearExclusive() {
982 exclusive_access_addr_ = 0;
983 exclusive_access_value_ = 0;
984}
985
986intptr_t Simulator::ReadExclusiveW(uword addr, Instr* instr) {
987 exclusive_access_addr_ = addr;
988 exclusive_access_value_ = ReadW(addr, instr);
989 return exclusive_access_value_;
990}
991
992intptr_t Simulator::WriteExclusiveW(uword addr, intptr_t value, Instr* instr) {
993 // In a well-formed code store-exclusive instruction should always follow
994 // a corresponding load-exclusive instruction with the same address.
995 ASSERT((exclusive_access_addr_ == 0) || (exclusive_access_addr_ == addr));
996 if (exclusive_access_addr_ != addr) {
997 return 1; // Failure.
998 }
999
1000 int32_t old_value = static_cast<uint32_t>(exclusive_access_value_);
1001 ClearExclusive();
1002
1003 auto atomic_addr = reinterpret_cast<RelaxedAtomic<int32_t>*>(addr);
1004 if (atomic_addr->compare_exchange_weak(old_value, value)) {
1005 return 0; // Success.
1006 }
1007 return 1; // Failure.
1008}
1009
1010bool Simulator::IsTracingExecution() const {
1011 return icount_ > FLAG_trace_sim_after;
1012}
1013
1014// Unsupported instructions use Format to print an error and stop execution.
1015void Simulator::Format(Instr* instr, const char* format) {
1016 OS::PrintErr("Simulator found unsupported instruction:\n 0x%p: %s\n", instr,
1017 format);
1018 UNIMPLEMENTED();
1019}
1020
1021// Checks if the current instruction should be executed based on its
1022// condition bits.
1023DART_FORCE_INLINE bool Simulator::ConditionallyExecute(Instr* instr) {
1024 switch (instr->ConditionField()) {
1025 case EQ:
1026 return z_flag_;
1027 case NE:
1028 return !z_flag_;
1029 case CS:
1030 return c_flag_;
1031 case CC:
1032 return !c_flag_;
1033 case MI:
1034 return n_flag_;
1035 case PL:
1036 return !n_flag_;
1037 case VS:
1038 return v_flag_;
1039 case VC:
1040 return !v_flag_;
1041 case HI:
1042 return c_flag_ && !z_flag_;
1043 case LS:
1044 return !c_flag_ || z_flag_;
1045 case GE:
1046 return n_flag_ == v_flag_;
1047 case LT:
1048 return n_flag_ != v_flag_;
1049 case GT:
1050 return !z_flag_ && (n_flag_ == v_flag_);
1051 case LE:
1052 return z_flag_ || (n_flag_ != v_flag_);
1053 case AL:
1054 return true;
1055 default:
1056 UNREACHABLE();
1057 }
1058 return false;
1059}
1060
1061// Calculate and set the Negative and Zero flags.
1062DART_FORCE_INLINE void Simulator::SetNZFlags(int32_t val) {
1063 n_flag_ = (val < 0);
1064 z_flag_ = (val == 0);
1065}
1066
1067// Set the Carry flag.
1068DART_FORCE_INLINE void Simulator::SetCFlag(bool val) {
1069 c_flag_ = val;
1070}
1071
1072// Set the oVerflow flag.
1073DART_FORCE_INLINE void Simulator::SetVFlag(bool val) {
1074 v_flag_ = val;
1075}
1076
1077// Calculate C flag value for additions (and subtractions with adjusted args).
1078DART_FORCE_INLINE bool Simulator::CarryFrom(int32_t left,
1079 int32_t right,
1080 int32_t carry) {
1081 uint64_t uleft = static_cast<uint32_t>(left);
1082 uint64_t uright = static_cast<uint32_t>(right);
1083 uint64_t ucarry = static_cast<uint32_t>(carry);
1084 return ((uleft + uright + ucarry) >> 32) != 0;
1085}
1086
1087// Calculate V flag value for additions (and subtractions with adjusted args).
1088DART_FORCE_INLINE bool Simulator::OverflowFrom(int32_t left,
1089 int32_t right,
1090 int32_t carry) {
1091 int64_t result = static_cast<int64_t>(left) + right + carry;
1092 return (result >> 31) != (result >> 32);
1093}
1094
1095// Addressing Mode 1 - Data-processing operands:
1096// Get the value based on the shifter_operand with register.
1097int32_t Simulator::GetShiftRm(Instr* instr, bool* carry_out) {
1098 Shift shift = instr->ShiftField();
1099 int shift_amount = instr->ShiftAmountField();
1100 int32_t result = get_register(instr->RmField());
1101 if (instr->Bit(4) == 0) {
1102 // by immediate
1103 if ((shift == ROR) && (shift_amount == 0)) {
1104 UnimplementedInstruction(instr);
1105 } else if (((shift == LSR) || (shift == ASR)) && (shift_amount == 0)) {
1106 shift_amount = 32;
1107 }
1108 switch (shift) {
1109 case ASR: {
1110 if (shift_amount == 0) {
1111 if (result < 0) {
1112 result = 0xffffffff;
1113 *carry_out = true;
1114 } else {
1115 result = 0;
1116 *carry_out = false;
1117 }
1118 } else {
1119 result >>= (shift_amount - 1);
1120 *carry_out = (result & 1) == 1;
1121 result >>= 1;
1122 }
1123 break;
1124 }
1125
1126 case LSL: {
1127 if (shift_amount == 0) {
1128 *carry_out = c_flag_;
1129 } else {
1130 result = static_cast<uint32_t>(result) << (shift_amount - 1);
1131 *carry_out = (result < 0);
1132 result = static_cast<uint32_t>(result) << 1;
1133 }
1134 break;
1135 }
1136
1137 case LSR: {
1138 if (shift_amount == 0) {
1139 result = 0;
1140 *carry_out = c_flag_;
1141 } else {
1142 uint32_t uresult = static_cast<uint32_t>(result);
1143 uresult >>= (shift_amount - 1);
1144 *carry_out = (uresult & 1) == 1;
1145 uresult >>= 1;
1146 result = static_cast<int32_t>(uresult);
1147 }
1148 break;
1149 }
1150
1151 case ROR: {
1152 UnimplementedInstruction(instr);
1153 break;
1154 }
1155
1156 default: {
1157 UNREACHABLE();
1158 break;
1159 }
1160 }
1161 } else {
1162 // by register
1163 Register rs = instr->RsField();
1164 shift_amount = get_register(rs) & 0xff;
1165 switch (shift) {
1166 case ASR: {
1167 if (shift_amount == 0) {
1168 *carry_out = c_flag_;
1169 } else if (shift_amount < 32) {
1170 result >>= (shift_amount - 1);
1171 *carry_out = (result & 1) == 1;
1172 result >>= 1;
1173 } else {
1174 ASSERT(shift_amount >= 32);
1175 if (result < 0) {
1176 *carry_out = true;
1177 result = 0xffffffff;
1178 } else {
1179 *carry_out = false;
1180 result = 0;
1181 }
1182 }
1183 break;
1184 }
1185
1186 case LSL: {
1187 if (shift_amount == 0) {
1188 *carry_out = c_flag_;
1189 } else if (shift_amount < 32) {
1190 result = static_cast<uint32_t>(result) << (shift_amount - 1);
1191 *carry_out = (result < 0);
1192 result = static_cast<uint32_t>(result) << 1;
1193 } else if (shift_amount == 32) {
1194 *carry_out = (result & 1) == 1;
1195 result = 0;
1196 } else {
1197 ASSERT(shift_amount > 32);
1198 *carry_out = false;
1199 result = 0;
1200 }
1201 break;
1202 }
1203
1204 case LSR: {
1205 if (shift_amount == 0) {
1206 *carry_out = c_flag_;
1207 } else if (shift_amount < 32) {
1208 uint32_t uresult = static_cast<uint32_t>(result);
1209 uresult >>= (shift_amount - 1);
1210 *carry_out = (uresult & 1) == 1;
1211 uresult >>= 1;
1212 result = static_cast<int32_t>(uresult);
1213 } else if (shift_amount == 32) {
1214 *carry_out = (result < 0);
1215 result = 0;
1216 } else {
1217 *carry_out = false;
1218 result = 0;
1219 }
1220 break;
1221 }
1222
1223 case ROR: {
1224 UnimplementedInstruction(instr);
1225 break;
1226 }
1227
1228 default: {
1229 UNREACHABLE();
1230 break;
1231 }
1232 }
1233 }
1234 return result;
1235}
1236
1237// Addressing Mode 1 - Data-processing operands:
1238// Get the value based on the shifter_operand with immediate.
1239DART_FORCE_INLINE int32_t Simulator::GetImm(Instr* instr, bool* carry_out) {
1240 uint8_t rotate = instr->RotateField() * 2;
1241 int32_t immed8 = instr->Immed8Field();
1242 int32_t imm = Utils::RotateRight(immed8, rotate);
1243 *carry_out = (rotate == 0) ? c_flag_ : (imm < 0);
1244 return imm;
1245}
1246
1247// Addressing Mode 4 - Load and Store Multiple
1248void Simulator::HandleRList(Instr* instr, bool load) {
1249 Register rn = instr->RnField();
1250 int32_t rn_val = get_register(rn);
1251 int rlist = instr->RlistField();
1252 int num_regs = Utils::CountOneBits32(static_cast<uint32_t>(rlist));
1253
1254 uword address = 0;
1255 uword end_address = 0;
1256 switch (instr->PUField()) {
1257 case 0: {
1258 // Print("da");
1259 address = rn_val - (num_regs * 4) + 4;
1260 end_address = rn_val + 4;
1261 rn_val = rn_val - (num_regs * 4);
1262 break;
1263 }
1264 case 1: {
1265 // Print("ia");
1266 address = rn_val;
1267 end_address = rn_val + (num_regs * 4);
1268 rn_val = rn_val + (num_regs * 4);
1269 break;
1270 }
1271 case 2: {
1272 // Print("db");
1273 address = rn_val - (num_regs * 4);
1274 end_address = rn_val;
1275 rn_val = address;
1276 break;
1277 }
1278 case 3: {
1279 // Print("ib");
1280 address = rn_val + 4;
1281 end_address = rn_val + (num_regs * 4) + 4;
1282 rn_val = rn_val + (num_regs * 4);
1283 break;
1284 }
1285 default: {
1286 UNREACHABLE();
1287 break;
1288 }
1289 }
1290 if (IsIllegalAddress(address)) {
1291 HandleIllegalAccess(address, instr);
1292 } else {
1293 if (instr->HasW()) {
1294 set_register(rn, rn_val);
1295 }
1296 int reg = 0;
1297 while (rlist != 0) {
1298 if ((rlist & 1) != 0) {
1299 if (load) {
1300 set_register(static_cast<Register>(reg), ReadW(address, instr));
1301 } else {
1302 WriteW(address, get_register(static_cast<Register>(reg)), instr);
1303 }
1304 address += 4;
1305 }
1306 reg++;
1307 rlist >>= 1;
1308 }
1309 ASSERT(end_address == address);
1310 }
1311}
1312
1313// Calls into the Dart runtime are based on this interface.
1314typedef void (*SimulatorRuntimeCall)(NativeArguments arguments);
1315
1316// Calls to leaf Dart runtime functions are based on this interface.
1317typedef int32_t (*SimulatorLeafRuntimeCall)(int32_t r0,
1318 int32_t r1,
1319 int32_t r2,
1320 int32_t r3,
1321 int32_t r4);
1322
1323// [target] has several different signatures that differ from
1324// SimulatorLeafRuntimeCall. We can call them all from here only because in
1325// IA32's calling convention a function can be called with extra arguments
1326// and the callee will see the first arguments and won't unbalance the stack.
1327NO_SANITIZE_UNDEFINED("function")
1328static int32_t InvokeLeafRuntime(SimulatorLeafRuntimeCall target,
1329 int32_t r0,
1330 int32_t r1,
1331 int32_t r2,
1332 int32_t r3,
1333 int32_t r4) {
1334 return target(r0, r1, r2, r3, r4);
1335}
1336
1337// Calls to leaf float Dart runtime functions are based on this interface.
1338typedef double (*SimulatorLeafFloatRuntimeCall)(double d0, double d1);
1339
1340// [target] has several different signatures that differ from
1341// SimulatorFloatLeafRuntimeCall. We can call them all from here only because
1342// IA32's calling convention a function can be called with extra arguments
1343// and the callee will see the first arguments and won't unbalance the stack.
1344NO_SANITIZE_UNDEFINED("function")
1345static double InvokeFloatLeafRuntime(SimulatorLeafFloatRuntimeCall target,
1346 double d0,
1347 double d1) {
1348 return target(d0, d1);
1349}
1350
1351// Calls to native Dart functions are based on this interface.
1352typedef void (*SimulatorNativeCallWrapper)(Dart_NativeArguments arguments,
1353 Dart_NativeFunction target);
1354
1355void Simulator::SupervisorCall(Instr* instr) {
1356 int svc = instr->SvcField();
1357 switch (svc) {
1358 case Instr::kSimulatorRedirectCode: {
1359 SimulatorSetjmpBuffer buffer(this);
1360
1361 if (!setjmp(buffer.buffer_)) {
1362 int32_t saved_lr = get_register(LR);
1363 Redirection* redirection = Redirection::FromSvcInstruction(instr);
1364 uword external = redirection->external_function();
1365 if (IsTracingExecution()) {
1366 THR_Print("Call to host function at 0x%" Pd "\n", external);
1367 }
1368 if (redirection->call_kind() == kRuntimeCall) {
1369 NativeArguments arguments(NULL, 0, NULL, NULL);
1370 ASSERT(sizeof(NativeArguments) == 4 * kWordSize);
1371 arguments.thread_ = reinterpret_cast<Thread*>(get_register(R0));
1372 arguments.argc_tag_ = get_register(R1);
1373 arguments.argv_ = reinterpret_cast<ObjectPtr*>(get_register(R2));
1374 arguments.retval_ = reinterpret_cast<ObjectPtr*>(get_register(R3));
1375 SimulatorRuntimeCall target =
1376 reinterpret_cast<SimulatorRuntimeCall>(external);
1377 target(arguments);
1378 set_register(R0, icount_); // Zap result register from void function.
1379 set_register(R1, icount_);
1380 } else if (redirection->call_kind() == kLeafRuntimeCall) {
1381 ASSERT((0 <= redirection->argument_count()) &&
1382 (redirection->argument_count() <= 5));
1383 int32_t r0 = get_register(R0);
1384 int32_t r1 = get_register(R1);
1385 int32_t r2 = get_register(R2);
1386 int32_t r3 = get_register(R3);
1387 int32_t r4 = *reinterpret_cast<int32_t*>(get_register(SP));
1388 SimulatorLeafRuntimeCall target =
1389 reinterpret_cast<SimulatorLeafRuntimeCall>(external);
1390 r0 = InvokeLeafRuntime(target, r0, r1, r2, r3, r4);
1391 set_register(R0, r0); // Set returned result from function.
1392 set_register(R1, icount_); // Zap unused result register.
1393 } else if (redirection->call_kind() == kLeafFloatRuntimeCall) {
1394 ASSERT((0 <= redirection->argument_count()) &&
1395 (redirection->argument_count() <= 2));
1396 SimulatorLeafFloatRuntimeCall target =
1397 reinterpret_cast<SimulatorLeafFloatRuntimeCall>(external);
1398 if (TargetCPUFeatures::hardfp_supported()) {
1399 // If we're doing "hardfp", the double arguments are already in the
1400 // floating point registers.
1401 double d0 = get_dregister(D0);
1402 double d1 = get_dregister(D1);
1403 d0 = InvokeFloatLeafRuntime(target, d0, d1);
1404 set_dregister(D0, d0);
1405 } else {
1406 // If we're not doing "hardfp", we must be doing "soft" or "softfp",
1407 // So take the double arguments from the integer registers.
1408 uint32_t r0 = get_register(R0);
1409 int32_t r1 = get_register(R1);
1410 uint32_t r2 = get_register(R2);
1411 int32_t r3 = get_register(R3);
1412 int64_t a0 = Utils::LowHighTo64Bits(r0, r1);
1413 int64_t a1 = Utils::LowHighTo64Bits(r2, r3);
1414 double d0 = bit_cast<double, int64_t>(a0);
1415 double d1 = bit_cast<double, int64_t>(a1);
1416 d0 = InvokeFloatLeafRuntime(target, d0, d1);
1417 a0 = bit_cast<int64_t, double>(d0);
1418 r0 = Utils::Low32Bits(a0);
1419 r1 = Utils::High32Bits(a0);
1420 set_register(R0, r0);
1421 set_register(R1, r1);
1422 }
1423 } else {
1424 ASSERT(redirection->call_kind() == kNativeCallWrapper);
1425 SimulatorNativeCallWrapper wrapper =
1426 reinterpret_cast<SimulatorNativeCallWrapper>(external);
1427 Dart_NativeArguments arguments =
1428 reinterpret_cast<Dart_NativeArguments>(get_register(R0));
1429 Dart_NativeFunction target_func =
1430 reinterpret_cast<Dart_NativeFunction>(get_register(R1));
1431 wrapper(arguments, target_func);
1432 set_register(R0, icount_); // Zap result register from void function.
1433 set_register(R1, icount_);
1434 }
1435
1436 // Zap caller-saved registers, since the actual runtime call could have
1437 // used them.
1438 set_register(R2, icount_);
1439 set_register(R3, icount_);
1440 set_register(IP, icount_);
1441 set_register(LR, icount_);
1442 if (TargetCPUFeatures::vfp_supported()) {
1443 double zap_dvalue = static_cast<double>(icount_);
1444 // Do not zap D0, as it may contain a float result.
1445 for (int i = D1; i <= D7; i++) {
1446 set_dregister(static_cast<DRegister>(i), zap_dvalue);
1447 }
1448// The above loop also zaps overlapping registers S2-S15.
1449// Registers D8-D15 (overlapping with S16-S31) are preserved.
1450#if defined(VFPv3_D32)
1451 for (int i = D16; i <= D31; i++) {
1452 set_dregister(static_cast<DRegister>(i), zap_dvalue);
1453 }
1454#endif
1455 }
1456
1457 // Return.
1458 set_pc(saved_lr);
1459 } else {
1460 // Coming via long jump from a throw. Continue to exception handler.
1461 }
1462
1463 break;
1464 }
1465 case Instr::kSimulatorBreakCode: {
1466 SimulatorDebugger dbg(this);
1467 dbg.Stop(instr, "breakpoint");
1468 break;
1469 }
1470 default: {
1471 UNREACHABLE();
1472 break;
1473 }
1474 }
1475}
1476
1477// Handle execution based on instruction types.
1478
1479// Instruction types 0 and 1 are both rolled into one function because they
1480// only differ in the handling of the shifter_operand.
1481DART_FORCE_INLINE void Simulator::DecodeType01(Instr* instr) {
1482 if (!instr->IsDataProcessing()) {
1483 // miscellaneous, multiply, sync primitives, extra loads and stores.
1484 if (instr->IsMiscellaneous()) {
1485 switch (instr->Bits(4, 3)) {
1486 case 1: {
1487 if (instr->Bits(21, 2) == 0x3) {
1488 // Format(instr, "clz'cond 'rd, 'rm");
1489 Register rm = instr->RmField();
1490 Register rd = instr->RdField();
1491 int32_t rm_val = get_register(rm);
1492 int32_t rd_val = 0;
1493 if (rm_val != 0) {
1494 while (rm_val > 0) {
1495 rd_val++;
1496 rm_val <<= 1;
1497 }
1498 } else {
1499 rd_val = 32;
1500 }
1501 set_register(rd, rd_val);
1502 } else {
1503 ASSERT(instr->Bits(21, 2) == 0x1);
1504 // Format(instr, "bx'cond 'rm");
1505 Register rm = instr->RmField();
1506 int32_t rm_val = get_register(rm);
1507 set_pc(rm_val);
1508 }
1509 break;
1510 }
1511 case 3: {
1512 ASSERT(instr->Bits(21, 2) == 0x1);
1513 // Format(instr, "blx'cond 'rm");
1514 Register rm = instr->RmField();
1515 int32_t rm_val = get_register(rm);
1516 intptr_t pc = get_pc();
1517 set_register(LR, pc + Instr::kInstrSize);
1518 set_pc(rm_val);
1519 break;
1520 }
1521 case 7: {
1522 if ((instr->Bits(21, 2) == 0x1) && (instr->ConditionField() == AL)) {
1523 // Format(instr, "bkpt #'imm12_4");
1524 SimulatorDebugger dbg(this);
1525 int32_t imm = instr->BkptField();
1526 char buffer[32];
1527 snprintf(buffer, sizeof(buffer), "bkpt #0x%x", imm);
1528 set_pc(get_pc() + Instr::kInstrSize);
1529 dbg.Stop(instr, buffer);
1530 } else {
1531 // Format(instr, "smc'cond");
1532 UnimplementedInstruction(instr);
1533 }
1534 break;
1535 }
1536 default: {
1537 UnimplementedInstruction(instr);
1538 break;
1539 }
1540 }
1541 } else if (instr->IsMultiplyOrSyncPrimitive()) {
1542 if (instr->Bit(24) == 0) {
1543 // multiply instructions.
1544 Register rn = instr->RnField();
1545 Register rd = instr->RdField();
1546 Register rs = instr->RsField();
1547 Register rm = instr->RmField();
1548 uint32_t rm_val = get_register(rm);
1549 uint32_t rs_val = get_register(rs);
1550 uint32_t rd_val = 0;
1551 switch (instr->Bits(21, 3)) {
1552 case 1:
1553 // Registers rd, rn, rm, ra are encoded as rn, rm, rs, rd.
1554 // Format(instr, "mla'cond's 'rn, 'rm, 'rs, 'rd");
1555 case 3: {
1556 // Registers rd, rn, rm, ra are encoded as rn, rm, rs, rd.
1557 // Format(instr, "mls'cond's 'rn, 'rm, 'rs, 'rd");
1558 rd_val = get_register(rd);
1559 FALL_THROUGH;
1560 }
1561 case 0: {
1562 // Registers rd, rn, rm are encoded as rn, rm, rs.
1563 // Format(instr, "mul'cond's 'rn, 'rm, 'rs");
1564 uint32_t alu_out = rm_val * rs_val;
1565 if (instr->Bits(21, 3) == 3) { // mls
1566 alu_out = -alu_out;
1567 }
1568 alu_out += rd_val;
1569 set_register(rn, alu_out);
1570 if (instr->HasS()) {
1571 SetNZFlags(alu_out);
1572 }
1573 break;
1574 }
1575 case 4:
1576 // Registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs.
1577 // Format(instr, "umull'cond's 'rd, 'rn, 'rm, 'rs");
1578 case 6: {
1579 // Registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs.
1580 // Format(instr, "smull'cond's 'rd, 'rn, 'rm, 'rs");
1581 int64_t result;
1582 if (instr->Bits(21, 3) == 4) { // umull
1583 uint64_t left_op = static_cast<uint32_t>(rm_val);
1584 uint64_t right_op = static_cast<uint32_t>(rs_val);
1585 result = left_op * right_op; // Unsigned multiplication.
1586 } else { // smull
1587 int64_t left_op = static_cast<int32_t>(rm_val);
1588 int64_t right_op = static_cast<int32_t>(rs_val);
1589 result = left_op * right_op; // Signed multiplication.
1590 }
1591 int32_t hi_res = Utils::High32Bits(result);
1592 int32_t lo_res = Utils::Low32Bits(result);
1593 set_register(rd, lo_res);
1594 set_register(rn, hi_res);
1595 if (instr->HasS()) {
1596 if (lo_res != 0) {
1597 // Collapse bits 0..31 into bit 32 so that 32-bit Z check works.
1598 hi_res |= 1;
1599 }
1600 ASSERT((result == 0) == (hi_res == 0)); // Z bit
1601 ASSERT(((result & (1LL << 63)) != 0) == (hi_res < 0)); // N bit
1602 SetNZFlags(hi_res);
1603 }
1604 break;
1605 }
1606 case 2:
1607 // Registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs.
1608 // Format(instr, "umaal'cond's 'rd, 'rn, 'rm, 'rs");
1609 FALL_THROUGH;
1610 case 5:
1611 // Registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs.
1612 // Format(instr, "umlal'cond's 'rd, 'rn, 'rm, 'rs");
1613 FALL_THROUGH;
1614 case 7: {
1615 // Registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs.
1616 // Format(instr, "smlal'cond's 'rd, 'rn, 'rm, 'rs");
1617 int32_t rd_lo_val = get_register(rd);
1618 int32_t rd_hi_val = get_register(rn);
1619 uint32_t accum_lo = static_cast<uint32_t>(rd_lo_val);
1620 int32_t accum_hi = static_cast<int32_t>(rd_hi_val);
1621 int64_t accum = Utils::LowHighTo64Bits(accum_lo, accum_hi);
1622 int64_t result;
1623 if (instr->Bits(21, 3) == 5) { // umlal
1624 uint64_t left_op = static_cast<uint32_t>(rm_val);
1625 uint64_t right_op = static_cast<uint32_t>(rs_val);
1626 result = accum + left_op * right_op; // Unsigned multiplication.
1627 } else if (instr->Bits(21, 3) == 7) { // smlal
1628 int64_t left_op = static_cast<int32_t>(rm_val);
1629 int64_t right_op = static_cast<int32_t>(rs_val);
1630 result = accum + left_op * right_op; // Signed multiplication.
1631 } else {
1632 ASSERT(instr->Bits(21, 3) == 2); // umaal
1633 ASSERT(!instr->HasS());
1634 uint64_t left_op = static_cast<uint32_t>(rm_val);
1635 uint64_t right_op = static_cast<uint32_t>(rs_val);
1636 result = left_op * right_op + // Unsigned multiplication.
1637 static_cast<uint32_t>(rd_lo_val) +
1638 static_cast<uint32_t>(rd_hi_val);
1639 }
1640 int32_t hi_res = Utils::High32Bits(result);
1641 int32_t lo_res = Utils::Low32Bits(result);
1642 set_register(rd, lo_res);
1643 set_register(rn, hi_res);
1644 if (instr->HasS()) {
1645 if (lo_res != 0) {
1646 // Collapse bits 0..31 into bit 32 so that 32-bit Z check works.
1647 hi_res |= 1;
1648 }
1649 ASSERT((result == 0) == (hi_res == 0)); // Z bit
1650 ASSERT(((result & (1LL << 63)) != 0) == (hi_res < 0)); // N bit
1651 SetNZFlags(hi_res);
1652 }
1653 break;
1654 }
1655 default: {
1656 UnimplementedInstruction(instr);
1657 break;
1658 }
1659 }
1660 } else {
1661 // synchronization primitives
1662 Register rd = instr->RdField();
1663 Register rn = instr->RnField();
1664 uword addr = get_register(rn);
1665 switch (instr->Bits(20, 4)) {
1666 case 8: {
1667 // Format(instr, "strex'cond 'rd, 'rm, ['rn]");
1668 if (IsIllegalAddress(addr)) {
1669 HandleIllegalAccess(addr, instr);
1670 } else {
1671 Register rm = instr->RmField();
1672 set_register(rd, WriteExclusiveW(addr, get_register(rm), instr));
1673 }
1674 break;
1675 }
1676 case 9: {
1677 // Format(instr, "ldrex'cond 'rd, ['rn]");
1678 if (IsIllegalAddress(addr)) {
1679 HandleIllegalAccess(addr, instr);
1680 } else {
1681 set_register(rd, ReadExclusiveW(addr, instr));
1682 }
1683 break;
1684 }
1685 default: {
1686 UnimplementedInstruction(instr);
1687 break;
1688 }
1689 }
1690 }
1691 } else if (instr->Bit(25) == 1) {
1692 // 16-bit immediate loads, msr (immediate), and hints
1693 switch (instr->Bits(20, 5)) {
1694 case 16:
1695 case 20: {
1696 uint16_t imm16 = instr->MovwField();
1697 Register rd = instr->RdField();
1698 if (instr->Bit(22) == 0) {
1699 // Format(instr, "movw'cond 'rd, #'imm4_12");
1700 set_register(rd, imm16);
1701 } else {
1702 // Format(instr, "movt'cond 'rd, #'imm4_12");
1703 set_register(rd, (get_register(rd) & 0xffff) | (imm16 << 16));
1704 }
1705 break;
1706 }
1707 case 18: {
1708 if ((instr->Bits(16, 4) == 0) && (instr->Bits(0, 8) == 0)) {
1709 // Format(instr, "nop'cond");
1710 } else {
1711 UnimplementedInstruction(instr);
1712 }
1713 break;
1714 }
1715 default: {
1716 UnimplementedInstruction(instr);
1717 break;
1718 }
1719 }
1720 } else {
1721 // extra load/store instructions
1722 Register rd = instr->RdField();
1723 Register rn = instr->RnField();
1724 int32_t rn_val = get_register(rn);
1725 uword addr = 0;
1726 bool write_back = false;
1727 if (instr->Bit(22) == 0) {
1728 Register rm = instr->RmField();
1729 int32_t rm_val = get_register(rm);
1730 switch (instr->PUField()) {
1731 case 0: {
1732 // Format(instr, "'memop'cond'x 'rd2, ['rn], -'rm");
1733 ASSERT(!instr->HasW());
1734 addr = rn_val;
1735 rn_val -= rm_val;
1736 write_back = true;
1737 break;
1738 }
1739 case 1: {
1740 // Format(instr, "'memop'cond'x 'rd2, ['rn], +'rm");
1741 ASSERT(!instr->HasW());
1742 addr = rn_val;
1743 rn_val += rm_val;
1744 write_back = true;
1745 break;
1746 }
1747 case 2: {
1748 // Format(instr, "'memop'cond'x 'rd2, ['rn, -'rm]'w");
1749 rn_val -= rm_val;
1750 addr = rn_val;
1751 write_back = instr->HasW();
1752 break;
1753 }
1754 case 3: {
1755 // Format(instr, "'memop'cond'x 'rd2, ['rn, +'rm]'w");
1756 rn_val += rm_val;
1757 addr = rn_val;
1758 write_back = instr->HasW();
1759 break;
1760 }
1761 default: {
1762 // The PU field is a 2-bit field.
1763 UNREACHABLE();
1764 break;
1765 }
1766 }
1767 } else {
1768 int32_t imm_val = (instr->ImmedHField() << 4) | instr->ImmedLField();
1769 switch (instr->PUField()) {
1770 case 0: {
1771 // Format(instr, "'memop'cond'x 'rd2, ['rn], #-'off8");
1772 ASSERT(!instr->HasW());
1773 addr = rn_val;
1774 rn_val -= imm_val;
1775 write_back = true;
1776 break;
1777 }
1778 case 1: {
1779 // Format(instr, "'memop'cond'x 'rd2, ['rn], #+'off8");
1780 ASSERT(!instr->HasW());
1781 addr = rn_val;
1782 rn_val += imm_val;
1783 write_back = true;
1784 break;
1785 }
1786 case 2: {
1787 // Format(instr, "'memop'cond'x 'rd2, ['rn, #-'off8]'w");
1788 rn_val -= imm_val;
1789 addr = rn_val;
1790 write_back = instr->HasW();
1791 break;
1792 }
1793 case 3: {
1794 // Format(instr, "'memop'cond'x 'rd2, ['rn, #+'off8]'w");
1795 rn_val += imm_val;
1796 addr = rn_val;
1797 write_back = instr->HasW();
1798 break;
1799 }
1800 default: {
1801 // The PU field is a 2-bit field.
1802 UNREACHABLE();
1803 break;
1804 }
1805 }
1806 }
1807 if (IsIllegalAddress(addr)) {
1808 HandleIllegalAccess(addr, instr);
1809 } else {
1810 if (write_back) {
1811 ASSERT(rd != rn); // Unpredictable.
1812 set_register(rn, rn_val);
1813 }
1814 if (!instr->HasSign()) {
1815 if (instr->HasL()) {
1816 uint16_t val = ReadHU(addr, instr);
1817 set_register(rd, val);
1818 } else {
1819 uint16_t val = get_register(rd);
1820 WriteH(addr, val, instr);
1821 }
1822 } else if (instr->HasL()) {
1823 if (instr->HasH()) {
1824 int16_t val = ReadH(addr, instr);
1825 set_register(rd, val);
1826 } else {
1827 int8_t val = ReadB(addr);
1828 set_register(rd, val);
1829 }
1830 } else if ((rd & 1) == 0) {
1831 Register rd1 = static_cast<Register>(rd | 1);
1832 ASSERT(rd1 < kNumberOfCpuRegisters);
1833 if (instr->HasH()) {
1834 int32_t val_low = get_register(rd);
1835 int32_t val_high = get_register(rd1);
1836 WriteW(addr, val_low, instr);
1837 WriteW(addr + 4, val_high, instr);
1838 } else {
1839 int32_t val_low = ReadW(addr, instr);
1840 int32_t val_high = ReadW(addr + 4, instr);
1841 set_register(rd, val_low);
1842 set_register(rd1, val_high);
1843 }
1844 } else {
1845 UnimplementedInstruction(instr);
1846 }
1847 }
1848 }
1849 } else {
1850 Register rd = instr->RdField();
1851 Register rn = instr->RnField();
1852 uint32_t rn_val = get_register(rn);
1853 uint32_t shifter_operand = 0;
1854 bool shifter_carry_out = 0;
1855 if (instr->TypeField() == 0) {
1856 shifter_operand = GetShiftRm(instr, &shifter_carry_out);
1857 } else {
1858 ASSERT(instr->TypeField() == 1);
1859 shifter_operand = GetImm(instr, &shifter_carry_out);
1860 }
1861 uint32_t carry_in;
1862 uint32_t alu_out;
1863
1864 switch (instr->OpcodeField()) {
1865 case AND: {
1866 // Format(instr, "and'cond's 'rd, 'rn, 'shift_rm");
1867 // Format(instr, "and'cond's 'rd, 'rn, 'imm");
1868 alu_out = rn_val & shifter_operand;
1869 set_register(rd, alu_out);
1870 if (instr->HasS()) {
1871 SetNZFlags(alu_out);
1872 SetCFlag(shifter_carry_out);
1873 }
1874 break;
1875 }
1876
1877 case EOR: {
1878 // Format(instr, "eor'cond's 'rd, 'rn, 'shift_rm");
1879 // Format(instr, "eor'cond's 'rd, 'rn, 'imm");
1880 alu_out = rn_val ^ shifter_operand;
1881 set_register(rd, alu_out);
1882 if (instr->HasS()) {
1883 SetNZFlags(alu_out);
1884 SetCFlag(shifter_carry_out);
1885 }
1886 break;
1887 }
1888
1889 case SUB: {
1890 // Format(instr, "sub'cond's 'rd, 'rn, 'shift_rm");
1891 // Format(instr, "sub'cond's 'rd, 'rn, 'imm");
1892 alu_out = rn_val - shifter_operand;
1893 set_register(rd, alu_out);
1894 if (instr->HasS()) {
1895 SetNZFlags(alu_out);
1896 SetCFlag(CarryFrom(rn_val, ~shifter_operand, 1));
1897 SetVFlag(OverflowFrom(rn_val, ~shifter_operand, 1));
1898 }
1899 break;
1900 }
1901
1902 case RSB: {
1903 // Format(instr, "rsb'cond's 'rd, 'rn, 'shift_rm");
1904 // Format(instr, "rsb'cond's 'rd, 'rn, 'imm");
1905 alu_out = shifter_operand - rn_val;
1906 set_register(rd, alu_out);
1907 if (instr->HasS()) {
1908 SetNZFlags(alu_out);
1909 SetCFlag(CarryFrom(shifter_operand, ~rn_val, 1));
1910 SetVFlag(OverflowFrom(shifter_operand, ~rn_val, 1));
1911 }
1912 break;
1913 }
1914
1915 case ADD: {
1916 // Format(instr, "add'cond's 'rd, 'rn, 'shift_rm");
1917 // Format(instr, "add'cond's 'rd, 'rn, 'imm");
1918 alu_out = rn_val + shifter_operand;
1919 set_register(rd, alu_out);
1920 if (instr->HasS()) {
1921 SetNZFlags(alu_out);
1922 SetCFlag(CarryFrom(rn_val, shifter_operand, 0));
1923 SetVFlag(OverflowFrom(rn_val, shifter_operand, 0));
1924 }
1925 break;
1926 }
1927
1928 case ADC: {
1929 // Format(instr, "adc'cond's 'rd, 'rn, 'shift_rm");
1930 // Format(instr, "adc'cond's 'rd, 'rn, 'imm");
1931 carry_in = c_flag_ ? 1 : 0;
1932 alu_out = rn_val + shifter_operand + carry_in;
1933 set_register(rd, alu_out);
1934 if (instr->HasS()) {
1935 SetNZFlags(alu_out);
1936 SetCFlag(CarryFrom(rn_val, shifter_operand, carry_in));
1937 SetVFlag(OverflowFrom(rn_val, shifter_operand, carry_in));
1938 }
1939 break;
1940 }
1941
1942 case SBC: {
1943 // Format(instr, "sbc'cond's 'rd, 'rn, 'shift_rm");
1944 // Format(instr, "sbc'cond's 'rd, 'rn, 'imm");
1945 carry_in = c_flag_ ? 1 : 0;
1946 alu_out = rn_val + ~shifter_operand + carry_in;
1947 set_register(rd, alu_out);
1948 if (instr->HasS()) {
1949 SetNZFlags(alu_out);
1950 SetCFlag(CarryFrom(rn_val, ~shifter_operand, carry_in));
1951 SetVFlag(OverflowFrom(rn_val, ~shifter_operand, carry_in));
1952 }
1953 break;
1954 }
1955
1956 case RSC: {
1957 // Format(instr, "rsc'cond's 'rd, 'rn, 'shift_rm");
1958 // Format(instr, "rsc'cond's 'rd, 'rn, 'imm");
1959 carry_in = c_flag_ ? 1 : 0;
1960 alu_out = shifter_operand + ~rn_val + carry_in;
1961 set_register(rd, alu_out);
1962 if (instr->HasS()) {
1963 SetNZFlags(alu_out);
1964 SetCFlag(CarryFrom(shifter_operand, ~rn_val, carry_in));
1965 SetVFlag(OverflowFrom(shifter_operand, ~rn_val, carry_in));
1966 }
1967 break;
1968 }
1969
1970 case TST: {
1971 if (instr->HasS()) {
1972 // Format(instr, "tst'cond 'rn, 'shift_rm");
1973 // Format(instr, "tst'cond 'rn, 'imm");
1974 alu_out = rn_val & shifter_operand;
1975 SetNZFlags(alu_out);
1976 SetCFlag(shifter_carry_out);
1977 } else {
1978 UnimplementedInstruction(instr);
1979 }
1980 break;
1981 }
1982
1983 case TEQ: {
1984 if (instr->HasS()) {
1985 // Format(instr, "teq'cond 'rn, 'shift_rm");
1986 // Format(instr, "teq'cond 'rn, 'imm");
1987 alu_out = rn_val ^ shifter_operand;
1988 SetNZFlags(alu_out);
1989 SetCFlag(shifter_carry_out);
1990 } else {
1991 UnimplementedInstruction(instr);
1992 }
1993 break;
1994 }
1995
1996 case CMP: {
1997 if (instr->HasS()) {
1998 // Format(instr, "cmp'cond 'rn, 'shift_rm");
1999 // Format(instr, "cmp'cond 'rn, 'imm");
2000 alu_out = rn_val - shifter_operand;
2001 SetNZFlags(alu_out);
2002 SetCFlag(CarryFrom(rn_val, ~shifter_operand, 1));
2003 SetVFlag(OverflowFrom(rn_val, ~shifter_operand, 1));
2004 } else {
2005 UnimplementedInstruction(instr);
2006 }
2007 break;
2008 }
2009
2010 case CMN: {
2011 if (instr->HasS()) {
2012 // Format(instr, "cmn'cond 'rn, 'shift_rm");
2013 // Format(instr, "cmn'cond 'rn, 'imm");
2014 alu_out = rn_val + shifter_operand;
2015 SetNZFlags(alu_out);
2016 SetCFlag(CarryFrom(rn_val, shifter_operand, 0));
2017 SetVFlag(OverflowFrom(rn_val, shifter_operand, 0));
2018 } else {
2019 UnimplementedInstruction(instr);
2020 }
2021 break;
2022 }
2023
2024 case ORR: {
2025 // Format(instr, "orr'cond's 'rd, 'rn, 'shift_rm");
2026 // Format(instr, "orr'cond's 'rd, 'rn, 'imm");
2027 alu_out = rn_val | shifter_operand;
2028 set_register(rd, alu_out);
2029 if (instr->HasS()) {
2030 SetNZFlags(alu_out);
2031 SetCFlag(shifter_carry_out);
2032 }
2033 break;
2034 }
2035
2036 case MOV: {
2037 // Format(instr, "mov'cond's 'rd, 'shift_rm");
2038 // Format(instr, "mov'cond's 'rd, 'imm");
2039 alu_out = shifter_operand;
2040 set_register(rd, alu_out);
2041 if (instr->HasS()) {
2042 SetNZFlags(alu_out);
2043 SetCFlag(shifter_carry_out);
2044 }
2045 break;
2046 }
2047
2048 case BIC: {
2049 // Format(instr, "bic'cond's 'rd, 'rn, 'shift_rm");
2050 // Format(instr, "bic'cond's 'rd, 'rn, 'imm");
2051 alu_out = rn_val & ~shifter_operand;
2052 set_register(rd, alu_out);
2053 if (instr->HasS()) {
2054 SetNZFlags(alu_out);
2055 SetCFlag(shifter_carry_out);
2056 }
2057 break;
2058 }
2059
2060 case MVN: {
2061 // Format(instr, "mvn'cond's 'rd, 'shift_rm");
2062 // Format(instr, "mvn'cond's 'rd, 'imm");
2063 alu_out = ~shifter_operand;
2064 set_register(rd, alu_out);
2065 if (instr->HasS()) {
2066 SetNZFlags(alu_out);
2067 SetCFlag(shifter_carry_out);
2068 }
2069 break;
2070 }
2071
2072 default: {
2073 UNREACHABLE();
2074 break;
2075 }
2076 }
2077 }
2078}
2079
2080DART_FORCE_INLINE void Simulator::DecodeType2(Instr* instr) {
2081 Register rd = instr->RdField();
2082 Register rn = instr->RnField();
2083 int32_t rn_val = get_register(rn);
2084 int32_t im_val = instr->Offset12Field();
2085 uword addr = 0;
2086 bool write_back = false;
2087 switch (instr->PUField()) {
2088 case 0: {
2089 // Format(instr, "'memop'cond'b 'rd, ['rn], #-'off12");
2090 ASSERT(!instr->HasW());
2091 addr = rn_val;
2092 rn_val -= im_val;
2093 write_back = true;
2094 break;
2095 }
2096 case 1: {
2097 // Format(instr, "'memop'cond'b 'rd, ['rn], #+'off12");
2098 ASSERT(!instr->HasW());
2099 addr = rn_val;
2100 rn_val += im_val;
2101 write_back = true;
2102 break;
2103 }
2104 case 2: {
2105 // Format(instr, "'memop'cond'b 'rd, ['rn, #-'off12]'w");
2106 rn_val -= im_val;
2107 addr = rn_val;
2108 write_back = instr->HasW();
2109 break;
2110 }
2111 case 3: {
2112 // Format(instr, "'memop'cond'b 'rd, ['rn, #+'off12]'w");
2113 rn_val += im_val;
2114 addr = rn_val;
2115 write_back = instr->HasW();
2116 break;
2117 }
2118 default: {
2119 UNREACHABLE();
2120 break;
2121 }
2122 }
2123 if (IsIllegalAddress(addr)) {
2124 HandleIllegalAccess(addr, instr);
2125 } else {
2126 if (write_back) {
2127 ASSERT(rd != rn); // Unpredictable.
2128 set_register(rn, rn_val);
2129 }
2130 if (instr->HasB()) {
2131 if (instr->HasL()) {
2132 unsigned char val = ReadBU(addr);
2133 set_register(rd, val);
2134 } else {
2135 unsigned char val = get_register(rd);
2136 WriteB(addr, val);
2137 }
2138 } else {
2139 if (instr->HasL()) {
2140 set_register(rd, ReadW(addr, instr));
2141 } else {
2142 WriteW(addr, get_register(rd), instr);
2143 }
2144 }
2145 }
2146}
2147
2148void Simulator::DoDivision(Instr* instr) {
2149 const Register rd = instr->DivRdField();
2150 const Register rn = instr->DivRnField();
2151 const Register rm = instr->DivRmField();
2152
2153 if (!TargetCPUFeatures::integer_division_supported()) {
2154 UnimplementedInstruction(instr);
2155 return;
2156 }
2157
2158 // ARMv7-a does not trap on divide-by-zero. The destination register is just
2159 // set to 0.
2160 if (get_register(rm) == 0) {
2161 set_register(rd, 0);
2162 return;
2163 }
2164
2165 if (instr->Bit(21) == 1) {
2166 // unsigned division.
2167 uint32_t rn_val = static_cast<uint32_t>(get_register(rn));
2168 uint32_t rm_val = static_cast<uint32_t>(get_register(rm));
2169 uint32_t result = rn_val / rm_val;
2170 set_register(rd, static_cast<int32_t>(result));
2171 } else {
2172 // signed division.
2173 int32_t rn_val = get_register(rn);
2174 int32_t rm_val = get_register(rm);
2175 int32_t result;
2176 if ((rn_val == static_cast<int32_t>(0x80000000)) &&
2177 (rm_val == static_cast<int32_t>(0xffffffff))) {
2178 result = 0x80000000;
2179 } else {
2180 result = rn_val / rm_val;
2181 }
2182 set_register(rd, result);
2183 }
2184}
2185
2186void Simulator::DecodeType3(Instr* instr) {
2187 if (instr->IsDivision()) {
2188 DoDivision(instr);
2189 return;
2190 } else if (instr->IsRbit()) {
2191 // Format(instr, "rbit'cond 'rd, 'rm");
2192 Register rm = instr->RmField();
2193 Register rd = instr->RdField();
2194 set_register(rd, Utils::ReverseBits32(get_register(rm)));
2195 return;
2196 }
2197 Register rd = instr->RdField();
2198 Register rn = instr->RnField();
2199 int32_t rn_val = get_register(rn);
2200 bool shifter_carry_out = 0;
2201 int32_t shifter_operand = GetShiftRm(instr, &shifter_carry_out);
2202 uword addr = 0;
2203 bool write_back = false;
2204 switch (instr->PUField()) {
2205 case 0: {
2206 // Format(instr, "'memop'cond'b 'rd, ['rn], -'shift_rm");
2207 ASSERT(!instr->HasW());
2208 addr = rn_val;
2209 rn_val -= shifter_operand;
2210 write_back = true;
2211 break;
2212 }
2213 case 1: {
2214 // Format(instr, "'memop'cond'b 'rd, ['rn], +'shift_rm");
2215 ASSERT(!instr->HasW());
2216 addr = rn_val;
2217 rn_val += shifter_operand;
2218 write_back = true;
2219 break;
2220 }
2221 case 2: {
2222 // Format(instr, "'memop'cond'b 'rd, ['rn, -'shift_rm]'w");
2223 rn_val -= shifter_operand;
2224 addr = rn_val;
2225 write_back = instr->HasW();
2226 break;
2227 }
2228 case 3: {
2229 // Format(instr, "'memop'cond'b 'rd, ['rn, +'shift_rm]'w");
2230 rn_val += shifter_operand;
2231 addr = rn_val;
2232 write_back = instr->HasW();
2233 break;
2234 }
2235 default: {
2236 UNREACHABLE();
2237 break;
2238 }
2239 }
2240 if (IsIllegalAddress(addr)) {
2241 HandleIllegalAccess(addr, instr);
2242 } else {
2243 if (write_back) {
2244 ASSERT(rd != rn); // Unpredictable.
2245 set_register(rn, rn_val);
2246 }
2247 if (instr->HasB()) {
2248 if (instr->HasL()) {
2249 unsigned char val = ReadBU(addr);
2250 set_register(rd, val);
2251 } else {
2252 unsigned char val = get_register(rd);
2253 WriteB(addr, val);
2254 }
2255 } else {
2256 if (instr->HasL()) {
2257 set_register(rd, ReadW(addr, instr));
2258 } else {
2259 WriteW(addr, get_register(rd), instr);
2260 }
2261 }
2262 }
2263}
2264
2265void Simulator::DecodeType4(Instr* instr) {
2266 ASSERT(instr->Bit(22) == 0); // only allowed to be set in privileged mode
2267 if (instr->HasL()) {
2268 // Format(instr, "ldm'cond'pu 'rn'w, 'rlist");
2269 HandleRList(instr, true);
2270 } else {
2271 // Format(instr, "stm'cond'pu 'rn'w, 'rlist");
2272 HandleRList(instr, false);
2273 }
2274}
2275
2276void Simulator::DecodeType5(Instr* instr) {
2277 // Format(instr, "b'l'cond 'target");
2278 uint32_t off = (static_cast<uint32_t>(instr->SImmed24Field()) << 2) + 8;
2279 uint32_t pc = get_pc();
2280 if (instr->HasLink()) {
2281 set_register(LR, pc + Instr::kInstrSize);
2282 }
2283 set_pc(pc + off);
2284}
2285
2286void Simulator::DecodeType6(Instr* instr) {
2287 if (instr->IsVFPDoubleTransfer()) {
2288 Register rd = instr->RdField();
2289 Register rn = instr->RnField();
2290 if (instr->Bit(8) == 0) {
2291 SRegister sm = instr->SmField();
2292 SRegister sm1 = static_cast<SRegister>(sm + 1);
2293 ASSERT(sm1 < kNumberOfSRegisters);
2294 if (instr->Bit(20) == 1) {
2295 // Format(instr, "vmovrrs'cond 'rd, 'rn, {'sm', 'sm1}");
2296 set_register(rd, get_sregister_bits(sm));
2297 set_register(rn, get_sregister_bits(sm1));
2298 } else {
2299 // Format(instr, "vmovsrr'cond {'sm, 'sm1}, 'rd', 'rn");
2300 set_sregister_bits(sm, get_register(rd));
2301 set_sregister_bits(sm1, get_register(rn));
2302 }
2303 } else {
2304 DRegister dm = instr->DmField();
2305 if (instr->Bit(20) == 1) {
2306 // Format(instr, "vmovrrd'cond 'rd, 'rn, 'dm");
2307 int64_t dm_val = get_dregister_bits(dm);
2308 set_register(rd, Utils::Low32Bits(dm_val));
2309 set_register(rn, Utils::High32Bits(dm_val));
2310 } else {
2311 // Format(instr, "vmovdrr'cond 'dm, 'rd, 'rn");
2312 int64_t dm_val =
2313 Utils::LowHighTo64Bits(get_register(rd), get_register(rn));
2314 set_dregister_bits(dm, dm_val);
2315 }
2316 }
2317 } else if (instr->IsVFPLoadStore()) {
2318 Register rn = instr->RnField();
2319 int32_t addr = get_register(rn);
2320 int32_t imm_val = instr->Bits(0, 8) << 2;
2321 if (instr->Bit(23) == 1) {
2322 addr += imm_val;
2323 } else {
2324 addr -= imm_val;
2325 }
2326 if (IsIllegalAddress(addr)) {
2327 HandleIllegalAccess(addr, instr);
2328 } else {
2329 if (instr->Bit(8) == 0) {
2330 SRegister sd = instr->SdField();
2331 if (instr->Bit(20) == 1) { // vldrs
2332 // Format(instr, "vldrs'cond 'sd, ['rn, #+'off10]");
2333 // Format(instr, "vldrs'cond 'sd, ['rn, #-'off10]");
2334 set_sregister_bits(sd, ReadW(addr, instr));
2335 } else { // vstrs
2336 // Format(instr, "vstrs'cond 'sd, ['rn, #+'off10]");
2337 // Format(instr, "vstrs'cond 'sd, ['rn, #-'off10]");
2338 WriteW(addr, get_sregister_bits(sd), instr);
2339 }
2340 } else {
2341 DRegister dd = instr->DdField();
2342 if (instr->Bit(20) == 1) { // vldrd
2343 // Format(instr, "vldrd'cond 'dd, ['rn, #+'off10]");
2344 // Format(instr, "vldrd'cond 'dd, ['rn, #-'off10]");
2345 int64_t dd_val = Utils::LowHighTo64Bits(ReadW(addr, instr),
2346 ReadW(addr + 4, instr));
2347 set_dregister_bits(dd, dd_val);
2348 } else { // vstrd
2349 // Format(instr, "vstrd'cond 'dd, ['rn, #+'off10]");
2350 // Format(instr, "vstrd'cond 'dd, ['rn, #-'off10]");
2351 int64_t dd_val = get_dregister_bits(dd);
2352 WriteW(addr, Utils::Low32Bits(dd_val), instr);
2353 WriteW(addr + 4, Utils::High32Bits(dd_val), instr);
2354 }
2355 }
2356 }
2357 } else if (instr->IsVFPMultipleLoadStore()) {
2358 Register rn = instr->RnField();
2359 int32_t addr = get_register(rn);
2360 int32_t imm_val = instr->Bits(0, 8);
2361 if (instr->Bit(23) == 0) {
2362 addr -= (imm_val << 2);
2363 }
2364 if (instr->HasW()) {
2365 if (instr->Bit(23) == 1) {
2366 set_register(rn, addr + (imm_val << 2));
2367 } else {
2368 set_register(rn, addr); // already subtracted from addr
2369 }
2370 }
2371 if (IsIllegalAddress(addr)) {
2372 HandleIllegalAccess(addr, instr);
2373 } else {
2374 if (instr->Bit(8) == 0) {
2375 int32_t regs_cnt = imm_val;
2376 int32_t start = instr->Bit(22) | (instr->Bits(12, 4) << 1);
2377 for (int i = start; i < start + regs_cnt; i++) {
2378 SRegister sd = static_cast<SRegister>(i);
2379 if (instr->Bit(20) == 1) {
2380 // Format(instr, "vldms'cond'pu 'rn'w, 'slist");
2381 set_sregister_bits(sd, ReadW(addr, instr));
2382 } else {
2383 // Format(instr, "vstms'cond'pu 'rn'w, 'slist");
2384 WriteW(addr, get_sregister_bits(sd), instr);
2385 }
2386 addr += 4;
2387 }
2388 } else {
2389 int32_t regs_cnt = imm_val >> 1;
2390 int32_t start = (instr->Bit(22) << 4) | instr->Bits(12, 4);
2391 if ((regs_cnt <= 16) && (start + regs_cnt <= kNumberOfDRegisters)) {
2392 for (int i = start; i < start + regs_cnt; i++) {
2393 DRegister dd = static_cast<DRegister>(i);
2394 if (instr->Bit(20) == 1) {
2395 // Format(instr, "vldmd'cond'pu 'rn'w, 'dlist");
2396 int64_t dd_val = Utils::LowHighTo64Bits(ReadW(addr, instr),
2397 ReadW(addr + 4, instr));
2398 set_dregister_bits(dd, dd_val);
2399 } else {
2400 // Format(instr, "vstmd'cond'pu 'rn'w, 'dlist");
2401 int64_t dd_val = get_dregister_bits(dd);
2402 WriteW(addr, Utils::Low32Bits(dd_val), instr);
2403 WriteW(addr + 4, Utils::High32Bits(dd_val), instr);
2404 }
2405 addr += 8;
2406 }
2407 } else {
2408 UnimplementedInstruction(instr);
2409 }
2410 }
2411 }
2412 } else {
2413 UnimplementedInstruction(instr);
2414 }
2415}
2416
2417void Simulator::DecodeType7(Instr* instr) {
2418 if (instr->Bit(24) == 1) {
2419 // Format(instr, "svc #'svc");
2420 SupervisorCall(instr);
2421 } else if (instr->IsVFPDataProcessingOrSingleTransfer()) {
2422 if (instr->Bit(4) == 0) {
2423 // VFP Data Processing
2424 SRegister sd;
2425 SRegister sn;
2426 SRegister sm;
2427 DRegister dd;
2428 DRegister dn;
2429 DRegister dm;
2430 if (instr->Bit(8) == 0) {
2431 sd = instr->SdField();
2432 sn = instr->SnField();
2433 sm = instr->SmField();
2434 dd = kNoDRegister;
2435 dn = kNoDRegister;
2436 dm = kNoDRegister;
2437 } else {
2438 sd = kNoSRegister;
2439 sn = kNoSRegister;
2440 sm = kNoSRegister;
2441 dd = instr->DdField();
2442 dn = instr->DnField();
2443 dm = instr->DmField();
2444 }
2445 switch (instr->Bits(20, 4) & 0xb) {
2446 case 1: // vnmla, vnmls, vnmul
2447 default: {
2448 UnimplementedInstruction(instr);
2449 break;
2450 }
2451 case 0: { // vmla, vmls floating-point
2452 if (instr->Bit(8) == 0) {
2453 float addend = get_sregister(sn) * get_sregister(sm);
2454 float sd_val = get_sregister(sd);
2455 if (instr->Bit(6) == 0) {
2456 // Format(instr, "vmlas'cond 'sd, 'sn, 'sm");
2457 } else {
2458 // Format(instr, "vmlss'cond 'sd, 'sn, 'sm");
2459 addend = -addend;
2460 }
2461 set_sregister(sd, sd_val + addend);
2462 } else {
2463 double addend = get_dregister(dn) * get_dregister(dm);
2464 double dd_val = get_dregister(dd);
2465 if (instr->Bit(6) == 0) {
2466 // Format(instr, "vmlad'cond 'dd, 'dn, 'dm");
2467 } else {
2468 // Format(instr, "vmlsd'cond 'dd, 'dn, 'dm");
2469 addend = -addend;
2470 }
2471 set_dregister(dd, dd_val + addend);
2472 }
2473 break;
2474 }
2475 case 2: { // vmul
2476 if (instr->Bit(8) == 0) {
2477 // Format(instr, "vmuls'cond 'sd, 'sn, 'sm");
2478 set_sregister(sd, get_sregister(sn) * get_sregister(sm));
2479 } else {
2480 // Format(instr, "vmuld'cond 'dd, 'dn, 'dm");
2481 set_dregister(dd, get_dregister(dn) * get_dregister(dm));
2482 }
2483 break;
2484 }
2485 case 8: { // vdiv
2486 if (instr->Bit(8) == 0) {
2487 // Format(instr, "vdivs'cond 'sd, 'sn, 'sm");
2488 set_sregister(sd, get_sregister(sn) / get_sregister(sm));
2489 } else {
2490 // Format(instr, "vdivd'cond 'dd, 'dn, 'dm");
2491 set_dregister(dd, get_dregister(dn) / get_dregister(dm));
2492 }
2493 break;
2494 }
2495 case 3: { // vadd, vsub floating-point
2496 if (instr->Bit(8) == 0) {
2497 if (instr->Bit(6) == 0) {
2498 // Format(instr, "vadds'cond 'sd, 'sn, 'sm");
2499 set_sregister(sd, get_sregister(sn) + get_sregister(sm));
2500 } else {
2501 // Format(instr, "vsubs'cond 'sd, 'sn, 'sm");
2502 set_sregister(sd, get_sregister(sn) - get_sregister(sm));
2503 }
2504 } else {
2505 if (instr->Bit(6) == 0) {
2506 // Format(instr, "vaddd'cond 'dd, 'dn, 'dm");
2507 set_dregister(dd, get_dregister(dn) + get_dregister(dm));
2508 } else {
2509 // Format(instr, "vsubd'cond 'dd, 'dn, 'dm");
2510 set_dregister(dd, get_dregister(dn) - get_dregister(dm));
2511 }
2512 }
2513 break;
2514 }
2515 case 0xb: { // Other VFP data-processing instructions
2516 if (instr->Bit(6) == 0) { // vmov immediate
2517 if (instr->Bit(8) == 0) {
2518 // Format(instr, "vmovs'cond 'sd, #'immf");
2519 set_sregister(sd, instr->ImmFloatField());
2520 } else {
2521 // Format(instr, "vmovd'cond 'dd, #'immd");
2522 set_dregister(dd, instr->ImmDoubleField());
2523 }
2524 break;
2525 }
2526 switch (instr->Bits(16, 4)) {
2527 case 0: { // vmov immediate, vmov register, vabs
2528 switch (instr->Bits(6, 2)) {
2529 case 1: { // vmov register
2530 if (instr->Bit(8) == 0) {
2531 // Format(instr, "vmovs'cond 'sd, 'sm");
2532 set_sregister(sd, get_sregister(sm));
2533 } else {
2534 // Format(instr, "vmovd'cond 'dd, 'dm");
2535 set_dregister(dd, get_dregister(dm));
2536 }
2537 break;
2538 }
2539 case 3: { // vabs
2540 if (instr->Bit(8) == 0) {
2541 // Format(instr, "vabss'cond 'sd, 'sm");
2542 set_sregister(sd, fabsf(get_sregister(sm)));
2543 } else {
2544 // Format(instr, "vabsd'cond 'dd, 'dm");
2545 set_dregister(dd, fabs(get_dregister(dm)));
2546 }
2547 break;
2548 }
2549 default: {
2550 UnimplementedInstruction(instr);
2551 break;
2552 }
2553 }
2554 break;
2555 }
2556 case 1: { // vneg, vsqrt
2557 switch (instr->Bits(6, 2)) {
2558 case 1: { // vneg
2559 if (instr->Bit(8) == 0) {
2560 // Format(instr, "vnegs'cond 'sd, 'sm");
2561 set_sregister(sd, -get_sregister(sm));
2562 } else {
2563 // Format(instr, "vnegd'cond 'dd, 'dm");
2564 set_dregister(dd, -get_dregister(dm));
2565 }
2566 break;
2567 }
2568 case 3: { // vsqrt
2569 if (instr->Bit(8) == 0) {
2570 // Format(instr, "vsqrts'cond 'sd, 'sm");
2571 set_sregister(sd, sqrtf(get_sregister(sm)));
2572 } else {
2573 // Format(instr, "vsqrtd'cond 'dd, 'dm");
2574 set_dregister(dd, sqrt(get_dregister(dm)));
2575 }
2576 break;
2577 }
2578 default: {
2579 UnimplementedInstruction(instr);
2580 break;
2581 }
2582 }
2583 break;
2584 }
2585 case 4: // vcmp, vcmpe
2586 case 5: { // vcmp #0.0, vcmpe #0.0
2587 if (instr->Bit(7) == 1) { // vcmpe
2588 UnimplementedInstruction(instr);
2589 } else {
2590 fp_n_flag_ = false;
2591 fp_z_flag_ = false;
2592 fp_c_flag_ = false;
2593 fp_v_flag_ = false;
2594 if (instr->Bit(8) == 0) { // vcmps
2595 float sd_val = get_sregister(sd);
2596 float sm_val;
2597 if (instr->Bit(16) == 0) {
2598 // Format(instr, "vcmps'cond 'sd, 'sm");
2599 sm_val = get_sregister(sm);
2600 } else {
2601 // Format(instr, "vcmps'cond 'sd, #0.0");
2602 sm_val = 0.0f;
2603 }
2604 if (isnan(sd_val) || isnan(sm_val)) {
2605 fp_c_flag_ = true;
2606 fp_v_flag_ = true;
2607 } else if (sd_val == sm_val) {
2608 fp_z_flag_ = true;
2609 fp_c_flag_ = true;
2610 } else if (sd_val < sm_val) {
2611 fp_n_flag_ = true;
2612 } else {
2613 fp_c_flag_ = true;
2614 }
2615 } else { // vcmpd
2616 double dd_val = get_dregister(dd);
2617 double dm_val;
2618 if (instr->Bit(16) == 0) {
2619 // Format(instr, "vcmpd'cond 'dd, 'dm");
2620 dm_val = get_dregister(dm);
2621 } else {
2622 // Format(instr, "vcmpd'cond 'dd, #0.0");
2623 dm_val = 0.0;
2624 }
2625 if (isnan(dd_val) || isnan(dm_val)) {
2626 fp_c_flag_ = true;
2627 fp_v_flag_ = true;
2628 } else if (dd_val == dm_val) {
2629 fp_z_flag_ = true;
2630 fp_c_flag_ = true;
2631 } else if (dd_val < dm_val) {
2632 fp_n_flag_ = true;
2633 } else {
2634 fp_c_flag_ = true;
2635 }
2636 }
2637 }
2638 break;
2639 }
2640 case 7: { // vcvt between double-precision and single-precision
2641 if (instr->Bit(8) == 0) {
2642 // Format(instr, "vcvtds'cond 'dd, 'sm");
2643 dd = instr->DdField();
2644 set_dregister(dd, static_cast<double>(get_sregister(sm)));
2645 } else {
2646 // Format(instr, "vcvtsd'cond 'sd, 'dm");
2647 sd = instr->SdField();
2648 set_sregister(sd, static_cast<float>(get_dregister(dm)));
2649 }
2650 break;
2651 }
2652 case 8: { // vcvt, vcvtr between floating-point and integer
2653 sm = instr->SmField();
2654 int32_t sm_int = get_sregister_bits(sm);
2655 uint32_t ud_val = 0;
2656 int32_t id_val = 0;
2657 if (instr->Bit(7) == 0) { // vcvtsu, vcvtdu
2658 ud_val = static_cast<uint32_t>(sm_int);
2659 } else { // vcvtsi, vcvtdi
2660 id_val = sm_int;
2661 }
2662 if (instr->Bit(8) == 0) {
2663 float sd_val;
2664 if (instr->Bit(7) == 0) {
2665 // Format(instr, "vcvtsu'cond 'sd, 'sm");
2666 sd_val = static_cast<float>(ud_val);
2667 } else {
2668 // Format(instr, "vcvtsi'cond 'sd, 'sm");
2669 sd_val = static_cast<float>(id_val);
2670 }
2671 set_sregister(sd, sd_val);
2672 } else {
2673 double dd_val;
2674 if (instr->Bit(7) == 0) {
2675 // Format(instr, "vcvtdu'cond 'dd, 'sm");
2676 dd_val = static_cast<double>(ud_val);
2677 } else {
2678 // Format(instr, "vcvtdi'cond 'dd, 'sm");
2679 dd_val = static_cast<double>(id_val);
2680 }
2681 set_dregister(dd, dd_val);
2682 }
2683 break;
2684 }
2685 case 12:
2686 case 13: { // vcvt, vcvtr between floating-point and integer
2687 // We do not need to record exceptions in the FPSCR cumulative
2688 // flags, because we do not use them.
2689 if (instr->Bit(7) == 0) {
2690 // We only support round-to-zero mode
2691 UnimplementedInstruction(instr);
2692 break;
2693 }
2694 int32_t id_val = 0;
2695 uint32_t ud_val = 0;
2696 if (instr->Bit(8) == 0) {
2697 float sm_val = get_sregister(sm);
2698 if (instr->Bit(16) == 0) {
2699 // Format(instr, "vcvtus'cond 'sd, 'sm");
2700 if (sm_val >= static_cast<float>(INT32_MAX)) {
2701 ud_val = INT32_MAX;
2702 } else if (sm_val > 0.0) {
2703 ud_val = static_cast<uint32_t>(sm_val);
2704 }
2705 } else {
2706 // Format(instr, "vcvtis'cond 'sd, 'sm");
2707 if (sm_val <= static_cast<float>(INT32_MIN)) {
2708 id_val = INT32_MIN;
2709 } else if (sm_val >= static_cast<float>(INT32_MAX)) {
2710 id_val = INT32_MAX;
2711 } else {
2712 id_val = static_cast<int32_t>(sm_val);
2713 }
2714 ASSERT((id_val >= 0) || !(sm_val >= 0.0));
2715 }
2716 } else {
2717 sd = instr->SdField();
2718 double dm_val = get_dregister(dm);
2719 if (instr->Bit(16) == 0) {
2720 // Format(instr, "vcvtud'cond 'sd, 'dm");
2721 if (dm_val >= static_cast<double>(INT32_MAX)) {
2722 ud_val = INT32_MAX;
2723 } else if (dm_val > 0.0) {
2724 ud_val = static_cast<uint32_t>(dm_val);
2725 }
2726 } else {
2727 // Format(instr, "vcvtid'cond 'sd, 'dm");
2728 if (dm_val <= static_cast<double>(INT32_MIN)) {
2729 id_val = INT32_MIN;
2730 } else if (dm_val >= static_cast<double>(INT32_MAX)) {
2731 id_val = INT32_MAX;
2732 } else if (isnan(dm_val)) {
2733 id_val = 0;
2734 } else {
2735 id_val = static_cast<int32_t>(dm_val);
2736 }
2737 ASSERT((id_val >= 0) || !(dm_val >= 0.0));
2738 }
2739 }
2740 int32_t sd_val;
2741 if (instr->Bit(16) == 0) {
2742 sd_val = static_cast<int32_t>(ud_val);
2743 } else {
2744 sd_val = id_val;
2745 }
2746 set_sregister_bits(sd, sd_val);
2747 break;
2748 }
2749 case 2: // vcvtb, vcvtt
2750 case 3: // vcvtb, vcvtt
2751 case 9: // undefined
2752 case 10: // vcvt between floating-point and fixed-point
2753 case 11: // vcvt between floating-point and fixed-point
2754 case 14: // vcvt between floating-point and fixed-point
2755 case 15: // vcvt between floating-point and fixed-point
2756 default: {
2757 UnimplementedInstruction(instr);
2758 break;
2759 }
2760 }
2761 } break;
2762 }
2763 } else {
2764 // 8, 16, or 32-bit Transfer between ARM Core and VFP
2765 if ((instr->Bits(21, 3) == 0) && (instr->Bit(8) == 0)) {
2766 Register rd = instr->RdField();
2767 SRegister sn = instr->SnField();
2768 if (instr->Bit(20) == 0) {
2769 // Format(instr, "vmovs'cond 'sn, 'rd");
2770 set_sregister_bits(sn, get_register(rd));
2771 } else {
2772 // Format(instr, "vmovr'cond 'rd, 'sn");
2773 set_register(rd, get_sregister_bits(sn));
2774 }
2775 } else if ((instr->Bits(22, 3) == 0) && (instr->Bit(20) == 0) &&
2776 (instr->Bit(8) == 1) && (instr->Bits(5, 2) == 0)) {
2777 DRegister dn = instr->DnField();
2778 Register rd = instr->RdField();
2779 if (instr->Bit(21) == 0) {
2780 // Format(instr, "vmovd'cond 'dd[0], 'rd");
2781 SRegister sd = EvenSRegisterOf(dn);
2782 set_sregister_bits(sd, get_register(rd));
2783 } else {
2784 // Format(instr, "vmovd'cond 'dd[1], 'rd");
2785 SRegister sd = OddSRegisterOf(dn);
2786 set_sregister_bits(sd, get_register(rd));
2787 }
2788 } else if ((instr->Bits(20, 4) == 0xf) && (instr->Bit(8) == 0)) {
2789 if (instr->Bits(12, 4) == 0xf) {
2790 // Format(instr, "vmrs'cond APSR, FPSCR");
2791 n_flag_ = fp_n_flag_;
2792 z_flag_ = fp_z_flag_;
2793 c_flag_ = fp_c_flag_;
2794 v_flag_ = fp_v_flag_;
2795 } else {
2796 // Format(instr, "vmrs'cond 'rd, FPSCR");
2797 const int32_t n_flag = fp_n_flag_ ? (1 << 31) : 0;
2798 const int32_t z_flag = fp_z_flag_ ? (1 << 30) : 0;
2799 const int32_t c_flag = fp_c_flag_ ? (1 << 29) : 0;
2800 const int32_t v_flag = fp_v_flag_ ? (1 << 28) : 0;
2801 set_register(instr->RdField(), n_flag | z_flag | c_flag | v_flag);
2802 }
2803 } else {
2804 UnimplementedInstruction(instr);
2805 }
2806 }
2807 } else {
2808 UnimplementedInstruction(instr);
2809 }
2810}
2811
2812static void simd_value_swap(simd_value_t* s1,
2813 int i1,
2814 simd_value_t* s2,
2815 int i2) {
2816 uint32_t tmp;
2817 tmp = s1->data_[i1].u;
2818 s1->data_[i1].u = s2->data_[i2].u;
2819 s2->data_[i2].u = tmp;
2820}
2821
2822void Simulator::DecodeSIMDDataProcessing(Instr* instr) {
2823 ASSERT(instr->ConditionField() == kSpecialCondition);
2824
2825 if (instr->Bit(6) == 1) {
2826 // Q = 1, Using 128-bit Q registers.
2827 const QRegister qd = instr->QdField();
2828 const QRegister qn = instr->QnField();
2829 const QRegister qm = instr->QmField();
2830 simd_value_t s8d;
2831 simd_value_t s8n;
2832 simd_value_t s8m;
2833
2834 get_qregister(qn, &s8n);
2835 get_qregister(qm, &s8m);
2836 int8_t* s8d_8 = reinterpret_cast<int8_t*>(&s8d);
2837 int8_t* s8n_8 = reinterpret_cast<int8_t*>(&s8n);
2838 int8_t* s8m_8 = reinterpret_cast<int8_t*>(&s8m);
2839 uint8_t* s8d_u8 = reinterpret_cast<uint8_t*>(&s8d);
2840 uint8_t* s8n_u8 = reinterpret_cast<uint8_t*>(&s8n);
2841 uint8_t* s8m_u8 = reinterpret_cast<uint8_t*>(&s8m);
2842 int16_t* s8d_16 = reinterpret_cast<int16_t*>(&s8d);
2843 int16_t* s8n_16 = reinterpret_cast<int16_t*>(&s8n);
2844 int16_t* s8m_16 = reinterpret_cast<int16_t*>(&s8m);
2845 uint16_t* s8d_u16 = reinterpret_cast<uint16_t*>(&s8d);
2846 uint16_t* s8n_u16 = reinterpret_cast<uint16_t*>(&s8n);
2847 uint16_t* s8m_u16 = reinterpret_cast<uint16_t*>(&s8m);
2848 int32_t* s8d_32 = reinterpret_cast<int32_t*>(&s8d);
2849 int32_t* s8n_32 = reinterpret_cast<int32_t*>(&s8n);
2850 int32_t* s8m_32 = reinterpret_cast<int32_t*>(&s8m);
2851 uint32_t* s8d_u32 = reinterpret_cast<uint32_t*>(&s8d);
2852 uint32_t* s8m_u32 = reinterpret_cast<uint32_t*>(&s8m);
2853 int64_t* s8d_64 = reinterpret_cast<int64_t*>(&s8d);
2854 int64_t* s8n_64 = reinterpret_cast<int64_t*>(&s8n);
2855 int64_t* s8m_64 = reinterpret_cast<int64_t*>(&s8m);
2856 uint64_t* s8d_u64 = reinterpret_cast<uint64_t*>(&s8d);
2857 uint64_t* s8m_u64 = reinterpret_cast<uint64_t*>(&s8m);
2858
2859 if ((instr->Bits(8, 4) == 8) && (instr->Bit(4) == 0) &&
2860 (instr->Bits(23, 2) == 0)) {
2861 // Uses q registers.
2862 // Format(instr, "vadd.'sz 'qd, 'qn, 'qm");
2863 const int size = instr->Bits(20, 2);
2864 if (size == 0) {
2865 for (int i = 0; i < 16; i++) {
2866 s8d_8[i] = s8n_8[i] + s8m_8[i];
2867 }
2868 } else if (size == 1) {
2869 for (int i = 0; i < 8; i++) {
2870 s8d_16[i] = s8n_16[i] + s8m_16[i];
2871 }
2872 } else if (size == 2) {
2873 for (int i = 0; i < 4; i++) {
2874 s8d.data_[i].u = s8n.data_[i].u + s8m.data_[i].u;
2875 }
2876 } else if (size == 3) {
2877 for (int i = 0; i < 2; i++) {
2878 s8d_64[i] = s8n_64[i] + s8m_64[i];
2879 }
2880 } else {
2881 UNREACHABLE();
2882 }
2883 } else if ((instr->Bits(8, 4) == 13) && (instr->Bit(4) == 0) &&
2884 (instr->Bits(23, 2) == 0) && (instr->Bit(21) == 0)) {
2885 // Format(instr, "vadd.F32 'qd, 'qn, 'qm");
2886 for (int i = 0; i < 4; i++) {
2887 s8d.data_[i].f = s8n.data_[i].f + s8m.data_[i].f;
2888 }
2889 } else if ((instr->Bits(8, 4) == 8) && (instr->Bit(4) == 0) &&
2890 (instr->Bits(23, 2) == 2)) {
2891 // Format(instr, "vsub.'sz 'qd, 'qn, 'qm");
2892 const int size = instr->Bits(20, 2);
2893 if (size == 0) {
2894 for (int i = 0; i < 16; i++) {
2895 s8d_8[i] = s8n_8[i] - s8m_8[i];
2896 }
2897 } else if (size == 1) {
2898 for (int i = 0; i < 8; i++) {
2899 s8d_16[i] = s8n_16[i] - s8m_16[i];
2900 }
2901 } else if (size == 2) {
2902 for (int i = 0; i < 4; i++) {
2903 s8d.data_[i].u = s8n.data_[i].u - s8m.data_[i].u;
2904 }
2905 } else if (size == 3) {
2906 for (int i = 0; i < 2; i++) {
2907 s8d_64[i] = s8n_64[i] - s8m_64[i];
2908 }
2909 } else {
2910 UNREACHABLE();
2911 }
2912 } else if ((instr->Bits(8, 4) == 13) && (instr->Bit(4) == 0) &&
2913 (instr->Bits(23, 2) == 0) && (instr->Bit(21) == 1)) {
2914 // Format(instr, "vsub.F32 'qd, 'qn, 'qm");
2915 for (int i = 0; i < 4; i++) {
2916 s8d.data_[i].f = s8n.data_[i].f - s8m.data_[i].f;
2917 }
2918 } else if ((instr->Bits(8, 4) == 9) && (instr->Bit(4) == 1) &&
2919 (instr->Bits(23, 2) == 0)) {
2920 // Format(instr, "vmul.'sz 'qd, 'qn, 'qm");
2921 const int size = instr->Bits(20, 2);
2922 if (size == 0) {
2923 for (int i = 0; i < 16; i++) {
2924 s8d_8[i] = s8n_8[i] * s8m_8[i];
2925 }
2926 } else if (size == 1) {
2927 for (int i = 0; i < 8; i++) {
2928 s8d_16[i] = s8n_16[i] * s8m_16[i];
2929 }
2930 } else if (size == 2) {
2931 for (int i = 0; i < 4; i++) {
2932 s8d.data_[i].u = s8n.data_[i].u * s8m.data_[i].u;
2933 }
2934 } else if (size == 3) {
2935 UnimplementedInstruction(instr);
2936 } else {
2937 UNREACHABLE();
2938 }
2939 } else if ((instr->Bits(8, 4) == 13) && (instr->Bit(4) == 1) &&
2940 (instr->Bits(23, 2) == 2) && (instr->Bit(21) == 0)) {
2941 // Format(instr, "vmul.F32 'qd, 'qn, 'qm");
2942 for (int i = 0; i < 4; i++) {
2943 s8d.data_[i].f = s8n.data_[i].f * s8m.data_[i].f;
2944 }
2945 } else if ((instr->Bits(8, 4) == 4) && (instr->Bit(4) == 0) &&
2946 (instr->Bit(23) == 0) && (instr->Bits(25, 3) == 1)) {
2947 // Format(instr, "vshlqu'sz 'qd, 'qm, 'qn");
2948 // Format(instr, "vshlqi'sz 'qd, 'qm, 'qn");
2949 const bool signd = instr->Bit(24) == 0;
2950 const int size = instr->Bits(20, 2);
2951 if (size == 0) {
2952 for (int i = 0; i < 16; i++) {
2953 int8_t shift = s8n_8[i];
2954 if (shift > 0) {
2955 s8d_u8[i] = s8m_u8[i] << shift;
2956 } else if (shift < 0) {
2957 if (signd) {
2958 s8d_8[i] = s8m_8[i] >> (-shift);
2959 } else {
2960 s8d_u8[i] = s8m_u8[i] >> (-shift);
2961 }
2962 }
2963 }
2964 } else if (size == 1) {
2965 for (int i = 0; i < 8; i++) {
2966 int8_t shift = s8n_8[i * 2];
2967 if (shift > 0) {
2968 s8d_u16[i] = s8m_u16[i] << shift;
2969 } else if (shift < 0) {
2970 if (signd) {
2971 s8d_16[i] = s8m_16[i] >> (-shift);
2972 } else {
2973 s8d_u16[i] = s8m_u16[i] >> (-shift);
2974 }
2975 }
2976 }
2977 } else if (size == 2) {
2978 for (int i = 0; i < 4; i++) {
2979 int8_t shift = s8n_8[i * 4];
2980 if (shift > 0) {
2981 s8d_u32[i] = s8m_u32[i] << shift;
2982 } else if (shift < 0) {
2983 if (signd) {
2984 s8d_32[i] = s8m_32[i] >> (-shift);
2985 } else {
2986 s8d_u32[i] = s8m_u32[i] >> (-shift);
2987 }
2988 }
2989 }
2990 } else {
2991 ASSERT(size == 3);
2992 for (int i = 0; i < 2; i++) {
2993 int8_t shift = s8n_8[i * 8];
2994 if (shift > 0) {
2995 s8d_u64[i] = s8m_u64[i] << shift;
2996 } else if (shift < 0) {
2997 if (signd) {
2998 s8d_64[i] = s8m_64[i] >> (-shift);
2999 } else {
3000 s8d_u64[i] = s8m_u64[i] >> (-shift);
3001 }
3002 }
3003 }
3004 }
3005 } else if ((instr->Bits(8, 4) == 1) && (instr->Bit(4) == 1) &&
3006 (instr->Bits(20, 2) == 0) && (instr->Bits(23, 2) == 2)) {
3007 // Format(instr, "veorq 'qd, 'qn, 'qm");
3008 for (int i = 0; i < 4; i++) {
3009 s8d.data_[i].u = s8n.data_[i].u ^ s8m.data_[i].u;
3010 }
3011 } else if ((instr->Bits(8, 4) == 1) && (instr->Bit(4) == 1) &&
3012 (instr->Bits(20, 2) == 3) && (instr->Bits(23, 2) == 0)) {
3013 // Format(instr, "vornq 'qd, 'qn, 'qm");
3014 for (int i = 0; i < 4; i++) {
3015 s8d.data_[i].u = s8n.data_[i].u | ~s8m.data_[i].u;
3016 }
3017 } else if ((instr->Bits(8, 4) == 1) && (instr->Bit(4) == 1) &&
3018 (instr->Bits(20, 2) == 2) && (instr->Bits(23, 2) == 0)) {
3019 if (qm == qn) {
3020 // Format(instr, "vmovq 'qd, 'qm");
3021 for (int i = 0; i < 4; i++) {
3022 s8d.data_[i].u = s8m.data_[i].u;
3023 }
3024 } else {
3025 // Format(instr, "vorrq 'qd, 'qm");
3026 for (int i = 0; i < 4; i++) {
3027 s8d.data_[i].u = s8n.data_[i].u | s8m.data_[i].u;
3028 }
3029 }
3030 } else if ((instr->Bits(8, 4) == 1) && (instr->Bit(4) == 1) &&
3031 (instr->Bits(20, 2) == 0) && (instr->Bits(23, 2) == 0)) {
3032 // Format(instr, "vandq 'qd, 'qn, 'qm");
3033 for (int i = 0; i < 4; i++) {
3034 s8d.data_[i].u = s8n.data_[i].u & s8m.data_[i].u;
3035 }
3036 } else if ((instr->Bits(7, 5) == 11) && (instr->Bit(4) == 0) &&
3037 (instr->Bits(20, 2) == 3) && (instr->Bits(23, 5) == 7) &&
3038 (instr->Bits(16, 4) == 0)) {
3039 // Format(instr, "vmvnq 'qd, 'qm");
3040 for (int i = 0; i < 4; i++) {
3041 s8d.data_[i].u = ~s8m.data_[i].u;
3042 }
3043 } else if ((instr->Bits(8, 4) == 15) && (instr->Bit(4) == 0) &&
3044 (instr->Bits(20, 2) == 2) && (instr->Bits(23, 2) == 0)) {
3045 // Format(instr, "vminqs 'qd, 'qn, 'qm");
3046 for (int i = 0; i < 4; i++) {
3047 s8d.data_[i].f = fminf(s8n.data_[i].f, s8m.data_[i].f);
3048 }
3049 } else if ((instr->Bits(8, 4) == 15) && (instr->Bit(4) == 0) &&
3050 (instr->Bits(20, 2) == 0) && (instr->Bits(23, 2) == 0)) {
3051 // Format(instr, "vmaxqs 'qd, 'qn, 'qm");
3052 for (int i = 0; i < 4; i++) {
3053 s8d.data_[i].f = fmaxf(s8n.data_[i].f, s8m.data_[i].f);
3054 }
3055 } else if ((instr->Bits(8, 4) == 7) && (instr->Bit(4) == 0) &&
3056 (instr->Bits(20, 2) == 3) && (instr->Bits(23, 2) == 3) &&
3057 (instr->Bit(7) == 0) && (instr->Bits(16, 4) == 9)) {
3058 // Format(instr, "vabsqs 'qd, 'qm");
3059 for (int i = 0; i < 4; i++) {
3060 s8d.data_[i].f = fabsf(s8m.data_[i].f);
3061 }
3062 } else if ((instr->Bits(8, 4) == 7) && (instr->Bit(4) == 0) &&
3063 (instr->Bits(20, 2) == 3) && (instr->Bits(23, 2) == 3) &&
3064 (instr->Bit(7) == 1) && (instr->Bits(16, 4) == 9)) {
3065 // Format(instr, "vnegqs 'qd, 'qm");
3066 for (int i = 0; i < 4; i++) {
3067 s8d.data_[i].f = -s8m.data_[i].f;
3068 }
3069 } else if ((instr->Bits(7, 5) == 10) && (instr->Bit(4) == 0) &&
3070 (instr->Bits(20, 2) == 3) && (instr->Bits(23, 2) == 3) &&
3071 (instr->Bits(16, 4) == 11)) {
3072 // Format(instr, "vrecpeq 'qd, 'qm");
3073 for (int i = 0; i < 4; i++) {
3074 s8d.data_[i].f = ReciprocalEstimate(s8m.data_[i].f);
3075 }
3076 } else if ((instr->Bits(8, 4) == 15) && (instr->Bit(4) == 1) &&
3077 (instr->Bits(20, 2) == 0) && (instr->Bits(23, 2) == 0)) {
3078 // Format(instr, "vrecpsq 'qd, 'qn, 'qm");
3079 for (int i = 0; i < 4; i++) {
3080 s8d.data_[i].f = ReciprocalStep(s8n.data_[i].f, s8m.data_[i].f);
3081 }
3082 } else if ((instr->Bits(8, 4) == 5) && (instr->Bit(4) == 0) &&
3083 (instr->Bits(20, 2) == 3) && (instr->Bits(23, 2) == 3) &&
3084 (instr->Bit(7) == 1) && (instr->Bits(16, 4) == 11)) {
3085 // Format(instr, "vrsqrteqs 'qd, 'qm");
3086 for (int i = 0; i < 4; i++) {
3087 s8d.data_[i].f = ReciprocalSqrtEstimate(s8m.data_[i].f);
3088 }
3089 } else if ((instr->Bits(8, 4) == 15) && (instr->Bit(4) == 1) &&
3090 (instr->Bits(20, 2) == 2) && (instr->Bits(23, 2) == 0)) {
3091 // Format(instr, "vrsqrtsqs 'qd, 'qn, 'qm");
3092 for (int i = 0; i < 4; i++) {
3093 s8d.data_[i].f = ReciprocalSqrtStep(s8n.data_[i].f, s8m.data_[i].f);
3094 }
3095 } else if ((instr->Bits(8, 4) == 12) && (instr->Bit(4) == 0) &&
3096 (instr->Bits(20, 2) == 3) && (instr->Bits(23, 2) == 3) &&
3097 (instr->Bit(7) == 0)) {
3098 DRegister dm = instr->DmField();
3099 int64_t dm_value = get_dregister_bits(dm);
3100 int32_t imm4 = instr->Bits(16, 4);
3101 int32_t idx;
3102 if ((imm4 & 1) != 0) {
3103 // Format(instr, "vdupb 'qd, 'dm['imm4_vdup]");
3104 int8_t* dm_b = reinterpret_cast<int8_t*>(&dm_value);
3105 idx = imm4 >> 1;
3106 int8_t val = dm_b[idx];
3107 for (int i = 0; i < 16; i++) {
3108 s8d_8[i] = val;
3109 }
3110 } else if ((imm4 & 2) != 0) {
3111 // Format(instr, "vduph 'qd, 'dm['imm4_vdup]");
3112 int16_t* dm_h = reinterpret_cast<int16_t*>(&dm_value);
3113 idx = imm4 >> 2;
3114 int16_t val = dm_h[idx];
3115 for (int i = 0; i < 8; i++) {
3116 s8d_16[i] = val;
3117 }
3118 } else if ((imm4 & 4) != 0) {
3119 // Format(instr, "vdupw 'qd, 'dm['imm4_vdup]");
3120 int32_t* dm_w = reinterpret_cast<int32_t*>(&dm_value);
3121 idx = imm4 >> 3;
3122 int32_t val = dm_w[idx];
3123 for (int i = 0; i < 4; i++) {
3124 s8d.data_[i].u = val;
3125 }
3126 } else {
3127 UnimplementedInstruction(instr);
3128 }
3129 } else if ((instr->Bits(8, 4) == 1) && (instr->Bit(4) == 0) &&
3130 (instr->Bits(20, 2) == 3) && (instr->Bits(23, 2) == 3) &&
3131 (instr->Bit(7) == 1) && (instr->Bits(16, 4) == 10)) {
3132 // Format(instr, "vzipqw 'qd, 'qm");
3133 get_qregister(qd, &s8d);
3134
3135 // Interleave the elements with the low words in qd, and the high words
3136 // in qm.
3137 simd_value_swap(&s8d, 3, &s8m, 2);
3138 simd_value_swap(&s8d, 3, &s8m, 1);
3139 simd_value_swap(&s8d, 2, &s8m, 0);
3140 simd_value_swap(&s8d, 2, &s8d, 1);
3141
3142 set_qregister(qm, s8m); // Writes both qd and qm.
3143 } else if ((instr->Bits(8, 4) == 8) && (instr->Bit(4) == 1) &&
3144 (instr->Bits(23, 2) == 2)) {
3145 // Format(instr, "vceqq'sz 'qd, 'qn, 'qm");
3146 const int size = instr->Bits(20, 2);
3147 if (size == 0) {
3148 for (int i = 0; i < 16; i++) {
3149 s8d_8[i] = s8n_8[i] == s8m_8[i] ? 0xff : 0;
3150 }
3151 } else if (size == 1) {
3152 for (int i = 0; i < 8; i++) {
3153 s8d_16[i] = s8n_16[i] == s8m_16[i] ? 0xffff : 0;
3154 }
3155 } else if (size == 2) {
3156 for (int i = 0; i < 4; i++) {
3157 s8d.data_[i].u = s8n.data_[i].u == s8m.data_[i].u ? 0xffffffff : 0;
3158 }
3159 } else if (size == 3) {
3160 UnimplementedInstruction(instr);
3161 } else {
3162 UNREACHABLE();
3163 }
3164 } else if ((instr->Bits(8, 4) == 14) && (instr->Bit(4) == 0) &&
3165 (instr->Bits(20, 2) == 0) && (instr->Bits(23, 2) == 0)) {
3166 // Format(instr, "vceqqs 'qd, 'qn, 'qm");
3167 for (int i = 0; i < 4; i++) {
3168 s8d.data_[i].u = s8n.data_[i].f == s8m.data_[i].f ? 0xffffffff : 0;
3169 }
3170 } else if ((instr->Bits(8, 4) == 3) && (instr->Bit(4) == 1) &&
3171 (instr->Bits(23, 2) == 0)) {
3172 // Format(instr, "vcgeq'sz 'qd, 'qn, 'qm");
3173 const int size = instr->Bits(20, 2);
3174 if (size == 0) {
3175 for (int i = 0; i < 16; i++) {
3176 s8d_8[i] = s8n_8[i] >= s8m_8[i] ? 0xff : 0;
3177 }
3178 } else if (size == 1) {
3179 for (int i = 0; i < 8; i++) {
3180 s8d_16[i] = s8n_16[i] >= s8m_16[i] ? 0xffff : 0;
3181 }
3182 } else if (size == 2) {
3183 for (int i = 0; i < 4; i++) {
3184 s8d.data_[i].u = s8n_32[i] >= s8m_32[i] ? 0xffffffff : 0;
3185 }
3186 } else if (size == 3) {
3187 UnimplementedInstruction(instr);
3188 } else {
3189 UNREACHABLE();
3190 }
3191 } else if ((instr->Bits(8, 4) == 3) && (instr->Bit(4) == 1) &&
3192 (instr->Bits(23, 2) == 2)) {
3193 // Format(instr, "vcugeq'sz 'qd, 'qn, 'qm");
3194 const int size = instr->Bits(20, 2);
3195 if (size == 0) {
3196 for (int i = 0; i < 16; i++) {
3197 s8d_8[i] = s8n_u8[i] >= s8m_u8[i] ? 0xff : 0;
3198 }
3199 } else if (size == 1) {
3200 for (int i = 0; i < 8; i++) {
3201 s8d_16[i] = s8n_u16[i] >= s8m_u16[i] ? 0xffff : 0;
3202 }
3203 } else if (size == 2) {
3204 for (int i = 0; i < 4; i++) {
3205 s8d.data_[i].u = s8n.data_[i].u >= s8m.data_[i].u ? 0xffffffff : 0;
3206 }
3207 } else if (size == 3) {
3208 UnimplementedInstruction(instr);
3209 } else {
3210 UNREACHABLE();
3211 }
3212 } else if ((instr->Bits(8, 4) == 14) && (instr->Bit(4) == 0) &&
3213 (instr->Bits(20, 2) == 0) && (instr->Bits(23, 2) == 2)) {
3214 // Format(instr, "vcgeqs 'qd, 'qn, 'qm");
3215 for (int i = 0; i < 4; i++) {
3216 s8d.data_[i].u = s8n.data_[i].f >= s8m.data_[i].f ? 0xffffffff : 0;
3217 }
3218 } else if ((instr->Bits(8, 4) == 3) && (instr->Bit(4) == 0) &&
3219 (instr->Bits(23, 2) == 0)) {
3220 // Format(instr, "vcgtq'sz 'qd, 'qn, 'qm");
3221 const int size = instr->Bits(20, 2);
3222 if (size == 0) {
3223 for (int i = 0; i < 16; i++) {
3224 s8d_8[i] = s8n_8[i] > s8m_8[i] ? 0xff : 0;
3225 }
3226 } else if (size == 1) {
3227 for (int i = 0; i < 8; i++) {
3228 s8d_16[i] = s8n_16[i] > s8m_16[i] ? 0xffff : 0;
3229 }
3230 } else if (size == 2) {
3231 for (int i = 0; i < 4; i++) {
3232 s8d.data_[i].u = s8n_32[i] > s8m_32[i] ? 0xffffffff : 0;
3233 }
3234 } else if (size == 3) {
3235 UnimplementedInstruction(instr);
3236 } else {
3237 UNREACHABLE();
3238 }
3239 } else if ((instr->Bits(8, 4) == 3) && (instr->Bit(4) == 0) &&
3240 (instr->Bits(23, 2) == 2)) {
3241 // Format(instr, "vcugtq'sz 'qd, 'qn, 'qm");
3242 const int size = instr->Bits(20, 2);
3243 if (size == 0) {
3244 for (int i = 0; i < 16; i++) {
3245 s8d_8[i] = s8n_u8[i] > s8m_u8[i] ? 0xff : 0;
3246 }
3247 } else if (size == 1) {
3248 for (int i = 0; i < 8; i++) {
3249 s8d_16[i] = s8n_u16[i] > s8m_u16[i] ? 0xffff : 0;
3250 }
3251 } else if (size == 2) {
3252 for (int i = 0; i < 4; i++) {
3253 s8d.data_[i].u = s8n.data_[i].u > s8m.data_[i].u ? 0xffffffff : 0;
3254 }
3255 } else if (size == 3) {
3256 UnimplementedInstruction(instr);
3257 } else {
3258 UNREACHABLE();
3259 }
3260 } else if ((instr->Bits(8, 4) == 14) && (instr->Bit(4) == 0) &&
3261 (instr->Bits(20, 2) == 2) && (instr->Bits(23, 2) == 2)) {
3262 // Format(instr, "vcgtqs 'qd, 'qn, 'qm");
3263 for (int i = 0; i < 4; i++) {
3264 s8d.data_[i].u = s8n.data_[i].f > s8m.data_[i].f ? 0xffffffff : 0;
3265 }
3266 } else {
3267 UnimplementedInstruction(instr);
3268 }
3269
3270 set_qregister(qd, s8d);
3271 } else {
3272 // Q == 0, Uses 64-bit D registers.
3273 if ((instr->Bits(23, 2) == 3) && (instr->Bits(20, 2) == 3) &&
3274 (instr->Bits(10, 2) == 2) && (instr->Bit(4) == 0)) {
3275 // Format(instr, "vtbl 'dd, 'dtbllist, 'dm");
3276 DRegister dd = instr->DdField();
3277 DRegister dm = instr->DmField();
3278 int reg_count = instr->Bits(8, 2) + 1;
3279 int start = (instr->Bit(7) << 4) | instr->Bits(16, 4);
3280 int64_t table[4];
3281
3282 for (int i = 0; i < reg_count; i++) {
3283 DRegister d = static_cast<DRegister>(start + i);
3284 table[i] = get_dregister_bits(d);
3285 }
3286 for (int i = reg_count; i < 4; i++) {
3287 table[i] = 0;
3288 }
3289
3290 int64_t dm_value = get_dregister_bits(dm);
3291 int64_t result;
3292 int8_t* dm_bytes = reinterpret_cast<int8_t*>(&dm_value);
3293 int8_t* result_bytes = reinterpret_cast<int8_t*>(&result);
3294 int8_t* table_bytes = reinterpret_cast<int8_t*>(&table[0]);
3295 for (int i = 0; i < 8; i++) {
3296 int idx = dm_bytes[i];
3297 if ((idx >= 0) && (idx < 256)) {
3298 result_bytes[i] = table_bytes[idx];
3299 } else {
3300 result_bytes[i] = 0;
3301 }
3302 }
3303
3304 set_dregister_bits(dd, result);
3305 } else {
3306 UnimplementedInstruction(instr);
3307 }
3308 }
3309}
3310
3311// Executes the current instruction.
3312DART_FORCE_INLINE void Simulator::InstructionDecodeImpl(Instr* instr) {
3313 pc_modified_ = false;
3314 if (instr->ConditionField() == kSpecialCondition) {
3315 if (instr->InstructionBits() == static_cast<int32_t>(0xf57ff01f)) {
3316 // Format(instr, "clrex");
3317 ClearExclusive();
3318 } else if (instr->InstructionBits() ==
3319 static_cast<int32_t>(kDataMemoryBarrier)) {
3320 // Format(instr, "dmb ish");
3321 std::atomic_thread_fence(std::memory_order_seq_cst);
3322 } else {
3323 if (instr->IsSIMDDataProcessing()) {
3324 DecodeSIMDDataProcessing(instr);
3325 } else {
3326 UnimplementedInstruction(instr);
3327 }
3328 }
3329 } else if (ConditionallyExecute(instr)) {
3330 switch (instr->TypeField()) {
3331 case 0:
3332 case 1: {
3333 DecodeType01(instr);
3334 break;
3335 }
3336 case 2: {
3337 DecodeType2(instr);
3338 break;
3339 }
3340 case 3: {
3341 DecodeType3(instr);
3342 break;
3343 }
3344 case 4: {
3345 DecodeType4(instr);
3346 break;
3347 }
3348 case 5: {
3349 DecodeType5(instr);
3350 break;
3351 }
3352 case 6: {
3353 DecodeType6(instr);
3354 break;
3355 }
3356 case 7: {
3357 DecodeType7(instr);
3358 break;
3359 }
3360 default: {
3361 // Type field is three bits.
3362 UNREACHABLE();
3363 break;
3364 }
3365 }
3366 }
3367 if (!pc_modified_) {
3368 set_register(PC, reinterpret_cast<int32_t>(instr) + Instr::kInstrSize);
3369 }
3370}
3371
3372void Simulator::InstructionDecode(Instr* instr) {
3373 if (IsTracingExecution()) {
3374 THR_Print("%" Pu64 " ", icount_);
3375 const uword start = reinterpret_cast<uword>(instr);
3376 const uword end = start + Instr::kInstrSize;
3377 if (FLAG_support_disassembler) {
3378 Disassembler::Disassemble(start, end);
3379 } else {
3380 THR_Print("Disassembler not supported in this mode.\n");
3381 }
3382 }
3383 InstructionDecodeImpl(instr);
3384}
3385
3386void Simulator::Execute() {
3387 // Get the PC to simulate. Cannot use the accessor here as we need the
3388 // raw PC value and not the one used as input to arithmetic instructions.
3389 uword program_counter = get_pc();
3390
3391 if (FLAG_stop_sim_at == ULLONG_MAX && FLAG_trace_sim_after == ULLONG_MAX) {
3392 // Fast version of the dispatch loop without checking whether the simulator
3393 // should be stopping at a particular executed instruction.
3394 while (program_counter != kEndSimulatingPC) {
3395 Instr* instr = reinterpret_cast<Instr*>(program_counter);
3396 icount_++;
3397 if (IsIllegalAddress(program_counter)) {
3398 HandleIllegalAccess(program_counter, instr);
3399 } else {
3400 InstructionDecodeImpl(instr);
3401 }
3402 program_counter = get_pc();
3403 }
3404 } else {
3405 // FLAG_stop_sim_at is at the non-default value. Stop in the debugger when
3406 // we reach the particular instruction count or address.
3407 while (program_counter != kEndSimulatingPC) {
3408 Instr* instr = reinterpret_cast<Instr*>(program_counter);
3409 icount_++;
3410 if (icount_ == FLAG_stop_sim_at) {
3411 SimulatorDebugger dbg(this);
3412 dbg.Stop(instr, "Instruction count reached");
3413 } else if (reinterpret_cast<uint64_t>(instr) == FLAG_stop_sim_at) {
3414 SimulatorDebugger dbg(this);
3415 dbg.Stop(instr, "Instruction address reached");
3416 } else if (IsIllegalAddress(program_counter)) {
3417 HandleIllegalAccess(program_counter, instr);
3418 } else {
3419 InstructionDecode(instr);
3420 }
3421 program_counter = get_pc();
3422 }
3423 }
3424}
3425
3426int64_t Simulator::Call(int32_t entry,
3427 int32_t parameter0,
3428 int32_t parameter1,
3429 int32_t parameter2,
3430 int32_t parameter3,
3431 bool fp_return,
3432 bool fp_args) {
3433 // Save the SP register before the call so we can restore it.
3434 int32_t sp_before_call = get_register(SP);
3435
3436 // Setup parameters.
3437 if (fp_args) {
3438 ASSERT(TargetCPUFeatures::vfp_supported());
3439 set_sregister(S0, bit_cast<float, int32_t>(parameter0));
3440 set_sregister(S1, bit_cast<float, int32_t>(parameter1));
3441 set_sregister(S2, bit_cast<float, int32_t>(parameter2));
3442 set_sregister(S3, bit_cast<float, int32_t>(parameter3));
3443 } else {
3444 set_register(R0, parameter0);
3445 set_register(R1, parameter1);
3446 set_register(R2, parameter2);
3447 set_register(R3, parameter3);
3448 }
3449
3450 // Make sure the activation frames are properly aligned.
3451 int32_t stack_pointer = sp_before_call;
3452 if (OS::ActivationFrameAlignment() > 1) {
3453 stack_pointer =
3454 Utils::RoundDown(stack_pointer, OS::ActivationFrameAlignment());
3455 }
3456 set_register(SP, stack_pointer);
3457
3458 // Prepare to execute the code at entry.
3459 set_register(PC, entry);
3460 // Put down marker for end of simulation. The simulator will stop simulation
3461 // when the PC reaches this value. By saving the "end simulation" value into
3462 // the LR the simulation stops when returning to this call point.
3463 set_register(LR, kEndSimulatingPC);
3464
3465 // Remember the values of callee-saved registers.
3466 // The code below assumes that r9 is not used as sb (static base) in
3467 // simulator code and therefore is regarded as a callee-saved register.
3468 int32_t r4_val = get_register(R4);
3469 int32_t r5_val = get_register(R5);
3470 int32_t r6_val = get_register(R6);
3471 int32_t r7_val = get_register(R7);
3472 int32_t r8_val = get_register(R8);
3473#if !defined(TARGET_OS_MACOS) && !defined(TARGET_OS_MACOS_IOS)
3474 int32_t r9_val = get_register(R9);
3475#endif
3476 int32_t r10_val = get_register(R10);
3477 int32_t r11_val = get_register(R11);
3478
3479 double d8_val = 0.0;
3480 double d9_val = 0.0;
3481 double d10_val = 0.0;
3482 double d11_val = 0.0;
3483 double d12_val = 0.0;
3484 double d13_val = 0.0;
3485 double d14_val = 0.0;
3486 double d15_val = 0.0;
3487
3488 if (TargetCPUFeatures::vfp_supported()) {
3489 d8_val = get_dregister(D8);
3490 d9_val = get_dregister(D9);
3491 d10_val = get_dregister(D10);
3492 d11_val = get_dregister(D11);
3493 d12_val = get_dregister(D12);
3494 d13_val = get_dregister(D13);
3495 d14_val = get_dregister(D14);
3496 d15_val = get_dregister(D15);
3497 }
3498
3499 // Setup the callee-saved registers with a known value. To be able to check
3500 // that they are preserved properly across dart execution.
3501 int32_t callee_saved_value = icount_;
3502 set_register(R4, callee_saved_value);
3503 set_register(R5, callee_saved_value);
3504 set_register(R6, callee_saved_value);
3505 set_register(R7, callee_saved_value);
3506 set_register(R8, callee_saved_value);
3507#if !defined(TARGET_OS_MACOS) && !defined(TARGET_OS_MACOS_IOS)
3508 set_register(R9, callee_saved_value);
3509#endif
3510 set_register(R10, callee_saved_value);
3511 set_register(R11, callee_saved_value);
3512
3513 double callee_saved_dvalue = 0.0;
3514 if (TargetCPUFeatures::vfp_supported()) {
3515 callee_saved_dvalue = static_cast<double>(icount_);
3516 set_dregister(D8, callee_saved_dvalue);
3517 set_dregister(D9, callee_saved_dvalue);
3518 set_dregister(D10, callee_saved_dvalue);
3519 set_dregister(D11, callee_saved_dvalue);
3520 set_dregister(D12, callee_saved_dvalue);
3521 set_dregister(D13, callee_saved_dvalue);
3522 set_dregister(D14, callee_saved_dvalue);
3523 set_dregister(D15, callee_saved_dvalue);
3524 }
3525
3526 // Start the simulation
3527 Execute();
3528
3529 // Check that the callee-saved registers have been preserved.
3530 ASSERT(callee_saved_value == get_register(R4));
3531 ASSERT(callee_saved_value == get_register(R5));
3532 ASSERT(callee_saved_value == get_register(R6));
3533 ASSERT(callee_saved_value == get_register(R7));
3534 ASSERT(callee_saved_value == get_register(R8));
3535#if !defined(TARGET_OS_MACOS) && !defined(TARGET_OS_MACOS_IOS)
3536 ASSERT(callee_saved_value == get_register(R9));
3537#endif
3538 ASSERT(callee_saved_value == get_register(R10));
3539 ASSERT(callee_saved_value == get_register(R11));
3540
3541 if (TargetCPUFeatures::vfp_supported()) {
3542 ASSERT(callee_saved_dvalue == get_dregister(D8));
3543 ASSERT(callee_saved_dvalue == get_dregister(D9));
3544 ASSERT(callee_saved_dvalue == get_dregister(D10));
3545 ASSERT(callee_saved_dvalue == get_dregister(D11));
3546 ASSERT(callee_saved_dvalue == get_dregister(D12));
3547 ASSERT(callee_saved_dvalue == get_dregister(D13));
3548 ASSERT(callee_saved_dvalue == get_dregister(D14));
3549 ASSERT(callee_saved_dvalue == get_dregister(D15));
3550 }
3551
3552 // Restore callee-saved registers with the original value.
3553 set_register(R4, r4_val);
3554 set_register(R5, r5_val);
3555 set_register(R6, r6_val);
3556 set_register(R7, r7_val);
3557 set_register(R8, r8_val);
3558#if !defined(TARGET_OS_MACOS) && !defined(TARGET_OS_MACOS_IOS)
3559 set_register(R9, r9_val);
3560#endif
3561 set_register(R10, r10_val);
3562 set_register(R11, r11_val);
3563
3564 if (TargetCPUFeatures::vfp_supported()) {
3565 set_dregister(D8, d8_val);
3566 set_dregister(D9, d9_val);
3567 set_dregister(D10, d10_val);
3568 set_dregister(D11, d11_val);
3569 set_dregister(D12, d12_val);
3570 set_dregister(D13, d13_val);
3571 set_dregister(D14, d14_val);
3572 set_dregister(D15, d15_val);
3573 }
3574
3575 // Restore the SP register and return R1:R0.
3576 set_register(SP, sp_before_call);
3577 int64_t return_value;
3578 if (fp_return) {
3579 ASSERT(TargetCPUFeatures::vfp_supported());
3580 return_value = bit_cast<int64_t, double>(get_dregister(D0));
3581 } else {
3582 return_value = Utils::LowHighTo64Bits(get_register(R0), get_register(R1));
3583 }
3584 return return_value;
3585}
3586
3587void Simulator::JumpToFrame(uword pc, uword sp, uword fp, Thread* thread) {
3588 // Walk over all setjmp buffers (simulated --> C++ transitions)
3589 // and try to find the setjmp associated with the simulated stack pointer.
3590 SimulatorSetjmpBuffer* buf = last_setjmp_buffer();
3591 while (buf->link() != NULL && buf->link()->sp() <= sp) {
3592 buf = buf->link();
3593 }
3594 ASSERT(buf != NULL);
3595
3596 // The C++ caller has not cleaned up the stack memory of C++ frames.
3597 // Prepare for unwinding frames by destroying all the stack resources
3598 // in the previous C++ frames.
3599 StackResource::Unwind(thread);
3600
3601 // Unwind the C++ stack and continue simulation in the target frame.
3602 set_register(PC, static_cast<int32_t>(pc));
3603 set_register(SP, static_cast<int32_t>(sp));
3604 set_register(FP, static_cast<int32_t>(fp));
3605 set_register(THR, reinterpret_cast<uword>(thread));
3606 // Set the tag.
3607 thread->set_vm_tag(VMTag::kDartCompiledTagId);
3608 // Clear top exit frame.
3609 thread->set_top_exit_frame_info(0);
3610 // Restore pool pointer.
3611 int32_t code =
3612 *reinterpret_cast<int32_t*>(fp + kPcMarkerSlotFromFp * kWordSize);
3613 int32_t pp = (FLAG_precompiled_mode && FLAG_use_bare_instructions)
3614 ? static_cast<int32_t>(thread->global_object_pool())
3615 : *reinterpret_cast<int32_t*>(
3616 (code + Code::object_pool_offset() - kHeapObjectTag));
3617
3618 set_register(CODE_REG, code);
3619 set_register(PP, pp);
3620 buf->Longjmp();
3621}
3622
3623} // namespace dart
3624
3625#endif // defined(USING_SIMULATOR)
3626
3627#endif // defined TARGET_ARCH_ARM
3628