1 | /* |
2 | * Copyright 2012-present Facebook, Inc. |
3 | * |
4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
5 | * you may not use this file except in compliance with the License. |
6 | * You may obtain a copy of the License at |
7 | * |
8 | * http://www.apache.org/licenses/LICENSE-2.0 |
9 | * |
10 | * Unless required by applicable law or agreed to in writing, software |
11 | * distributed under the License is distributed on an "AS IS" BASIS, |
12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
13 | * See the License for the specific language governing permissions and |
14 | * limitations under the License. |
15 | */ |
16 | |
17 | #pragma once |
18 | |
19 | #include <cstdint> |
20 | |
21 | #include <folly/Portability.h> |
22 | |
23 | #ifdef _MSC_VER |
24 | #include <intrin.h> |
25 | #endif |
26 | |
27 | namespace folly { |
28 | |
29 | /** |
30 | * Identification of an Intel CPU. |
31 | * Supports CPUID feature flags (EAX=1) and extended features (EAX=7, ECX=0). |
32 | * Values from |
33 | * http://www.intel.com/content/www/us/en/processors/processor-identification-cpuid-instruction-note.html |
34 | */ |
35 | class CpuId { |
36 | public: |
37 | // Always inline in order for this to be usable from a __ifunc__. |
38 | // In shared library mode, a __ifunc__ runs at relocation time, while the |
39 | // PLT hasn't been fully populated yet; thus, ifuncs cannot use symbols |
40 | // with potentially external linkage. (This issue is less likely in opt |
41 | // mode since inlining happens more likely, and it doesn't happen for |
42 | // statically linked binaries which don't depend on the PLT) |
43 | FOLLY_ALWAYS_INLINE CpuId() { |
44 | #if defined(_MSC_VER) && (FOLLY_X64 || defined(_M_IX86)) |
45 | int reg[4]; |
46 | __cpuid(static_cast<int*>(reg), 0); |
47 | const int n = reg[0]; |
48 | if (n >= 1) { |
49 | __cpuid(static_cast<int*>(reg), 1); |
50 | f1c_ = uint32_t(reg[2]); |
51 | f1d_ = uint32_t(reg[3]); |
52 | } |
53 | if (n >= 7) { |
54 | __cpuidex(static_cast<int*>(reg), 7, 0); |
55 | f7b_ = uint32_t(reg[1]); |
56 | f7c_ = uint32_t(reg[2]); |
57 | } |
58 | #elif defined(__i386__) && defined(__PIC__) && !defined(__clang__) && \ |
59 | defined(__GNUC__) |
60 | // The following block like the normal cpuid branch below, but gcc |
61 | // reserves ebx for use of its pic register so we must specially |
62 | // handle the save and restore to avoid clobbering the register |
63 | uint32_t n; |
64 | __asm__( |
65 | "pushl %%ebx\n\t" |
66 | "cpuid\n\t" |
67 | "popl %%ebx\n\t" |
68 | : "=a" (n) |
69 | : "a" (0) |
70 | : "ecx" , "edx" ); |
71 | if (n >= 1) { |
72 | uint32_t f1a; |
73 | __asm__( |
74 | "pushl %%ebx\n\t" |
75 | "cpuid\n\t" |
76 | "popl %%ebx\n\t" |
77 | : "=a" (f1a), "=c" (f1c_), "=d" (f1d_) |
78 | : "a" (1) |
79 | :); |
80 | } |
81 | if (n >= 7) { |
82 | __asm__( |
83 | "pushl %%ebx\n\t" |
84 | "cpuid\n\t" |
85 | "movl %%ebx, %%eax\n\r" |
86 | "popl %%ebx" |
87 | : "=a" (f7b_), "=c" (f7c_) |
88 | : "a" (7), "c" (0) |
89 | : "edx" ); |
90 | } |
91 | #elif FOLLY_X64 || defined(__i386__) |
92 | uint32_t n; |
93 | __asm__("cpuid" : "=a" (n) : "a" (0) : "ebx" , "ecx" , "edx" ); |
94 | if (n >= 1) { |
95 | uint32_t f1a; |
96 | __asm__("cpuid" : "=a" (f1a), "=c" (f1c_), "=d" (f1d_) : "a" (1) : "ebx" ); |
97 | } |
98 | if (n >= 7) { |
99 | uint32_t f7a; |
100 | __asm__("cpuid" |
101 | : "=a" (f7a), "=b" (f7b_), "=c" (f7c_) |
102 | : "a" (7), "c" (0) |
103 | : "edx" ); |
104 | } |
105 | #endif |
106 | } |
107 | |
108 | #define X(name, r, bit) \ |
109 | FOLLY_ALWAYS_INLINE bool name() const { \ |
110 | return ((r) & (1U << bit)) != 0; \ |
111 | } |
112 | |
113 | // cpuid(1): Processor Info and Feature Bits. |
114 | #define C(name, bit) X(name, f1c_, bit) |
115 | C(sse3, 0) |
116 | C(pclmuldq, 1) |
117 | C(dtes64, 2) |
118 | C(monitor, 3) |
119 | C(dscpl, 4) |
120 | C(vmx, 5) |
121 | C(smx, 6) |
122 | C(eist, 7) |
123 | C(tm2, 8) |
124 | C(ssse3, 9) |
125 | C(cnxtid, 10) |
126 | C(fma, 12) |
127 | C(cx16, 13) |
128 | C(xtpr, 14) |
129 | C(pdcm, 15) |
130 | C(pcid, 17) |
131 | C(dca, 18) |
132 | C(sse41, 19) |
133 | C(sse42, 20) |
134 | C(x2apic, 21) |
135 | C(movbe, 22) |
136 | C(popcnt, 23) |
137 | C(tscdeadline, 24) |
138 | C(aes, 25) |
139 | C(xsave, 26) |
140 | C(osxsave, 27) |
141 | C(avx, 28) |
142 | C(f16c, 29) |
143 | C(rdrand, 30) |
144 | #undef C |
145 | #define D(name, bit) X(name, f1d_, bit) |
146 | D(fpu, 0) |
147 | D(vme, 1) |
148 | D(de, 2) |
149 | D(pse, 3) |
150 | D(tsc, 4) |
151 | D(msr, 5) |
152 | D(pae, 6) |
153 | D(mce, 7) |
154 | D(cx8, 8) |
155 | D(apic, 9) |
156 | D(sep, 11) |
157 | D(mtrr, 12) |
158 | D(pge, 13) |
159 | D(mca, 14) |
160 | D(cmov, 15) |
161 | D(pat, 16) |
162 | D(pse36, 17) |
163 | D(psn, 18) |
164 | D(clfsh, 19) |
165 | D(ds, 21) |
166 | D(acpi, 22) |
167 | D(mmx, 23) |
168 | D(fxsr, 24) |
169 | D(sse, 25) |
170 | D(sse2, 26) |
171 | D(ss, 27) |
172 | D(htt, 28) |
173 | D(tm, 29) |
174 | D(pbe, 31) |
175 | #undef D |
176 | |
177 | // cpuid(7): Extended Features. |
178 | #define B(name, bit) X(name, f7b_, bit) |
179 | B(bmi1, 3) |
180 | B(hle, 4) |
181 | B(avx2, 5) |
182 | B(smep, 7) |
183 | B(bmi2, 8) |
184 | B(erms, 9) |
185 | B(invpcid, 10) |
186 | B(rtm, 11) |
187 | B(mpx, 14) |
188 | B(avx512f, 16) |
189 | B(avx512dq, 17) |
190 | B(rdseed, 18) |
191 | B(adx, 19) |
192 | B(smap, 20) |
193 | B(avx512ifma, 21) |
194 | B(pcommit, 22) |
195 | B(clflushopt, 23) |
196 | B(clwb, 24) |
197 | B(avx512pf, 26) |
198 | B(avx512er, 27) |
199 | B(avx512cd, 28) |
200 | B(sha, 29) |
201 | B(avx512bw, 30) |
202 | B(avx512vl, 31) |
203 | #undef B |
204 | #define C(name, bit) X(name, f7c_, bit) |
205 | C(prefetchwt1, 0) |
206 | C(avx512vbmi, 1) |
207 | #undef C |
208 | |
209 | #undef X |
210 | |
211 | private: |
212 | uint32_t f1c_ = 0; |
213 | uint32_t f1d_ = 0; |
214 | uint32_t f7b_ = 0; |
215 | uint32_t f7c_ = 0; |
216 | }; |
217 | |
218 | } // namespace folly |
219 | |