1/* Copyright (C) 2002-2020 Free Software Foundation, Inc.
2 This file is part of the GNU C Library.
3 Contributed by Ulrich Drepper <drepper@redhat.com>, 2002.
4
5 The GNU C Library is free software; you can redistribute it and/or
6 modify it under the terms of the GNU Lesser General Public
7 License as published by the Free Software Foundation; either
8 version 2.1 of the License, or (at your option) any later version.
9
10 The GNU C Library is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 Lesser General Public License for more details.
14
15 You should have received a copy of the GNU Lesser General Public
16 License along with the GNU C Library; if not, see
17 <https://www.gnu.org/licenses/>. */
18
19/* Default stack size. */
20#define ARCH_STACK_DEFAULT_SIZE (2 * 1024 * 1024)
21
22/* Required stack pointer alignment at beginning. SSE requires 16
23 bytes. */
24#define STACK_ALIGN 16
25
26/* Minimal stack size after allocating thread descriptor and guard size. */
27#define MINIMAL_REST_STACK 2048
28
29/* Alignment requirement for TCB.
30
31 We need to store post-AVX vector registers in the TCB and we want the
32 storage to be aligned to at least 32 bytes.
33
34 Some processors such as Intel Atom pay a big penalty on every
35 access using a segment override if that segment's base is not
36 aligned to the size of a cache line. (See Intel 64 and IA-32
37 Architectures Optimization Reference Manual, section 13.3.3.3,
38 "Segment Base".) On such machines, a cache line is 64 bytes. */
39#define TCB_ALIGNMENT 64
40
41
42/* Location of current stack frame. The frame pointer is not usable. */
43#define CURRENT_STACK_FRAME \
44 ({ register char *frame __asm__("rsp"); frame; })
45