1/*******************************************************************************
2* Copyright 2017-2018 Intel Corporation
3*
4* Licensed under the Apache License, Version 2.0 (the "License");
5* you may not use this file except in compliance with the License.
6* You may obtain a copy of the License at
7*
8* http://www.apache.org/licenses/LICENSE-2.0
9*
10* Unless required by applicable law or agreed to in writing, software
11* distributed under the License is distributed on an "AS IS" BASIS,
12* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13* See the License for the specific language governing permissions and
14* limitations under the License.
15*******************************************************************************/
16
17#ifndef CPU_BARRIER_HPP
18#define CPU_BARRIER_HPP
19
20#include <assert.h>
21
22#include "jit_generator.hpp"
23#include "utils.hpp"
24
25namespace mkldnn {
26namespace impl {
27namespace cpu {
28
29namespace simple_barrier {
30
31STRUCT_ALIGN(64,
32struct ctx_t {
33 enum { CACHE_LINE_SIZE = 64 };
34 volatile size_t ctr;
35 char pad1[CACHE_LINE_SIZE - 1 * sizeof(size_t)];
36 volatile size_t sense;
37 char pad2[CACHE_LINE_SIZE - 1 * sizeof(size_t)];
38});
39
40inline void ctx_init(ctx_t *ctx) { *ctx = utils::zero<ctx_t>(); }
41void barrier(ctx_t *ctx, int nthr);
42
43/** injects actual barrier implementation into another jitted code
44 * @params:
45 * code -- jit_generator object where the barrier is to be injected
46 * reg_ctx -- read-only register with pointer to the barrier context
47 * reg_nnthr -- read-only register with the # of synchronizing threads
48 */
49void generate(jit_generator &code, Xbyak::Reg64 reg_ctx,
50 Xbyak::Reg64 reg_nthr);
51
52}
53
54}
55}
56}
57
58#endif
59
60// vim: et ts=4 sw=4 cindent cino^=l0,\:0,N-s
61