1 | /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * |
2 | * Mupen64plus - mi_controller.h * |
3 | * Mupen64Plus homepage: https://mupen64plus.org/ * |
4 | * Copyright (C) 2014 Bobby Smiles * |
5 | * * |
6 | * This program is free software; you can redistribute it and/or modify * |
7 | * it under the terms of the GNU General Public License as published by * |
8 | * the Free Software Foundation; either version 2 of the License, or * |
9 | * (at your option) any later version. * |
10 | * * |
11 | * This program is distributed in the hope that it will be useful, * |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of * |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * |
14 | * GNU General Public License for more details. * |
15 | * * |
16 | * You should have received a copy of the GNU General Public License * |
17 | * along with this program; if not, write to the * |
18 | * Free Software Foundation, Inc., * |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * |
20 | * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */ |
21 | |
22 | #ifndef M64P_DEVICE_RCP_MI_MI_CONTROLLER_H |
23 | #define M64P_DEVICE_RCP_MI_MI_CONTROLLER_H |
24 | |
25 | #include <stdint.h> |
26 | |
27 | #include "osal/preproc.h" |
28 | |
29 | struct r4300_core; |
30 | |
31 | enum mi_registers |
32 | { |
33 | MI_INIT_MODE_REG, |
34 | MI_VERSION_REG, |
35 | MI_INTR_REG, |
36 | MI_INTR_MASK_REG, |
37 | MI_REGS_COUNT |
38 | }; |
39 | |
40 | |
41 | enum mi_intr |
42 | { |
43 | MI_INTR_SP = 0x01, |
44 | MI_INTR_SI = 0x02, |
45 | MI_INTR_AI = 0x04, |
46 | MI_INTR_VI = 0x08, |
47 | MI_INTR_PI = 0x10, |
48 | MI_INTR_DP = 0x20 |
49 | }; |
50 | |
51 | struct mi_controller |
52 | { |
53 | uint32_t regs[MI_REGS_COUNT]; |
54 | |
55 | struct r4300_core* r4300; |
56 | }; |
57 | |
58 | static osal_inline uint32_t mi_reg(uint32_t address) |
59 | { |
60 | return (address & 0xffff) >> 2; |
61 | } |
62 | |
63 | void init_mi(struct mi_controller* mi, struct r4300_core* r4300); |
64 | void poweron_mi(struct mi_controller* mi); |
65 | |
66 | void read_mi_regs(void* opaque, uint32_t address, uint32_t* value); |
67 | void write_mi_regs(void* opaque, uint32_t address, uint32_t value, uint32_t mask); |
68 | |
69 | void raise_rcp_interrupt(struct mi_controller* mi, uint32_t mi_intr); |
70 | void signal_rcp_interrupt(struct mi_controller* mi, uint32_t mi_intr); |
71 | void clear_rcp_interrupt(struct mi_controller* mi, uint32_t mi_intr); |
72 | |
73 | #endif |
74 | |