1 | /* This file is autogenerated by tracetool, do not edit. */ |
2 | |
3 | #include "qemu/osdep.h" |
4 | #include "qemu/module.h" |
5 | #include "trace.h" |
6 | |
7 | uint16_t _TRACE_JAZZ_LED_READ_DSTATE; |
8 | uint16_t _TRACE_JAZZ_LED_WRITE_DSTATE; |
9 | uint16_t _TRACE_XENFB_MOUSE_EVENT_DSTATE; |
10 | uint16_t _TRACE_XENFB_KEY_EVENT_DSTATE; |
11 | uint16_t _TRACE_XENFB_INPUT_CONNECTED_DSTATE; |
12 | uint16_t _TRACE_G364FB_READ_DSTATE; |
13 | uint16_t _TRACE_G364FB_WRITE_DSTATE; |
14 | uint16_t _TRACE_MILKYMIST_TMU2_MEMORY_READ_DSTATE; |
15 | uint16_t _TRACE_MILKYMIST_TMU2_MEMORY_WRITE_DSTATE; |
16 | uint16_t _TRACE_MILKYMIST_TMU2_START_DSTATE; |
17 | uint16_t _TRACE_MILKYMIST_TMU2_PULSE_IRQ_DSTATE; |
18 | uint16_t _TRACE_MILKYMIST_VGAFB_MEMORY_READ_DSTATE; |
19 | uint16_t _TRACE_MILKYMIST_VGAFB_MEMORY_WRITE_DSTATE; |
20 | uint16_t _TRACE_VMWARE_VALUE_READ_DSTATE; |
21 | uint16_t _TRACE_VMWARE_VALUE_WRITE_DSTATE; |
22 | uint16_t _TRACE_VMWARE_PALETTE_READ_DSTATE; |
23 | uint16_t _TRACE_VMWARE_PALETTE_WRITE_DSTATE; |
24 | uint16_t _TRACE_VMWARE_SCRATCH_READ_DSTATE; |
25 | uint16_t _TRACE_VMWARE_SCRATCH_WRITE_DSTATE; |
26 | uint16_t _TRACE_VMWARE_SETMODE_DSTATE; |
27 | uint16_t _TRACE_VIRTIO_GPU_FEATURES_DSTATE; |
28 | uint16_t _TRACE_VIRTIO_GPU_CMD_GET_DISPLAY_INFO_DSTATE; |
29 | uint16_t _TRACE_VIRTIO_GPU_CMD_GET_EDID_DSTATE; |
30 | uint16_t _TRACE_VIRTIO_GPU_CMD_SET_SCANOUT_DSTATE; |
31 | uint16_t _TRACE_VIRTIO_GPU_CMD_RES_CREATE_2D_DSTATE; |
32 | uint16_t _TRACE_VIRTIO_GPU_CMD_RES_CREATE_3D_DSTATE; |
33 | uint16_t _TRACE_VIRTIO_GPU_CMD_RES_UNREF_DSTATE; |
34 | uint16_t _TRACE_VIRTIO_GPU_CMD_RES_BACK_ATTACH_DSTATE; |
35 | uint16_t _TRACE_VIRTIO_GPU_CMD_RES_BACK_DETACH_DSTATE; |
36 | uint16_t _TRACE_VIRTIO_GPU_CMD_RES_XFER_TOH_2D_DSTATE; |
37 | uint16_t _TRACE_VIRTIO_GPU_CMD_RES_XFER_TOH_3D_DSTATE; |
38 | uint16_t _TRACE_VIRTIO_GPU_CMD_RES_XFER_FROMH_3D_DSTATE; |
39 | uint16_t _TRACE_VIRTIO_GPU_CMD_RES_FLUSH_DSTATE; |
40 | uint16_t _TRACE_VIRTIO_GPU_CMD_CTX_CREATE_DSTATE; |
41 | uint16_t _TRACE_VIRTIO_GPU_CMD_CTX_DESTROY_DSTATE; |
42 | uint16_t _TRACE_VIRTIO_GPU_CMD_CTX_RES_ATTACH_DSTATE; |
43 | uint16_t _TRACE_VIRTIO_GPU_CMD_CTX_RES_DETACH_DSTATE; |
44 | uint16_t _TRACE_VIRTIO_GPU_CMD_CTX_SUBMIT_DSTATE; |
45 | uint16_t _TRACE_VIRTIO_GPU_UPDATE_CURSOR_DSTATE; |
46 | uint16_t _TRACE_VIRTIO_GPU_FENCE_CTRL_DSTATE; |
47 | uint16_t _TRACE_VIRTIO_GPU_FENCE_RESP_DSTATE; |
48 | uint16_t _TRACE_QXL_INTERFACE_SET_MM_TIME_DSTATE; |
49 | uint16_t _TRACE_QXL_IO_WRITE_VGA_DSTATE; |
50 | uint16_t _TRACE_QXL_CREATE_GUEST_PRIMARY_DSTATE; |
51 | uint16_t _TRACE_QXL_CREATE_GUEST_PRIMARY_REST_DSTATE; |
52 | uint16_t _TRACE_QXL_DESTROY_PRIMARY_DSTATE; |
53 | uint16_t _TRACE_QXL_ENTER_VGA_MODE_DSTATE; |
54 | uint16_t _TRACE_QXL_EXIT_VGA_MODE_DSTATE; |
55 | uint16_t _TRACE_QXL_HARD_RESET_DSTATE; |
56 | uint16_t _TRACE_QXL_INTERFACE_ASYNC_COMPLETE_IO_DSTATE; |
57 | uint16_t _TRACE_QXL_INTERFACE_ATTACH_WORKER_DSTATE; |
58 | uint16_t _TRACE_QXL_INTERFACE_GET_INIT_INFO_DSTATE; |
59 | uint16_t _TRACE_QXL_INTERFACE_SET_COMPRESSION_LEVEL_DSTATE; |
60 | uint16_t _TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_DSTATE; |
61 | uint16_t _TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_REST_DSTATE; |
62 | uint16_t _TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_OVERFLOW_DSTATE; |
63 | uint16_t _TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_SCHEDULE_BH_DSTATE; |
64 | uint16_t _TRACE_QXL_IO_DESTROY_PRIMARY_IGNORED_DSTATE; |
65 | uint16_t _TRACE_QXL_IO_LOG_DSTATE; |
66 | uint16_t _TRACE_QXL_IO_READ_UNEXPECTED_DSTATE; |
67 | uint16_t _TRACE_QXL_IO_UNEXPECTED_VGA_MODE_DSTATE; |
68 | uint16_t _TRACE_QXL_IO_WRITE_DSTATE; |
69 | uint16_t _TRACE_QXL_MEMSLOT_ADD_GUEST_DSTATE; |
70 | uint16_t _TRACE_QXL_POST_LOAD_DSTATE; |
71 | uint16_t _TRACE_QXL_PRE_LOAD_DSTATE; |
72 | uint16_t _TRACE_QXL_PRE_SAVE_DSTATE; |
73 | uint16_t _TRACE_QXL_RESET_SURFACES_DSTATE; |
74 | uint16_t _TRACE_QXL_RING_COMMAND_CHECK_DSTATE; |
75 | uint16_t _TRACE_QXL_RING_COMMAND_GET_DSTATE; |
76 | uint16_t _TRACE_QXL_RING_COMMAND_REQ_NOTIFICATION_DSTATE; |
77 | uint16_t _TRACE_QXL_RING_CURSOR_CHECK_DSTATE; |
78 | uint16_t _TRACE_QXL_RING_CURSOR_GET_DSTATE; |
79 | uint16_t _TRACE_QXL_RING_CURSOR_REQ_NOTIFICATION_DSTATE; |
80 | uint16_t _TRACE_QXL_RING_RES_PUSH_DSTATE; |
81 | uint16_t _TRACE_QXL_RING_RES_PUSH_REST_DSTATE; |
82 | uint16_t _TRACE_QXL_RING_RES_PUT_DSTATE; |
83 | uint16_t _TRACE_QXL_SET_MODE_DSTATE; |
84 | uint16_t _TRACE_QXL_SOFT_RESET_DSTATE; |
85 | uint16_t _TRACE_QXL_SPICE_DESTROY_SURFACES_COMPLETE_DSTATE; |
86 | uint16_t _TRACE_QXL_SPICE_DESTROY_SURFACES_DSTATE; |
87 | uint16_t _TRACE_QXL_SPICE_DESTROY_SURFACE_WAIT_COMPLETE_DSTATE; |
88 | uint16_t _TRACE_QXL_SPICE_DESTROY_SURFACE_WAIT_DSTATE; |
89 | uint16_t _TRACE_QXL_SPICE_FLUSH_SURFACES_ASYNC_DSTATE; |
90 | uint16_t _TRACE_QXL_SPICE_MONITORS_CONFIG_DSTATE; |
91 | uint16_t _TRACE_QXL_SPICE_LOADVM_COMMANDS_DSTATE; |
92 | uint16_t _TRACE_QXL_SPICE_OOM_DSTATE; |
93 | uint16_t _TRACE_QXL_SPICE_RESET_CURSOR_DSTATE; |
94 | uint16_t _TRACE_QXL_SPICE_RESET_IMAGE_CACHE_DSTATE; |
95 | uint16_t _TRACE_QXL_SPICE_RESET_MEMSLOTS_DSTATE; |
96 | uint16_t _TRACE_QXL_SPICE_UPDATE_AREA_DSTATE; |
97 | uint16_t _TRACE_QXL_SPICE_UPDATE_AREA_REST_DSTATE; |
98 | uint16_t _TRACE_QXL_SURFACES_DIRTY_DSTATE; |
99 | uint16_t _TRACE_QXL_SEND_EVENTS_DSTATE; |
100 | uint16_t _TRACE_QXL_SEND_EVENTS_VM_STOPPED_DSTATE; |
101 | uint16_t _TRACE_QXL_SET_GUEST_BUG_DSTATE; |
102 | uint16_t _TRACE_QXL_INTERRUPT_CLIENT_MONITORS_CONFIG_DSTATE; |
103 | uint16_t _TRACE_QXL_CLIENT_MONITORS_CONFIG_UNSUPPORTED_BY_GUEST_DSTATE; |
104 | uint16_t _TRACE_QXL_CLIENT_MONITORS_CONFIG_UNSUPPORTED_BY_DEVICE_DSTATE; |
105 | uint16_t _TRACE_QXL_CLIENT_MONITORS_CONFIG_CAPPED_DSTATE; |
106 | uint16_t _TRACE_QXL_CLIENT_MONITORS_CONFIG_CRC_DSTATE; |
107 | uint16_t _TRACE_QXL_SET_CLIENT_CAPABILITIES_UNSUPPORTED_BY_REVISION_DSTATE; |
108 | uint16_t _TRACE_QXL_RENDER_BLIT_DSTATE; |
109 | uint16_t _TRACE_QXL_RENDER_GUEST_PRIMARY_RESIZED_DSTATE; |
110 | uint16_t _TRACE_QXL_RENDER_UPDATE_AREA_DONE_DSTATE; |
111 | uint16_t _TRACE_VGA_STD_READ_IO_DSTATE; |
112 | uint16_t _TRACE_VGA_STD_WRITE_IO_DSTATE; |
113 | uint16_t _TRACE_VGA_VBE_READ_DSTATE; |
114 | uint16_t _TRACE_VGA_VBE_WRITE_DSTATE; |
115 | uint16_t _TRACE_VGA_CIRRUS_READ_IO_DSTATE; |
116 | uint16_t _TRACE_VGA_CIRRUS_WRITE_IO_DSTATE; |
117 | uint16_t _TRACE_VGA_CIRRUS_WRITE_BLT_DSTATE; |
118 | uint16_t _TRACE_SII9022_READ_REG_DSTATE; |
119 | uint16_t _TRACE_SII9022_WRITE_REG_DSTATE; |
120 | uint16_t _TRACE_SII9022_SWITCH_MODE_DSTATE; |
121 | uint16_t _TRACE_ATI_MM_READ_DSTATE; |
122 | uint16_t _TRACE_ATI_MM_WRITE_DSTATE; |
123 | TraceEvent _TRACE_JAZZ_LED_READ_EVENT = { |
124 | .id = 0, |
125 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
126 | .name = "jazz_led_read" , |
127 | .sstate = TRACE_JAZZ_LED_READ_ENABLED, |
128 | .dstate = &_TRACE_JAZZ_LED_READ_DSTATE |
129 | }; |
130 | TraceEvent _TRACE_JAZZ_LED_WRITE_EVENT = { |
131 | .id = 0, |
132 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
133 | .name = "jazz_led_write" , |
134 | .sstate = TRACE_JAZZ_LED_WRITE_ENABLED, |
135 | .dstate = &_TRACE_JAZZ_LED_WRITE_DSTATE |
136 | }; |
137 | TraceEvent _TRACE_XENFB_MOUSE_EVENT_EVENT = { |
138 | .id = 0, |
139 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
140 | .name = "xenfb_mouse_event" , |
141 | .sstate = TRACE_XENFB_MOUSE_EVENT_ENABLED, |
142 | .dstate = &_TRACE_XENFB_MOUSE_EVENT_DSTATE |
143 | }; |
144 | TraceEvent _TRACE_XENFB_KEY_EVENT_EVENT = { |
145 | .id = 0, |
146 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
147 | .name = "xenfb_key_event" , |
148 | .sstate = TRACE_XENFB_KEY_EVENT_ENABLED, |
149 | .dstate = &_TRACE_XENFB_KEY_EVENT_DSTATE |
150 | }; |
151 | TraceEvent _TRACE_XENFB_INPUT_CONNECTED_EVENT = { |
152 | .id = 0, |
153 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
154 | .name = "xenfb_input_connected" , |
155 | .sstate = TRACE_XENFB_INPUT_CONNECTED_ENABLED, |
156 | .dstate = &_TRACE_XENFB_INPUT_CONNECTED_DSTATE |
157 | }; |
158 | TraceEvent _TRACE_G364FB_READ_EVENT = { |
159 | .id = 0, |
160 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
161 | .name = "g364fb_read" , |
162 | .sstate = TRACE_G364FB_READ_ENABLED, |
163 | .dstate = &_TRACE_G364FB_READ_DSTATE |
164 | }; |
165 | TraceEvent _TRACE_G364FB_WRITE_EVENT = { |
166 | .id = 0, |
167 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
168 | .name = "g364fb_write" , |
169 | .sstate = TRACE_G364FB_WRITE_ENABLED, |
170 | .dstate = &_TRACE_G364FB_WRITE_DSTATE |
171 | }; |
172 | TraceEvent _TRACE_MILKYMIST_TMU2_MEMORY_READ_EVENT = { |
173 | .id = 0, |
174 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
175 | .name = "milkymist_tmu2_memory_read" , |
176 | .sstate = TRACE_MILKYMIST_TMU2_MEMORY_READ_ENABLED, |
177 | .dstate = &_TRACE_MILKYMIST_TMU2_MEMORY_READ_DSTATE |
178 | }; |
179 | TraceEvent _TRACE_MILKYMIST_TMU2_MEMORY_WRITE_EVENT = { |
180 | .id = 0, |
181 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
182 | .name = "milkymist_tmu2_memory_write" , |
183 | .sstate = TRACE_MILKYMIST_TMU2_MEMORY_WRITE_ENABLED, |
184 | .dstate = &_TRACE_MILKYMIST_TMU2_MEMORY_WRITE_DSTATE |
185 | }; |
186 | TraceEvent _TRACE_MILKYMIST_TMU2_START_EVENT = { |
187 | .id = 0, |
188 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
189 | .name = "milkymist_tmu2_start" , |
190 | .sstate = TRACE_MILKYMIST_TMU2_START_ENABLED, |
191 | .dstate = &_TRACE_MILKYMIST_TMU2_START_DSTATE |
192 | }; |
193 | TraceEvent _TRACE_MILKYMIST_TMU2_PULSE_IRQ_EVENT = { |
194 | .id = 0, |
195 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
196 | .name = "milkymist_tmu2_pulse_irq" , |
197 | .sstate = TRACE_MILKYMIST_TMU2_PULSE_IRQ_ENABLED, |
198 | .dstate = &_TRACE_MILKYMIST_TMU2_PULSE_IRQ_DSTATE |
199 | }; |
200 | TraceEvent _TRACE_MILKYMIST_VGAFB_MEMORY_READ_EVENT = { |
201 | .id = 0, |
202 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
203 | .name = "milkymist_vgafb_memory_read" , |
204 | .sstate = TRACE_MILKYMIST_VGAFB_MEMORY_READ_ENABLED, |
205 | .dstate = &_TRACE_MILKYMIST_VGAFB_MEMORY_READ_DSTATE |
206 | }; |
207 | TraceEvent _TRACE_MILKYMIST_VGAFB_MEMORY_WRITE_EVENT = { |
208 | .id = 0, |
209 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
210 | .name = "milkymist_vgafb_memory_write" , |
211 | .sstate = TRACE_MILKYMIST_VGAFB_MEMORY_WRITE_ENABLED, |
212 | .dstate = &_TRACE_MILKYMIST_VGAFB_MEMORY_WRITE_DSTATE |
213 | }; |
214 | TraceEvent _TRACE_VMWARE_VALUE_READ_EVENT = { |
215 | .id = 0, |
216 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
217 | .name = "vmware_value_read" , |
218 | .sstate = TRACE_VMWARE_VALUE_READ_ENABLED, |
219 | .dstate = &_TRACE_VMWARE_VALUE_READ_DSTATE |
220 | }; |
221 | TraceEvent _TRACE_VMWARE_VALUE_WRITE_EVENT = { |
222 | .id = 0, |
223 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
224 | .name = "vmware_value_write" , |
225 | .sstate = TRACE_VMWARE_VALUE_WRITE_ENABLED, |
226 | .dstate = &_TRACE_VMWARE_VALUE_WRITE_DSTATE |
227 | }; |
228 | TraceEvent _TRACE_VMWARE_PALETTE_READ_EVENT = { |
229 | .id = 0, |
230 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
231 | .name = "vmware_palette_read" , |
232 | .sstate = TRACE_VMWARE_PALETTE_READ_ENABLED, |
233 | .dstate = &_TRACE_VMWARE_PALETTE_READ_DSTATE |
234 | }; |
235 | TraceEvent _TRACE_VMWARE_PALETTE_WRITE_EVENT = { |
236 | .id = 0, |
237 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
238 | .name = "vmware_palette_write" , |
239 | .sstate = TRACE_VMWARE_PALETTE_WRITE_ENABLED, |
240 | .dstate = &_TRACE_VMWARE_PALETTE_WRITE_DSTATE |
241 | }; |
242 | TraceEvent _TRACE_VMWARE_SCRATCH_READ_EVENT = { |
243 | .id = 0, |
244 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
245 | .name = "vmware_scratch_read" , |
246 | .sstate = TRACE_VMWARE_SCRATCH_READ_ENABLED, |
247 | .dstate = &_TRACE_VMWARE_SCRATCH_READ_DSTATE |
248 | }; |
249 | TraceEvent _TRACE_VMWARE_SCRATCH_WRITE_EVENT = { |
250 | .id = 0, |
251 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
252 | .name = "vmware_scratch_write" , |
253 | .sstate = TRACE_VMWARE_SCRATCH_WRITE_ENABLED, |
254 | .dstate = &_TRACE_VMWARE_SCRATCH_WRITE_DSTATE |
255 | }; |
256 | TraceEvent _TRACE_VMWARE_SETMODE_EVENT = { |
257 | .id = 0, |
258 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
259 | .name = "vmware_setmode" , |
260 | .sstate = TRACE_VMWARE_SETMODE_ENABLED, |
261 | .dstate = &_TRACE_VMWARE_SETMODE_DSTATE |
262 | }; |
263 | TraceEvent _TRACE_VIRTIO_GPU_FEATURES_EVENT = { |
264 | .id = 0, |
265 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
266 | .name = "virtio_gpu_features" , |
267 | .sstate = TRACE_VIRTIO_GPU_FEATURES_ENABLED, |
268 | .dstate = &_TRACE_VIRTIO_GPU_FEATURES_DSTATE |
269 | }; |
270 | TraceEvent _TRACE_VIRTIO_GPU_CMD_GET_DISPLAY_INFO_EVENT = { |
271 | .id = 0, |
272 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
273 | .name = "virtio_gpu_cmd_get_display_info" , |
274 | .sstate = TRACE_VIRTIO_GPU_CMD_GET_DISPLAY_INFO_ENABLED, |
275 | .dstate = &_TRACE_VIRTIO_GPU_CMD_GET_DISPLAY_INFO_DSTATE |
276 | }; |
277 | TraceEvent _TRACE_VIRTIO_GPU_CMD_GET_EDID_EVENT = { |
278 | .id = 0, |
279 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
280 | .name = "virtio_gpu_cmd_get_edid" , |
281 | .sstate = TRACE_VIRTIO_GPU_CMD_GET_EDID_ENABLED, |
282 | .dstate = &_TRACE_VIRTIO_GPU_CMD_GET_EDID_DSTATE |
283 | }; |
284 | TraceEvent _TRACE_VIRTIO_GPU_CMD_SET_SCANOUT_EVENT = { |
285 | .id = 0, |
286 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
287 | .name = "virtio_gpu_cmd_set_scanout" , |
288 | .sstate = TRACE_VIRTIO_GPU_CMD_SET_SCANOUT_ENABLED, |
289 | .dstate = &_TRACE_VIRTIO_GPU_CMD_SET_SCANOUT_DSTATE |
290 | }; |
291 | TraceEvent _TRACE_VIRTIO_GPU_CMD_RES_CREATE_2D_EVENT = { |
292 | .id = 0, |
293 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
294 | .name = "virtio_gpu_cmd_res_create_2d" , |
295 | .sstate = TRACE_VIRTIO_GPU_CMD_RES_CREATE_2D_ENABLED, |
296 | .dstate = &_TRACE_VIRTIO_GPU_CMD_RES_CREATE_2D_DSTATE |
297 | }; |
298 | TraceEvent _TRACE_VIRTIO_GPU_CMD_RES_CREATE_3D_EVENT = { |
299 | .id = 0, |
300 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
301 | .name = "virtio_gpu_cmd_res_create_3d" , |
302 | .sstate = TRACE_VIRTIO_GPU_CMD_RES_CREATE_3D_ENABLED, |
303 | .dstate = &_TRACE_VIRTIO_GPU_CMD_RES_CREATE_3D_DSTATE |
304 | }; |
305 | TraceEvent _TRACE_VIRTIO_GPU_CMD_RES_UNREF_EVENT = { |
306 | .id = 0, |
307 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
308 | .name = "virtio_gpu_cmd_res_unref" , |
309 | .sstate = TRACE_VIRTIO_GPU_CMD_RES_UNREF_ENABLED, |
310 | .dstate = &_TRACE_VIRTIO_GPU_CMD_RES_UNREF_DSTATE |
311 | }; |
312 | TraceEvent _TRACE_VIRTIO_GPU_CMD_RES_BACK_ATTACH_EVENT = { |
313 | .id = 0, |
314 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
315 | .name = "virtio_gpu_cmd_res_back_attach" , |
316 | .sstate = TRACE_VIRTIO_GPU_CMD_RES_BACK_ATTACH_ENABLED, |
317 | .dstate = &_TRACE_VIRTIO_GPU_CMD_RES_BACK_ATTACH_DSTATE |
318 | }; |
319 | TraceEvent _TRACE_VIRTIO_GPU_CMD_RES_BACK_DETACH_EVENT = { |
320 | .id = 0, |
321 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
322 | .name = "virtio_gpu_cmd_res_back_detach" , |
323 | .sstate = TRACE_VIRTIO_GPU_CMD_RES_BACK_DETACH_ENABLED, |
324 | .dstate = &_TRACE_VIRTIO_GPU_CMD_RES_BACK_DETACH_DSTATE |
325 | }; |
326 | TraceEvent _TRACE_VIRTIO_GPU_CMD_RES_XFER_TOH_2D_EVENT = { |
327 | .id = 0, |
328 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
329 | .name = "virtio_gpu_cmd_res_xfer_toh_2d" , |
330 | .sstate = TRACE_VIRTIO_GPU_CMD_RES_XFER_TOH_2D_ENABLED, |
331 | .dstate = &_TRACE_VIRTIO_GPU_CMD_RES_XFER_TOH_2D_DSTATE |
332 | }; |
333 | TraceEvent _TRACE_VIRTIO_GPU_CMD_RES_XFER_TOH_3D_EVENT = { |
334 | .id = 0, |
335 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
336 | .name = "virtio_gpu_cmd_res_xfer_toh_3d" , |
337 | .sstate = TRACE_VIRTIO_GPU_CMD_RES_XFER_TOH_3D_ENABLED, |
338 | .dstate = &_TRACE_VIRTIO_GPU_CMD_RES_XFER_TOH_3D_DSTATE |
339 | }; |
340 | TraceEvent _TRACE_VIRTIO_GPU_CMD_RES_XFER_FROMH_3D_EVENT = { |
341 | .id = 0, |
342 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
343 | .name = "virtio_gpu_cmd_res_xfer_fromh_3d" , |
344 | .sstate = TRACE_VIRTIO_GPU_CMD_RES_XFER_FROMH_3D_ENABLED, |
345 | .dstate = &_TRACE_VIRTIO_GPU_CMD_RES_XFER_FROMH_3D_DSTATE |
346 | }; |
347 | TraceEvent _TRACE_VIRTIO_GPU_CMD_RES_FLUSH_EVENT = { |
348 | .id = 0, |
349 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
350 | .name = "virtio_gpu_cmd_res_flush" , |
351 | .sstate = TRACE_VIRTIO_GPU_CMD_RES_FLUSH_ENABLED, |
352 | .dstate = &_TRACE_VIRTIO_GPU_CMD_RES_FLUSH_DSTATE |
353 | }; |
354 | TraceEvent _TRACE_VIRTIO_GPU_CMD_CTX_CREATE_EVENT = { |
355 | .id = 0, |
356 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
357 | .name = "virtio_gpu_cmd_ctx_create" , |
358 | .sstate = TRACE_VIRTIO_GPU_CMD_CTX_CREATE_ENABLED, |
359 | .dstate = &_TRACE_VIRTIO_GPU_CMD_CTX_CREATE_DSTATE |
360 | }; |
361 | TraceEvent _TRACE_VIRTIO_GPU_CMD_CTX_DESTROY_EVENT = { |
362 | .id = 0, |
363 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
364 | .name = "virtio_gpu_cmd_ctx_destroy" , |
365 | .sstate = TRACE_VIRTIO_GPU_CMD_CTX_DESTROY_ENABLED, |
366 | .dstate = &_TRACE_VIRTIO_GPU_CMD_CTX_DESTROY_DSTATE |
367 | }; |
368 | TraceEvent _TRACE_VIRTIO_GPU_CMD_CTX_RES_ATTACH_EVENT = { |
369 | .id = 0, |
370 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
371 | .name = "virtio_gpu_cmd_ctx_res_attach" , |
372 | .sstate = TRACE_VIRTIO_GPU_CMD_CTX_RES_ATTACH_ENABLED, |
373 | .dstate = &_TRACE_VIRTIO_GPU_CMD_CTX_RES_ATTACH_DSTATE |
374 | }; |
375 | TraceEvent _TRACE_VIRTIO_GPU_CMD_CTX_RES_DETACH_EVENT = { |
376 | .id = 0, |
377 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
378 | .name = "virtio_gpu_cmd_ctx_res_detach" , |
379 | .sstate = TRACE_VIRTIO_GPU_CMD_CTX_RES_DETACH_ENABLED, |
380 | .dstate = &_TRACE_VIRTIO_GPU_CMD_CTX_RES_DETACH_DSTATE |
381 | }; |
382 | TraceEvent _TRACE_VIRTIO_GPU_CMD_CTX_SUBMIT_EVENT = { |
383 | .id = 0, |
384 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
385 | .name = "virtio_gpu_cmd_ctx_submit" , |
386 | .sstate = TRACE_VIRTIO_GPU_CMD_CTX_SUBMIT_ENABLED, |
387 | .dstate = &_TRACE_VIRTIO_GPU_CMD_CTX_SUBMIT_DSTATE |
388 | }; |
389 | TraceEvent _TRACE_VIRTIO_GPU_UPDATE_CURSOR_EVENT = { |
390 | .id = 0, |
391 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
392 | .name = "virtio_gpu_update_cursor" , |
393 | .sstate = TRACE_VIRTIO_GPU_UPDATE_CURSOR_ENABLED, |
394 | .dstate = &_TRACE_VIRTIO_GPU_UPDATE_CURSOR_DSTATE |
395 | }; |
396 | TraceEvent _TRACE_VIRTIO_GPU_FENCE_CTRL_EVENT = { |
397 | .id = 0, |
398 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
399 | .name = "virtio_gpu_fence_ctrl" , |
400 | .sstate = TRACE_VIRTIO_GPU_FENCE_CTRL_ENABLED, |
401 | .dstate = &_TRACE_VIRTIO_GPU_FENCE_CTRL_DSTATE |
402 | }; |
403 | TraceEvent _TRACE_VIRTIO_GPU_FENCE_RESP_EVENT = { |
404 | .id = 0, |
405 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
406 | .name = "virtio_gpu_fence_resp" , |
407 | .sstate = TRACE_VIRTIO_GPU_FENCE_RESP_ENABLED, |
408 | .dstate = &_TRACE_VIRTIO_GPU_FENCE_RESP_DSTATE |
409 | }; |
410 | TraceEvent _TRACE_QXL_INTERFACE_SET_MM_TIME_EVENT = { |
411 | .id = 0, |
412 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
413 | .name = "qxl_interface_set_mm_time" , |
414 | .sstate = TRACE_QXL_INTERFACE_SET_MM_TIME_ENABLED, |
415 | .dstate = &_TRACE_QXL_INTERFACE_SET_MM_TIME_DSTATE |
416 | }; |
417 | TraceEvent _TRACE_QXL_IO_WRITE_VGA_EVENT = { |
418 | .id = 0, |
419 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
420 | .name = "qxl_io_write_vga" , |
421 | .sstate = TRACE_QXL_IO_WRITE_VGA_ENABLED, |
422 | .dstate = &_TRACE_QXL_IO_WRITE_VGA_DSTATE |
423 | }; |
424 | TraceEvent _TRACE_QXL_CREATE_GUEST_PRIMARY_EVENT = { |
425 | .id = 0, |
426 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
427 | .name = "qxl_create_guest_primary" , |
428 | .sstate = TRACE_QXL_CREATE_GUEST_PRIMARY_ENABLED, |
429 | .dstate = &_TRACE_QXL_CREATE_GUEST_PRIMARY_DSTATE |
430 | }; |
431 | TraceEvent _TRACE_QXL_CREATE_GUEST_PRIMARY_REST_EVENT = { |
432 | .id = 0, |
433 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
434 | .name = "qxl_create_guest_primary_rest" , |
435 | .sstate = TRACE_QXL_CREATE_GUEST_PRIMARY_REST_ENABLED, |
436 | .dstate = &_TRACE_QXL_CREATE_GUEST_PRIMARY_REST_DSTATE |
437 | }; |
438 | TraceEvent _TRACE_QXL_DESTROY_PRIMARY_EVENT = { |
439 | .id = 0, |
440 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
441 | .name = "qxl_destroy_primary" , |
442 | .sstate = TRACE_QXL_DESTROY_PRIMARY_ENABLED, |
443 | .dstate = &_TRACE_QXL_DESTROY_PRIMARY_DSTATE |
444 | }; |
445 | TraceEvent _TRACE_QXL_ENTER_VGA_MODE_EVENT = { |
446 | .id = 0, |
447 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
448 | .name = "qxl_enter_vga_mode" , |
449 | .sstate = TRACE_QXL_ENTER_VGA_MODE_ENABLED, |
450 | .dstate = &_TRACE_QXL_ENTER_VGA_MODE_DSTATE |
451 | }; |
452 | TraceEvent _TRACE_QXL_EXIT_VGA_MODE_EVENT = { |
453 | .id = 0, |
454 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
455 | .name = "qxl_exit_vga_mode" , |
456 | .sstate = TRACE_QXL_EXIT_VGA_MODE_ENABLED, |
457 | .dstate = &_TRACE_QXL_EXIT_VGA_MODE_DSTATE |
458 | }; |
459 | TraceEvent _TRACE_QXL_HARD_RESET_EVENT = { |
460 | .id = 0, |
461 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
462 | .name = "qxl_hard_reset" , |
463 | .sstate = TRACE_QXL_HARD_RESET_ENABLED, |
464 | .dstate = &_TRACE_QXL_HARD_RESET_DSTATE |
465 | }; |
466 | TraceEvent _TRACE_QXL_INTERFACE_ASYNC_COMPLETE_IO_EVENT = { |
467 | .id = 0, |
468 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
469 | .name = "qxl_interface_async_complete_io" , |
470 | .sstate = TRACE_QXL_INTERFACE_ASYNC_COMPLETE_IO_ENABLED, |
471 | .dstate = &_TRACE_QXL_INTERFACE_ASYNC_COMPLETE_IO_DSTATE |
472 | }; |
473 | TraceEvent _TRACE_QXL_INTERFACE_ATTACH_WORKER_EVENT = { |
474 | .id = 0, |
475 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
476 | .name = "qxl_interface_attach_worker" , |
477 | .sstate = TRACE_QXL_INTERFACE_ATTACH_WORKER_ENABLED, |
478 | .dstate = &_TRACE_QXL_INTERFACE_ATTACH_WORKER_DSTATE |
479 | }; |
480 | TraceEvent _TRACE_QXL_INTERFACE_GET_INIT_INFO_EVENT = { |
481 | .id = 0, |
482 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
483 | .name = "qxl_interface_get_init_info" , |
484 | .sstate = TRACE_QXL_INTERFACE_GET_INIT_INFO_ENABLED, |
485 | .dstate = &_TRACE_QXL_INTERFACE_GET_INIT_INFO_DSTATE |
486 | }; |
487 | TraceEvent _TRACE_QXL_INTERFACE_SET_COMPRESSION_LEVEL_EVENT = { |
488 | .id = 0, |
489 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
490 | .name = "qxl_interface_set_compression_level" , |
491 | .sstate = TRACE_QXL_INTERFACE_SET_COMPRESSION_LEVEL_ENABLED, |
492 | .dstate = &_TRACE_QXL_INTERFACE_SET_COMPRESSION_LEVEL_DSTATE |
493 | }; |
494 | TraceEvent _TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_EVENT = { |
495 | .id = 0, |
496 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
497 | .name = "qxl_interface_update_area_complete" , |
498 | .sstate = TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_ENABLED, |
499 | .dstate = &_TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_DSTATE |
500 | }; |
501 | TraceEvent _TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_REST_EVENT = { |
502 | .id = 0, |
503 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
504 | .name = "qxl_interface_update_area_complete_rest" , |
505 | .sstate = TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_REST_ENABLED, |
506 | .dstate = &_TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_REST_DSTATE |
507 | }; |
508 | TraceEvent _TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_OVERFLOW_EVENT = { |
509 | .id = 0, |
510 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
511 | .name = "qxl_interface_update_area_complete_overflow" , |
512 | .sstate = TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_OVERFLOW_ENABLED, |
513 | .dstate = &_TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_OVERFLOW_DSTATE |
514 | }; |
515 | TraceEvent _TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_SCHEDULE_BH_EVENT = { |
516 | .id = 0, |
517 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
518 | .name = "qxl_interface_update_area_complete_schedule_bh" , |
519 | .sstate = TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_SCHEDULE_BH_ENABLED, |
520 | .dstate = &_TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_SCHEDULE_BH_DSTATE |
521 | }; |
522 | TraceEvent _TRACE_QXL_IO_DESTROY_PRIMARY_IGNORED_EVENT = { |
523 | .id = 0, |
524 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
525 | .name = "qxl_io_destroy_primary_ignored" , |
526 | .sstate = TRACE_QXL_IO_DESTROY_PRIMARY_IGNORED_ENABLED, |
527 | .dstate = &_TRACE_QXL_IO_DESTROY_PRIMARY_IGNORED_DSTATE |
528 | }; |
529 | TraceEvent _TRACE_QXL_IO_LOG_EVENT = { |
530 | .id = 0, |
531 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
532 | .name = "qxl_io_log" , |
533 | .sstate = TRACE_QXL_IO_LOG_ENABLED, |
534 | .dstate = &_TRACE_QXL_IO_LOG_DSTATE |
535 | }; |
536 | TraceEvent _TRACE_QXL_IO_READ_UNEXPECTED_EVENT = { |
537 | .id = 0, |
538 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
539 | .name = "qxl_io_read_unexpected" , |
540 | .sstate = TRACE_QXL_IO_READ_UNEXPECTED_ENABLED, |
541 | .dstate = &_TRACE_QXL_IO_READ_UNEXPECTED_DSTATE |
542 | }; |
543 | TraceEvent _TRACE_QXL_IO_UNEXPECTED_VGA_MODE_EVENT = { |
544 | .id = 0, |
545 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
546 | .name = "qxl_io_unexpected_vga_mode" , |
547 | .sstate = TRACE_QXL_IO_UNEXPECTED_VGA_MODE_ENABLED, |
548 | .dstate = &_TRACE_QXL_IO_UNEXPECTED_VGA_MODE_DSTATE |
549 | }; |
550 | TraceEvent _TRACE_QXL_IO_WRITE_EVENT = { |
551 | .id = 0, |
552 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
553 | .name = "qxl_io_write" , |
554 | .sstate = TRACE_QXL_IO_WRITE_ENABLED, |
555 | .dstate = &_TRACE_QXL_IO_WRITE_DSTATE |
556 | }; |
557 | TraceEvent _TRACE_QXL_MEMSLOT_ADD_GUEST_EVENT = { |
558 | .id = 0, |
559 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
560 | .name = "qxl_memslot_add_guest" , |
561 | .sstate = TRACE_QXL_MEMSLOT_ADD_GUEST_ENABLED, |
562 | .dstate = &_TRACE_QXL_MEMSLOT_ADD_GUEST_DSTATE |
563 | }; |
564 | TraceEvent _TRACE_QXL_POST_LOAD_EVENT = { |
565 | .id = 0, |
566 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
567 | .name = "qxl_post_load" , |
568 | .sstate = TRACE_QXL_POST_LOAD_ENABLED, |
569 | .dstate = &_TRACE_QXL_POST_LOAD_DSTATE |
570 | }; |
571 | TraceEvent _TRACE_QXL_PRE_LOAD_EVENT = { |
572 | .id = 0, |
573 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
574 | .name = "qxl_pre_load" , |
575 | .sstate = TRACE_QXL_PRE_LOAD_ENABLED, |
576 | .dstate = &_TRACE_QXL_PRE_LOAD_DSTATE |
577 | }; |
578 | TraceEvent _TRACE_QXL_PRE_SAVE_EVENT = { |
579 | .id = 0, |
580 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
581 | .name = "qxl_pre_save" , |
582 | .sstate = TRACE_QXL_PRE_SAVE_ENABLED, |
583 | .dstate = &_TRACE_QXL_PRE_SAVE_DSTATE |
584 | }; |
585 | TraceEvent _TRACE_QXL_RESET_SURFACES_EVENT = { |
586 | .id = 0, |
587 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
588 | .name = "qxl_reset_surfaces" , |
589 | .sstate = TRACE_QXL_RESET_SURFACES_ENABLED, |
590 | .dstate = &_TRACE_QXL_RESET_SURFACES_DSTATE |
591 | }; |
592 | TraceEvent _TRACE_QXL_RING_COMMAND_CHECK_EVENT = { |
593 | .id = 0, |
594 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
595 | .name = "qxl_ring_command_check" , |
596 | .sstate = TRACE_QXL_RING_COMMAND_CHECK_ENABLED, |
597 | .dstate = &_TRACE_QXL_RING_COMMAND_CHECK_DSTATE |
598 | }; |
599 | TraceEvent _TRACE_QXL_RING_COMMAND_GET_EVENT = { |
600 | .id = 0, |
601 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
602 | .name = "qxl_ring_command_get" , |
603 | .sstate = TRACE_QXL_RING_COMMAND_GET_ENABLED, |
604 | .dstate = &_TRACE_QXL_RING_COMMAND_GET_DSTATE |
605 | }; |
606 | TraceEvent _TRACE_QXL_RING_COMMAND_REQ_NOTIFICATION_EVENT = { |
607 | .id = 0, |
608 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
609 | .name = "qxl_ring_command_req_notification" , |
610 | .sstate = TRACE_QXL_RING_COMMAND_REQ_NOTIFICATION_ENABLED, |
611 | .dstate = &_TRACE_QXL_RING_COMMAND_REQ_NOTIFICATION_DSTATE |
612 | }; |
613 | TraceEvent _TRACE_QXL_RING_CURSOR_CHECK_EVENT = { |
614 | .id = 0, |
615 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
616 | .name = "qxl_ring_cursor_check" , |
617 | .sstate = TRACE_QXL_RING_CURSOR_CHECK_ENABLED, |
618 | .dstate = &_TRACE_QXL_RING_CURSOR_CHECK_DSTATE |
619 | }; |
620 | TraceEvent _TRACE_QXL_RING_CURSOR_GET_EVENT = { |
621 | .id = 0, |
622 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
623 | .name = "qxl_ring_cursor_get" , |
624 | .sstate = TRACE_QXL_RING_CURSOR_GET_ENABLED, |
625 | .dstate = &_TRACE_QXL_RING_CURSOR_GET_DSTATE |
626 | }; |
627 | TraceEvent _TRACE_QXL_RING_CURSOR_REQ_NOTIFICATION_EVENT = { |
628 | .id = 0, |
629 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
630 | .name = "qxl_ring_cursor_req_notification" , |
631 | .sstate = TRACE_QXL_RING_CURSOR_REQ_NOTIFICATION_ENABLED, |
632 | .dstate = &_TRACE_QXL_RING_CURSOR_REQ_NOTIFICATION_DSTATE |
633 | }; |
634 | TraceEvent _TRACE_QXL_RING_RES_PUSH_EVENT = { |
635 | .id = 0, |
636 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
637 | .name = "qxl_ring_res_push" , |
638 | .sstate = TRACE_QXL_RING_RES_PUSH_ENABLED, |
639 | .dstate = &_TRACE_QXL_RING_RES_PUSH_DSTATE |
640 | }; |
641 | TraceEvent _TRACE_QXL_RING_RES_PUSH_REST_EVENT = { |
642 | .id = 0, |
643 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
644 | .name = "qxl_ring_res_push_rest" , |
645 | .sstate = TRACE_QXL_RING_RES_PUSH_REST_ENABLED, |
646 | .dstate = &_TRACE_QXL_RING_RES_PUSH_REST_DSTATE |
647 | }; |
648 | TraceEvent _TRACE_QXL_RING_RES_PUT_EVENT = { |
649 | .id = 0, |
650 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
651 | .name = "qxl_ring_res_put" , |
652 | .sstate = TRACE_QXL_RING_RES_PUT_ENABLED, |
653 | .dstate = &_TRACE_QXL_RING_RES_PUT_DSTATE |
654 | }; |
655 | TraceEvent _TRACE_QXL_SET_MODE_EVENT = { |
656 | .id = 0, |
657 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
658 | .name = "qxl_set_mode" , |
659 | .sstate = TRACE_QXL_SET_MODE_ENABLED, |
660 | .dstate = &_TRACE_QXL_SET_MODE_DSTATE |
661 | }; |
662 | TraceEvent _TRACE_QXL_SOFT_RESET_EVENT = { |
663 | .id = 0, |
664 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
665 | .name = "qxl_soft_reset" , |
666 | .sstate = TRACE_QXL_SOFT_RESET_ENABLED, |
667 | .dstate = &_TRACE_QXL_SOFT_RESET_DSTATE |
668 | }; |
669 | TraceEvent _TRACE_QXL_SPICE_DESTROY_SURFACES_COMPLETE_EVENT = { |
670 | .id = 0, |
671 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
672 | .name = "qxl_spice_destroy_surfaces_complete" , |
673 | .sstate = TRACE_QXL_SPICE_DESTROY_SURFACES_COMPLETE_ENABLED, |
674 | .dstate = &_TRACE_QXL_SPICE_DESTROY_SURFACES_COMPLETE_DSTATE |
675 | }; |
676 | TraceEvent _TRACE_QXL_SPICE_DESTROY_SURFACES_EVENT = { |
677 | .id = 0, |
678 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
679 | .name = "qxl_spice_destroy_surfaces" , |
680 | .sstate = TRACE_QXL_SPICE_DESTROY_SURFACES_ENABLED, |
681 | .dstate = &_TRACE_QXL_SPICE_DESTROY_SURFACES_DSTATE |
682 | }; |
683 | TraceEvent _TRACE_QXL_SPICE_DESTROY_SURFACE_WAIT_COMPLETE_EVENT = { |
684 | .id = 0, |
685 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
686 | .name = "qxl_spice_destroy_surface_wait_complete" , |
687 | .sstate = TRACE_QXL_SPICE_DESTROY_SURFACE_WAIT_COMPLETE_ENABLED, |
688 | .dstate = &_TRACE_QXL_SPICE_DESTROY_SURFACE_WAIT_COMPLETE_DSTATE |
689 | }; |
690 | TraceEvent _TRACE_QXL_SPICE_DESTROY_SURFACE_WAIT_EVENT = { |
691 | .id = 0, |
692 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
693 | .name = "qxl_spice_destroy_surface_wait" , |
694 | .sstate = TRACE_QXL_SPICE_DESTROY_SURFACE_WAIT_ENABLED, |
695 | .dstate = &_TRACE_QXL_SPICE_DESTROY_SURFACE_WAIT_DSTATE |
696 | }; |
697 | TraceEvent _TRACE_QXL_SPICE_FLUSH_SURFACES_ASYNC_EVENT = { |
698 | .id = 0, |
699 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
700 | .name = "qxl_spice_flush_surfaces_async" , |
701 | .sstate = TRACE_QXL_SPICE_FLUSH_SURFACES_ASYNC_ENABLED, |
702 | .dstate = &_TRACE_QXL_SPICE_FLUSH_SURFACES_ASYNC_DSTATE |
703 | }; |
704 | TraceEvent _TRACE_QXL_SPICE_MONITORS_CONFIG_EVENT = { |
705 | .id = 0, |
706 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
707 | .name = "qxl_spice_monitors_config" , |
708 | .sstate = TRACE_QXL_SPICE_MONITORS_CONFIG_ENABLED, |
709 | .dstate = &_TRACE_QXL_SPICE_MONITORS_CONFIG_DSTATE |
710 | }; |
711 | TraceEvent _TRACE_QXL_SPICE_LOADVM_COMMANDS_EVENT = { |
712 | .id = 0, |
713 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
714 | .name = "qxl_spice_loadvm_commands" , |
715 | .sstate = TRACE_QXL_SPICE_LOADVM_COMMANDS_ENABLED, |
716 | .dstate = &_TRACE_QXL_SPICE_LOADVM_COMMANDS_DSTATE |
717 | }; |
718 | TraceEvent _TRACE_QXL_SPICE_OOM_EVENT = { |
719 | .id = 0, |
720 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
721 | .name = "qxl_spice_oom" , |
722 | .sstate = TRACE_QXL_SPICE_OOM_ENABLED, |
723 | .dstate = &_TRACE_QXL_SPICE_OOM_DSTATE |
724 | }; |
725 | TraceEvent _TRACE_QXL_SPICE_RESET_CURSOR_EVENT = { |
726 | .id = 0, |
727 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
728 | .name = "qxl_spice_reset_cursor" , |
729 | .sstate = TRACE_QXL_SPICE_RESET_CURSOR_ENABLED, |
730 | .dstate = &_TRACE_QXL_SPICE_RESET_CURSOR_DSTATE |
731 | }; |
732 | TraceEvent _TRACE_QXL_SPICE_RESET_IMAGE_CACHE_EVENT = { |
733 | .id = 0, |
734 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
735 | .name = "qxl_spice_reset_image_cache" , |
736 | .sstate = TRACE_QXL_SPICE_RESET_IMAGE_CACHE_ENABLED, |
737 | .dstate = &_TRACE_QXL_SPICE_RESET_IMAGE_CACHE_DSTATE |
738 | }; |
739 | TraceEvent _TRACE_QXL_SPICE_RESET_MEMSLOTS_EVENT = { |
740 | .id = 0, |
741 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
742 | .name = "qxl_spice_reset_memslots" , |
743 | .sstate = TRACE_QXL_SPICE_RESET_MEMSLOTS_ENABLED, |
744 | .dstate = &_TRACE_QXL_SPICE_RESET_MEMSLOTS_DSTATE |
745 | }; |
746 | TraceEvent _TRACE_QXL_SPICE_UPDATE_AREA_EVENT = { |
747 | .id = 0, |
748 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
749 | .name = "qxl_spice_update_area" , |
750 | .sstate = TRACE_QXL_SPICE_UPDATE_AREA_ENABLED, |
751 | .dstate = &_TRACE_QXL_SPICE_UPDATE_AREA_DSTATE |
752 | }; |
753 | TraceEvent _TRACE_QXL_SPICE_UPDATE_AREA_REST_EVENT = { |
754 | .id = 0, |
755 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
756 | .name = "qxl_spice_update_area_rest" , |
757 | .sstate = TRACE_QXL_SPICE_UPDATE_AREA_REST_ENABLED, |
758 | .dstate = &_TRACE_QXL_SPICE_UPDATE_AREA_REST_DSTATE |
759 | }; |
760 | TraceEvent _TRACE_QXL_SURFACES_DIRTY_EVENT = { |
761 | .id = 0, |
762 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
763 | .name = "qxl_surfaces_dirty" , |
764 | .sstate = TRACE_QXL_SURFACES_DIRTY_ENABLED, |
765 | .dstate = &_TRACE_QXL_SURFACES_DIRTY_DSTATE |
766 | }; |
767 | TraceEvent _TRACE_QXL_SEND_EVENTS_EVENT = { |
768 | .id = 0, |
769 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
770 | .name = "qxl_send_events" , |
771 | .sstate = TRACE_QXL_SEND_EVENTS_ENABLED, |
772 | .dstate = &_TRACE_QXL_SEND_EVENTS_DSTATE |
773 | }; |
774 | TraceEvent _TRACE_QXL_SEND_EVENTS_VM_STOPPED_EVENT = { |
775 | .id = 0, |
776 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
777 | .name = "qxl_send_events_vm_stopped" , |
778 | .sstate = TRACE_QXL_SEND_EVENTS_VM_STOPPED_ENABLED, |
779 | .dstate = &_TRACE_QXL_SEND_EVENTS_VM_STOPPED_DSTATE |
780 | }; |
781 | TraceEvent _TRACE_QXL_SET_GUEST_BUG_EVENT = { |
782 | .id = 0, |
783 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
784 | .name = "qxl_set_guest_bug" , |
785 | .sstate = TRACE_QXL_SET_GUEST_BUG_ENABLED, |
786 | .dstate = &_TRACE_QXL_SET_GUEST_BUG_DSTATE |
787 | }; |
788 | TraceEvent _TRACE_QXL_INTERRUPT_CLIENT_MONITORS_CONFIG_EVENT = { |
789 | .id = 0, |
790 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
791 | .name = "qxl_interrupt_client_monitors_config" , |
792 | .sstate = TRACE_QXL_INTERRUPT_CLIENT_MONITORS_CONFIG_ENABLED, |
793 | .dstate = &_TRACE_QXL_INTERRUPT_CLIENT_MONITORS_CONFIG_DSTATE |
794 | }; |
795 | TraceEvent _TRACE_QXL_CLIENT_MONITORS_CONFIG_UNSUPPORTED_BY_GUEST_EVENT = { |
796 | .id = 0, |
797 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
798 | .name = "qxl_client_monitors_config_unsupported_by_guest" , |
799 | .sstate = TRACE_QXL_CLIENT_MONITORS_CONFIG_UNSUPPORTED_BY_GUEST_ENABLED, |
800 | .dstate = &_TRACE_QXL_CLIENT_MONITORS_CONFIG_UNSUPPORTED_BY_GUEST_DSTATE |
801 | }; |
802 | TraceEvent _TRACE_QXL_CLIENT_MONITORS_CONFIG_UNSUPPORTED_BY_DEVICE_EVENT = { |
803 | .id = 0, |
804 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
805 | .name = "qxl_client_monitors_config_unsupported_by_device" , |
806 | .sstate = TRACE_QXL_CLIENT_MONITORS_CONFIG_UNSUPPORTED_BY_DEVICE_ENABLED, |
807 | .dstate = &_TRACE_QXL_CLIENT_MONITORS_CONFIG_UNSUPPORTED_BY_DEVICE_DSTATE |
808 | }; |
809 | TraceEvent _TRACE_QXL_CLIENT_MONITORS_CONFIG_CAPPED_EVENT = { |
810 | .id = 0, |
811 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
812 | .name = "qxl_client_monitors_config_capped" , |
813 | .sstate = TRACE_QXL_CLIENT_MONITORS_CONFIG_CAPPED_ENABLED, |
814 | .dstate = &_TRACE_QXL_CLIENT_MONITORS_CONFIG_CAPPED_DSTATE |
815 | }; |
816 | TraceEvent _TRACE_QXL_CLIENT_MONITORS_CONFIG_CRC_EVENT = { |
817 | .id = 0, |
818 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
819 | .name = "qxl_client_monitors_config_crc" , |
820 | .sstate = TRACE_QXL_CLIENT_MONITORS_CONFIG_CRC_ENABLED, |
821 | .dstate = &_TRACE_QXL_CLIENT_MONITORS_CONFIG_CRC_DSTATE |
822 | }; |
823 | TraceEvent _TRACE_QXL_SET_CLIENT_CAPABILITIES_UNSUPPORTED_BY_REVISION_EVENT = { |
824 | .id = 0, |
825 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
826 | .name = "qxl_set_client_capabilities_unsupported_by_revision" , |
827 | .sstate = TRACE_QXL_SET_CLIENT_CAPABILITIES_UNSUPPORTED_BY_REVISION_ENABLED, |
828 | .dstate = &_TRACE_QXL_SET_CLIENT_CAPABILITIES_UNSUPPORTED_BY_REVISION_DSTATE |
829 | }; |
830 | TraceEvent _TRACE_QXL_RENDER_BLIT_EVENT = { |
831 | .id = 0, |
832 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
833 | .name = "qxl_render_blit" , |
834 | .sstate = TRACE_QXL_RENDER_BLIT_ENABLED, |
835 | .dstate = &_TRACE_QXL_RENDER_BLIT_DSTATE |
836 | }; |
837 | TraceEvent _TRACE_QXL_RENDER_GUEST_PRIMARY_RESIZED_EVENT = { |
838 | .id = 0, |
839 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
840 | .name = "qxl_render_guest_primary_resized" , |
841 | .sstate = TRACE_QXL_RENDER_GUEST_PRIMARY_RESIZED_ENABLED, |
842 | .dstate = &_TRACE_QXL_RENDER_GUEST_PRIMARY_RESIZED_DSTATE |
843 | }; |
844 | TraceEvent _TRACE_QXL_RENDER_UPDATE_AREA_DONE_EVENT = { |
845 | .id = 0, |
846 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
847 | .name = "qxl_render_update_area_done" , |
848 | .sstate = TRACE_QXL_RENDER_UPDATE_AREA_DONE_ENABLED, |
849 | .dstate = &_TRACE_QXL_RENDER_UPDATE_AREA_DONE_DSTATE |
850 | }; |
851 | TraceEvent _TRACE_VGA_STD_READ_IO_EVENT = { |
852 | .id = 0, |
853 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
854 | .name = "vga_std_read_io" , |
855 | .sstate = TRACE_VGA_STD_READ_IO_ENABLED, |
856 | .dstate = &_TRACE_VGA_STD_READ_IO_DSTATE |
857 | }; |
858 | TraceEvent _TRACE_VGA_STD_WRITE_IO_EVENT = { |
859 | .id = 0, |
860 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
861 | .name = "vga_std_write_io" , |
862 | .sstate = TRACE_VGA_STD_WRITE_IO_ENABLED, |
863 | .dstate = &_TRACE_VGA_STD_WRITE_IO_DSTATE |
864 | }; |
865 | TraceEvent _TRACE_VGA_VBE_READ_EVENT = { |
866 | .id = 0, |
867 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
868 | .name = "vga_vbe_read" , |
869 | .sstate = TRACE_VGA_VBE_READ_ENABLED, |
870 | .dstate = &_TRACE_VGA_VBE_READ_DSTATE |
871 | }; |
872 | TraceEvent _TRACE_VGA_VBE_WRITE_EVENT = { |
873 | .id = 0, |
874 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
875 | .name = "vga_vbe_write" , |
876 | .sstate = TRACE_VGA_VBE_WRITE_ENABLED, |
877 | .dstate = &_TRACE_VGA_VBE_WRITE_DSTATE |
878 | }; |
879 | TraceEvent _TRACE_VGA_CIRRUS_READ_IO_EVENT = { |
880 | .id = 0, |
881 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
882 | .name = "vga_cirrus_read_io" , |
883 | .sstate = TRACE_VGA_CIRRUS_READ_IO_ENABLED, |
884 | .dstate = &_TRACE_VGA_CIRRUS_READ_IO_DSTATE |
885 | }; |
886 | TraceEvent _TRACE_VGA_CIRRUS_WRITE_IO_EVENT = { |
887 | .id = 0, |
888 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
889 | .name = "vga_cirrus_write_io" , |
890 | .sstate = TRACE_VGA_CIRRUS_WRITE_IO_ENABLED, |
891 | .dstate = &_TRACE_VGA_CIRRUS_WRITE_IO_DSTATE |
892 | }; |
893 | TraceEvent _TRACE_VGA_CIRRUS_WRITE_BLT_EVENT = { |
894 | .id = 0, |
895 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
896 | .name = "vga_cirrus_write_blt" , |
897 | .sstate = TRACE_VGA_CIRRUS_WRITE_BLT_ENABLED, |
898 | .dstate = &_TRACE_VGA_CIRRUS_WRITE_BLT_DSTATE |
899 | }; |
900 | TraceEvent _TRACE_SII9022_READ_REG_EVENT = { |
901 | .id = 0, |
902 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
903 | .name = "sii9022_read_reg" , |
904 | .sstate = TRACE_SII9022_READ_REG_ENABLED, |
905 | .dstate = &_TRACE_SII9022_READ_REG_DSTATE |
906 | }; |
907 | TraceEvent _TRACE_SII9022_WRITE_REG_EVENT = { |
908 | .id = 0, |
909 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
910 | .name = "sii9022_write_reg" , |
911 | .sstate = TRACE_SII9022_WRITE_REG_ENABLED, |
912 | .dstate = &_TRACE_SII9022_WRITE_REG_DSTATE |
913 | }; |
914 | TraceEvent _TRACE_SII9022_SWITCH_MODE_EVENT = { |
915 | .id = 0, |
916 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
917 | .name = "sii9022_switch_mode" , |
918 | .sstate = TRACE_SII9022_SWITCH_MODE_ENABLED, |
919 | .dstate = &_TRACE_SII9022_SWITCH_MODE_DSTATE |
920 | }; |
921 | TraceEvent _TRACE_ATI_MM_READ_EVENT = { |
922 | .id = 0, |
923 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
924 | .name = "ati_mm_read" , |
925 | .sstate = TRACE_ATI_MM_READ_ENABLED, |
926 | .dstate = &_TRACE_ATI_MM_READ_DSTATE |
927 | }; |
928 | TraceEvent _TRACE_ATI_MM_WRITE_EVENT = { |
929 | .id = 0, |
930 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
931 | .name = "ati_mm_write" , |
932 | .sstate = TRACE_ATI_MM_WRITE_ENABLED, |
933 | .dstate = &_TRACE_ATI_MM_WRITE_DSTATE |
934 | }; |
935 | TraceEvent *hw_display_trace_events[] = { |
936 | &_TRACE_JAZZ_LED_READ_EVENT, |
937 | &_TRACE_JAZZ_LED_WRITE_EVENT, |
938 | &_TRACE_XENFB_MOUSE_EVENT_EVENT, |
939 | &_TRACE_XENFB_KEY_EVENT_EVENT, |
940 | &_TRACE_XENFB_INPUT_CONNECTED_EVENT, |
941 | &_TRACE_G364FB_READ_EVENT, |
942 | &_TRACE_G364FB_WRITE_EVENT, |
943 | &_TRACE_MILKYMIST_TMU2_MEMORY_READ_EVENT, |
944 | &_TRACE_MILKYMIST_TMU2_MEMORY_WRITE_EVENT, |
945 | &_TRACE_MILKYMIST_TMU2_START_EVENT, |
946 | &_TRACE_MILKYMIST_TMU2_PULSE_IRQ_EVENT, |
947 | &_TRACE_MILKYMIST_VGAFB_MEMORY_READ_EVENT, |
948 | &_TRACE_MILKYMIST_VGAFB_MEMORY_WRITE_EVENT, |
949 | &_TRACE_VMWARE_VALUE_READ_EVENT, |
950 | &_TRACE_VMWARE_VALUE_WRITE_EVENT, |
951 | &_TRACE_VMWARE_PALETTE_READ_EVENT, |
952 | &_TRACE_VMWARE_PALETTE_WRITE_EVENT, |
953 | &_TRACE_VMWARE_SCRATCH_READ_EVENT, |
954 | &_TRACE_VMWARE_SCRATCH_WRITE_EVENT, |
955 | &_TRACE_VMWARE_SETMODE_EVENT, |
956 | &_TRACE_VIRTIO_GPU_FEATURES_EVENT, |
957 | &_TRACE_VIRTIO_GPU_CMD_GET_DISPLAY_INFO_EVENT, |
958 | &_TRACE_VIRTIO_GPU_CMD_GET_EDID_EVENT, |
959 | &_TRACE_VIRTIO_GPU_CMD_SET_SCANOUT_EVENT, |
960 | &_TRACE_VIRTIO_GPU_CMD_RES_CREATE_2D_EVENT, |
961 | &_TRACE_VIRTIO_GPU_CMD_RES_CREATE_3D_EVENT, |
962 | &_TRACE_VIRTIO_GPU_CMD_RES_UNREF_EVENT, |
963 | &_TRACE_VIRTIO_GPU_CMD_RES_BACK_ATTACH_EVENT, |
964 | &_TRACE_VIRTIO_GPU_CMD_RES_BACK_DETACH_EVENT, |
965 | &_TRACE_VIRTIO_GPU_CMD_RES_XFER_TOH_2D_EVENT, |
966 | &_TRACE_VIRTIO_GPU_CMD_RES_XFER_TOH_3D_EVENT, |
967 | &_TRACE_VIRTIO_GPU_CMD_RES_XFER_FROMH_3D_EVENT, |
968 | &_TRACE_VIRTIO_GPU_CMD_RES_FLUSH_EVENT, |
969 | &_TRACE_VIRTIO_GPU_CMD_CTX_CREATE_EVENT, |
970 | &_TRACE_VIRTIO_GPU_CMD_CTX_DESTROY_EVENT, |
971 | &_TRACE_VIRTIO_GPU_CMD_CTX_RES_ATTACH_EVENT, |
972 | &_TRACE_VIRTIO_GPU_CMD_CTX_RES_DETACH_EVENT, |
973 | &_TRACE_VIRTIO_GPU_CMD_CTX_SUBMIT_EVENT, |
974 | &_TRACE_VIRTIO_GPU_UPDATE_CURSOR_EVENT, |
975 | &_TRACE_VIRTIO_GPU_FENCE_CTRL_EVENT, |
976 | &_TRACE_VIRTIO_GPU_FENCE_RESP_EVENT, |
977 | &_TRACE_QXL_INTERFACE_SET_MM_TIME_EVENT, |
978 | &_TRACE_QXL_IO_WRITE_VGA_EVENT, |
979 | &_TRACE_QXL_CREATE_GUEST_PRIMARY_EVENT, |
980 | &_TRACE_QXL_CREATE_GUEST_PRIMARY_REST_EVENT, |
981 | &_TRACE_QXL_DESTROY_PRIMARY_EVENT, |
982 | &_TRACE_QXL_ENTER_VGA_MODE_EVENT, |
983 | &_TRACE_QXL_EXIT_VGA_MODE_EVENT, |
984 | &_TRACE_QXL_HARD_RESET_EVENT, |
985 | &_TRACE_QXL_INTERFACE_ASYNC_COMPLETE_IO_EVENT, |
986 | &_TRACE_QXL_INTERFACE_ATTACH_WORKER_EVENT, |
987 | &_TRACE_QXL_INTERFACE_GET_INIT_INFO_EVENT, |
988 | &_TRACE_QXL_INTERFACE_SET_COMPRESSION_LEVEL_EVENT, |
989 | &_TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_EVENT, |
990 | &_TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_REST_EVENT, |
991 | &_TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_OVERFLOW_EVENT, |
992 | &_TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_SCHEDULE_BH_EVENT, |
993 | &_TRACE_QXL_IO_DESTROY_PRIMARY_IGNORED_EVENT, |
994 | &_TRACE_QXL_IO_LOG_EVENT, |
995 | &_TRACE_QXL_IO_READ_UNEXPECTED_EVENT, |
996 | &_TRACE_QXL_IO_UNEXPECTED_VGA_MODE_EVENT, |
997 | &_TRACE_QXL_IO_WRITE_EVENT, |
998 | &_TRACE_QXL_MEMSLOT_ADD_GUEST_EVENT, |
999 | &_TRACE_QXL_POST_LOAD_EVENT, |
1000 | &_TRACE_QXL_PRE_LOAD_EVENT, |
1001 | &_TRACE_QXL_PRE_SAVE_EVENT, |
1002 | &_TRACE_QXL_RESET_SURFACES_EVENT, |
1003 | &_TRACE_QXL_RING_COMMAND_CHECK_EVENT, |
1004 | &_TRACE_QXL_RING_COMMAND_GET_EVENT, |
1005 | &_TRACE_QXL_RING_COMMAND_REQ_NOTIFICATION_EVENT, |
1006 | &_TRACE_QXL_RING_CURSOR_CHECK_EVENT, |
1007 | &_TRACE_QXL_RING_CURSOR_GET_EVENT, |
1008 | &_TRACE_QXL_RING_CURSOR_REQ_NOTIFICATION_EVENT, |
1009 | &_TRACE_QXL_RING_RES_PUSH_EVENT, |
1010 | &_TRACE_QXL_RING_RES_PUSH_REST_EVENT, |
1011 | &_TRACE_QXL_RING_RES_PUT_EVENT, |
1012 | &_TRACE_QXL_SET_MODE_EVENT, |
1013 | &_TRACE_QXL_SOFT_RESET_EVENT, |
1014 | &_TRACE_QXL_SPICE_DESTROY_SURFACES_COMPLETE_EVENT, |
1015 | &_TRACE_QXL_SPICE_DESTROY_SURFACES_EVENT, |
1016 | &_TRACE_QXL_SPICE_DESTROY_SURFACE_WAIT_COMPLETE_EVENT, |
1017 | &_TRACE_QXL_SPICE_DESTROY_SURFACE_WAIT_EVENT, |
1018 | &_TRACE_QXL_SPICE_FLUSH_SURFACES_ASYNC_EVENT, |
1019 | &_TRACE_QXL_SPICE_MONITORS_CONFIG_EVENT, |
1020 | &_TRACE_QXL_SPICE_LOADVM_COMMANDS_EVENT, |
1021 | &_TRACE_QXL_SPICE_OOM_EVENT, |
1022 | &_TRACE_QXL_SPICE_RESET_CURSOR_EVENT, |
1023 | &_TRACE_QXL_SPICE_RESET_IMAGE_CACHE_EVENT, |
1024 | &_TRACE_QXL_SPICE_RESET_MEMSLOTS_EVENT, |
1025 | &_TRACE_QXL_SPICE_UPDATE_AREA_EVENT, |
1026 | &_TRACE_QXL_SPICE_UPDATE_AREA_REST_EVENT, |
1027 | &_TRACE_QXL_SURFACES_DIRTY_EVENT, |
1028 | &_TRACE_QXL_SEND_EVENTS_EVENT, |
1029 | &_TRACE_QXL_SEND_EVENTS_VM_STOPPED_EVENT, |
1030 | &_TRACE_QXL_SET_GUEST_BUG_EVENT, |
1031 | &_TRACE_QXL_INTERRUPT_CLIENT_MONITORS_CONFIG_EVENT, |
1032 | &_TRACE_QXL_CLIENT_MONITORS_CONFIG_UNSUPPORTED_BY_GUEST_EVENT, |
1033 | &_TRACE_QXL_CLIENT_MONITORS_CONFIG_UNSUPPORTED_BY_DEVICE_EVENT, |
1034 | &_TRACE_QXL_CLIENT_MONITORS_CONFIG_CAPPED_EVENT, |
1035 | &_TRACE_QXL_CLIENT_MONITORS_CONFIG_CRC_EVENT, |
1036 | &_TRACE_QXL_SET_CLIENT_CAPABILITIES_UNSUPPORTED_BY_REVISION_EVENT, |
1037 | &_TRACE_QXL_RENDER_BLIT_EVENT, |
1038 | &_TRACE_QXL_RENDER_GUEST_PRIMARY_RESIZED_EVENT, |
1039 | &_TRACE_QXL_RENDER_UPDATE_AREA_DONE_EVENT, |
1040 | &_TRACE_VGA_STD_READ_IO_EVENT, |
1041 | &_TRACE_VGA_STD_WRITE_IO_EVENT, |
1042 | &_TRACE_VGA_VBE_READ_EVENT, |
1043 | &_TRACE_VGA_VBE_WRITE_EVENT, |
1044 | &_TRACE_VGA_CIRRUS_READ_IO_EVENT, |
1045 | &_TRACE_VGA_CIRRUS_WRITE_IO_EVENT, |
1046 | &_TRACE_VGA_CIRRUS_WRITE_BLT_EVENT, |
1047 | &_TRACE_SII9022_READ_REG_EVENT, |
1048 | &_TRACE_SII9022_WRITE_REG_EVENT, |
1049 | &_TRACE_SII9022_SWITCH_MODE_EVENT, |
1050 | &_TRACE_ATI_MM_READ_EVENT, |
1051 | &_TRACE_ATI_MM_WRITE_EVENT, |
1052 | NULL, |
1053 | }; |
1054 | |
1055 | static void trace_hw_display_register_events(void) |
1056 | { |
1057 | trace_event_register_group(hw_display_trace_events); |
1058 | } |
1059 | trace_init(trace_hw_display_register_events) |
1060 | |