1/* This file is autogenerated by tracetool, do not edit. */
2
3#ifndef TRACE_HW_TIMER_GENERATED_TRACERS_H
4#define TRACE_HW_TIMER_GENERATED_TRACERS_H
5
6#include "trace/control.h"
7
8extern TraceEvent _TRACE_SLAVIO_TIMER_GET_OUT_EVENT;
9extern TraceEvent _TRACE_SLAVIO_TIMER_IRQ_EVENT;
10extern TraceEvent _TRACE_SLAVIO_TIMER_MEM_READL_INVALID_EVENT;
11extern TraceEvent _TRACE_SLAVIO_TIMER_MEM_READL_EVENT;
12extern TraceEvent _TRACE_SLAVIO_TIMER_MEM_WRITEL_EVENT;
13extern TraceEvent _TRACE_SLAVIO_TIMER_MEM_WRITEL_LIMIT_EVENT;
14extern TraceEvent _TRACE_SLAVIO_TIMER_MEM_WRITEL_COUNTER_INVALID_EVENT;
15extern TraceEvent _TRACE_SLAVIO_TIMER_MEM_WRITEL_STATUS_START_EVENT;
16extern TraceEvent _TRACE_SLAVIO_TIMER_MEM_WRITEL_STATUS_STOP_EVENT;
17extern TraceEvent _TRACE_SLAVIO_TIMER_MEM_WRITEL_MODE_USER_EVENT;
18extern TraceEvent _TRACE_SLAVIO_TIMER_MEM_WRITEL_MODE_COUNTER_EVENT;
19extern TraceEvent _TRACE_SLAVIO_TIMER_MEM_WRITEL_MODE_INVALID_EVENT;
20extern TraceEvent _TRACE_SLAVIO_TIMER_MEM_WRITEL_INVALID_EVENT;
21extern TraceEvent _TRACE_GRLIB_GPTIMER_ENABLE_EVENT;
22extern TraceEvent _TRACE_GRLIB_GPTIMER_DISABLED_EVENT;
23extern TraceEvent _TRACE_GRLIB_GPTIMER_RESTART_EVENT;
24extern TraceEvent _TRACE_GRLIB_GPTIMER_SET_SCALER_EVENT;
25extern TraceEvent _TRACE_GRLIB_GPTIMER_HIT_EVENT;
26extern TraceEvent _TRACE_GRLIB_GPTIMER_READL_EVENT;
27extern TraceEvent _TRACE_GRLIB_GPTIMER_WRITEL_EVENT;
28extern TraceEvent _TRACE_LM32_TIMER_MEMORY_WRITE_EVENT;
29extern TraceEvent _TRACE_LM32_TIMER_MEMORY_READ_EVENT;
30extern TraceEvent _TRACE_LM32_TIMER_HIT_EVENT;
31extern TraceEvent _TRACE_LM32_TIMER_IRQ_STATE_EVENT;
32extern TraceEvent _TRACE_MILKYMIST_SYSCTL_MEMORY_READ_EVENT;
33extern TraceEvent _TRACE_MILKYMIST_SYSCTL_MEMORY_WRITE_EVENT;
34extern TraceEvent _TRACE_MILKYMIST_SYSCTL_ICAP_WRITE_EVENT;
35extern TraceEvent _TRACE_MILKYMIST_SYSCTL_START_TIMER0_EVENT;
36extern TraceEvent _TRACE_MILKYMIST_SYSCTL_STOP_TIMER0_EVENT;
37extern TraceEvent _TRACE_MILKYMIST_SYSCTL_START_TIMER1_EVENT;
38extern TraceEvent _TRACE_MILKYMIST_SYSCTL_STOP_TIMER1_EVENT;
39extern TraceEvent _TRACE_MILKYMIST_SYSCTL_PULSE_IRQ_TIMER0_EVENT;
40extern TraceEvent _TRACE_MILKYMIST_SYSCTL_PULSE_IRQ_TIMER1_EVENT;
41extern TraceEvent _TRACE_ASPEED_TIMER_CTRL_ENABLE_EVENT;
42extern TraceEvent _TRACE_ASPEED_TIMER_CTRL_EXTERNAL_CLOCK_EVENT;
43extern TraceEvent _TRACE_ASPEED_TIMER_CTRL_OVERFLOW_INTERRUPT_EVENT;
44extern TraceEvent _TRACE_ASPEED_TIMER_CTRL_PULSE_ENABLE_EVENT;
45extern TraceEvent _TRACE_ASPEED_TIMER_SET_CTRL2_EVENT;
46extern TraceEvent _TRACE_ASPEED_TIMER_SET_VALUE_EVENT;
47extern TraceEvent _TRACE_ASPEED_TIMER_READ_EVENT;
48extern TraceEvent _TRACE_SYSTICK_RELOAD_EVENT;
49extern TraceEvent _TRACE_SYSTICK_TIMER_TICK_EVENT;
50extern TraceEvent _TRACE_SYSTICK_READ_EVENT;
51extern TraceEvent _TRACE_SYSTICK_WRITE_EVENT;
52extern TraceEvent _TRACE_CMSDK_APB_TIMER_READ_EVENT;
53extern TraceEvent _TRACE_CMSDK_APB_TIMER_WRITE_EVENT;
54extern TraceEvent _TRACE_CMSDK_APB_TIMER_RESET_EVENT;
55extern TraceEvent _TRACE_CMSDK_APB_DUALTIMER_READ_EVENT;
56extern TraceEvent _TRACE_CMSDK_APB_DUALTIMER_WRITE_EVENT;
57extern TraceEvent _TRACE_CMSDK_APB_DUALTIMER_RESET_EVENT;
58extern TraceEvent _TRACE_ASPEED_RTC_READ_EVENT;
59extern TraceEvent _TRACE_ASPEED_RTC_WRITE_EVENT;
60extern TraceEvent _TRACE_SUN4V_RTC_READ_EVENT;
61extern TraceEvent _TRACE_SUN4V_RTC_WRITE_EVENT;
62extern TraceEvent _TRACE_XLNX_ZYNQMP_RTC_GETTIME_EVENT;
63extern TraceEvent _TRACE_NRF51_TIMER_READ_EVENT;
64extern TraceEvent _TRACE_NRF51_TIMER_WRITE_EVENT;
65extern TraceEvent _TRACE_PL031_IRQ_STATE_EVENT;
66extern TraceEvent _TRACE_PL031_READ_EVENT;
67extern TraceEvent _TRACE_PL031_WRITE_EVENT;
68extern TraceEvent _TRACE_PL031_ALARM_RAISED_EVENT;
69extern TraceEvent _TRACE_PL031_SET_ALARM_EVENT;
70extern uint16_t _TRACE_SLAVIO_TIMER_GET_OUT_DSTATE;
71extern uint16_t _TRACE_SLAVIO_TIMER_IRQ_DSTATE;
72extern uint16_t _TRACE_SLAVIO_TIMER_MEM_READL_INVALID_DSTATE;
73extern uint16_t _TRACE_SLAVIO_TIMER_MEM_READL_DSTATE;
74extern uint16_t _TRACE_SLAVIO_TIMER_MEM_WRITEL_DSTATE;
75extern uint16_t _TRACE_SLAVIO_TIMER_MEM_WRITEL_LIMIT_DSTATE;
76extern uint16_t _TRACE_SLAVIO_TIMER_MEM_WRITEL_COUNTER_INVALID_DSTATE;
77extern uint16_t _TRACE_SLAVIO_TIMER_MEM_WRITEL_STATUS_START_DSTATE;
78extern uint16_t _TRACE_SLAVIO_TIMER_MEM_WRITEL_STATUS_STOP_DSTATE;
79extern uint16_t _TRACE_SLAVIO_TIMER_MEM_WRITEL_MODE_USER_DSTATE;
80extern uint16_t _TRACE_SLAVIO_TIMER_MEM_WRITEL_MODE_COUNTER_DSTATE;
81extern uint16_t _TRACE_SLAVIO_TIMER_MEM_WRITEL_MODE_INVALID_DSTATE;
82extern uint16_t _TRACE_SLAVIO_TIMER_MEM_WRITEL_INVALID_DSTATE;
83extern uint16_t _TRACE_GRLIB_GPTIMER_ENABLE_DSTATE;
84extern uint16_t _TRACE_GRLIB_GPTIMER_DISABLED_DSTATE;
85extern uint16_t _TRACE_GRLIB_GPTIMER_RESTART_DSTATE;
86extern uint16_t _TRACE_GRLIB_GPTIMER_SET_SCALER_DSTATE;
87extern uint16_t _TRACE_GRLIB_GPTIMER_HIT_DSTATE;
88extern uint16_t _TRACE_GRLIB_GPTIMER_READL_DSTATE;
89extern uint16_t _TRACE_GRLIB_GPTIMER_WRITEL_DSTATE;
90extern uint16_t _TRACE_LM32_TIMER_MEMORY_WRITE_DSTATE;
91extern uint16_t _TRACE_LM32_TIMER_MEMORY_READ_DSTATE;
92extern uint16_t _TRACE_LM32_TIMER_HIT_DSTATE;
93extern uint16_t _TRACE_LM32_TIMER_IRQ_STATE_DSTATE;
94extern uint16_t _TRACE_MILKYMIST_SYSCTL_MEMORY_READ_DSTATE;
95extern uint16_t _TRACE_MILKYMIST_SYSCTL_MEMORY_WRITE_DSTATE;
96extern uint16_t _TRACE_MILKYMIST_SYSCTL_ICAP_WRITE_DSTATE;
97extern uint16_t _TRACE_MILKYMIST_SYSCTL_START_TIMER0_DSTATE;
98extern uint16_t _TRACE_MILKYMIST_SYSCTL_STOP_TIMER0_DSTATE;
99extern uint16_t _TRACE_MILKYMIST_SYSCTL_START_TIMER1_DSTATE;
100extern uint16_t _TRACE_MILKYMIST_SYSCTL_STOP_TIMER1_DSTATE;
101extern uint16_t _TRACE_MILKYMIST_SYSCTL_PULSE_IRQ_TIMER0_DSTATE;
102extern uint16_t _TRACE_MILKYMIST_SYSCTL_PULSE_IRQ_TIMER1_DSTATE;
103extern uint16_t _TRACE_ASPEED_TIMER_CTRL_ENABLE_DSTATE;
104extern uint16_t _TRACE_ASPEED_TIMER_CTRL_EXTERNAL_CLOCK_DSTATE;
105extern uint16_t _TRACE_ASPEED_TIMER_CTRL_OVERFLOW_INTERRUPT_DSTATE;
106extern uint16_t _TRACE_ASPEED_TIMER_CTRL_PULSE_ENABLE_DSTATE;
107extern uint16_t _TRACE_ASPEED_TIMER_SET_CTRL2_DSTATE;
108extern uint16_t _TRACE_ASPEED_TIMER_SET_VALUE_DSTATE;
109extern uint16_t _TRACE_ASPEED_TIMER_READ_DSTATE;
110extern uint16_t _TRACE_SYSTICK_RELOAD_DSTATE;
111extern uint16_t _TRACE_SYSTICK_TIMER_TICK_DSTATE;
112extern uint16_t _TRACE_SYSTICK_READ_DSTATE;
113extern uint16_t _TRACE_SYSTICK_WRITE_DSTATE;
114extern uint16_t _TRACE_CMSDK_APB_TIMER_READ_DSTATE;
115extern uint16_t _TRACE_CMSDK_APB_TIMER_WRITE_DSTATE;
116extern uint16_t _TRACE_CMSDK_APB_TIMER_RESET_DSTATE;
117extern uint16_t _TRACE_CMSDK_APB_DUALTIMER_READ_DSTATE;
118extern uint16_t _TRACE_CMSDK_APB_DUALTIMER_WRITE_DSTATE;
119extern uint16_t _TRACE_CMSDK_APB_DUALTIMER_RESET_DSTATE;
120extern uint16_t _TRACE_ASPEED_RTC_READ_DSTATE;
121extern uint16_t _TRACE_ASPEED_RTC_WRITE_DSTATE;
122extern uint16_t _TRACE_SUN4V_RTC_READ_DSTATE;
123extern uint16_t _TRACE_SUN4V_RTC_WRITE_DSTATE;
124extern uint16_t _TRACE_XLNX_ZYNQMP_RTC_GETTIME_DSTATE;
125extern uint16_t _TRACE_NRF51_TIMER_READ_DSTATE;
126extern uint16_t _TRACE_NRF51_TIMER_WRITE_DSTATE;
127extern uint16_t _TRACE_PL031_IRQ_STATE_DSTATE;
128extern uint16_t _TRACE_PL031_READ_DSTATE;
129extern uint16_t _TRACE_PL031_WRITE_DSTATE;
130extern uint16_t _TRACE_PL031_ALARM_RAISED_DSTATE;
131extern uint16_t _TRACE_PL031_SET_ALARM_DSTATE;
132#define TRACE_SLAVIO_TIMER_GET_OUT_ENABLED 1
133#define TRACE_SLAVIO_TIMER_IRQ_ENABLED 1
134#define TRACE_SLAVIO_TIMER_MEM_READL_INVALID_ENABLED 1
135#define TRACE_SLAVIO_TIMER_MEM_READL_ENABLED 1
136#define TRACE_SLAVIO_TIMER_MEM_WRITEL_ENABLED 1
137#define TRACE_SLAVIO_TIMER_MEM_WRITEL_LIMIT_ENABLED 1
138#define TRACE_SLAVIO_TIMER_MEM_WRITEL_COUNTER_INVALID_ENABLED 1
139#define TRACE_SLAVIO_TIMER_MEM_WRITEL_STATUS_START_ENABLED 1
140#define TRACE_SLAVIO_TIMER_MEM_WRITEL_STATUS_STOP_ENABLED 1
141#define TRACE_SLAVIO_TIMER_MEM_WRITEL_MODE_USER_ENABLED 1
142#define TRACE_SLAVIO_TIMER_MEM_WRITEL_MODE_COUNTER_ENABLED 1
143#define TRACE_SLAVIO_TIMER_MEM_WRITEL_MODE_INVALID_ENABLED 1
144#define TRACE_SLAVIO_TIMER_MEM_WRITEL_INVALID_ENABLED 1
145#define TRACE_GRLIB_GPTIMER_ENABLE_ENABLED 1
146#define TRACE_GRLIB_GPTIMER_DISABLED_ENABLED 1
147#define TRACE_GRLIB_GPTIMER_RESTART_ENABLED 1
148#define TRACE_GRLIB_GPTIMER_SET_SCALER_ENABLED 1
149#define TRACE_GRLIB_GPTIMER_HIT_ENABLED 1
150#define TRACE_GRLIB_GPTIMER_READL_ENABLED 1
151#define TRACE_GRLIB_GPTIMER_WRITEL_ENABLED 1
152#define TRACE_LM32_TIMER_MEMORY_WRITE_ENABLED 1
153#define TRACE_LM32_TIMER_MEMORY_READ_ENABLED 1
154#define TRACE_LM32_TIMER_HIT_ENABLED 1
155#define TRACE_LM32_TIMER_IRQ_STATE_ENABLED 1
156#define TRACE_MILKYMIST_SYSCTL_MEMORY_READ_ENABLED 1
157#define TRACE_MILKYMIST_SYSCTL_MEMORY_WRITE_ENABLED 1
158#define TRACE_MILKYMIST_SYSCTL_ICAP_WRITE_ENABLED 1
159#define TRACE_MILKYMIST_SYSCTL_START_TIMER0_ENABLED 1
160#define TRACE_MILKYMIST_SYSCTL_STOP_TIMER0_ENABLED 1
161#define TRACE_MILKYMIST_SYSCTL_START_TIMER1_ENABLED 1
162#define TRACE_MILKYMIST_SYSCTL_STOP_TIMER1_ENABLED 1
163#define TRACE_MILKYMIST_SYSCTL_PULSE_IRQ_TIMER0_ENABLED 1
164#define TRACE_MILKYMIST_SYSCTL_PULSE_IRQ_TIMER1_ENABLED 1
165#define TRACE_ASPEED_TIMER_CTRL_ENABLE_ENABLED 1
166#define TRACE_ASPEED_TIMER_CTRL_EXTERNAL_CLOCK_ENABLED 1
167#define TRACE_ASPEED_TIMER_CTRL_OVERFLOW_INTERRUPT_ENABLED 1
168#define TRACE_ASPEED_TIMER_CTRL_PULSE_ENABLE_ENABLED 1
169#define TRACE_ASPEED_TIMER_SET_CTRL2_ENABLED 1
170#define TRACE_ASPEED_TIMER_SET_VALUE_ENABLED 1
171#define TRACE_ASPEED_TIMER_READ_ENABLED 1
172#define TRACE_SYSTICK_RELOAD_ENABLED 1
173#define TRACE_SYSTICK_TIMER_TICK_ENABLED 1
174#define TRACE_SYSTICK_READ_ENABLED 1
175#define TRACE_SYSTICK_WRITE_ENABLED 1
176#define TRACE_CMSDK_APB_TIMER_READ_ENABLED 1
177#define TRACE_CMSDK_APB_TIMER_WRITE_ENABLED 1
178#define TRACE_CMSDK_APB_TIMER_RESET_ENABLED 1
179#define TRACE_CMSDK_APB_DUALTIMER_READ_ENABLED 1
180#define TRACE_CMSDK_APB_DUALTIMER_WRITE_ENABLED 1
181#define TRACE_CMSDK_APB_DUALTIMER_RESET_ENABLED 1
182#define TRACE_ASPEED_RTC_READ_ENABLED 1
183#define TRACE_ASPEED_RTC_WRITE_ENABLED 1
184#define TRACE_SUN4V_RTC_READ_ENABLED 1
185#define TRACE_SUN4V_RTC_WRITE_ENABLED 1
186#define TRACE_XLNX_ZYNQMP_RTC_GETTIME_ENABLED 1
187#define TRACE_NRF51_TIMER_READ_ENABLED 1
188#define TRACE_NRF51_TIMER_WRITE_ENABLED 1
189#define TRACE_PL031_IRQ_STATE_ENABLED 1
190#define TRACE_PL031_READ_ENABLED 1
191#define TRACE_PL031_WRITE_ENABLED 1
192#define TRACE_PL031_ALARM_RAISED_ENABLED 1
193#define TRACE_PL031_SET_ALARM_ENABLED 1
194#include "qemu/log-for-trace.h"
195
196
197#define TRACE_SLAVIO_TIMER_GET_OUT_BACKEND_DSTATE() ( \
198 trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_TIMER_GET_OUT) || \
199 false)
200
201static inline void _nocheck__trace_slavio_timer_get_out(uint64_t limit, uint32_t counthigh, uint32_t count)
202{
203 if (trace_event_get_state(TRACE_SLAVIO_TIMER_GET_OUT) && qemu_loglevel_mask(LOG_TRACE)) {
204 struct timeval _now;
205 gettimeofday(&_now, NULL);
206 qemu_log("%d@%zu.%06zu:slavio_timer_get_out " "limit 0x%"PRIx64" count 0x%x0x%08x" "\n",
207 qemu_get_thread_id(),
208 (size_t)_now.tv_sec, (size_t)_now.tv_usec
209 , limit, counthigh, count);
210 }
211}
212
213static inline void trace_slavio_timer_get_out(uint64_t limit, uint32_t counthigh, uint32_t count)
214{
215 if (true) {
216 _nocheck__trace_slavio_timer_get_out(limit, counthigh, count);
217 }
218}
219
220#define TRACE_SLAVIO_TIMER_IRQ_BACKEND_DSTATE() ( \
221 trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_TIMER_IRQ) || \
222 false)
223
224static inline void _nocheck__trace_slavio_timer_irq(uint32_t counthigh, uint32_t count)
225{
226 if (trace_event_get_state(TRACE_SLAVIO_TIMER_IRQ) && qemu_loglevel_mask(LOG_TRACE)) {
227 struct timeval _now;
228 gettimeofday(&_now, NULL);
229 qemu_log("%d@%zu.%06zu:slavio_timer_irq " "callback: count 0x%x0x%08x" "\n",
230 qemu_get_thread_id(),
231 (size_t)_now.tv_sec, (size_t)_now.tv_usec
232 , counthigh, count);
233 }
234}
235
236static inline void trace_slavio_timer_irq(uint32_t counthigh, uint32_t count)
237{
238 if (true) {
239 _nocheck__trace_slavio_timer_irq(counthigh, count);
240 }
241}
242
243#define TRACE_SLAVIO_TIMER_MEM_READL_INVALID_BACKEND_DSTATE() ( \
244 trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_TIMER_MEM_READL_INVALID) || \
245 false)
246
247static inline void _nocheck__trace_slavio_timer_mem_readl_invalid(uint64_t addr)
248{
249 if (trace_event_get_state(TRACE_SLAVIO_TIMER_MEM_READL_INVALID) && qemu_loglevel_mask(LOG_TRACE)) {
250 struct timeval _now;
251 gettimeofday(&_now, NULL);
252 qemu_log("%d@%zu.%06zu:slavio_timer_mem_readl_invalid " "invalid read address 0x%"PRIx64 "\n",
253 qemu_get_thread_id(),
254 (size_t)_now.tv_sec, (size_t)_now.tv_usec
255 , addr);
256 }
257}
258
259static inline void trace_slavio_timer_mem_readl_invalid(uint64_t addr)
260{
261 if (true) {
262 _nocheck__trace_slavio_timer_mem_readl_invalid(addr);
263 }
264}
265
266#define TRACE_SLAVIO_TIMER_MEM_READL_BACKEND_DSTATE() ( \
267 trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_TIMER_MEM_READL) || \
268 false)
269
270static inline void _nocheck__trace_slavio_timer_mem_readl(uint64_t addr, uint32_t ret)
271{
272 if (trace_event_get_state(TRACE_SLAVIO_TIMER_MEM_READL) && qemu_loglevel_mask(LOG_TRACE)) {
273 struct timeval _now;
274 gettimeofday(&_now, NULL);
275 qemu_log("%d@%zu.%06zu:slavio_timer_mem_readl " "read 0x%"PRIx64" = 0x%08x" "\n",
276 qemu_get_thread_id(),
277 (size_t)_now.tv_sec, (size_t)_now.tv_usec
278 , addr, ret);
279 }
280}
281
282static inline void trace_slavio_timer_mem_readl(uint64_t addr, uint32_t ret)
283{
284 if (true) {
285 _nocheck__trace_slavio_timer_mem_readl(addr, ret);
286 }
287}
288
289#define TRACE_SLAVIO_TIMER_MEM_WRITEL_BACKEND_DSTATE() ( \
290 trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_TIMER_MEM_WRITEL) || \
291 false)
292
293static inline void _nocheck__trace_slavio_timer_mem_writel(uint64_t addr, uint32_t val)
294{
295 if (trace_event_get_state(TRACE_SLAVIO_TIMER_MEM_WRITEL) && qemu_loglevel_mask(LOG_TRACE)) {
296 struct timeval _now;
297 gettimeofday(&_now, NULL);
298 qemu_log("%d@%zu.%06zu:slavio_timer_mem_writel " "write 0x%"PRIx64" = 0x%08x" "\n",
299 qemu_get_thread_id(),
300 (size_t)_now.tv_sec, (size_t)_now.tv_usec
301 , addr, val);
302 }
303}
304
305static inline void trace_slavio_timer_mem_writel(uint64_t addr, uint32_t val)
306{
307 if (true) {
308 _nocheck__trace_slavio_timer_mem_writel(addr, val);
309 }
310}
311
312#define TRACE_SLAVIO_TIMER_MEM_WRITEL_LIMIT_BACKEND_DSTATE() ( \
313 trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_TIMER_MEM_WRITEL_LIMIT) || \
314 false)
315
316static inline void _nocheck__trace_slavio_timer_mem_writel_limit(unsigned int timer_index, uint64_t count)
317{
318 if (trace_event_get_state(TRACE_SLAVIO_TIMER_MEM_WRITEL_LIMIT) && qemu_loglevel_mask(LOG_TRACE)) {
319 struct timeval _now;
320 gettimeofday(&_now, NULL);
321 qemu_log("%d@%zu.%06zu:slavio_timer_mem_writel_limit " "processor %d user timer set to 0x%016"PRIx64 "\n",
322 qemu_get_thread_id(),
323 (size_t)_now.tv_sec, (size_t)_now.tv_usec
324 , timer_index, count);
325 }
326}
327
328static inline void trace_slavio_timer_mem_writel_limit(unsigned int timer_index, uint64_t count)
329{
330 if (true) {
331 _nocheck__trace_slavio_timer_mem_writel_limit(timer_index, count);
332 }
333}
334
335#define TRACE_SLAVIO_TIMER_MEM_WRITEL_COUNTER_INVALID_BACKEND_DSTATE() ( \
336 trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_TIMER_MEM_WRITEL_COUNTER_INVALID) || \
337 false)
338
339static inline void _nocheck__trace_slavio_timer_mem_writel_counter_invalid(void)
340{
341 if (trace_event_get_state(TRACE_SLAVIO_TIMER_MEM_WRITEL_COUNTER_INVALID) && qemu_loglevel_mask(LOG_TRACE)) {
342 struct timeval _now;
343 gettimeofday(&_now, NULL);
344 qemu_log("%d@%zu.%06zu:slavio_timer_mem_writel_counter_invalid " "not user timer" "\n",
345 qemu_get_thread_id(),
346 (size_t)_now.tv_sec, (size_t)_now.tv_usec
347 );
348 }
349}
350
351static inline void trace_slavio_timer_mem_writel_counter_invalid(void)
352{
353 if (true) {
354 _nocheck__trace_slavio_timer_mem_writel_counter_invalid();
355 }
356}
357
358#define TRACE_SLAVIO_TIMER_MEM_WRITEL_STATUS_START_BACKEND_DSTATE() ( \
359 trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_TIMER_MEM_WRITEL_STATUS_START) || \
360 false)
361
362static inline void _nocheck__trace_slavio_timer_mem_writel_status_start(unsigned int timer_index)
363{
364 if (trace_event_get_state(TRACE_SLAVIO_TIMER_MEM_WRITEL_STATUS_START) && qemu_loglevel_mask(LOG_TRACE)) {
365 struct timeval _now;
366 gettimeofday(&_now, NULL);
367 qemu_log("%d@%zu.%06zu:slavio_timer_mem_writel_status_start " "processor %d user timer started" "\n",
368 qemu_get_thread_id(),
369 (size_t)_now.tv_sec, (size_t)_now.tv_usec
370 , timer_index);
371 }
372}
373
374static inline void trace_slavio_timer_mem_writel_status_start(unsigned int timer_index)
375{
376 if (true) {
377 _nocheck__trace_slavio_timer_mem_writel_status_start(timer_index);
378 }
379}
380
381#define TRACE_SLAVIO_TIMER_MEM_WRITEL_STATUS_STOP_BACKEND_DSTATE() ( \
382 trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_TIMER_MEM_WRITEL_STATUS_STOP) || \
383 false)
384
385static inline void _nocheck__trace_slavio_timer_mem_writel_status_stop(unsigned int timer_index)
386{
387 if (trace_event_get_state(TRACE_SLAVIO_TIMER_MEM_WRITEL_STATUS_STOP) && qemu_loglevel_mask(LOG_TRACE)) {
388 struct timeval _now;
389 gettimeofday(&_now, NULL);
390 qemu_log("%d@%zu.%06zu:slavio_timer_mem_writel_status_stop " "processor %d user timer stopped" "\n",
391 qemu_get_thread_id(),
392 (size_t)_now.tv_sec, (size_t)_now.tv_usec
393 , timer_index);
394 }
395}
396
397static inline void trace_slavio_timer_mem_writel_status_stop(unsigned int timer_index)
398{
399 if (true) {
400 _nocheck__trace_slavio_timer_mem_writel_status_stop(timer_index);
401 }
402}
403
404#define TRACE_SLAVIO_TIMER_MEM_WRITEL_MODE_USER_BACKEND_DSTATE() ( \
405 trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_TIMER_MEM_WRITEL_MODE_USER) || \
406 false)
407
408static inline void _nocheck__trace_slavio_timer_mem_writel_mode_user(unsigned int timer_index)
409{
410 if (trace_event_get_state(TRACE_SLAVIO_TIMER_MEM_WRITEL_MODE_USER) && qemu_loglevel_mask(LOG_TRACE)) {
411 struct timeval _now;
412 gettimeofday(&_now, NULL);
413 qemu_log("%d@%zu.%06zu:slavio_timer_mem_writel_mode_user " "processor %d changed from counter to user timer" "\n",
414 qemu_get_thread_id(),
415 (size_t)_now.tv_sec, (size_t)_now.tv_usec
416 , timer_index);
417 }
418}
419
420static inline void trace_slavio_timer_mem_writel_mode_user(unsigned int timer_index)
421{
422 if (true) {
423 _nocheck__trace_slavio_timer_mem_writel_mode_user(timer_index);
424 }
425}
426
427#define TRACE_SLAVIO_TIMER_MEM_WRITEL_MODE_COUNTER_BACKEND_DSTATE() ( \
428 trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_TIMER_MEM_WRITEL_MODE_COUNTER) || \
429 false)
430
431static inline void _nocheck__trace_slavio_timer_mem_writel_mode_counter(unsigned int timer_index)
432{
433 if (trace_event_get_state(TRACE_SLAVIO_TIMER_MEM_WRITEL_MODE_COUNTER) && qemu_loglevel_mask(LOG_TRACE)) {
434 struct timeval _now;
435 gettimeofday(&_now, NULL);
436 qemu_log("%d@%zu.%06zu:slavio_timer_mem_writel_mode_counter " "processor %d changed from user timer to counter" "\n",
437 qemu_get_thread_id(),
438 (size_t)_now.tv_sec, (size_t)_now.tv_usec
439 , timer_index);
440 }
441}
442
443static inline void trace_slavio_timer_mem_writel_mode_counter(unsigned int timer_index)
444{
445 if (true) {
446 _nocheck__trace_slavio_timer_mem_writel_mode_counter(timer_index);
447 }
448}
449
450#define TRACE_SLAVIO_TIMER_MEM_WRITEL_MODE_INVALID_BACKEND_DSTATE() ( \
451 trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_TIMER_MEM_WRITEL_MODE_INVALID) || \
452 false)
453
454static inline void _nocheck__trace_slavio_timer_mem_writel_mode_invalid(void)
455{
456 if (trace_event_get_state(TRACE_SLAVIO_TIMER_MEM_WRITEL_MODE_INVALID) && qemu_loglevel_mask(LOG_TRACE)) {
457 struct timeval _now;
458 gettimeofday(&_now, NULL);
459 qemu_log("%d@%zu.%06zu:slavio_timer_mem_writel_mode_invalid " "not system timer" "\n",
460 qemu_get_thread_id(),
461 (size_t)_now.tv_sec, (size_t)_now.tv_usec
462 );
463 }
464}
465
466static inline void trace_slavio_timer_mem_writel_mode_invalid(void)
467{
468 if (true) {
469 _nocheck__trace_slavio_timer_mem_writel_mode_invalid();
470 }
471}
472
473#define TRACE_SLAVIO_TIMER_MEM_WRITEL_INVALID_BACKEND_DSTATE() ( \
474 trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_TIMER_MEM_WRITEL_INVALID) || \
475 false)
476
477static inline void _nocheck__trace_slavio_timer_mem_writel_invalid(uint64_t addr)
478{
479 if (trace_event_get_state(TRACE_SLAVIO_TIMER_MEM_WRITEL_INVALID) && qemu_loglevel_mask(LOG_TRACE)) {
480 struct timeval _now;
481 gettimeofday(&_now, NULL);
482 qemu_log("%d@%zu.%06zu:slavio_timer_mem_writel_invalid " "invalid write address 0x%"PRIx64 "\n",
483 qemu_get_thread_id(),
484 (size_t)_now.tv_sec, (size_t)_now.tv_usec
485 , addr);
486 }
487}
488
489static inline void trace_slavio_timer_mem_writel_invalid(uint64_t addr)
490{
491 if (true) {
492 _nocheck__trace_slavio_timer_mem_writel_invalid(addr);
493 }
494}
495
496#define TRACE_GRLIB_GPTIMER_ENABLE_BACKEND_DSTATE() ( \
497 trace_event_get_state_dynamic_by_id(TRACE_GRLIB_GPTIMER_ENABLE) || \
498 false)
499
500static inline void _nocheck__trace_grlib_gptimer_enable(int id, uint32_t count)
501{
502 if (trace_event_get_state(TRACE_GRLIB_GPTIMER_ENABLE) && qemu_loglevel_mask(LOG_TRACE)) {
503 struct timeval _now;
504 gettimeofday(&_now, NULL);
505 qemu_log("%d@%zu.%06zu:grlib_gptimer_enable " "timer:%d set count 0x%x and run" "\n",
506 qemu_get_thread_id(),
507 (size_t)_now.tv_sec, (size_t)_now.tv_usec
508 , id, count);
509 }
510}
511
512static inline void trace_grlib_gptimer_enable(int id, uint32_t count)
513{
514 if (true) {
515 _nocheck__trace_grlib_gptimer_enable(id, count);
516 }
517}
518
519#define TRACE_GRLIB_GPTIMER_DISABLED_BACKEND_DSTATE() ( \
520 trace_event_get_state_dynamic_by_id(TRACE_GRLIB_GPTIMER_DISABLED) || \
521 false)
522
523static inline void _nocheck__trace_grlib_gptimer_disabled(int id, uint32_t config)
524{
525 if (trace_event_get_state(TRACE_GRLIB_GPTIMER_DISABLED) && qemu_loglevel_mask(LOG_TRACE)) {
526 struct timeval _now;
527 gettimeofday(&_now, NULL);
528 qemu_log("%d@%zu.%06zu:grlib_gptimer_disabled " "timer:%d Timer disable config 0x%x" "\n",
529 qemu_get_thread_id(),
530 (size_t)_now.tv_sec, (size_t)_now.tv_usec
531 , id, config);
532 }
533}
534
535static inline void trace_grlib_gptimer_disabled(int id, uint32_t config)
536{
537 if (true) {
538 _nocheck__trace_grlib_gptimer_disabled(id, config);
539 }
540}
541
542#define TRACE_GRLIB_GPTIMER_RESTART_BACKEND_DSTATE() ( \
543 trace_event_get_state_dynamic_by_id(TRACE_GRLIB_GPTIMER_RESTART) || \
544 false)
545
546static inline void _nocheck__trace_grlib_gptimer_restart(int id, uint32_t reload)
547{
548 if (trace_event_get_state(TRACE_GRLIB_GPTIMER_RESTART) && qemu_loglevel_mask(LOG_TRACE)) {
549 struct timeval _now;
550 gettimeofday(&_now, NULL);
551 qemu_log("%d@%zu.%06zu:grlib_gptimer_restart " "timer:%d reload val: 0x%x" "\n",
552 qemu_get_thread_id(),
553 (size_t)_now.tv_sec, (size_t)_now.tv_usec
554 , id, reload);
555 }
556}
557
558static inline void trace_grlib_gptimer_restart(int id, uint32_t reload)
559{
560 if (true) {
561 _nocheck__trace_grlib_gptimer_restart(id, reload);
562 }
563}
564
565#define TRACE_GRLIB_GPTIMER_SET_SCALER_BACKEND_DSTATE() ( \
566 trace_event_get_state_dynamic_by_id(TRACE_GRLIB_GPTIMER_SET_SCALER) || \
567 false)
568
569static inline void _nocheck__trace_grlib_gptimer_set_scaler(uint32_t scaler, uint32_t freq)
570{
571 if (trace_event_get_state(TRACE_GRLIB_GPTIMER_SET_SCALER) && qemu_loglevel_mask(LOG_TRACE)) {
572 struct timeval _now;
573 gettimeofday(&_now, NULL);
574 qemu_log("%d@%zu.%06zu:grlib_gptimer_set_scaler " "scaler:0x%x freq: 0x%x" "\n",
575 qemu_get_thread_id(),
576 (size_t)_now.tv_sec, (size_t)_now.tv_usec
577 , scaler, freq);
578 }
579}
580
581static inline void trace_grlib_gptimer_set_scaler(uint32_t scaler, uint32_t freq)
582{
583 if (true) {
584 _nocheck__trace_grlib_gptimer_set_scaler(scaler, freq);
585 }
586}
587
588#define TRACE_GRLIB_GPTIMER_HIT_BACKEND_DSTATE() ( \
589 trace_event_get_state_dynamic_by_id(TRACE_GRLIB_GPTIMER_HIT) || \
590 false)
591
592static inline void _nocheck__trace_grlib_gptimer_hit(int id)
593{
594 if (trace_event_get_state(TRACE_GRLIB_GPTIMER_HIT) && qemu_loglevel_mask(LOG_TRACE)) {
595 struct timeval _now;
596 gettimeofday(&_now, NULL);
597 qemu_log("%d@%zu.%06zu:grlib_gptimer_hit " "timer:%d HIT" "\n",
598 qemu_get_thread_id(),
599 (size_t)_now.tv_sec, (size_t)_now.tv_usec
600 , id);
601 }
602}
603
604static inline void trace_grlib_gptimer_hit(int id)
605{
606 if (true) {
607 _nocheck__trace_grlib_gptimer_hit(id);
608 }
609}
610
611#define TRACE_GRLIB_GPTIMER_READL_BACKEND_DSTATE() ( \
612 trace_event_get_state_dynamic_by_id(TRACE_GRLIB_GPTIMER_READL) || \
613 false)
614
615static inline void _nocheck__trace_grlib_gptimer_readl(int id, uint64_t addr, uint32_t val)
616{
617 if (trace_event_get_state(TRACE_GRLIB_GPTIMER_READL) && qemu_loglevel_mask(LOG_TRACE)) {
618 struct timeval _now;
619 gettimeofday(&_now, NULL);
620 qemu_log("%d@%zu.%06zu:grlib_gptimer_readl " "timer:%d addr 0x%"PRIx64" 0x%x" "\n",
621 qemu_get_thread_id(),
622 (size_t)_now.tv_sec, (size_t)_now.tv_usec
623 , id, addr, val);
624 }
625}
626
627static inline void trace_grlib_gptimer_readl(int id, uint64_t addr, uint32_t val)
628{
629 if (true) {
630 _nocheck__trace_grlib_gptimer_readl(id, addr, val);
631 }
632}
633
634#define TRACE_GRLIB_GPTIMER_WRITEL_BACKEND_DSTATE() ( \
635 trace_event_get_state_dynamic_by_id(TRACE_GRLIB_GPTIMER_WRITEL) || \
636 false)
637
638static inline void _nocheck__trace_grlib_gptimer_writel(int id, uint64_t addr, uint32_t val)
639{
640 if (trace_event_get_state(TRACE_GRLIB_GPTIMER_WRITEL) && qemu_loglevel_mask(LOG_TRACE)) {
641 struct timeval _now;
642 gettimeofday(&_now, NULL);
643 qemu_log("%d@%zu.%06zu:grlib_gptimer_writel " "timer:%d addr 0x%"PRIx64" 0x%x" "\n",
644 qemu_get_thread_id(),
645 (size_t)_now.tv_sec, (size_t)_now.tv_usec
646 , id, addr, val);
647 }
648}
649
650static inline void trace_grlib_gptimer_writel(int id, uint64_t addr, uint32_t val)
651{
652 if (true) {
653 _nocheck__trace_grlib_gptimer_writel(id, addr, val);
654 }
655}
656
657#define TRACE_LM32_TIMER_MEMORY_WRITE_BACKEND_DSTATE() ( \
658 trace_event_get_state_dynamic_by_id(TRACE_LM32_TIMER_MEMORY_WRITE) || \
659 false)
660
661static inline void _nocheck__trace_lm32_timer_memory_write(uint32_t addr, uint32_t value)
662{
663 if (trace_event_get_state(TRACE_LM32_TIMER_MEMORY_WRITE) && qemu_loglevel_mask(LOG_TRACE)) {
664 struct timeval _now;
665 gettimeofday(&_now, NULL);
666 qemu_log("%d@%zu.%06zu:lm32_timer_memory_write " "addr 0x%08x value 0x%08x" "\n",
667 qemu_get_thread_id(),
668 (size_t)_now.tv_sec, (size_t)_now.tv_usec
669 , addr, value);
670 }
671}
672
673static inline void trace_lm32_timer_memory_write(uint32_t addr, uint32_t value)
674{
675 if (true) {
676 _nocheck__trace_lm32_timer_memory_write(addr, value);
677 }
678}
679
680#define TRACE_LM32_TIMER_MEMORY_READ_BACKEND_DSTATE() ( \
681 trace_event_get_state_dynamic_by_id(TRACE_LM32_TIMER_MEMORY_READ) || \
682 false)
683
684static inline void _nocheck__trace_lm32_timer_memory_read(uint32_t addr, uint32_t value)
685{
686 if (trace_event_get_state(TRACE_LM32_TIMER_MEMORY_READ) && qemu_loglevel_mask(LOG_TRACE)) {
687 struct timeval _now;
688 gettimeofday(&_now, NULL);
689 qemu_log("%d@%zu.%06zu:lm32_timer_memory_read " "addr 0x%08x value 0x%08x" "\n",
690 qemu_get_thread_id(),
691 (size_t)_now.tv_sec, (size_t)_now.tv_usec
692 , addr, value);
693 }
694}
695
696static inline void trace_lm32_timer_memory_read(uint32_t addr, uint32_t value)
697{
698 if (true) {
699 _nocheck__trace_lm32_timer_memory_read(addr, value);
700 }
701}
702
703#define TRACE_LM32_TIMER_HIT_BACKEND_DSTATE() ( \
704 trace_event_get_state_dynamic_by_id(TRACE_LM32_TIMER_HIT) || \
705 false)
706
707static inline void _nocheck__trace_lm32_timer_hit(void)
708{
709 if (trace_event_get_state(TRACE_LM32_TIMER_HIT) && qemu_loglevel_mask(LOG_TRACE)) {
710 struct timeval _now;
711 gettimeofday(&_now, NULL);
712 qemu_log("%d@%zu.%06zu:lm32_timer_hit " "timer hit" "\n",
713 qemu_get_thread_id(),
714 (size_t)_now.tv_sec, (size_t)_now.tv_usec
715 );
716 }
717}
718
719static inline void trace_lm32_timer_hit(void)
720{
721 if (true) {
722 _nocheck__trace_lm32_timer_hit();
723 }
724}
725
726#define TRACE_LM32_TIMER_IRQ_STATE_BACKEND_DSTATE() ( \
727 trace_event_get_state_dynamic_by_id(TRACE_LM32_TIMER_IRQ_STATE) || \
728 false)
729
730static inline void _nocheck__trace_lm32_timer_irq_state(int level)
731{
732 if (trace_event_get_state(TRACE_LM32_TIMER_IRQ_STATE) && qemu_loglevel_mask(LOG_TRACE)) {
733 struct timeval _now;
734 gettimeofday(&_now, NULL);
735 qemu_log("%d@%zu.%06zu:lm32_timer_irq_state " "irq state %d" "\n",
736 qemu_get_thread_id(),
737 (size_t)_now.tv_sec, (size_t)_now.tv_usec
738 , level);
739 }
740}
741
742static inline void trace_lm32_timer_irq_state(int level)
743{
744 if (true) {
745 _nocheck__trace_lm32_timer_irq_state(level);
746 }
747}
748
749#define TRACE_MILKYMIST_SYSCTL_MEMORY_READ_BACKEND_DSTATE() ( \
750 trace_event_get_state_dynamic_by_id(TRACE_MILKYMIST_SYSCTL_MEMORY_READ) || \
751 false)
752
753static inline void _nocheck__trace_milkymist_sysctl_memory_read(uint32_t addr, uint32_t value)
754{
755 if (trace_event_get_state(TRACE_MILKYMIST_SYSCTL_MEMORY_READ) && qemu_loglevel_mask(LOG_TRACE)) {
756 struct timeval _now;
757 gettimeofday(&_now, NULL);
758 qemu_log("%d@%zu.%06zu:milkymist_sysctl_memory_read " "addr 0x%08x value 0x%08x" "\n",
759 qemu_get_thread_id(),
760 (size_t)_now.tv_sec, (size_t)_now.tv_usec
761 , addr, value);
762 }
763}
764
765static inline void trace_milkymist_sysctl_memory_read(uint32_t addr, uint32_t value)
766{
767 if (true) {
768 _nocheck__trace_milkymist_sysctl_memory_read(addr, value);
769 }
770}
771
772#define TRACE_MILKYMIST_SYSCTL_MEMORY_WRITE_BACKEND_DSTATE() ( \
773 trace_event_get_state_dynamic_by_id(TRACE_MILKYMIST_SYSCTL_MEMORY_WRITE) || \
774 false)
775
776static inline void _nocheck__trace_milkymist_sysctl_memory_write(uint32_t addr, uint32_t value)
777{
778 if (trace_event_get_state(TRACE_MILKYMIST_SYSCTL_MEMORY_WRITE) && qemu_loglevel_mask(LOG_TRACE)) {
779 struct timeval _now;
780 gettimeofday(&_now, NULL);
781 qemu_log("%d@%zu.%06zu:milkymist_sysctl_memory_write " "addr 0x%08x value 0x%08x" "\n",
782 qemu_get_thread_id(),
783 (size_t)_now.tv_sec, (size_t)_now.tv_usec
784 , addr, value);
785 }
786}
787
788static inline void trace_milkymist_sysctl_memory_write(uint32_t addr, uint32_t value)
789{
790 if (true) {
791 _nocheck__trace_milkymist_sysctl_memory_write(addr, value);
792 }
793}
794
795#define TRACE_MILKYMIST_SYSCTL_ICAP_WRITE_BACKEND_DSTATE() ( \
796 trace_event_get_state_dynamic_by_id(TRACE_MILKYMIST_SYSCTL_ICAP_WRITE) || \
797 false)
798
799static inline void _nocheck__trace_milkymist_sysctl_icap_write(uint32_t value)
800{
801 if (trace_event_get_state(TRACE_MILKYMIST_SYSCTL_ICAP_WRITE) && qemu_loglevel_mask(LOG_TRACE)) {
802 struct timeval _now;
803 gettimeofday(&_now, NULL);
804 qemu_log("%d@%zu.%06zu:milkymist_sysctl_icap_write " "value 0x%08x" "\n",
805 qemu_get_thread_id(),
806 (size_t)_now.tv_sec, (size_t)_now.tv_usec
807 , value);
808 }
809}
810
811static inline void trace_milkymist_sysctl_icap_write(uint32_t value)
812{
813 if (true) {
814 _nocheck__trace_milkymist_sysctl_icap_write(value);
815 }
816}
817
818#define TRACE_MILKYMIST_SYSCTL_START_TIMER0_BACKEND_DSTATE() ( \
819 trace_event_get_state_dynamic_by_id(TRACE_MILKYMIST_SYSCTL_START_TIMER0) || \
820 false)
821
822static inline void _nocheck__trace_milkymist_sysctl_start_timer0(void)
823{
824 if (trace_event_get_state(TRACE_MILKYMIST_SYSCTL_START_TIMER0) && qemu_loglevel_mask(LOG_TRACE)) {
825 struct timeval _now;
826 gettimeofday(&_now, NULL);
827 qemu_log("%d@%zu.%06zu:milkymist_sysctl_start_timer0 " "Start timer0" "\n",
828 qemu_get_thread_id(),
829 (size_t)_now.tv_sec, (size_t)_now.tv_usec
830 );
831 }
832}
833
834static inline void trace_milkymist_sysctl_start_timer0(void)
835{
836 if (true) {
837 _nocheck__trace_milkymist_sysctl_start_timer0();
838 }
839}
840
841#define TRACE_MILKYMIST_SYSCTL_STOP_TIMER0_BACKEND_DSTATE() ( \
842 trace_event_get_state_dynamic_by_id(TRACE_MILKYMIST_SYSCTL_STOP_TIMER0) || \
843 false)
844
845static inline void _nocheck__trace_milkymist_sysctl_stop_timer0(void)
846{
847 if (trace_event_get_state(TRACE_MILKYMIST_SYSCTL_STOP_TIMER0) && qemu_loglevel_mask(LOG_TRACE)) {
848 struct timeval _now;
849 gettimeofday(&_now, NULL);
850 qemu_log("%d@%zu.%06zu:milkymist_sysctl_stop_timer0 " "Stop timer0" "\n",
851 qemu_get_thread_id(),
852 (size_t)_now.tv_sec, (size_t)_now.tv_usec
853 );
854 }
855}
856
857static inline void trace_milkymist_sysctl_stop_timer0(void)
858{
859 if (true) {
860 _nocheck__trace_milkymist_sysctl_stop_timer0();
861 }
862}
863
864#define TRACE_MILKYMIST_SYSCTL_START_TIMER1_BACKEND_DSTATE() ( \
865 trace_event_get_state_dynamic_by_id(TRACE_MILKYMIST_SYSCTL_START_TIMER1) || \
866 false)
867
868static inline void _nocheck__trace_milkymist_sysctl_start_timer1(void)
869{
870 if (trace_event_get_state(TRACE_MILKYMIST_SYSCTL_START_TIMER1) && qemu_loglevel_mask(LOG_TRACE)) {
871 struct timeval _now;
872 gettimeofday(&_now, NULL);
873 qemu_log("%d@%zu.%06zu:milkymist_sysctl_start_timer1 " "Start timer1" "\n",
874 qemu_get_thread_id(),
875 (size_t)_now.tv_sec, (size_t)_now.tv_usec
876 );
877 }
878}
879
880static inline void trace_milkymist_sysctl_start_timer1(void)
881{
882 if (true) {
883 _nocheck__trace_milkymist_sysctl_start_timer1();
884 }
885}
886
887#define TRACE_MILKYMIST_SYSCTL_STOP_TIMER1_BACKEND_DSTATE() ( \
888 trace_event_get_state_dynamic_by_id(TRACE_MILKYMIST_SYSCTL_STOP_TIMER1) || \
889 false)
890
891static inline void _nocheck__trace_milkymist_sysctl_stop_timer1(void)
892{
893 if (trace_event_get_state(TRACE_MILKYMIST_SYSCTL_STOP_TIMER1) && qemu_loglevel_mask(LOG_TRACE)) {
894 struct timeval _now;
895 gettimeofday(&_now, NULL);
896 qemu_log("%d@%zu.%06zu:milkymist_sysctl_stop_timer1 " "Stop timer1" "\n",
897 qemu_get_thread_id(),
898 (size_t)_now.tv_sec, (size_t)_now.tv_usec
899 );
900 }
901}
902
903static inline void trace_milkymist_sysctl_stop_timer1(void)
904{
905 if (true) {
906 _nocheck__trace_milkymist_sysctl_stop_timer1();
907 }
908}
909
910#define TRACE_MILKYMIST_SYSCTL_PULSE_IRQ_TIMER0_BACKEND_DSTATE() ( \
911 trace_event_get_state_dynamic_by_id(TRACE_MILKYMIST_SYSCTL_PULSE_IRQ_TIMER0) || \
912 false)
913
914static inline void _nocheck__trace_milkymist_sysctl_pulse_irq_timer0(void)
915{
916 if (trace_event_get_state(TRACE_MILKYMIST_SYSCTL_PULSE_IRQ_TIMER0) && qemu_loglevel_mask(LOG_TRACE)) {
917 struct timeval _now;
918 gettimeofday(&_now, NULL);
919 qemu_log("%d@%zu.%06zu:milkymist_sysctl_pulse_irq_timer0 " "Pulse IRQ Timer0" "\n",
920 qemu_get_thread_id(),
921 (size_t)_now.tv_sec, (size_t)_now.tv_usec
922 );
923 }
924}
925
926static inline void trace_milkymist_sysctl_pulse_irq_timer0(void)
927{
928 if (true) {
929 _nocheck__trace_milkymist_sysctl_pulse_irq_timer0();
930 }
931}
932
933#define TRACE_MILKYMIST_SYSCTL_PULSE_IRQ_TIMER1_BACKEND_DSTATE() ( \
934 trace_event_get_state_dynamic_by_id(TRACE_MILKYMIST_SYSCTL_PULSE_IRQ_TIMER1) || \
935 false)
936
937static inline void _nocheck__trace_milkymist_sysctl_pulse_irq_timer1(void)
938{
939 if (trace_event_get_state(TRACE_MILKYMIST_SYSCTL_PULSE_IRQ_TIMER1) && qemu_loglevel_mask(LOG_TRACE)) {
940 struct timeval _now;
941 gettimeofday(&_now, NULL);
942 qemu_log("%d@%zu.%06zu:milkymist_sysctl_pulse_irq_timer1 " "Pulse IRQ Timer1" "\n",
943 qemu_get_thread_id(),
944 (size_t)_now.tv_sec, (size_t)_now.tv_usec
945 );
946 }
947}
948
949static inline void trace_milkymist_sysctl_pulse_irq_timer1(void)
950{
951 if (true) {
952 _nocheck__trace_milkymist_sysctl_pulse_irq_timer1();
953 }
954}
955
956#define TRACE_ASPEED_TIMER_CTRL_ENABLE_BACKEND_DSTATE() ( \
957 trace_event_get_state_dynamic_by_id(TRACE_ASPEED_TIMER_CTRL_ENABLE) || \
958 false)
959
960static inline void _nocheck__trace_aspeed_timer_ctrl_enable(uint8_t i, bool enable)
961{
962 if (trace_event_get_state(TRACE_ASPEED_TIMER_CTRL_ENABLE) && qemu_loglevel_mask(LOG_TRACE)) {
963 struct timeval _now;
964 gettimeofday(&_now, NULL);
965 qemu_log("%d@%zu.%06zu:aspeed_timer_ctrl_enable " "Timer %" PRIu8 ": %d" "\n",
966 qemu_get_thread_id(),
967 (size_t)_now.tv_sec, (size_t)_now.tv_usec
968 , i, enable);
969 }
970}
971
972static inline void trace_aspeed_timer_ctrl_enable(uint8_t i, bool enable)
973{
974 if (true) {
975 _nocheck__trace_aspeed_timer_ctrl_enable(i, enable);
976 }
977}
978
979#define TRACE_ASPEED_TIMER_CTRL_EXTERNAL_CLOCK_BACKEND_DSTATE() ( \
980 trace_event_get_state_dynamic_by_id(TRACE_ASPEED_TIMER_CTRL_EXTERNAL_CLOCK) || \
981 false)
982
983static inline void _nocheck__trace_aspeed_timer_ctrl_external_clock(uint8_t i, bool enable)
984{
985 if (trace_event_get_state(TRACE_ASPEED_TIMER_CTRL_EXTERNAL_CLOCK) && qemu_loglevel_mask(LOG_TRACE)) {
986 struct timeval _now;
987 gettimeofday(&_now, NULL);
988 qemu_log("%d@%zu.%06zu:aspeed_timer_ctrl_external_clock " "Timer %" PRIu8 ": %d" "\n",
989 qemu_get_thread_id(),
990 (size_t)_now.tv_sec, (size_t)_now.tv_usec
991 , i, enable);
992 }
993}
994
995static inline void trace_aspeed_timer_ctrl_external_clock(uint8_t i, bool enable)
996{
997 if (true) {
998 _nocheck__trace_aspeed_timer_ctrl_external_clock(i, enable);
999 }
1000}
1001
1002#define TRACE_ASPEED_TIMER_CTRL_OVERFLOW_INTERRUPT_BACKEND_DSTATE() ( \
1003 trace_event_get_state_dynamic_by_id(TRACE_ASPEED_TIMER_CTRL_OVERFLOW_INTERRUPT) || \
1004 false)
1005
1006static inline void _nocheck__trace_aspeed_timer_ctrl_overflow_interrupt(uint8_t i, bool enable)
1007{
1008 if (trace_event_get_state(TRACE_ASPEED_TIMER_CTRL_OVERFLOW_INTERRUPT) && qemu_loglevel_mask(LOG_TRACE)) {
1009 struct timeval _now;
1010 gettimeofday(&_now, NULL);
1011 qemu_log("%d@%zu.%06zu:aspeed_timer_ctrl_overflow_interrupt " "Timer %" PRIu8 ": %d" "\n",
1012 qemu_get_thread_id(),
1013 (size_t)_now.tv_sec, (size_t)_now.tv_usec
1014 , i, enable);
1015 }
1016}
1017
1018static inline void trace_aspeed_timer_ctrl_overflow_interrupt(uint8_t i, bool enable)
1019{
1020 if (true) {
1021 _nocheck__trace_aspeed_timer_ctrl_overflow_interrupt(i, enable);
1022 }
1023}
1024
1025#define TRACE_ASPEED_TIMER_CTRL_PULSE_ENABLE_BACKEND_DSTATE() ( \
1026 trace_event_get_state_dynamic_by_id(TRACE_ASPEED_TIMER_CTRL_PULSE_ENABLE) || \
1027 false)
1028
1029static inline void _nocheck__trace_aspeed_timer_ctrl_pulse_enable(uint8_t i, bool enable)
1030{
1031 if (trace_event_get_state(TRACE_ASPEED_TIMER_CTRL_PULSE_ENABLE) && qemu_loglevel_mask(LOG_TRACE)) {
1032 struct timeval _now;
1033 gettimeofday(&_now, NULL);
1034 qemu_log("%d@%zu.%06zu:aspeed_timer_ctrl_pulse_enable " "Timer %" PRIu8 ": %d" "\n",
1035 qemu_get_thread_id(),
1036 (size_t)_now.tv_sec, (size_t)_now.tv_usec
1037 , i, enable);
1038 }
1039}
1040
1041static inline void trace_aspeed_timer_ctrl_pulse_enable(uint8_t i, bool enable)
1042{
1043 if (true) {
1044 _nocheck__trace_aspeed_timer_ctrl_pulse_enable(i, enable);
1045 }
1046}
1047
1048#define TRACE_ASPEED_TIMER_SET_CTRL2_BACKEND_DSTATE() ( \
1049 trace_event_get_state_dynamic_by_id(TRACE_ASPEED_TIMER_SET_CTRL2) || \
1050 false)
1051
1052static inline void _nocheck__trace_aspeed_timer_set_ctrl2(uint32_t value)
1053{
1054 if (trace_event_get_state(TRACE_ASPEED_TIMER_SET_CTRL2) && qemu_loglevel_mask(LOG_TRACE)) {
1055 struct timeval _now;
1056 gettimeofday(&_now, NULL);
1057 qemu_log("%d@%zu.%06zu:aspeed_timer_set_ctrl2 " "Value: 0x%" PRIx32 "\n",
1058 qemu_get_thread_id(),
1059 (size_t)_now.tv_sec, (size_t)_now.tv_usec
1060 , value);
1061 }
1062}
1063
1064static inline void trace_aspeed_timer_set_ctrl2(uint32_t value)
1065{
1066 if (true) {
1067 _nocheck__trace_aspeed_timer_set_ctrl2(value);
1068 }
1069}
1070
1071#define TRACE_ASPEED_TIMER_SET_VALUE_BACKEND_DSTATE() ( \
1072 trace_event_get_state_dynamic_by_id(TRACE_ASPEED_TIMER_SET_VALUE) || \
1073 false)
1074
1075static inline void _nocheck__trace_aspeed_timer_set_value(int timer, int reg, uint32_t value)
1076{
1077 if (trace_event_get_state(TRACE_ASPEED_TIMER_SET_VALUE) && qemu_loglevel_mask(LOG_TRACE)) {
1078 struct timeval _now;
1079 gettimeofday(&_now, NULL);
1080 qemu_log("%d@%zu.%06zu:aspeed_timer_set_value " "Timer %d register %d: 0x%" PRIx32 "\n",
1081 qemu_get_thread_id(),
1082 (size_t)_now.tv_sec, (size_t)_now.tv_usec
1083 , timer, reg, value);
1084 }
1085}
1086
1087static inline void trace_aspeed_timer_set_value(int timer, int reg, uint32_t value)
1088{
1089 if (true) {
1090 _nocheck__trace_aspeed_timer_set_value(timer, reg, value);
1091 }
1092}
1093
1094#define TRACE_ASPEED_TIMER_READ_BACKEND_DSTATE() ( \
1095 trace_event_get_state_dynamic_by_id(TRACE_ASPEED_TIMER_READ) || \
1096 false)
1097
1098static inline void _nocheck__trace_aspeed_timer_read(uint64_t offset, unsigned size, uint64_t value)
1099{
1100 if (trace_event_get_state(TRACE_ASPEED_TIMER_READ) && qemu_loglevel_mask(LOG_TRACE)) {
1101 struct timeval _now;
1102 gettimeofday(&_now, NULL);
1103 qemu_log("%d@%zu.%06zu:aspeed_timer_read " "From 0x%" PRIx64 ": of size %u: 0x%" PRIx64 "\n",
1104 qemu_get_thread_id(),
1105 (size_t)_now.tv_sec, (size_t)_now.tv_usec
1106 , offset, size, value);
1107 }
1108}
1109
1110static inline void trace_aspeed_timer_read(uint64_t offset, unsigned size, uint64_t value)
1111{
1112 if (true) {
1113 _nocheck__trace_aspeed_timer_read(offset, size, value);
1114 }
1115}
1116
1117#define TRACE_SYSTICK_RELOAD_BACKEND_DSTATE() ( \
1118 trace_event_get_state_dynamic_by_id(TRACE_SYSTICK_RELOAD) || \
1119 false)
1120
1121static inline void _nocheck__trace_systick_reload(void)
1122{
1123 if (trace_event_get_state(TRACE_SYSTICK_RELOAD) && qemu_loglevel_mask(LOG_TRACE)) {
1124 struct timeval _now;
1125 gettimeofday(&_now, NULL);
1126 qemu_log("%d@%zu.%06zu:systick_reload " "systick reload" "\n",
1127 qemu_get_thread_id(),
1128 (size_t)_now.tv_sec, (size_t)_now.tv_usec
1129 );
1130 }
1131}
1132
1133static inline void trace_systick_reload(void)
1134{
1135 if (true) {
1136 _nocheck__trace_systick_reload();
1137 }
1138}
1139
1140#define TRACE_SYSTICK_TIMER_TICK_BACKEND_DSTATE() ( \
1141 trace_event_get_state_dynamic_by_id(TRACE_SYSTICK_TIMER_TICK) || \
1142 false)
1143
1144static inline void _nocheck__trace_systick_timer_tick(void)
1145{
1146 if (trace_event_get_state(TRACE_SYSTICK_TIMER_TICK) && qemu_loglevel_mask(LOG_TRACE)) {
1147 struct timeval _now;
1148 gettimeofday(&_now, NULL);
1149 qemu_log("%d@%zu.%06zu:systick_timer_tick " "systick reload" "\n",
1150 qemu_get_thread_id(),
1151 (size_t)_now.tv_sec, (size_t)_now.tv_usec
1152 );
1153 }
1154}
1155
1156static inline void trace_systick_timer_tick(void)
1157{
1158 if (true) {
1159 _nocheck__trace_systick_timer_tick();
1160 }
1161}
1162
1163#define TRACE_SYSTICK_READ_BACKEND_DSTATE() ( \
1164 trace_event_get_state_dynamic_by_id(TRACE_SYSTICK_READ) || \
1165 false)
1166
1167static inline void _nocheck__trace_systick_read(uint64_t addr, uint32_t value, unsigned size)
1168{
1169 if (trace_event_get_state(TRACE_SYSTICK_READ) && qemu_loglevel_mask(LOG_TRACE)) {
1170 struct timeval _now;
1171 gettimeofday(&_now, NULL);
1172 qemu_log("%d@%zu.%06zu:systick_read " "systick read addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u" "\n",
1173 qemu_get_thread_id(),
1174 (size_t)_now.tv_sec, (size_t)_now.tv_usec
1175 , addr, value, size);
1176 }
1177}
1178
1179static inline void trace_systick_read(uint64_t addr, uint32_t value, unsigned size)
1180{
1181 if (true) {
1182 _nocheck__trace_systick_read(addr, value, size);
1183 }
1184}
1185
1186#define TRACE_SYSTICK_WRITE_BACKEND_DSTATE() ( \
1187 trace_event_get_state_dynamic_by_id(TRACE_SYSTICK_WRITE) || \
1188 false)
1189
1190static inline void _nocheck__trace_systick_write(uint64_t addr, uint32_t value, unsigned size)
1191{
1192 if (trace_event_get_state(TRACE_SYSTICK_WRITE) && qemu_loglevel_mask(LOG_TRACE)) {
1193 struct timeval _now;
1194 gettimeofday(&_now, NULL);
1195 qemu_log("%d@%zu.%06zu:systick_write " "systick write addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u" "\n",
1196 qemu_get_thread_id(),
1197 (size_t)_now.tv_sec, (size_t)_now.tv_usec
1198 , addr, value, size);
1199 }
1200}
1201
1202static inline void trace_systick_write(uint64_t addr, uint32_t value, unsigned size)
1203{
1204 if (true) {
1205 _nocheck__trace_systick_write(addr, value, size);
1206 }
1207}
1208
1209#define TRACE_CMSDK_APB_TIMER_READ_BACKEND_DSTATE() ( \
1210 trace_event_get_state_dynamic_by_id(TRACE_CMSDK_APB_TIMER_READ) || \
1211 false)
1212
1213static inline void _nocheck__trace_cmsdk_apb_timer_read(uint64_t offset, uint64_t data, unsigned size)
1214{
1215 if (trace_event_get_state(TRACE_CMSDK_APB_TIMER_READ) && qemu_loglevel_mask(LOG_TRACE)) {
1216 struct timeval _now;
1217 gettimeofday(&_now, NULL);
1218 qemu_log("%d@%zu.%06zu:cmsdk_apb_timer_read " "CMSDK APB timer read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" "\n",
1219 qemu_get_thread_id(),
1220 (size_t)_now.tv_sec, (size_t)_now.tv_usec
1221 , offset, data, size);
1222 }
1223}
1224
1225static inline void trace_cmsdk_apb_timer_read(uint64_t offset, uint64_t data, unsigned size)
1226{
1227 if (true) {
1228 _nocheck__trace_cmsdk_apb_timer_read(offset, data, size);
1229 }
1230}
1231
1232#define TRACE_CMSDK_APB_TIMER_WRITE_BACKEND_DSTATE() ( \
1233 trace_event_get_state_dynamic_by_id(TRACE_CMSDK_APB_TIMER_WRITE) || \
1234 false)
1235
1236static inline void _nocheck__trace_cmsdk_apb_timer_write(uint64_t offset, uint64_t data, unsigned size)
1237{
1238 if (trace_event_get_state(TRACE_CMSDK_APB_TIMER_WRITE) && qemu_loglevel_mask(LOG_TRACE)) {
1239 struct timeval _now;
1240 gettimeofday(&_now, NULL);
1241 qemu_log("%d@%zu.%06zu:cmsdk_apb_timer_write " "CMSDK APB timer write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" "\n",
1242 qemu_get_thread_id(),
1243 (size_t)_now.tv_sec, (size_t)_now.tv_usec
1244 , offset, data, size);
1245 }
1246}
1247
1248static inline void trace_cmsdk_apb_timer_write(uint64_t offset, uint64_t data, unsigned size)
1249{
1250 if (true) {
1251 _nocheck__trace_cmsdk_apb_timer_write(offset, data, size);
1252 }
1253}
1254
1255#define TRACE_CMSDK_APB_TIMER_RESET_BACKEND_DSTATE() ( \
1256 trace_event_get_state_dynamic_by_id(TRACE_CMSDK_APB_TIMER_RESET) || \
1257 false)
1258
1259static inline void _nocheck__trace_cmsdk_apb_timer_reset(void)
1260{
1261 if (trace_event_get_state(TRACE_CMSDK_APB_TIMER_RESET) && qemu_loglevel_mask(LOG_TRACE)) {
1262 struct timeval _now;
1263 gettimeofday(&_now, NULL);
1264 qemu_log("%d@%zu.%06zu:cmsdk_apb_timer_reset " "CMSDK APB timer: reset" "\n",
1265 qemu_get_thread_id(),
1266 (size_t)_now.tv_sec, (size_t)_now.tv_usec
1267 );
1268 }
1269}
1270
1271static inline void trace_cmsdk_apb_timer_reset(void)
1272{
1273 if (true) {
1274 _nocheck__trace_cmsdk_apb_timer_reset();
1275 }
1276}
1277
1278#define TRACE_CMSDK_APB_DUALTIMER_READ_BACKEND_DSTATE() ( \
1279 trace_event_get_state_dynamic_by_id(TRACE_CMSDK_APB_DUALTIMER_READ) || \
1280 false)
1281
1282static inline void _nocheck__trace_cmsdk_apb_dualtimer_read(uint64_t offset, uint64_t data, unsigned size)
1283{
1284 if (trace_event_get_state(TRACE_CMSDK_APB_DUALTIMER_READ) && qemu_loglevel_mask(LOG_TRACE)) {
1285 struct timeval _now;
1286 gettimeofday(&_now, NULL);
1287 qemu_log("%d@%zu.%06zu:cmsdk_apb_dualtimer_read " "CMSDK APB dualtimer read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" "\n",
1288 qemu_get_thread_id(),
1289 (size_t)_now.tv_sec, (size_t)_now.tv_usec
1290 , offset, data, size);
1291 }
1292}
1293
1294static inline void trace_cmsdk_apb_dualtimer_read(uint64_t offset, uint64_t data, unsigned size)
1295{
1296 if (true) {
1297 _nocheck__trace_cmsdk_apb_dualtimer_read(offset, data, size);
1298 }
1299}
1300
1301#define TRACE_CMSDK_APB_DUALTIMER_WRITE_BACKEND_DSTATE() ( \
1302 trace_event_get_state_dynamic_by_id(TRACE_CMSDK_APB_DUALTIMER_WRITE) || \
1303 false)
1304
1305static inline void _nocheck__trace_cmsdk_apb_dualtimer_write(uint64_t offset, uint64_t data, unsigned size)
1306{
1307 if (trace_event_get_state(TRACE_CMSDK_APB_DUALTIMER_WRITE) && qemu_loglevel_mask(LOG_TRACE)) {
1308 struct timeval _now;
1309 gettimeofday(&_now, NULL);
1310 qemu_log("%d@%zu.%06zu:cmsdk_apb_dualtimer_write " "CMSDK APB dualtimer write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" "\n",
1311 qemu_get_thread_id(),
1312 (size_t)_now.tv_sec, (size_t)_now.tv_usec
1313 , offset, data, size);
1314 }
1315}
1316
1317static inline void trace_cmsdk_apb_dualtimer_write(uint64_t offset, uint64_t data, unsigned size)
1318{
1319 if (true) {
1320 _nocheck__trace_cmsdk_apb_dualtimer_write(offset, data, size);
1321 }
1322}
1323
1324#define TRACE_CMSDK_APB_DUALTIMER_RESET_BACKEND_DSTATE() ( \
1325 trace_event_get_state_dynamic_by_id(TRACE_CMSDK_APB_DUALTIMER_RESET) || \
1326 false)
1327
1328static inline void _nocheck__trace_cmsdk_apb_dualtimer_reset(void)
1329{
1330 if (trace_event_get_state(TRACE_CMSDK_APB_DUALTIMER_RESET) && qemu_loglevel_mask(LOG_TRACE)) {
1331 struct timeval _now;
1332 gettimeofday(&_now, NULL);
1333 qemu_log("%d@%zu.%06zu:cmsdk_apb_dualtimer_reset " "CMSDK APB dualtimer: reset" "\n",
1334 qemu_get_thread_id(),
1335 (size_t)_now.tv_sec, (size_t)_now.tv_usec
1336 );
1337 }
1338}
1339
1340static inline void trace_cmsdk_apb_dualtimer_reset(void)
1341{
1342 if (true) {
1343 _nocheck__trace_cmsdk_apb_dualtimer_reset();
1344 }
1345}
1346
1347#define TRACE_ASPEED_RTC_READ_BACKEND_DSTATE() ( \
1348 trace_event_get_state_dynamic_by_id(TRACE_ASPEED_RTC_READ) || \
1349 false)
1350
1351static inline void _nocheck__trace_aspeed_rtc_read(uint64_t addr, uint64_t value)
1352{
1353 if (trace_event_get_state(TRACE_ASPEED_RTC_READ) && qemu_loglevel_mask(LOG_TRACE)) {
1354 struct timeval _now;
1355 gettimeofday(&_now, NULL);
1356 qemu_log("%d@%zu.%06zu:aspeed_rtc_read " "addr 0x%02" PRIx64 " value 0x%08" PRIx64 "\n",
1357 qemu_get_thread_id(),
1358 (size_t)_now.tv_sec, (size_t)_now.tv_usec
1359 , addr, value);
1360 }
1361}
1362
1363static inline void trace_aspeed_rtc_read(uint64_t addr, uint64_t value)
1364{
1365 if (true) {
1366 _nocheck__trace_aspeed_rtc_read(addr, value);
1367 }
1368}
1369
1370#define TRACE_ASPEED_RTC_WRITE_BACKEND_DSTATE() ( \
1371 trace_event_get_state_dynamic_by_id(TRACE_ASPEED_RTC_WRITE) || \
1372 false)
1373
1374static inline void _nocheck__trace_aspeed_rtc_write(uint64_t addr, uint64_t value)
1375{
1376 if (trace_event_get_state(TRACE_ASPEED_RTC_WRITE) && qemu_loglevel_mask(LOG_TRACE)) {
1377 struct timeval _now;
1378 gettimeofday(&_now, NULL);
1379 qemu_log("%d@%zu.%06zu:aspeed_rtc_write " "addr 0x%02" PRIx64 " value 0x%08" PRIx64 "\n",
1380 qemu_get_thread_id(),
1381 (size_t)_now.tv_sec, (size_t)_now.tv_usec
1382 , addr, value);
1383 }
1384}
1385
1386static inline void trace_aspeed_rtc_write(uint64_t addr, uint64_t value)
1387{
1388 if (true) {
1389 _nocheck__trace_aspeed_rtc_write(addr, value);
1390 }
1391}
1392
1393#define TRACE_SUN4V_RTC_READ_BACKEND_DSTATE() ( \
1394 trace_event_get_state_dynamic_by_id(TRACE_SUN4V_RTC_READ) || \
1395 false)
1396
1397static inline void _nocheck__trace_sun4v_rtc_read(uint64_t addr, uint64_t value)
1398{
1399 if (trace_event_get_state(TRACE_SUN4V_RTC_READ) && qemu_loglevel_mask(LOG_TRACE)) {
1400 struct timeval _now;
1401 gettimeofday(&_now, NULL);
1402 qemu_log("%d@%zu.%06zu:sun4v_rtc_read " "read: addr 0x%" PRIx64 " value 0x%" PRIx64 "\n",
1403 qemu_get_thread_id(),
1404 (size_t)_now.tv_sec, (size_t)_now.tv_usec
1405 , addr, value);
1406 }
1407}
1408
1409static inline void trace_sun4v_rtc_read(uint64_t addr, uint64_t value)
1410{
1411 if (true) {
1412 _nocheck__trace_sun4v_rtc_read(addr, value);
1413 }
1414}
1415
1416#define TRACE_SUN4V_RTC_WRITE_BACKEND_DSTATE() ( \
1417 trace_event_get_state_dynamic_by_id(TRACE_SUN4V_RTC_WRITE) || \
1418 false)
1419
1420static inline void _nocheck__trace_sun4v_rtc_write(uint64_t addr, uint64_t value)
1421{
1422 if (trace_event_get_state(TRACE_SUN4V_RTC_WRITE) && qemu_loglevel_mask(LOG_TRACE)) {
1423 struct timeval _now;
1424 gettimeofday(&_now, NULL);
1425 qemu_log("%d@%zu.%06zu:sun4v_rtc_write " "write: addr 0x%" PRIx64 " value 0x%" PRIx64 "\n",
1426 qemu_get_thread_id(),
1427 (size_t)_now.tv_sec, (size_t)_now.tv_usec
1428 , addr, value);
1429 }
1430}
1431
1432static inline void trace_sun4v_rtc_write(uint64_t addr, uint64_t value)
1433{
1434 if (true) {
1435 _nocheck__trace_sun4v_rtc_write(addr, value);
1436 }
1437}
1438
1439#define TRACE_XLNX_ZYNQMP_RTC_GETTIME_BACKEND_DSTATE() ( \
1440 trace_event_get_state_dynamic_by_id(TRACE_XLNX_ZYNQMP_RTC_GETTIME) || \
1441 false)
1442
1443static inline void _nocheck__trace_xlnx_zynqmp_rtc_gettime(int year, int month, int day, int hour, int min, int sec)
1444{
1445 if (trace_event_get_state(TRACE_XLNX_ZYNQMP_RTC_GETTIME) && qemu_loglevel_mask(LOG_TRACE)) {
1446 struct timeval _now;
1447 gettimeofday(&_now, NULL);
1448 qemu_log("%d@%zu.%06zu:xlnx_zynqmp_rtc_gettime " "Get time from host: %d-%d-%d %2d:%02d:%02d" "\n",
1449 qemu_get_thread_id(),
1450 (size_t)_now.tv_sec, (size_t)_now.tv_usec
1451 , year, month, day, hour, min, sec);
1452 }
1453}
1454
1455static inline void trace_xlnx_zynqmp_rtc_gettime(int year, int month, int day, int hour, int min, int sec)
1456{
1457 if (true) {
1458 _nocheck__trace_xlnx_zynqmp_rtc_gettime(year, month, day, hour, min, sec);
1459 }
1460}
1461
1462#define TRACE_NRF51_TIMER_READ_BACKEND_DSTATE() ( \
1463 trace_event_get_state_dynamic_by_id(TRACE_NRF51_TIMER_READ) || \
1464 false)
1465
1466static inline void _nocheck__trace_nrf51_timer_read(uint64_t addr, uint32_t value, unsigned size)
1467{
1468 if (trace_event_get_state(TRACE_NRF51_TIMER_READ) && qemu_loglevel_mask(LOG_TRACE)) {
1469 struct timeval _now;
1470 gettimeofday(&_now, NULL);
1471 qemu_log("%d@%zu.%06zu:nrf51_timer_read " "read addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u" "\n",
1472 qemu_get_thread_id(),
1473 (size_t)_now.tv_sec, (size_t)_now.tv_usec
1474 , addr, value, size);
1475 }
1476}
1477
1478static inline void trace_nrf51_timer_read(uint64_t addr, uint32_t value, unsigned size)
1479{
1480 if (true) {
1481 _nocheck__trace_nrf51_timer_read(addr, value, size);
1482 }
1483}
1484
1485#define TRACE_NRF51_TIMER_WRITE_BACKEND_DSTATE() ( \
1486 trace_event_get_state_dynamic_by_id(TRACE_NRF51_TIMER_WRITE) || \
1487 false)
1488
1489static inline void _nocheck__trace_nrf51_timer_write(uint64_t addr, uint32_t value, unsigned size)
1490{
1491 if (trace_event_get_state(TRACE_NRF51_TIMER_WRITE) && qemu_loglevel_mask(LOG_TRACE)) {
1492 struct timeval _now;
1493 gettimeofday(&_now, NULL);
1494 qemu_log("%d@%zu.%06zu:nrf51_timer_write " "write addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u" "\n",
1495 qemu_get_thread_id(),
1496 (size_t)_now.tv_sec, (size_t)_now.tv_usec
1497 , addr, value, size);
1498 }
1499}
1500
1501static inline void trace_nrf51_timer_write(uint64_t addr, uint32_t value, unsigned size)
1502{
1503 if (true) {
1504 _nocheck__trace_nrf51_timer_write(addr, value, size);
1505 }
1506}
1507
1508#define TRACE_PL031_IRQ_STATE_BACKEND_DSTATE() ( \
1509 trace_event_get_state_dynamic_by_id(TRACE_PL031_IRQ_STATE) || \
1510 false)
1511
1512static inline void _nocheck__trace_pl031_irq_state(int level)
1513{
1514 if (trace_event_get_state(TRACE_PL031_IRQ_STATE) && qemu_loglevel_mask(LOG_TRACE)) {
1515 struct timeval _now;
1516 gettimeofday(&_now, NULL);
1517 qemu_log("%d@%zu.%06zu:pl031_irq_state " "irq state %d" "\n",
1518 qemu_get_thread_id(),
1519 (size_t)_now.tv_sec, (size_t)_now.tv_usec
1520 , level);
1521 }
1522}
1523
1524static inline void trace_pl031_irq_state(int level)
1525{
1526 if (true) {
1527 _nocheck__trace_pl031_irq_state(level);
1528 }
1529}
1530
1531#define TRACE_PL031_READ_BACKEND_DSTATE() ( \
1532 trace_event_get_state_dynamic_by_id(TRACE_PL031_READ) || \
1533 false)
1534
1535static inline void _nocheck__trace_pl031_read(uint32_t addr, uint32_t value)
1536{
1537 if (trace_event_get_state(TRACE_PL031_READ) && qemu_loglevel_mask(LOG_TRACE)) {
1538 struct timeval _now;
1539 gettimeofday(&_now, NULL);
1540 qemu_log("%d@%zu.%06zu:pl031_read " "addr 0x%08x value 0x%08x" "\n",
1541 qemu_get_thread_id(),
1542 (size_t)_now.tv_sec, (size_t)_now.tv_usec
1543 , addr, value);
1544 }
1545}
1546
1547static inline void trace_pl031_read(uint32_t addr, uint32_t value)
1548{
1549 if (true) {
1550 _nocheck__trace_pl031_read(addr, value);
1551 }
1552}
1553
1554#define TRACE_PL031_WRITE_BACKEND_DSTATE() ( \
1555 trace_event_get_state_dynamic_by_id(TRACE_PL031_WRITE) || \
1556 false)
1557
1558static inline void _nocheck__trace_pl031_write(uint32_t addr, uint32_t value)
1559{
1560 if (trace_event_get_state(TRACE_PL031_WRITE) && qemu_loglevel_mask(LOG_TRACE)) {
1561 struct timeval _now;
1562 gettimeofday(&_now, NULL);
1563 qemu_log("%d@%zu.%06zu:pl031_write " "addr 0x%08x value 0x%08x" "\n",
1564 qemu_get_thread_id(),
1565 (size_t)_now.tv_sec, (size_t)_now.tv_usec
1566 , addr, value);
1567 }
1568}
1569
1570static inline void trace_pl031_write(uint32_t addr, uint32_t value)
1571{
1572 if (true) {
1573 _nocheck__trace_pl031_write(addr, value);
1574 }
1575}
1576
1577#define TRACE_PL031_ALARM_RAISED_BACKEND_DSTATE() ( \
1578 trace_event_get_state_dynamic_by_id(TRACE_PL031_ALARM_RAISED) || \
1579 false)
1580
1581static inline void _nocheck__trace_pl031_alarm_raised(void)
1582{
1583 if (trace_event_get_state(TRACE_PL031_ALARM_RAISED) && qemu_loglevel_mask(LOG_TRACE)) {
1584 struct timeval _now;
1585 gettimeofday(&_now, NULL);
1586 qemu_log("%d@%zu.%06zu:pl031_alarm_raised " "alarm raised" "\n",
1587 qemu_get_thread_id(),
1588 (size_t)_now.tv_sec, (size_t)_now.tv_usec
1589 );
1590 }
1591}
1592
1593static inline void trace_pl031_alarm_raised(void)
1594{
1595 if (true) {
1596 _nocheck__trace_pl031_alarm_raised();
1597 }
1598}
1599
1600#define TRACE_PL031_SET_ALARM_BACKEND_DSTATE() ( \
1601 trace_event_get_state_dynamic_by_id(TRACE_PL031_SET_ALARM) || \
1602 false)
1603
1604static inline void _nocheck__trace_pl031_set_alarm(uint32_t ticks)
1605{
1606 if (trace_event_get_state(TRACE_PL031_SET_ALARM) && qemu_loglevel_mask(LOG_TRACE)) {
1607 struct timeval _now;
1608 gettimeofday(&_now, NULL);
1609 qemu_log("%d@%zu.%06zu:pl031_set_alarm " "alarm set for %u ticks" "\n",
1610 qemu_get_thread_id(),
1611 (size_t)_now.tv_sec, (size_t)_now.tv_usec
1612 , ticks);
1613 }
1614}
1615
1616static inline void trace_pl031_set_alarm(uint32_t ticks)
1617{
1618 if (true) {
1619 _nocheck__trace_pl031_set_alarm(ticks);
1620 }
1621}
1622#endif /* TRACE_HW_TIMER_GENERATED_TRACERS_H */
1623