1 | /* This file is autogenerated by tracetool, do not edit. */ |
2 | |
3 | #include "qemu/osdep.h" |
4 | #include "qemu/module.h" |
5 | #include "trace.h" |
6 | |
7 | uint16_t _TRACE_VISIT_FREE_DSTATE; |
8 | uint16_t _TRACE_VISIT_COMPLETE_DSTATE; |
9 | uint16_t _TRACE_VISIT_START_STRUCT_DSTATE; |
10 | uint16_t _TRACE_VISIT_CHECK_STRUCT_DSTATE; |
11 | uint16_t _TRACE_VISIT_END_STRUCT_DSTATE; |
12 | uint16_t _TRACE_VISIT_START_LIST_DSTATE; |
13 | uint16_t _TRACE_VISIT_NEXT_LIST_DSTATE; |
14 | uint16_t _TRACE_VISIT_CHECK_LIST_DSTATE; |
15 | uint16_t _TRACE_VISIT_END_LIST_DSTATE; |
16 | uint16_t _TRACE_VISIT_START_ALTERNATE_DSTATE; |
17 | uint16_t _TRACE_VISIT_END_ALTERNATE_DSTATE; |
18 | uint16_t _TRACE_VISIT_OPTIONAL_DSTATE; |
19 | uint16_t _TRACE_VISIT_TYPE_ENUM_DSTATE; |
20 | uint16_t _TRACE_VISIT_TYPE_INT_DSTATE; |
21 | uint16_t _TRACE_VISIT_TYPE_UINT8_DSTATE; |
22 | uint16_t _TRACE_VISIT_TYPE_UINT16_DSTATE; |
23 | uint16_t _TRACE_VISIT_TYPE_UINT32_DSTATE; |
24 | uint16_t _TRACE_VISIT_TYPE_UINT64_DSTATE; |
25 | uint16_t _TRACE_VISIT_TYPE_INT8_DSTATE; |
26 | uint16_t _TRACE_VISIT_TYPE_INT16_DSTATE; |
27 | uint16_t _TRACE_VISIT_TYPE_INT32_DSTATE; |
28 | uint16_t _TRACE_VISIT_TYPE_INT64_DSTATE; |
29 | uint16_t _TRACE_VISIT_TYPE_SIZE_DSTATE; |
30 | uint16_t _TRACE_VISIT_TYPE_BOOL_DSTATE; |
31 | uint16_t _TRACE_VISIT_TYPE_STR_DSTATE; |
32 | uint16_t _TRACE_VISIT_TYPE_NUMBER_DSTATE; |
33 | uint16_t _TRACE_VISIT_TYPE_ANY_DSTATE; |
34 | uint16_t _TRACE_VISIT_TYPE_NULL_DSTATE; |
35 | TraceEvent _TRACE_VISIT_FREE_EVENT = { |
36 | .id = 0, |
37 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
38 | .name = "visit_free" , |
39 | .sstate = TRACE_VISIT_FREE_ENABLED, |
40 | .dstate = &_TRACE_VISIT_FREE_DSTATE |
41 | }; |
42 | TraceEvent _TRACE_VISIT_COMPLETE_EVENT = { |
43 | .id = 0, |
44 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
45 | .name = "visit_complete" , |
46 | .sstate = TRACE_VISIT_COMPLETE_ENABLED, |
47 | .dstate = &_TRACE_VISIT_COMPLETE_DSTATE |
48 | }; |
49 | TraceEvent _TRACE_VISIT_START_STRUCT_EVENT = { |
50 | .id = 0, |
51 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
52 | .name = "visit_start_struct" , |
53 | .sstate = TRACE_VISIT_START_STRUCT_ENABLED, |
54 | .dstate = &_TRACE_VISIT_START_STRUCT_DSTATE |
55 | }; |
56 | TraceEvent _TRACE_VISIT_CHECK_STRUCT_EVENT = { |
57 | .id = 0, |
58 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
59 | .name = "visit_check_struct" , |
60 | .sstate = TRACE_VISIT_CHECK_STRUCT_ENABLED, |
61 | .dstate = &_TRACE_VISIT_CHECK_STRUCT_DSTATE |
62 | }; |
63 | TraceEvent _TRACE_VISIT_END_STRUCT_EVENT = { |
64 | .id = 0, |
65 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
66 | .name = "visit_end_struct" , |
67 | .sstate = TRACE_VISIT_END_STRUCT_ENABLED, |
68 | .dstate = &_TRACE_VISIT_END_STRUCT_DSTATE |
69 | }; |
70 | TraceEvent _TRACE_VISIT_START_LIST_EVENT = { |
71 | .id = 0, |
72 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
73 | .name = "visit_start_list" , |
74 | .sstate = TRACE_VISIT_START_LIST_ENABLED, |
75 | .dstate = &_TRACE_VISIT_START_LIST_DSTATE |
76 | }; |
77 | TraceEvent _TRACE_VISIT_NEXT_LIST_EVENT = { |
78 | .id = 0, |
79 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
80 | .name = "visit_next_list" , |
81 | .sstate = TRACE_VISIT_NEXT_LIST_ENABLED, |
82 | .dstate = &_TRACE_VISIT_NEXT_LIST_DSTATE |
83 | }; |
84 | TraceEvent _TRACE_VISIT_CHECK_LIST_EVENT = { |
85 | .id = 0, |
86 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
87 | .name = "visit_check_list" , |
88 | .sstate = TRACE_VISIT_CHECK_LIST_ENABLED, |
89 | .dstate = &_TRACE_VISIT_CHECK_LIST_DSTATE |
90 | }; |
91 | TraceEvent _TRACE_VISIT_END_LIST_EVENT = { |
92 | .id = 0, |
93 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
94 | .name = "visit_end_list" , |
95 | .sstate = TRACE_VISIT_END_LIST_ENABLED, |
96 | .dstate = &_TRACE_VISIT_END_LIST_DSTATE |
97 | }; |
98 | TraceEvent _TRACE_VISIT_START_ALTERNATE_EVENT = { |
99 | .id = 0, |
100 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
101 | .name = "visit_start_alternate" , |
102 | .sstate = TRACE_VISIT_START_ALTERNATE_ENABLED, |
103 | .dstate = &_TRACE_VISIT_START_ALTERNATE_DSTATE |
104 | }; |
105 | TraceEvent _TRACE_VISIT_END_ALTERNATE_EVENT = { |
106 | .id = 0, |
107 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
108 | .name = "visit_end_alternate" , |
109 | .sstate = TRACE_VISIT_END_ALTERNATE_ENABLED, |
110 | .dstate = &_TRACE_VISIT_END_ALTERNATE_DSTATE |
111 | }; |
112 | TraceEvent _TRACE_VISIT_OPTIONAL_EVENT = { |
113 | .id = 0, |
114 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
115 | .name = "visit_optional" , |
116 | .sstate = TRACE_VISIT_OPTIONAL_ENABLED, |
117 | .dstate = &_TRACE_VISIT_OPTIONAL_DSTATE |
118 | }; |
119 | TraceEvent _TRACE_VISIT_TYPE_ENUM_EVENT = { |
120 | .id = 0, |
121 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
122 | .name = "visit_type_enum" , |
123 | .sstate = TRACE_VISIT_TYPE_ENUM_ENABLED, |
124 | .dstate = &_TRACE_VISIT_TYPE_ENUM_DSTATE |
125 | }; |
126 | TraceEvent _TRACE_VISIT_TYPE_INT_EVENT = { |
127 | .id = 0, |
128 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
129 | .name = "visit_type_int" , |
130 | .sstate = TRACE_VISIT_TYPE_INT_ENABLED, |
131 | .dstate = &_TRACE_VISIT_TYPE_INT_DSTATE |
132 | }; |
133 | TraceEvent _TRACE_VISIT_TYPE_UINT8_EVENT = { |
134 | .id = 0, |
135 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
136 | .name = "visit_type_uint8" , |
137 | .sstate = TRACE_VISIT_TYPE_UINT8_ENABLED, |
138 | .dstate = &_TRACE_VISIT_TYPE_UINT8_DSTATE |
139 | }; |
140 | TraceEvent _TRACE_VISIT_TYPE_UINT16_EVENT = { |
141 | .id = 0, |
142 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
143 | .name = "visit_type_uint16" , |
144 | .sstate = TRACE_VISIT_TYPE_UINT16_ENABLED, |
145 | .dstate = &_TRACE_VISIT_TYPE_UINT16_DSTATE |
146 | }; |
147 | TraceEvent _TRACE_VISIT_TYPE_UINT32_EVENT = { |
148 | .id = 0, |
149 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
150 | .name = "visit_type_uint32" , |
151 | .sstate = TRACE_VISIT_TYPE_UINT32_ENABLED, |
152 | .dstate = &_TRACE_VISIT_TYPE_UINT32_DSTATE |
153 | }; |
154 | TraceEvent _TRACE_VISIT_TYPE_UINT64_EVENT = { |
155 | .id = 0, |
156 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
157 | .name = "visit_type_uint64" , |
158 | .sstate = TRACE_VISIT_TYPE_UINT64_ENABLED, |
159 | .dstate = &_TRACE_VISIT_TYPE_UINT64_DSTATE |
160 | }; |
161 | TraceEvent _TRACE_VISIT_TYPE_INT8_EVENT = { |
162 | .id = 0, |
163 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
164 | .name = "visit_type_int8" , |
165 | .sstate = TRACE_VISIT_TYPE_INT8_ENABLED, |
166 | .dstate = &_TRACE_VISIT_TYPE_INT8_DSTATE |
167 | }; |
168 | TraceEvent _TRACE_VISIT_TYPE_INT16_EVENT = { |
169 | .id = 0, |
170 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
171 | .name = "visit_type_int16" , |
172 | .sstate = TRACE_VISIT_TYPE_INT16_ENABLED, |
173 | .dstate = &_TRACE_VISIT_TYPE_INT16_DSTATE |
174 | }; |
175 | TraceEvent _TRACE_VISIT_TYPE_INT32_EVENT = { |
176 | .id = 0, |
177 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
178 | .name = "visit_type_int32" , |
179 | .sstate = TRACE_VISIT_TYPE_INT32_ENABLED, |
180 | .dstate = &_TRACE_VISIT_TYPE_INT32_DSTATE |
181 | }; |
182 | TraceEvent _TRACE_VISIT_TYPE_INT64_EVENT = { |
183 | .id = 0, |
184 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
185 | .name = "visit_type_int64" , |
186 | .sstate = TRACE_VISIT_TYPE_INT64_ENABLED, |
187 | .dstate = &_TRACE_VISIT_TYPE_INT64_DSTATE |
188 | }; |
189 | TraceEvent _TRACE_VISIT_TYPE_SIZE_EVENT = { |
190 | .id = 0, |
191 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
192 | .name = "visit_type_size" , |
193 | .sstate = TRACE_VISIT_TYPE_SIZE_ENABLED, |
194 | .dstate = &_TRACE_VISIT_TYPE_SIZE_DSTATE |
195 | }; |
196 | TraceEvent _TRACE_VISIT_TYPE_BOOL_EVENT = { |
197 | .id = 0, |
198 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
199 | .name = "visit_type_bool" , |
200 | .sstate = TRACE_VISIT_TYPE_BOOL_ENABLED, |
201 | .dstate = &_TRACE_VISIT_TYPE_BOOL_DSTATE |
202 | }; |
203 | TraceEvent _TRACE_VISIT_TYPE_STR_EVENT = { |
204 | .id = 0, |
205 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
206 | .name = "visit_type_str" , |
207 | .sstate = TRACE_VISIT_TYPE_STR_ENABLED, |
208 | .dstate = &_TRACE_VISIT_TYPE_STR_DSTATE |
209 | }; |
210 | TraceEvent _TRACE_VISIT_TYPE_NUMBER_EVENT = { |
211 | .id = 0, |
212 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
213 | .name = "visit_type_number" , |
214 | .sstate = TRACE_VISIT_TYPE_NUMBER_ENABLED, |
215 | .dstate = &_TRACE_VISIT_TYPE_NUMBER_DSTATE |
216 | }; |
217 | TraceEvent _TRACE_VISIT_TYPE_ANY_EVENT = { |
218 | .id = 0, |
219 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
220 | .name = "visit_type_any" , |
221 | .sstate = TRACE_VISIT_TYPE_ANY_ENABLED, |
222 | .dstate = &_TRACE_VISIT_TYPE_ANY_DSTATE |
223 | }; |
224 | TraceEvent _TRACE_VISIT_TYPE_NULL_EVENT = { |
225 | .id = 0, |
226 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
227 | .name = "visit_type_null" , |
228 | .sstate = TRACE_VISIT_TYPE_NULL_ENABLED, |
229 | .dstate = &_TRACE_VISIT_TYPE_NULL_DSTATE |
230 | }; |
231 | TraceEvent *qapi_trace_events[] = { |
232 | &_TRACE_VISIT_FREE_EVENT, |
233 | &_TRACE_VISIT_COMPLETE_EVENT, |
234 | &_TRACE_VISIT_START_STRUCT_EVENT, |
235 | &_TRACE_VISIT_CHECK_STRUCT_EVENT, |
236 | &_TRACE_VISIT_END_STRUCT_EVENT, |
237 | &_TRACE_VISIT_START_LIST_EVENT, |
238 | &_TRACE_VISIT_NEXT_LIST_EVENT, |
239 | &_TRACE_VISIT_CHECK_LIST_EVENT, |
240 | &_TRACE_VISIT_END_LIST_EVENT, |
241 | &_TRACE_VISIT_START_ALTERNATE_EVENT, |
242 | &_TRACE_VISIT_END_ALTERNATE_EVENT, |
243 | &_TRACE_VISIT_OPTIONAL_EVENT, |
244 | &_TRACE_VISIT_TYPE_ENUM_EVENT, |
245 | &_TRACE_VISIT_TYPE_INT_EVENT, |
246 | &_TRACE_VISIT_TYPE_UINT8_EVENT, |
247 | &_TRACE_VISIT_TYPE_UINT16_EVENT, |
248 | &_TRACE_VISIT_TYPE_UINT32_EVENT, |
249 | &_TRACE_VISIT_TYPE_UINT64_EVENT, |
250 | &_TRACE_VISIT_TYPE_INT8_EVENT, |
251 | &_TRACE_VISIT_TYPE_INT16_EVENT, |
252 | &_TRACE_VISIT_TYPE_INT32_EVENT, |
253 | &_TRACE_VISIT_TYPE_INT64_EVENT, |
254 | &_TRACE_VISIT_TYPE_SIZE_EVENT, |
255 | &_TRACE_VISIT_TYPE_BOOL_EVENT, |
256 | &_TRACE_VISIT_TYPE_STR_EVENT, |
257 | &_TRACE_VISIT_TYPE_NUMBER_EVENT, |
258 | &_TRACE_VISIT_TYPE_ANY_EVENT, |
259 | &_TRACE_VISIT_TYPE_NULL_EVENT, |
260 | NULL, |
261 | }; |
262 | |
263 | static void trace_qapi_register_events(void) |
264 | { |
265 | trace_event_register_group(qapi_trace_events); |
266 | } |
267 | trace_init(trace_qapi_register_events) |
268 | |