1#ifndef CAPSTONE_ARM64_H
2#define CAPSTONE_ARM64_H
3
4/* Capstone Disassembly Engine */
5/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
6
7#ifdef __cplusplus
8extern "C" {
9#endif
10
11#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
12#include <stdint.h>
13#endif
14
15#include "platform.h"
16
17#ifdef _MSC_VER
18#pragma warning(disable:4201)
19#endif
20
21//> ARM64 shift type
22typedef enum arm64_shifter {
23 ARM64_SFT_INVALID = 0,
24 ARM64_SFT_LSL = 1,
25 ARM64_SFT_MSL = 2,
26 ARM64_SFT_LSR = 3,
27 ARM64_SFT_ASR = 4,
28 ARM64_SFT_ROR = 5,
29} arm64_shifter;
30
31//> ARM64 extender type
32typedef enum arm64_extender {
33 ARM64_EXT_INVALID = 0,
34 ARM64_EXT_UXTB = 1,
35 ARM64_EXT_UXTH = 2,
36 ARM64_EXT_UXTW = 3,
37 ARM64_EXT_UXTX = 4,
38 ARM64_EXT_SXTB = 5,
39 ARM64_EXT_SXTH = 6,
40 ARM64_EXT_SXTW = 7,
41 ARM64_EXT_SXTX = 8,
42} arm64_extender;
43
44//> ARM64 condition code
45typedef enum arm64_cc {
46 ARM64_CC_INVALID = 0,
47 ARM64_CC_EQ = 1, // Equal
48 ARM64_CC_NE = 2, // Not equal: Not equal, or unordered
49 ARM64_CC_HS = 3, // Unsigned higher or same: >, ==, or unordered
50 ARM64_CC_LO = 4, // Unsigned lower or same: Less than
51 ARM64_CC_MI = 5, // Minus, negative: Less than
52 ARM64_CC_PL = 6, // Plus, positive or zero: >, ==, or unordered
53 ARM64_CC_VS = 7, // Overflow: Unordered
54 ARM64_CC_VC = 8, // No overflow: Ordered
55 ARM64_CC_HI = 9, // Unsigned higher: Greater than, or unordered
56 ARM64_CC_LS = 10, // Unsigned lower or same: Less than or equal
57 ARM64_CC_GE = 11, // Greater than or equal: Greater than or equal
58 ARM64_CC_LT = 12, // Less than: Less than, or unordered
59 ARM64_CC_GT = 13, // Signed greater than: Greater than
60 ARM64_CC_LE = 14, // Signed less than or equal: <, ==, or unordered
61 ARM64_CC_AL = 15, // Always (unconditional): Always (unconditional)
62 ARM64_CC_NV = 16, // Always (unconditional): Always (unconditional)
63 // Note the NV exists purely to disassemble 0b1111. Execution
64 // is "always".
65} arm64_cc;
66
67//> System registers
68typedef enum arm64_sysreg {
69 //> System registers for MRS
70 ARM64_SYSREG_INVALID = 0,
71 ARM64_SYSREG_MDCCSR_EL0 = 0x9808, // 10 011 0000 0001 000
72 ARM64_SYSREG_DBGDTRRX_EL0 = 0x9828, // 10 011 0000 0101 000
73 ARM64_SYSREG_MDRAR_EL1 = 0x8080, // 10 000 0001 0000 000
74 ARM64_SYSREG_OSLSR_EL1 = 0x808c, // 10 000 0001 0001 100
75 ARM64_SYSREG_DBGAUTHSTATUS_EL1 = 0x83f6, // 10 000 0111 1110 110
76 ARM64_SYSREG_PMCEID0_EL0 = 0xdce6, // 11 011 1001 1100 110
77 ARM64_SYSREG_PMCEID1_EL0 = 0xdce7, // 11 011 1001 1100 111
78 ARM64_SYSREG_MIDR_EL1 = 0xc000, // 11 000 0000 0000 000
79 ARM64_SYSREG_CCSIDR_EL1 = 0xc800, // 11 001 0000 0000 000
80 ARM64_SYSREG_CLIDR_EL1 = 0xc801, // 11 001 0000 0000 001
81 ARM64_SYSREG_CTR_EL0 = 0xd801, // 11 011 0000 0000 001
82 ARM64_SYSREG_MPIDR_EL1 = 0xc005, // 11 000 0000 0000 101
83 ARM64_SYSREG_REVIDR_EL1 = 0xc006, // 11 000 0000 0000 110
84 ARM64_SYSREG_AIDR_EL1 = 0xc807, // 11 001 0000 0000 111
85 ARM64_SYSREG_DCZID_EL0 = 0xd807, // 11 011 0000 0000 111
86 ARM64_SYSREG_ID_PFR0_EL1 = 0xc008, // 11 000 0000 0001 000
87 ARM64_SYSREG_ID_PFR1_EL1 = 0xc009, // 11 000 0000 0001 001
88 ARM64_SYSREG_ID_DFR0_EL1 = 0xc00a, // 11 000 0000 0001 010
89 ARM64_SYSREG_ID_AFR0_EL1 = 0xc00b, // 11 000 0000 0001 011
90 ARM64_SYSREG_ID_MMFR0_EL1 = 0xc00c, // 11 000 0000 0001 100
91 ARM64_SYSREG_ID_MMFR1_EL1 = 0xc00d, // 11 000 0000 0001 101
92 ARM64_SYSREG_ID_MMFR2_EL1 = 0xc00e, // 11 000 0000 0001 110
93 ARM64_SYSREG_ID_MMFR3_EL1 = 0xc00f, // 11 000 0000 0001 111
94 ARM64_SYSREG_ID_ISAR0_EL1 = 0xc010, // 11 000 0000 0010 000
95 ARM64_SYSREG_ID_ISAR1_EL1 = 0xc011, // 11 000 0000 0010 001
96 ARM64_SYSREG_ID_ISAR2_EL1 = 0xc012, // 11 000 0000 0010 010
97 ARM64_SYSREG_ID_ISAR3_EL1 = 0xc013, // 11 000 0000 0010 011
98 ARM64_SYSREG_ID_ISAR4_EL1 = 0xc014, // 11 000 0000 0010 100
99 ARM64_SYSREG_ID_ISAR5_EL1 = 0xc015, // 11 000 0000 0010 101
100 ARM64_SYSREG_ID_A64PFR0_EL1 = 0xc020, // 11 000 0000 0100 000
101 ARM64_SYSREG_ID_A64PFR1_EL1 = 0xc021, // 11 000 0000 0100 001
102 ARM64_SYSREG_ID_A64DFR0_EL1 = 0xc028, // 11 000 0000 0101 000
103 ARM64_SYSREG_ID_A64DFR1_EL1 = 0xc029, // 11 000 0000 0101 001
104 ARM64_SYSREG_ID_A64AFR0_EL1 = 0xc02c, // 11 000 0000 0101 100
105 ARM64_SYSREG_ID_A64AFR1_EL1 = 0xc02d, // 11 000 0000 0101 101
106 ARM64_SYSREG_ID_A64ISAR0_EL1 = 0xc030, // 11 000 0000 0110 000
107 ARM64_SYSREG_ID_A64ISAR1_EL1 = 0xc031, // 11 000 0000 0110 001
108 ARM64_SYSREG_ID_A64MMFR0_EL1 = 0xc038, // 11 000 0000 0111 000
109 ARM64_SYSREG_ID_A64MMFR1_EL1 = 0xc039, // 11 000 0000 0111 001
110 ARM64_SYSREG_MVFR0_EL1 = 0xc018, // 11 000 0000 0011 000
111 ARM64_SYSREG_MVFR1_EL1 = 0xc019, // 11 000 0000 0011 001
112 ARM64_SYSREG_MVFR2_EL1 = 0xc01a, // 11 000 0000 0011 010
113 ARM64_SYSREG_RVBAR_EL1 = 0xc601, // 11 000 1100 0000 001
114 ARM64_SYSREG_RVBAR_EL2 = 0xe601, // 11 100 1100 0000 001
115 ARM64_SYSREG_RVBAR_EL3 = 0xf601, // 11 110 1100 0000 001
116 ARM64_SYSREG_ISR_EL1 = 0xc608, // 11 000 1100 0001 000
117 ARM64_SYSREG_CNTPCT_EL0 = 0xdf01, // 11 011 1110 0000 001
118 ARM64_SYSREG_CNTVCT_EL0 = 0xdf02, // 11 011 1110 0000 010
119
120 // Trace registers
121 ARM64_SYSREG_TRCSTATR = 0x8818, // 10 001 0000 0011 000
122 ARM64_SYSREG_TRCIDR8 = 0x8806, // 10 001 0000 0000 110
123 ARM64_SYSREG_TRCIDR9 = 0x880e, // 10 001 0000 0001 110
124 ARM64_SYSREG_TRCIDR10 = 0x8816, // 10 001 0000 0010 110
125 ARM64_SYSREG_TRCIDR11 = 0x881e, // 10 001 0000 0011 110
126 ARM64_SYSREG_TRCIDR12 = 0x8826, // 10 001 0000 0100 110
127 ARM64_SYSREG_TRCIDR13 = 0x882e, // 10 001 0000 0101 110
128 ARM64_SYSREG_TRCIDR0 = 0x8847, // 10 001 0000 1000 111
129 ARM64_SYSREG_TRCIDR1 = 0x884f, // 10 001 0000 1001 111
130 ARM64_SYSREG_TRCIDR2 = 0x8857, // 10 001 0000 1010 111
131 ARM64_SYSREG_TRCIDR3 = 0x885f, // 10 001 0000 1011 111
132 ARM64_SYSREG_TRCIDR4 = 0x8867, // 10 001 0000 1100 111
133 ARM64_SYSREG_TRCIDR5 = 0x886f, // 10 001 0000 1101 111
134 ARM64_SYSREG_TRCIDR6 = 0x8877, // 10 001 0000 1110 111
135 ARM64_SYSREG_TRCIDR7 = 0x887f, // 10 001 0000 1111 111
136 ARM64_SYSREG_TRCOSLSR = 0x888c, // 10 001 0001 0001 100
137 ARM64_SYSREG_TRCPDSR = 0x88ac, // 10 001 0001 0101 100
138 ARM64_SYSREG_TRCDEVAFF0 = 0x8bd6, // 10 001 0111 1010 110
139 ARM64_SYSREG_TRCDEVAFF1 = 0x8bde, // 10 001 0111 1011 110
140 ARM64_SYSREG_TRCLSR = 0x8bee, // 10 001 0111 1101 110
141 ARM64_SYSREG_TRCAUTHSTATUS = 0x8bf6, // 10 001 0111 1110 110
142 ARM64_SYSREG_TRCDEVARCH = 0x8bfe, // 10 001 0111 1111 110
143 ARM64_SYSREG_TRCDEVID = 0x8b97, // 10 001 0111 0010 111
144 ARM64_SYSREG_TRCDEVTYPE = 0x8b9f, // 10 001 0111 0011 111
145 ARM64_SYSREG_TRCPIDR4 = 0x8ba7, // 10 001 0111 0100 111
146 ARM64_SYSREG_TRCPIDR5 = 0x8baf, // 10 001 0111 0101 111
147 ARM64_SYSREG_TRCPIDR6 = 0x8bb7, // 10 001 0111 0110 111
148 ARM64_SYSREG_TRCPIDR7 = 0x8bbf, // 10 001 0111 0111 111
149 ARM64_SYSREG_TRCPIDR0 = 0x8bc7, // 10 001 0111 1000 111
150 ARM64_SYSREG_TRCPIDR1 = 0x8bcf, // 10 001 0111 1001 111
151 ARM64_SYSREG_TRCPIDR2 = 0x8bd7, // 10 001 0111 1010 111
152 ARM64_SYSREG_TRCPIDR3 = 0x8bdf, // 10 001 0111 1011 111
153 ARM64_SYSREG_TRCCIDR0 = 0x8be7, // 10 001 0111 1100 111
154 ARM64_SYSREG_TRCCIDR1 = 0x8bef, // 10 001 0111 1101 111
155 ARM64_SYSREG_TRCCIDR2 = 0x8bf7, // 10 001 0111 1110 111
156 ARM64_SYSREG_TRCCIDR3 = 0x8bff, // 10 001 0111 1111 111
157
158 // GICv3 registers
159 ARM64_SYSREG_ICC_IAR1_EL1 = 0xc660, // 11 000 1100 1100 000
160 ARM64_SYSREG_ICC_IAR0_EL1 = 0xc640, // 11 000 1100 1000 000
161 ARM64_SYSREG_ICC_HPPIR1_EL1 = 0xc662, // 11 000 1100 1100 010
162 ARM64_SYSREG_ICC_HPPIR0_EL1 = 0xc642, // 11 000 1100 1000 010
163 ARM64_SYSREG_ICC_RPR_EL1 = 0xc65b, // 11 000 1100 1011 011
164 ARM64_SYSREG_ICH_VTR_EL2 = 0xe659, // 11 100 1100 1011 001
165 ARM64_SYSREG_ICH_EISR_EL2 = 0xe65b, // 11 100 1100 1011 011
166 ARM64_SYSREG_ICH_ELSR_EL2 = 0xe65d, // 11 100 1100 1011 101
167} arm64_sysreg;
168
169typedef enum arm64_msr_reg {
170 //> System registers for MSR
171 ARM64_SYSREG_DBGDTRTX_EL0 = 0x9828, // 10 011 0000 0101 000
172 ARM64_SYSREG_OSLAR_EL1 = 0x8084, // 10 000 0001 0000 100
173 ARM64_SYSREG_PMSWINC_EL0 = 0xdce4, // 11 011 1001 1100 100
174
175 // Trace Registers
176 ARM64_SYSREG_TRCOSLAR = 0x8884, // 10 001 0001 0000 100
177 ARM64_SYSREG_TRCLAR = 0x8be6, // 10 001 0111 1100 110
178
179 // GICv3 registers
180 ARM64_SYSREG_ICC_EOIR1_EL1 = 0xc661, // 11 000 1100 1100 001
181 ARM64_SYSREG_ICC_EOIR0_EL1 = 0xc641, // 11 000 1100 1000 001
182 ARM64_SYSREG_ICC_DIR_EL1 = 0xc659, // 11 000 1100 1011 001
183 ARM64_SYSREG_ICC_SGI1R_EL1 = 0xc65d, // 11 000 1100 1011 101
184 ARM64_SYSREG_ICC_ASGI1R_EL1 = 0xc65e, // 11 000 1100 1011 110
185 ARM64_SYSREG_ICC_SGI0R_EL1 = 0xc65f, // 11 000 1100 1011 111
186} arm64_msr_reg;
187
188//> System PState Field (MSR instruction)
189typedef enum arm64_pstate {
190 ARM64_PSTATE_INVALID = 0,
191 ARM64_PSTATE_SPSEL = 0x05,
192 ARM64_PSTATE_DAIFSET = 0x1e,
193 ARM64_PSTATE_DAIFCLR = 0x1f
194} arm64_pstate;
195
196//> Vector arrangement specifier (for FloatingPoint/Advanced SIMD insn)
197typedef enum arm64_vas {
198 ARM64_VAS_INVALID = 0,
199 ARM64_VAS_8B,
200 ARM64_VAS_16B,
201 ARM64_VAS_4H,
202 ARM64_VAS_8H,
203 ARM64_VAS_2S,
204 ARM64_VAS_4S,
205 ARM64_VAS_1D,
206 ARM64_VAS_2D,
207 ARM64_VAS_1Q,
208} arm64_vas;
209
210//> Vector element size specifier
211typedef enum arm64_vess {
212 ARM64_VESS_INVALID = 0,
213 ARM64_VESS_B,
214 ARM64_VESS_H,
215 ARM64_VESS_S,
216 ARM64_VESS_D,
217} arm64_vess;
218
219//> Memory barrier operands
220typedef enum arm64_barrier_op {
221 ARM64_BARRIER_INVALID = 0,
222 ARM64_BARRIER_OSHLD = 0x1,
223 ARM64_BARRIER_OSHST = 0x2,
224 ARM64_BARRIER_OSH = 0x3,
225 ARM64_BARRIER_NSHLD = 0x5,
226 ARM64_BARRIER_NSHST = 0x6,
227 ARM64_BARRIER_NSH = 0x7,
228 ARM64_BARRIER_ISHLD = 0x9,
229 ARM64_BARRIER_ISHST = 0xa,
230 ARM64_BARRIER_ISH = 0xb,
231 ARM64_BARRIER_LD = 0xd,
232 ARM64_BARRIER_ST = 0xe,
233 ARM64_BARRIER_SY = 0xf
234} arm64_barrier_op;
235
236//> Operand type for instruction's operands
237typedef enum arm64_op_type {
238 ARM64_OP_INVALID = 0, // = CS_OP_INVALID (Uninitialized).
239 ARM64_OP_REG, // = CS_OP_REG (Register operand).
240 ARM64_OP_IMM, // = CS_OP_IMM (Immediate operand).
241 ARM64_OP_MEM, // = CS_OP_MEM (Memory operand).
242 ARM64_OP_FP, // = CS_OP_FP (Floating-Point operand).
243 ARM64_OP_CIMM = 64, // C-Immediate
244 ARM64_OP_REG_MRS, // MRS register operand.
245 ARM64_OP_REG_MSR, // MSR register operand.
246 ARM64_OP_PSTATE, // PState operand.
247 ARM64_OP_SYS, // SYS operand for IC/DC/AT/TLBI instructions.
248 ARM64_OP_PREFETCH, // Prefetch operand (PRFM).
249 ARM64_OP_BARRIER, // Memory barrier operand (ISB/DMB/DSB instructions).
250} arm64_op_type;
251
252//> TLBI operations
253typedef enum arm64_tlbi_op {
254 ARM64_TLBI_INVALID = 0,
255 ARM64_TLBI_VMALLE1IS,
256 ARM64_TLBI_VAE1IS,
257 ARM64_TLBI_ASIDE1IS,
258 ARM64_TLBI_VAAE1IS,
259 ARM64_TLBI_VALE1IS,
260 ARM64_TLBI_VAALE1IS,
261 ARM64_TLBI_ALLE2IS,
262 ARM64_TLBI_VAE2IS,
263 ARM64_TLBI_ALLE1IS,
264 ARM64_TLBI_VALE2IS,
265 ARM64_TLBI_VMALLS12E1IS,
266 ARM64_TLBI_ALLE3IS,
267 ARM64_TLBI_VAE3IS,
268 ARM64_TLBI_VALE3IS,
269 ARM64_TLBI_IPAS2E1IS,
270 ARM64_TLBI_IPAS2LE1IS,
271 ARM64_TLBI_IPAS2E1,
272 ARM64_TLBI_IPAS2LE1,
273 ARM64_TLBI_VMALLE1,
274 ARM64_TLBI_VAE1,
275 ARM64_TLBI_ASIDE1,
276 ARM64_TLBI_VAAE1,
277 ARM64_TLBI_VALE1,
278 ARM64_TLBI_VAALE1,
279 ARM64_TLBI_ALLE2,
280 ARM64_TLBI_VAE2,
281 ARM64_TLBI_ALLE1,
282 ARM64_TLBI_VALE2,
283 ARM64_TLBI_VMALLS12E1,
284 ARM64_TLBI_ALLE3,
285 ARM64_TLBI_VAE3,
286 ARM64_TLBI_VALE3,
287} arm64_tlbi_op;
288
289//> AT operations
290typedef enum arm64_at_op {
291 ARM64_AT_S1E1R,
292 ARM64_AT_S1E1W,
293 ARM64_AT_S1E0R,
294 ARM64_AT_S1E0W,
295 ARM64_AT_S1E2R,
296 ARM64_AT_S1E2W,
297 ARM64_AT_S12E1R,
298 ARM64_AT_S12E1W,
299 ARM64_AT_S12E0R,
300 ARM64_AT_S12E0W,
301 ARM64_AT_S1E3R,
302 ARM64_AT_S1E3W,
303} arm64_at_op;
304
305//> DC operations
306typedef enum arm64_dc_op {
307 ARM64_DC_INVALID = 0,
308 ARM64_DC_ZVA,
309 ARM64_DC_IVAC,
310 ARM64_DC_ISW,
311 ARM64_DC_CVAC,
312 ARM64_DC_CSW,
313 ARM64_DC_CVAU,
314 ARM64_DC_CIVAC,
315 ARM64_DC_CISW,
316} arm64_dc_op;
317
318//> IC operations
319typedef enum arm64_ic_op {
320 ARM64_IC_INVALID = 0,
321 ARM64_IC_IALLUIS,
322 ARM64_IC_IALLU,
323 ARM64_IC_IVAU,
324} arm64_ic_op;
325
326//> Prefetch operations (PRFM)
327typedef enum arm64_prefetch_op {
328 ARM64_PRFM_INVALID = 0,
329 ARM64_PRFM_PLDL1KEEP = 0x00 + 1,
330 ARM64_PRFM_PLDL1STRM = 0x01 + 1,
331 ARM64_PRFM_PLDL2KEEP = 0x02 + 1,
332 ARM64_PRFM_PLDL2STRM = 0x03 + 1,
333 ARM64_PRFM_PLDL3KEEP = 0x04 + 1,
334 ARM64_PRFM_PLDL3STRM = 0x05 + 1,
335 ARM64_PRFM_PLIL1KEEP = 0x08 + 1,
336 ARM64_PRFM_PLIL1STRM = 0x09 + 1,
337 ARM64_PRFM_PLIL2KEEP = 0x0a + 1,
338 ARM64_PRFM_PLIL2STRM = 0x0b + 1,
339 ARM64_PRFM_PLIL3KEEP = 0x0c + 1,
340 ARM64_PRFM_PLIL3STRM = 0x0d + 1,
341 ARM64_PRFM_PSTL1KEEP = 0x10 + 1,
342 ARM64_PRFM_PSTL1STRM = 0x11 + 1,
343 ARM64_PRFM_PSTL2KEEP = 0x12 + 1,
344 ARM64_PRFM_PSTL2STRM = 0x13 + 1,
345 ARM64_PRFM_PSTL3KEEP = 0x14 + 1,
346 ARM64_PRFM_PSTL3STRM = 0x15 + 1,
347} arm64_prefetch_op;
348
349// Instruction's operand referring to memory
350// This is associated with ARM64_OP_MEM operand type above
351typedef struct arm64_op_mem {
352 unsigned int base; // base register
353 unsigned int index; // index register
354 int32_t disp; // displacement/offset value
355} arm64_op_mem;
356
357// Instruction operand
358typedef struct cs_arm64_op {
359 int vector_index; // Vector Index for some vector operands (or -1 if irrelevant)
360 arm64_vas vas; // Vector Arrangement Specifier
361 arm64_vess vess; // Vector Element Size Specifier
362 struct {
363 arm64_shifter type; // shifter type of this operand
364 unsigned int value; // shifter value of this operand
365 } shift;
366 arm64_extender ext; // extender type of this operand
367 arm64_op_type type; // operand type
368 union {
369 unsigned int reg; // register value for REG operand
370 int64_t imm; // immediate value, or index for C-IMM or IMM operand
371 double fp; // floating point value for FP operand
372 arm64_op_mem mem; // base/index/scale/disp value for MEM operand
373 arm64_pstate pstate; // PState field of MSR instruction.
374 unsigned int sys; // IC/DC/AT/TLBI operation (see arm64_ic_op, arm64_dc_op, arm64_at_op, arm64_tlbi_op)
375 arm64_prefetch_op prefetch; // PRFM operation.
376 arm64_barrier_op barrier; // Memory barrier operation (ISB/DMB/DSB instructions).
377 };
378} cs_arm64_op;
379
380// Instruction structure
381typedef struct cs_arm64 {
382 arm64_cc cc; // conditional code for this insn
383 bool update_flags; // does this insn update flags?
384 bool writeback; // does this insn request writeback? 'True' means 'yes'
385
386 // Number of operands of this instruction,
387 // or 0 when instruction has no operand.
388 uint8_t op_count;
389
390 cs_arm64_op operands[8]; // operands for this instruction.
391} cs_arm64;
392
393//> ARM64 registers
394typedef enum arm64_reg {
395 ARM64_REG_INVALID = 0,
396
397 ARM64_REG_X29,
398 ARM64_REG_X30,
399 ARM64_REG_NZCV,
400 ARM64_REG_SP,
401 ARM64_REG_WSP,
402 ARM64_REG_WZR,
403 ARM64_REG_XZR,
404 ARM64_REG_B0,
405 ARM64_REG_B1,
406 ARM64_REG_B2,
407 ARM64_REG_B3,
408 ARM64_REG_B4,
409 ARM64_REG_B5,
410 ARM64_REG_B6,
411 ARM64_REG_B7,
412 ARM64_REG_B8,
413 ARM64_REG_B9,
414 ARM64_REG_B10,
415 ARM64_REG_B11,
416 ARM64_REG_B12,
417 ARM64_REG_B13,
418 ARM64_REG_B14,
419 ARM64_REG_B15,
420 ARM64_REG_B16,
421 ARM64_REG_B17,
422 ARM64_REG_B18,
423 ARM64_REG_B19,
424 ARM64_REG_B20,
425 ARM64_REG_B21,
426 ARM64_REG_B22,
427 ARM64_REG_B23,
428 ARM64_REG_B24,
429 ARM64_REG_B25,
430 ARM64_REG_B26,
431 ARM64_REG_B27,
432 ARM64_REG_B28,
433 ARM64_REG_B29,
434 ARM64_REG_B30,
435 ARM64_REG_B31,
436 ARM64_REG_D0,
437 ARM64_REG_D1,
438 ARM64_REG_D2,
439 ARM64_REG_D3,
440 ARM64_REG_D4,
441 ARM64_REG_D5,
442 ARM64_REG_D6,
443 ARM64_REG_D7,
444 ARM64_REG_D8,
445 ARM64_REG_D9,
446 ARM64_REG_D10,
447 ARM64_REG_D11,
448 ARM64_REG_D12,
449 ARM64_REG_D13,
450 ARM64_REG_D14,
451 ARM64_REG_D15,
452 ARM64_REG_D16,
453 ARM64_REG_D17,
454 ARM64_REG_D18,
455 ARM64_REG_D19,
456 ARM64_REG_D20,
457 ARM64_REG_D21,
458 ARM64_REG_D22,
459 ARM64_REG_D23,
460 ARM64_REG_D24,
461 ARM64_REG_D25,
462 ARM64_REG_D26,
463 ARM64_REG_D27,
464 ARM64_REG_D28,
465 ARM64_REG_D29,
466 ARM64_REG_D30,
467 ARM64_REG_D31,
468 ARM64_REG_H0,
469 ARM64_REG_H1,
470 ARM64_REG_H2,
471 ARM64_REG_H3,
472 ARM64_REG_H4,
473 ARM64_REG_H5,
474 ARM64_REG_H6,
475 ARM64_REG_H7,
476 ARM64_REG_H8,
477 ARM64_REG_H9,
478 ARM64_REG_H10,
479 ARM64_REG_H11,
480 ARM64_REG_H12,
481 ARM64_REG_H13,
482 ARM64_REG_H14,
483 ARM64_REG_H15,
484 ARM64_REG_H16,
485 ARM64_REG_H17,
486 ARM64_REG_H18,
487 ARM64_REG_H19,
488 ARM64_REG_H20,
489 ARM64_REG_H21,
490 ARM64_REG_H22,
491 ARM64_REG_H23,
492 ARM64_REG_H24,
493 ARM64_REG_H25,
494 ARM64_REG_H26,
495 ARM64_REG_H27,
496 ARM64_REG_H28,
497 ARM64_REG_H29,
498 ARM64_REG_H30,
499 ARM64_REG_H31,
500 ARM64_REG_Q0,
501 ARM64_REG_Q1,
502 ARM64_REG_Q2,
503 ARM64_REG_Q3,
504 ARM64_REG_Q4,
505 ARM64_REG_Q5,
506 ARM64_REG_Q6,
507 ARM64_REG_Q7,
508 ARM64_REG_Q8,
509 ARM64_REG_Q9,
510 ARM64_REG_Q10,
511 ARM64_REG_Q11,
512 ARM64_REG_Q12,
513 ARM64_REG_Q13,
514 ARM64_REG_Q14,
515 ARM64_REG_Q15,
516 ARM64_REG_Q16,
517 ARM64_REG_Q17,
518 ARM64_REG_Q18,
519 ARM64_REG_Q19,
520 ARM64_REG_Q20,
521 ARM64_REG_Q21,
522 ARM64_REG_Q22,
523 ARM64_REG_Q23,
524 ARM64_REG_Q24,
525 ARM64_REG_Q25,
526 ARM64_REG_Q26,
527 ARM64_REG_Q27,
528 ARM64_REG_Q28,
529 ARM64_REG_Q29,
530 ARM64_REG_Q30,
531 ARM64_REG_Q31,
532 ARM64_REG_S0,
533 ARM64_REG_S1,
534 ARM64_REG_S2,
535 ARM64_REG_S3,
536 ARM64_REG_S4,
537 ARM64_REG_S5,
538 ARM64_REG_S6,
539 ARM64_REG_S7,
540 ARM64_REG_S8,
541 ARM64_REG_S9,
542 ARM64_REG_S10,
543 ARM64_REG_S11,
544 ARM64_REG_S12,
545 ARM64_REG_S13,
546 ARM64_REG_S14,
547 ARM64_REG_S15,
548 ARM64_REG_S16,
549 ARM64_REG_S17,
550 ARM64_REG_S18,
551 ARM64_REG_S19,
552 ARM64_REG_S20,
553 ARM64_REG_S21,
554 ARM64_REG_S22,
555 ARM64_REG_S23,
556 ARM64_REG_S24,
557 ARM64_REG_S25,
558 ARM64_REG_S26,
559 ARM64_REG_S27,
560 ARM64_REG_S28,
561 ARM64_REG_S29,
562 ARM64_REG_S30,
563 ARM64_REG_S31,
564 ARM64_REG_W0,
565 ARM64_REG_W1,
566 ARM64_REG_W2,
567 ARM64_REG_W3,
568 ARM64_REG_W4,
569 ARM64_REG_W5,
570 ARM64_REG_W6,
571 ARM64_REG_W7,
572 ARM64_REG_W8,
573 ARM64_REG_W9,
574 ARM64_REG_W10,
575 ARM64_REG_W11,
576 ARM64_REG_W12,
577 ARM64_REG_W13,
578 ARM64_REG_W14,
579 ARM64_REG_W15,
580 ARM64_REG_W16,
581 ARM64_REG_W17,
582 ARM64_REG_W18,
583 ARM64_REG_W19,
584 ARM64_REG_W20,
585 ARM64_REG_W21,
586 ARM64_REG_W22,
587 ARM64_REG_W23,
588 ARM64_REG_W24,
589 ARM64_REG_W25,
590 ARM64_REG_W26,
591 ARM64_REG_W27,
592 ARM64_REG_W28,
593 ARM64_REG_W29,
594 ARM64_REG_W30,
595 ARM64_REG_X0,
596 ARM64_REG_X1,
597 ARM64_REG_X2,
598 ARM64_REG_X3,
599 ARM64_REG_X4,
600 ARM64_REG_X5,
601 ARM64_REG_X6,
602 ARM64_REG_X7,
603 ARM64_REG_X8,
604 ARM64_REG_X9,
605 ARM64_REG_X10,
606 ARM64_REG_X11,
607 ARM64_REG_X12,
608 ARM64_REG_X13,
609 ARM64_REG_X14,
610 ARM64_REG_X15,
611 ARM64_REG_X16,
612 ARM64_REG_X17,
613 ARM64_REG_X18,
614 ARM64_REG_X19,
615 ARM64_REG_X20,
616 ARM64_REG_X21,
617 ARM64_REG_X22,
618 ARM64_REG_X23,
619 ARM64_REG_X24,
620 ARM64_REG_X25,
621 ARM64_REG_X26,
622 ARM64_REG_X27,
623 ARM64_REG_X28,
624
625 ARM64_REG_V0,
626 ARM64_REG_V1,
627 ARM64_REG_V2,
628 ARM64_REG_V3,
629 ARM64_REG_V4,
630 ARM64_REG_V5,
631 ARM64_REG_V6,
632 ARM64_REG_V7,
633 ARM64_REG_V8,
634 ARM64_REG_V9,
635 ARM64_REG_V10,
636 ARM64_REG_V11,
637 ARM64_REG_V12,
638 ARM64_REG_V13,
639 ARM64_REG_V14,
640 ARM64_REG_V15,
641 ARM64_REG_V16,
642 ARM64_REG_V17,
643 ARM64_REG_V18,
644 ARM64_REG_V19,
645 ARM64_REG_V20,
646 ARM64_REG_V21,
647 ARM64_REG_V22,
648 ARM64_REG_V23,
649 ARM64_REG_V24,
650 ARM64_REG_V25,
651 ARM64_REG_V26,
652 ARM64_REG_V27,
653 ARM64_REG_V28,
654 ARM64_REG_V29,
655 ARM64_REG_V30,
656 ARM64_REG_V31,
657
658 ARM64_REG_ENDING, // <-- mark the end of the list of registers
659
660 //> alias registers
661
662 ARM64_REG_IP1 = ARM64_REG_X16,
663 ARM64_REG_IP0 = ARM64_REG_X17,
664 ARM64_REG_FP = ARM64_REG_X29,
665 ARM64_REG_LR = ARM64_REG_X30,
666} arm64_reg;
667
668//> ARM64 instruction
669typedef enum arm64_insn {
670 ARM64_INS_INVALID = 0,
671
672 ARM64_INS_ABS,
673 ARM64_INS_ADC,
674 ARM64_INS_ADDHN,
675 ARM64_INS_ADDHN2,
676 ARM64_INS_ADDP,
677 ARM64_INS_ADD,
678 ARM64_INS_ADDV,
679 ARM64_INS_ADR,
680 ARM64_INS_ADRP,
681 ARM64_INS_AESD,
682 ARM64_INS_AESE,
683 ARM64_INS_AESIMC,
684 ARM64_INS_AESMC,
685 ARM64_INS_AND,
686 ARM64_INS_ASR,
687 ARM64_INS_B,
688 ARM64_INS_BFM,
689 ARM64_INS_BIC,
690 ARM64_INS_BIF,
691 ARM64_INS_BIT,
692 ARM64_INS_BL,
693 ARM64_INS_BLR,
694 ARM64_INS_BR,
695 ARM64_INS_BRK,
696 ARM64_INS_BSL,
697 ARM64_INS_CBNZ,
698 ARM64_INS_CBZ,
699 ARM64_INS_CCMN,
700 ARM64_INS_CCMP,
701 ARM64_INS_CLREX,
702 ARM64_INS_CLS,
703 ARM64_INS_CLZ,
704 ARM64_INS_CMEQ,
705 ARM64_INS_CMGE,
706 ARM64_INS_CMGT,
707 ARM64_INS_CMHI,
708 ARM64_INS_CMHS,
709 ARM64_INS_CMLE,
710 ARM64_INS_CMLT,
711 ARM64_INS_CMTST,
712 ARM64_INS_CNT,
713 ARM64_INS_MOV,
714 ARM64_INS_CRC32B,
715 ARM64_INS_CRC32CB,
716 ARM64_INS_CRC32CH,
717 ARM64_INS_CRC32CW,
718 ARM64_INS_CRC32CX,
719 ARM64_INS_CRC32H,
720 ARM64_INS_CRC32W,
721 ARM64_INS_CRC32X,
722 ARM64_INS_CSEL,
723 ARM64_INS_CSINC,
724 ARM64_INS_CSINV,
725 ARM64_INS_CSNEG,
726 ARM64_INS_DCPS1,
727 ARM64_INS_DCPS2,
728 ARM64_INS_DCPS3,
729 ARM64_INS_DMB,
730 ARM64_INS_DRPS,
731 ARM64_INS_DSB,
732 ARM64_INS_DUP,
733 ARM64_INS_EON,
734 ARM64_INS_EOR,
735 ARM64_INS_ERET,
736 ARM64_INS_EXTR,
737 ARM64_INS_EXT,
738 ARM64_INS_FABD,
739 ARM64_INS_FABS,
740 ARM64_INS_FACGE,
741 ARM64_INS_FACGT,
742 ARM64_INS_FADD,
743 ARM64_INS_FADDP,
744 ARM64_INS_FCCMP,
745 ARM64_INS_FCCMPE,
746 ARM64_INS_FCMEQ,
747 ARM64_INS_FCMGE,
748 ARM64_INS_FCMGT,
749 ARM64_INS_FCMLE,
750 ARM64_INS_FCMLT,
751 ARM64_INS_FCMP,
752 ARM64_INS_FCMPE,
753 ARM64_INS_FCSEL,
754 ARM64_INS_FCVTAS,
755 ARM64_INS_FCVTAU,
756 ARM64_INS_FCVT,
757 ARM64_INS_FCVTL,
758 ARM64_INS_FCVTL2,
759 ARM64_INS_FCVTMS,
760 ARM64_INS_FCVTMU,
761 ARM64_INS_FCVTNS,
762 ARM64_INS_FCVTNU,
763 ARM64_INS_FCVTN,
764 ARM64_INS_FCVTN2,
765 ARM64_INS_FCVTPS,
766 ARM64_INS_FCVTPU,
767 ARM64_INS_FCVTXN,
768 ARM64_INS_FCVTXN2,
769 ARM64_INS_FCVTZS,
770 ARM64_INS_FCVTZU,
771 ARM64_INS_FDIV,
772 ARM64_INS_FMADD,
773 ARM64_INS_FMAX,
774 ARM64_INS_FMAXNM,
775 ARM64_INS_FMAXNMP,
776 ARM64_INS_FMAXNMV,
777 ARM64_INS_FMAXP,
778 ARM64_INS_FMAXV,
779 ARM64_INS_FMIN,
780 ARM64_INS_FMINNM,
781 ARM64_INS_FMINNMP,
782 ARM64_INS_FMINNMV,
783 ARM64_INS_FMINP,
784 ARM64_INS_FMINV,
785 ARM64_INS_FMLA,
786 ARM64_INS_FMLS,
787 ARM64_INS_FMOV,
788 ARM64_INS_FMSUB,
789 ARM64_INS_FMUL,
790 ARM64_INS_FMULX,
791 ARM64_INS_FNEG,
792 ARM64_INS_FNMADD,
793 ARM64_INS_FNMSUB,
794 ARM64_INS_FNMUL,
795 ARM64_INS_FRECPE,
796 ARM64_INS_FRECPS,
797 ARM64_INS_FRECPX,
798 ARM64_INS_FRINTA,
799 ARM64_INS_FRINTI,
800 ARM64_INS_FRINTM,
801 ARM64_INS_FRINTN,
802 ARM64_INS_FRINTP,
803 ARM64_INS_FRINTX,
804 ARM64_INS_FRINTZ,
805 ARM64_INS_FRSQRTE,
806 ARM64_INS_FRSQRTS,
807 ARM64_INS_FSQRT,
808 ARM64_INS_FSUB,
809 ARM64_INS_HINT,
810 ARM64_INS_HLT,
811 ARM64_INS_HVC,
812 ARM64_INS_INS,
813
814 ARM64_INS_ISB,
815 ARM64_INS_LD1,
816 ARM64_INS_LD1R,
817 ARM64_INS_LD2R,
818 ARM64_INS_LD2,
819 ARM64_INS_LD3R,
820 ARM64_INS_LD3,
821 ARM64_INS_LD4,
822 ARM64_INS_LD4R,
823
824 ARM64_INS_LDARB,
825 ARM64_INS_LDARH,
826 ARM64_INS_LDAR,
827 ARM64_INS_LDAXP,
828 ARM64_INS_LDAXRB,
829 ARM64_INS_LDAXRH,
830 ARM64_INS_LDAXR,
831 ARM64_INS_LDNP,
832 ARM64_INS_LDP,
833 ARM64_INS_LDPSW,
834 ARM64_INS_LDRB,
835 ARM64_INS_LDR,
836 ARM64_INS_LDRH,
837 ARM64_INS_LDRSB,
838 ARM64_INS_LDRSH,
839 ARM64_INS_LDRSW,
840 ARM64_INS_LDTRB,
841 ARM64_INS_LDTRH,
842 ARM64_INS_LDTRSB,
843
844 ARM64_INS_LDTRSH,
845 ARM64_INS_LDTRSW,
846 ARM64_INS_LDTR,
847 ARM64_INS_LDURB,
848 ARM64_INS_LDUR,
849 ARM64_INS_LDURH,
850 ARM64_INS_LDURSB,
851 ARM64_INS_LDURSH,
852 ARM64_INS_LDURSW,
853 ARM64_INS_LDXP,
854 ARM64_INS_LDXRB,
855 ARM64_INS_LDXRH,
856 ARM64_INS_LDXR,
857 ARM64_INS_LSL,
858 ARM64_INS_LSR,
859 ARM64_INS_MADD,
860 ARM64_INS_MLA,
861 ARM64_INS_MLS,
862 ARM64_INS_MOVI,
863 ARM64_INS_MOVK,
864 ARM64_INS_MOVN,
865 ARM64_INS_MOVZ,
866 ARM64_INS_MRS,
867 ARM64_INS_MSR,
868 ARM64_INS_MSUB,
869 ARM64_INS_MUL,
870 ARM64_INS_MVNI,
871 ARM64_INS_NEG,
872 ARM64_INS_NOT,
873 ARM64_INS_ORN,
874 ARM64_INS_ORR,
875 ARM64_INS_PMULL2,
876 ARM64_INS_PMULL,
877 ARM64_INS_PMUL,
878 ARM64_INS_PRFM,
879 ARM64_INS_PRFUM,
880 ARM64_INS_RADDHN,
881 ARM64_INS_RADDHN2,
882 ARM64_INS_RBIT,
883 ARM64_INS_RET,
884 ARM64_INS_REV16,
885 ARM64_INS_REV32,
886 ARM64_INS_REV64,
887 ARM64_INS_REV,
888 ARM64_INS_ROR,
889 ARM64_INS_RSHRN2,
890 ARM64_INS_RSHRN,
891 ARM64_INS_RSUBHN,
892 ARM64_INS_RSUBHN2,
893 ARM64_INS_SABAL2,
894 ARM64_INS_SABAL,
895
896 ARM64_INS_SABA,
897 ARM64_INS_SABDL2,
898 ARM64_INS_SABDL,
899 ARM64_INS_SABD,
900 ARM64_INS_SADALP,
901 ARM64_INS_SADDLP,
902 ARM64_INS_SADDLV,
903 ARM64_INS_SADDL2,
904 ARM64_INS_SADDL,
905 ARM64_INS_SADDW2,
906 ARM64_INS_SADDW,
907 ARM64_INS_SBC,
908 ARM64_INS_SBFM,
909 ARM64_INS_SCVTF,
910 ARM64_INS_SDIV,
911 ARM64_INS_SHA1C,
912 ARM64_INS_SHA1H,
913 ARM64_INS_SHA1M,
914 ARM64_INS_SHA1P,
915 ARM64_INS_SHA1SU0,
916 ARM64_INS_SHA1SU1,
917 ARM64_INS_SHA256H2,
918 ARM64_INS_SHA256H,
919 ARM64_INS_SHA256SU0,
920 ARM64_INS_SHA256SU1,
921 ARM64_INS_SHADD,
922 ARM64_INS_SHLL2,
923 ARM64_INS_SHLL,
924 ARM64_INS_SHL,
925 ARM64_INS_SHRN2,
926 ARM64_INS_SHRN,
927 ARM64_INS_SHSUB,
928 ARM64_INS_SLI,
929 ARM64_INS_SMADDL,
930 ARM64_INS_SMAXP,
931 ARM64_INS_SMAXV,
932 ARM64_INS_SMAX,
933 ARM64_INS_SMC,
934 ARM64_INS_SMINP,
935 ARM64_INS_SMINV,
936 ARM64_INS_SMIN,
937 ARM64_INS_SMLAL2,
938 ARM64_INS_SMLAL,
939 ARM64_INS_SMLSL2,
940 ARM64_INS_SMLSL,
941 ARM64_INS_SMOV,
942 ARM64_INS_SMSUBL,
943 ARM64_INS_SMULH,
944 ARM64_INS_SMULL2,
945 ARM64_INS_SMULL,
946 ARM64_INS_SQABS,
947 ARM64_INS_SQADD,
948 ARM64_INS_SQDMLAL,
949 ARM64_INS_SQDMLAL2,
950 ARM64_INS_SQDMLSL,
951 ARM64_INS_SQDMLSL2,
952 ARM64_INS_SQDMULH,
953 ARM64_INS_SQDMULL,
954 ARM64_INS_SQDMULL2,
955 ARM64_INS_SQNEG,
956 ARM64_INS_SQRDMULH,
957 ARM64_INS_SQRSHL,
958 ARM64_INS_SQRSHRN,
959 ARM64_INS_SQRSHRN2,
960 ARM64_INS_SQRSHRUN,
961 ARM64_INS_SQRSHRUN2,
962 ARM64_INS_SQSHLU,
963 ARM64_INS_SQSHL,
964 ARM64_INS_SQSHRN,
965 ARM64_INS_SQSHRN2,
966 ARM64_INS_SQSHRUN,
967 ARM64_INS_SQSHRUN2,
968 ARM64_INS_SQSUB,
969 ARM64_INS_SQXTN2,
970 ARM64_INS_SQXTN,
971 ARM64_INS_SQXTUN2,
972 ARM64_INS_SQXTUN,
973 ARM64_INS_SRHADD,
974 ARM64_INS_SRI,
975 ARM64_INS_SRSHL,
976 ARM64_INS_SRSHR,
977 ARM64_INS_SRSRA,
978 ARM64_INS_SSHLL2,
979 ARM64_INS_SSHLL,
980 ARM64_INS_SSHL,
981 ARM64_INS_SSHR,
982 ARM64_INS_SSRA,
983 ARM64_INS_SSUBL2,
984 ARM64_INS_SSUBL,
985 ARM64_INS_SSUBW2,
986 ARM64_INS_SSUBW,
987 ARM64_INS_ST1,
988 ARM64_INS_ST2,
989 ARM64_INS_ST3,
990 ARM64_INS_ST4,
991 ARM64_INS_STLRB,
992 ARM64_INS_STLRH,
993 ARM64_INS_STLR,
994 ARM64_INS_STLXP,
995 ARM64_INS_STLXRB,
996 ARM64_INS_STLXRH,
997 ARM64_INS_STLXR,
998 ARM64_INS_STNP,
999 ARM64_INS_STP,
1000 ARM64_INS_STRB,
1001 ARM64_INS_STR,
1002 ARM64_INS_STRH,
1003 ARM64_INS_STTRB,
1004 ARM64_INS_STTRH,
1005 ARM64_INS_STTR,
1006 ARM64_INS_STURB,
1007 ARM64_INS_STUR,
1008 ARM64_INS_STURH,
1009 ARM64_INS_STXP,
1010 ARM64_INS_STXRB,
1011 ARM64_INS_STXRH,
1012 ARM64_INS_STXR,
1013 ARM64_INS_SUBHN,
1014 ARM64_INS_SUBHN2,
1015 ARM64_INS_SUB,
1016 ARM64_INS_SUQADD,
1017 ARM64_INS_SVC,
1018 ARM64_INS_SYSL,
1019 ARM64_INS_SYS,
1020 ARM64_INS_TBL,
1021 ARM64_INS_TBNZ,
1022 ARM64_INS_TBX,
1023 ARM64_INS_TBZ,
1024 ARM64_INS_TRN1,
1025 ARM64_INS_TRN2,
1026 ARM64_INS_UABAL2,
1027 ARM64_INS_UABAL,
1028 ARM64_INS_UABA,
1029 ARM64_INS_UABDL2,
1030 ARM64_INS_UABDL,
1031 ARM64_INS_UABD,
1032 ARM64_INS_UADALP,
1033 ARM64_INS_UADDLP,
1034 ARM64_INS_UADDLV,
1035 ARM64_INS_UADDL2,
1036 ARM64_INS_UADDL,
1037 ARM64_INS_UADDW2,
1038 ARM64_INS_UADDW,
1039 ARM64_INS_UBFM,
1040 ARM64_INS_UCVTF,
1041 ARM64_INS_UDIV,
1042 ARM64_INS_UHADD,
1043 ARM64_INS_UHSUB,
1044 ARM64_INS_UMADDL,
1045 ARM64_INS_UMAXP,
1046 ARM64_INS_UMAXV,
1047 ARM64_INS_UMAX,
1048 ARM64_INS_UMINP,
1049 ARM64_INS_UMINV,
1050 ARM64_INS_UMIN,
1051 ARM64_INS_UMLAL2,
1052 ARM64_INS_UMLAL,
1053 ARM64_INS_UMLSL2,
1054 ARM64_INS_UMLSL,
1055 ARM64_INS_UMOV,
1056 ARM64_INS_UMSUBL,
1057 ARM64_INS_UMULH,
1058 ARM64_INS_UMULL2,
1059 ARM64_INS_UMULL,
1060 ARM64_INS_UQADD,
1061 ARM64_INS_UQRSHL,
1062 ARM64_INS_UQRSHRN,
1063 ARM64_INS_UQRSHRN2,
1064 ARM64_INS_UQSHL,
1065 ARM64_INS_UQSHRN,
1066 ARM64_INS_UQSHRN2,
1067 ARM64_INS_UQSUB,
1068 ARM64_INS_UQXTN2,
1069 ARM64_INS_UQXTN,
1070 ARM64_INS_URECPE,
1071 ARM64_INS_URHADD,
1072 ARM64_INS_URSHL,
1073 ARM64_INS_URSHR,
1074 ARM64_INS_URSQRTE,
1075 ARM64_INS_URSRA,
1076 ARM64_INS_USHLL2,
1077 ARM64_INS_USHLL,
1078 ARM64_INS_USHL,
1079 ARM64_INS_USHR,
1080 ARM64_INS_USQADD,
1081 ARM64_INS_USRA,
1082 ARM64_INS_USUBL2,
1083 ARM64_INS_USUBL,
1084 ARM64_INS_USUBW2,
1085 ARM64_INS_USUBW,
1086 ARM64_INS_UZP1,
1087 ARM64_INS_UZP2,
1088 ARM64_INS_XTN2,
1089 ARM64_INS_XTN,
1090 ARM64_INS_ZIP1,
1091 ARM64_INS_ZIP2,
1092
1093 // alias insn
1094 ARM64_INS_MNEG,
1095 ARM64_INS_UMNEGL,
1096 ARM64_INS_SMNEGL,
1097 ARM64_INS_NOP,
1098 ARM64_INS_YIELD,
1099 ARM64_INS_WFE,
1100 ARM64_INS_WFI,
1101 ARM64_INS_SEV,
1102 ARM64_INS_SEVL,
1103 ARM64_INS_NGC,
1104 ARM64_INS_SBFIZ,
1105 ARM64_INS_UBFIZ,
1106 ARM64_INS_SBFX,
1107 ARM64_INS_UBFX,
1108 ARM64_INS_BFI,
1109 ARM64_INS_BFXIL,
1110 ARM64_INS_CMN,
1111 ARM64_INS_MVN,
1112 ARM64_INS_TST,
1113 ARM64_INS_CSET,
1114 ARM64_INS_CINC,
1115 ARM64_INS_CSETM,
1116 ARM64_INS_CINV,
1117 ARM64_INS_CNEG,
1118 ARM64_INS_SXTB,
1119 ARM64_INS_SXTH,
1120 ARM64_INS_SXTW,
1121 ARM64_INS_CMP,
1122 ARM64_INS_UXTB,
1123 ARM64_INS_UXTH,
1124 ARM64_INS_UXTW,
1125 ARM64_INS_IC,
1126 ARM64_INS_DC,
1127 ARM64_INS_AT,
1128 ARM64_INS_TLBI,
1129
1130 ARM64_INS_ENDING, // <-- mark the end of the list of insn
1131} arm64_insn;
1132
1133//> Group of ARM64 instructions
1134typedef enum arm64_insn_group {
1135 ARM64_GRP_INVALID = 0, // = CS_GRP_INVALID
1136
1137 //> Generic groups
1138 // all jump instructions (conditional+direct+indirect jumps)
1139 ARM64_GRP_JUMP, // = CS_GRP_JUMP
1140
1141 //> Architecture-specific groups
1142 ARM64_GRP_CRYPTO = 128,
1143 ARM64_GRP_FPARMV8,
1144 ARM64_GRP_NEON,
1145 ARM64_GRP_CRC,
1146
1147 ARM64_GRP_ENDING, // <-- mark the end of the list of groups
1148} arm64_insn_group;
1149
1150#ifdef __cplusplus
1151}
1152#endif
1153
1154#endif
1155