1 | /* Disassemble Xilinx microblaze instructions. |
2 | Copyright (C) 1993, 1999, 2000 Free Software Foundation, Inc. |
3 | |
4 | This program is free software; you can redistribute it and/or modify |
5 | it under the terms of the GNU General Public License as published by |
6 | the Free Software Foundation; either version 2 of the License, or |
7 | (at your option) any later version. |
8 | |
9 | This program is distributed in the hope that it will be useful, |
10 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
11 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
12 | GNU General Public License for more details. |
13 | |
14 | You should have received a copy of the GNU General Public License |
15 | along with this program; if not, see <http://www.gnu.org/licenses/>. */ |
16 | |
17 | /* |
18 | * Copyright (c) 2001 Xilinx, Inc. All rights reserved. |
19 | * |
20 | * Redistribution and use in source and binary forms are permitted |
21 | * provided that the above copyright notice and this paragraph are |
22 | * duplicated in all such forms and that any documentation, |
23 | * advertising materials, and other materials related to such |
24 | * distribution and use acknowledge that the software was developed |
25 | * by Xilinx, Inc. The name of the Company may not be used to endorse |
26 | * or promote products derived from this software without specific prior |
27 | * written permission. |
28 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR |
29 | * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED |
30 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. |
31 | * |
32 | * Xilinx, Inc. |
33 | */ |
34 | |
35 | |
36 | #include "qemu/osdep.h" |
37 | #define STATIC_TABLE |
38 | #define DEFINE_TABLE |
39 | |
40 | #ifndef MICROBLAZE_OPC |
41 | #define MICROBLAZE_OPC |
42 | /* Assembler instructions for Xilinx's microblaze processor |
43 | Copyright (C) 1999, 2000 Free Software Foundation, Inc. |
44 | |
45 | |
46 | This program is free software; you can redistribute it and/or modify |
47 | it under the terms of the GNU General Public License as published by |
48 | the Free Software Foundation; either version 2 of the License, or |
49 | (at your option) any later version. |
50 | |
51 | This program is distributed in the hope that it will be useful, |
52 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
53 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
54 | GNU General Public License for more details. |
55 | |
56 | You should have received a copy of the GNU General Public License |
57 | along with this program; if not, see <http://www.gnu.org/licenses/>. */ |
58 | |
59 | /* |
60 | * Copyright (c) 2001 Xilinx, Inc. All rights reserved. |
61 | * |
62 | * Redistribution and use in source and binary forms are permitted |
63 | * provided that the above copyright notice and this paragraph are |
64 | * duplicated in all such forms and that any documentation, |
65 | * advertising materials, and other materials related to such |
66 | * distribution and use acknowledge that the software was developed |
67 | * by Xilinx, Inc. The name of the Company may not be used to endorse |
68 | * or promote products derived from this software without specific prior |
69 | * written permission. |
70 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR |
71 | * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED |
72 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. |
73 | * |
74 | * Xilinx, Inc. |
75 | */ |
76 | |
77 | |
78 | #ifndef MICROBLAZE_OPCM |
79 | #define MICROBLAZE_OPCM |
80 | |
81 | /* |
82 | * Copyright (c) 2001 Xilinx, Inc. All rights reserved. |
83 | * |
84 | * Redistribution and use in source and binary forms are permitted |
85 | * provided that the above copyright notice and this paragraph are |
86 | * duplicated in all such forms and that any documentation, |
87 | * advertising materials, and other materials related to such |
88 | * distribution and use acknowledge that the software was developed |
89 | * by Xilinx, Inc. The name of the Company may not be used to endorse |
90 | * or promote products derived from this software without specific prior |
91 | * written permission. |
92 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR |
93 | * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED |
94 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. |
95 | * |
96 | * Xilinx, Inc. |
97 | * $Header: |
98 | */ |
99 | |
100 | enum microblaze_instr { |
101 | add, rsub, addc, rsubc, addk, rsubk, addkc, rsubkc, cmp, cmpu, |
102 | addi, rsubi, addic, rsubic, addik, rsubik, addikc, rsubikc, mul, mulh, mulhu, mulhsu, |
103 | idiv, idivu, bsll, bsra, bsrl, get, put, nget, nput, cget, cput, |
104 | ncget, ncput, muli, bslli, bsrai, bsrli, mului, or, and, xor, |
105 | andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16, wic, wdc, wdcclear, wdcflush, mts, mfs, br, brd, |
106 | brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned, blt, |
107 | bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni, |
108 | imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid, |
109 | brki, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti, |
110 | bgtid, bgei, bgeid, lbu, lhu, lw, lwx, sb, sh, sw, swx, lbui, lhui, lwi, |
111 | sbi, shi, swi, msrset, msrclr, tuqula, fadd, frsub, fmul, fdiv, |
112 | fcmp_lt, fcmp_eq, fcmp_le, fcmp_gt, fcmp_ne, fcmp_ge, fcmp_un, flt, fint, fsqrt, |
113 | tget, tcget, tnget, tncget, tput, tcput, tnput, tncput, |
114 | eget, ecget, neget, necget, eput, ecput, neput, necput, |
115 | teget, tecget, tneget, tnecget, teput, tecput, tneput, tnecput, |
116 | aget, caget, naget, ncaget, aput, caput, naput, ncaput, |
117 | taget, tcaget, tnaget, tncaget, taput, tcaput, tnaput, tncaput, |
118 | eaget, ecaget, neaget, necaget, eaput, ecaput, neaput, necaput, |
119 | teaget, tecaget, tneaget, tnecaget, teaput, tecaput, tneaput, tnecaput, |
120 | getd, tgetd, cgetd, tcgetd, ngetd, tngetd, ncgetd, tncgetd, |
121 | putd, tputd, cputd, tcputd, nputd, tnputd, ncputd, tncputd, |
122 | egetd, tegetd, ecgetd, tecgetd, negetd, tnegetd, necgetd, tnecgetd, |
123 | eputd, teputd, ecputd, tecputd, neputd, tneputd, necputd, tnecputd, |
124 | agetd, tagetd, cagetd, tcagetd, nagetd, tnagetd, ncagetd, tncagetd, |
125 | aputd, taputd, caputd, tcaputd, naputd, tnaputd, ncaputd, tncaputd, |
126 | eagetd, teagetd, ecagetd, tecagetd, neagetd, tneagetd, necagetd, tnecagetd, |
127 | eaputd, teaputd, ecaputd, tecaputd, neaputd, tneaputd, necaputd, tnecaputd, |
128 | invalid_inst } ; |
129 | |
130 | enum microblaze_instr_type { |
131 | arithmetic_inst, logical_inst, mult_inst, div_inst, branch_inst, |
132 | return_inst, immediate_inst, special_inst, memory_load_inst, |
133 | memory_store_inst, barrel_shift_inst, anyware_inst }; |
134 | |
135 | #define INST_WORD_SIZE 4 |
136 | |
137 | /* gen purpose regs go from 0 to 31 */ |
138 | /* mask is reg num - max_reg_num, ie reg_num - 32 in this case */ |
139 | |
140 | #define REG_PC_MASK 0x8000 |
141 | #define REG_MSR_MASK 0x8001 |
142 | #define REG_EAR_MASK 0x8003 |
143 | #define REG_ESR_MASK 0x8005 |
144 | #define REG_FSR_MASK 0x8007 |
145 | #define REG_BTR_MASK 0x800b |
146 | #define REG_EDR_MASK 0x800d |
147 | #define REG_PVR_MASK 0xa000 |
148 | |
149 | #define REG_PID_MASK 0x9000 |
150 | #define REG_ZPR_MASK 0x9001 |
151 | #define REG_TLBX_MASK 0x9002 |
152 | #define REG_TLBLO_MASK 0x9003 |
153 | #define REG_TLBHI_MASK 0x9004 |
154 | #define REG_TLBSX_MASK 0x9005 |
155 | |
156 | #define MIN_REGNUM 0 |
157 | #define MAX_REGNUM 31 |
158 | |
159 | #define MIN_PVR_REGNUM 0 |
160 | #define MAX_PVR_REGNUM 15 |
161 | |
162 | /* 32 is REG_PC */ |
163 | #define REG_MSR 33 /* machine status reg */ |
164 | #define REG_EAR 35 /* Exception reg */ |
165 | #define REG_ESR 37 /* Exception reg */ |
166 | #define REG_FSR 39 /* FPU Status reg */ |
167 | #define REG_BTR 43 /* Branch Target reg */ |
168 | #define REG_EDR 45 /* Exception reg */ |
169 | #define REG_PVR 40960 /* Program Verification reg */ |
170 | |
171 | #define REG_PID 36864 /* MMU: Process ID reg */ |
172 | #define REG_ZPR 36865 /* MMU: Zone Protect reg */ |
173 | #define REG_TLBX 36866 /* MMU: TLB Index reg */ |
174 | #define REG_TLBLO 36867 /* MMU: TLB Low reg */ |
175 | #define REG_TLBHI 36868 /* MMU: TLB High reg */ |
176 | #define REG_TLBSX 36869 /* MMU: TLB Search Index reg */ |
177 | |
178 | /* alternate names for gen purpose regs */ |
179 | #define REG_ROSDP 2 /* read-only small data pointer */ |
180 | #define REG_RWSDP 13 /* read-write small data pointer */ |
181 | |
182 | /* Assembler Register - Used in Delay Slot Optimization */ |
183 | #define REG_AS 18 |
184 | #define REG_ZERO 0 |
185 | |
186 | #define RD_LOW 21 /* low bit for RD */ |
187 | #define RA_LOW 16 /* low bit for RA */ |
188 | #define RB_LOW 11 /* low bit for RB */ |
189 | #define IMM_LOW 0 /* low bit for immediate */ |
190 | |
191 | #define RD_MASK 0x03E00000 |
192 | #define RA_MASK 0x001F0000 |
193 | #define RB_MASK 0x0000F800 |
194 | #define IMM_MASK 0x0000FFFF |
195 | |
196 | // imm mask for barrel shifts |
197 | #define IMM5_MASK 0x0000001F |
198 | |
199 | |
200 | // FSL imm mask for get, put instructions |
201 | #define RFSL_MASK 0x000000F |
202 | |
203 | // imm mask for msrset, msrclr instructions |
204 | #define IMM15_MASK 0x00007FFF |
205 | |
206 | #endif /* MICROBLAZE-OPCM */ |
207 | |
208 | #define INST_TYPE_RD_R1_R2 0 |
209 | #define INST_TYPE_RD_R1_IMM 1 |
210 | #define INST_TYPE_RD_R1_UNSIGNED_IMM 2 |
211 | #define INST_TYPE_RD_R1 3 |
212 | #define INST_TYPE_RD_R2 4 |
213 | #define INST_TYPE_RD_IMM 5 |
214 | #define INST_TYPE_R2 6 |
215 | #define INST_TYPE_R1_R2 7 |
216 | #define INST_TYPE_R1_IMM 8 |
217 | #define INST_TYPE_IMM 9 |
218 | #define INST_TYPE_SPECIAL_R1 10 |
219 | #define INST_TYPE_RD_SPECIAL 11 |
220 | #define INST_TYPE_R1 12 |
221 | // new instn type for barrel shift imms |
222 | #define INST_TYPE_RD_R1_IMM5 13 |
223 | #define INST_TYPE_RD_RFSL 14 |
224 | #define INST_TYPE_R1_RFSL 15 |
225 | |
226 | // new insn type for insn cache |
227 | #define INST_TYPE_RD_R1_SPECIAL 16 |
228 | |
229 | // new insn type for msrclr, msrset insns. |
230 | #define INST_TYPE_RD_IMM15 17 |
231 | |
232 | // new insn type for tuqula rd - addik rd, r0, 42 |
233 | #define INST_TYPE_RD 18 |
234 | |
235 | // new insn type for t*put |
236 | #define INST_TYPE_RFSL 19 |
237 | |
238 | #define INST_TYPE_NONE 25 |
239 | |
240 | |
241 | |
242 | #define INST_PC_OFFSET 1 /* instructions where the label address is resolved as a PC offset (for branch label)*/ |
243 | #define INST_NO_OFFSET 0 /* instructions where the label address is resolved as an absolute value (for data mem or abs address)*/ |
244 | |
245 | #define IMMVAL_MASK_NON_SPECIAL 0x0000 |
246 | #define IMMVAL_MASK_MTS 0x4000 |
247 | #define IMMVAL_MASK_MFS 0x0000 |
248 | |
249 | #define OPCODE_MASK_H 0xFC000000 /* High 6 bits only */ |
250 | #define OPCODE_MASK_H1 0xFFE00000 /* High 11 bits */ |
251 | #define OPCODE_MASK_H2 0xFC1F0000 /* High 6 and bits 20-16 */ |
252 | #define OPCODE_MASK_H12 0xFFFF0000 /* High 16 */ |
253 | #define OPCODE_MASK_H4 0xFC0007FF /* High 6 and low 11 bits */ |
254 | #define OPCODE_MASK_H13S 0xFFE0EFF0 /* High 11 and 15:1 bits and last nibble of last byte for spr */ |
255 | #define OPCODE_MASK_H23S 0xFC1FC000 /* High 6, 20-16 and 15:1 bits and last nibble of last byte for spr */ |
256 | #define OPCODE_MASK_H34 0xFC00FFFF /* High 6 and low 16 bits */ |
257 | #define OPCODE_MASK_H14 0xFFE007FF /* High 11 and low 11 bits */ |
258 | #define OPCODE_MASK_H24 0xFC1F07FF /* High 6, bits 20-16 and low 11 bits */ |
259 | #define OPCODE_MASK_H124 0xFFFF07FF /* High 16, and low 11 bits */ |
260 | #define OPCODE_MASK_H1234 0xFFFFFFFF /* All 32 bits */ |
261 | #define OPCODE_MASK_H3 0xFC000600 /* High 6 bits and bits 21, 22 */ |
262 | #define OPCODE_MASK_H32 0xFC00FC00 /* High 6 bits and bit 16-21 */ |
263 | #define OPCODE_MASK_H34B 0xFC0000FF /* High 6 bits and low 8 bits */ |
264 | #define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26 */ |
265 | |
266 | // New Mask for msrset, msrclr insns. |
267 | #define OPCODE_MASK_H23N 0xFC1F8000 /* High 6 and bits 11 - 16 */ |
268 | |
269 | #define DELAY_SLOT 1 |
270 | #define NO_DELAY_SLOT 0 |
271 | |
272 | #define MAX_OPCODES 280 |
273 | |
274 | static const struct op_code_struct { |
275 | const char *name; |
276 | short inst_type; /* registers and immediate values involved */ |
277 | short inst_offset_type; /* immediate vals offset from PC? (= 1 for branches) */ |
278 | short delay_slots; /* info about delay slots needed after this instr. */ |
279 | short immval_mask; |
280 | unsigned long bit_sequence; /* all the fixed bits for the op are set and all the variable bits (reg names, imm vals) are set to 0 */ |
281 | unsigned long opcode_mask; /* which bits define the opcode */ |
282 | enum microblaze_instr instr; |
283 | enum microblaze_instr_type instr_type; |
284 | /* more info about output format here */ |
285 | } opcodes[MAX_OPCODES] = |
286 | |
287 | { |
288 | {"add" , INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x00000000, OPCODE_MASK_H4, add, arithmetic_inst }, |
289 | {"rsub" , INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H4, rsub, arithmetic_inst }, |
290 | {"addc" , INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x08000000, OPCODE_MASK_H4, addc, arithmetic_inst }, |
291 | {"rsubc" , INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x0C000000, OPCODE_MASK_H4, rsubc, arithmetic_inst }, |
292 | {"addk" , INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x10000000, OPCODE_MASK_H4, addk, arithmetic_inst }, |
293 | {"rsubk" , INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000000, OPCODE_MASK_H4, rsubk, arithmetic_inst }, |
294 | {"cmp" , INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000001, OPCODE_MASK_H4, cmp, arithmetic_inst }, |
295 | {"cmpu" , INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000003, OPCODE_MASK_H4, cmpu, arithmetic_inst }, |
296 | {"addkc" , INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x18000000, OPCODE_MASK_H4, addkc, arithmetic_inst }, |
297 | {"rsubkc" ,INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x1C000000, OPCODE_MASK_H4, rsubkc, arithmetic_inst }, |
298 | {"addi" , INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x20000000, OPCODE_MASK_H, addi, arithmetic_inst }, |
299 | {"rsubi" , INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x24000000, OPCODE_MASK_H, rsubi, arithmetic_inst }, |
300 | {"addic" , INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x28000000, OPCODE_MASK_H, addic, arithmetic_inst }, |
301 | {"rsubic" ,INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x2C000000, OPCODE_MASK_H, rsubic, arithmetic_inst }, |
302 | {"addik" , INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, addik, arithmetic_inst }, |
303 | {"rsubik" ,INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x34000000, OPCODE_MASK_H, rsubik, arithmetic_inst }, |
304 | {"addikc" ,INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x38000000, OPCODE_MASK_H, addikc, arithmetic_inst }, |
305 | {"rsubikc" ,INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x3C000000, OPCODE_MASK_H, rsubikc, arithmetic_inst }, |
306 | {"mul" , INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000000, OPCODE_MASK_H4, mul, mult_inst }, |
307 | {"mulh" , INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000001, OPCODE_MASK_H4, mulh, mult_inst }, |
308 | {"mulhu" , INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000003, OPCODE_MASK_H4, mulhu, mult_inst }, |
309 | {"mulhsu" ,INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000002, OPCODE_MASK_H4, mulhsu, mult_inst }, |
310 | {"idiv" , INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x48000000, OPCODE_MASK_H4, idiv, div_inst }, |
311 | {"idivu" , INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x48000002, OPCODE_MASK_H4, idivu, div_inst }, |
312 | {"bsll" , INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000400, OPCODE_MASK_H3, bsll, barrel_shift_inst }, |
313 | {"bsra" , INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000200, OPCODE_MASK_H3, bsra, barrel_shift_inst }, |
314 | {"bsrl" , INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000000, OPCODE_MASK_H3, bsrl, barrel_shift_inst }, |
315 | {"get" , INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C000000, OPCODE_MASK_H32, get, anyware_inst }, |
316 | {"put" , INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C008000, OPCODE_MASK_H32, put, anyware_inst }, |
317 | {"nget" , INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C004000, OPCODE_MASK_H32, nget, anyware_inst }, |
318 | {"nput" , INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00C000, OPCODE_MASK_H32, nput, anyware_inst }, |
319 | {"cget" , INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C002000, OPCODE_MASK_H32, cget, anyware_inst }, |
320 | {"cput" , INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00A000, OPCODE_MASK_H32, cput, anyware_inst }, |
321 | {"ncget" , INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C006000, OPCODE_MASK_H32, ncget, anyware_inst }, |
322 | {"ncput" , INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00E000, OPCODE_MASK_H32, ncput, anyware_inst }, |
323 | {"muli" , INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x60000000, OPCODE_MASK_H, muli, mult_inst }, |
324 | {"bslli" , INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3, bslli, barrel_shift_inst }, |
325 | {"bsrai" , INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3, bsrai, barrel_shift_inst }, |
326 | {"bsrli" , INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3, bsrli, barrel_shift_inst }, |
327 | {"or" , INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000000, OPCODE_MASK_H4, or, logical_inst }, |
328 | {"and" , INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x84000000, OPCODE_MASK_H4, and, logical_inst }, |
329 | {"xor" , INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000000, OPCODE_MASK_H4, xor, logical_inst }, |
330 | {"andn" , INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x8C000000, OPCODE_MASK_H4, andn, logical_inst }, |
331 | {"pcmpbf" ,INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000400, OPCODE_MASK_H4, pcmpbf, logical_inst }, |
332 | {"pcmpbc" ,INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x84000400, OPCODE_MASK_H4, pcmpbc, logical_inst }, |
333 | {"pcmpeq" ,INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000400, OPCODE_MASK_H4, pcmpeq, logical_inst }, |
334 | {"pcmpne" ,INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x8C000400, OPCODE_MASK_H4, pcmpne, logical_inst }, |
335 | {"sra" , INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000001, OPCODE_MASK_H34, sra, logical_inst }, |
336 | {"src" , INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000021, OPCODE_MASK_H34, src, logical_inst }, |
337 | {"srl" , INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000041, OPCODE_MASK_H34, srl, logical_inst }, |
338 | {"sext8" , INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000060, OPCODE_MASK_H34, sext8, logical_inst }, |
339 | {"sext16" ,INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000061, OPCODE_MASK_H34, sext16, logical_inst }, |
340 | {"wic" , INST_TYPE_RD_R1_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000068, OPCODE_MASK_H34B, wic, special_inst }, |
341 | {"wdc" , INST_TYPE_RD_R1_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000064, OPCODE_MASK_H34B, wdc, special_inst }, |
342 | {"wdc.clear" , INST_TYPE_RD_R1_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000066, OPCODE_MASK_H34B, wdcclear, special_inst }, |
343 | {"wdc.flush" , INST_TYPE_RD_R1_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000074, OPCODE_MASK_H34B, wdcflush, special_inst }, |
344 | {"mts" , INST_TYPE_SPECIAL_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MTS, 0x9400C000, OPCODE_MASK_H13S, mts, special_inst }, |
345 | {"mfs" , INST_TYPE_RD_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MFS, 0x94008000, OPCODE_MASK_H23S, mfs, special_inst }, |
346 | {"br" , INST_TYPE_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98000000, OPCODE_MASK_H124, br, branch_inst }, |
347 | {"brd" , INST_TYPE_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98100000, OPCODE_MASK_H124, brd, branch_inst }, |
348 | {"brld" , INST_TYPE_RD_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98140000, OPCODE_MASK_H24, brld, branch_inst }, |
349 | {"bra" , INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98080000, OPCODE_MASK_H124, bra, branch_inst }, |
350 | {"brad" , INST_TYPE_R2, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98180000, OPCODE_MASK_H124, brad, branch_inst }, |
351 | {"brald" , INST_TYPE_RD_R2, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x981C0000, OPCODE_MASK_H24, brald, branch_inst }, |
352 | {"brk" , INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x980C0000, OPCODE_MASK_H24, microblaze_brk, branch_inst }, |
353 | {"beq" , INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9C000000, OPCODE_MASK_H14, beq, branch_inst }, |
354 | {"beqd" , INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9E000000, OPCODE_MASK_H14, beqd, branch_inst }, |
355 | {"bne" , INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9C200000, OPCODE_MASK_H14, bne, branch_inst }, |
356 | {"bned" , INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9E200000, OPCODE_MASK_H14, bned, branch_inst }, |
357 | {"blt" , INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9C400000, OPCODE_MASK_H14, blt, branch_inst }, |
358 | {"bltd" , INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9E400000, OPCODE_MASK_H14, bltd, branch_inst }, |
359 | {"ble" , INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9C600000, OPCODE_MASK_H14, ble, branch_inst }, |
360 | {"bled" , INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9E600000, OPCODE_MASK_H14, bled, branch_inst }, |
361 | {"bgt" , INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9C800000, OPCODE_MASK_H14, bgt, branch_inst }, |
362 | {"bgtd" , INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9E800000, OPCODE_MASK_H14, bgtd, branch_inst }, |
363 | {"bge" , INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9CA00000, OPCODE_MASK_H14, bge, branch_inst }, |
364 | {"bged" , INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9EA00000, OPCODE_MASK_H14, bged, branch_inst }, |
365 | {"ori" , INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA0000000, OPCODE_MASK_H, ori, logical_inst }, |
366 | {"andi" , INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA4000000, OPCODE_MASK_H, andi, logical_inst }, |
367 | {"xori" , INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA8000000, OPCODE_MASK_H, xori, logical_inst }, |
368 | {"andni" , INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xAC000000, OPCODE_MASK_H, andni, logical_inst }, |
369 | {"imm" , INST_TYPE_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB0000000, OPCODE_MASK_H12, imm, immediate_inst }, |
370 | {"rtsd" , INST_TYPE_R1_IMM, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB6000000, OPCODE_MASK_H1, rtsd, return_inst }, |
371 | {"rtid" , INST_TYPE_R1_IMM, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB6200000, OPCODE_MASK_H1, rtid, return_inst }, |
372 | {"rtbd" , INST_TYPE_R1_IMM, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB6400000, OPCODE_MASK_H1, rtbd, return_inst }, |
373 | {"rted" , INST_TYPE_R1_IMM, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB6800000, OPCODE_MASK_H1, rted, return_inst }, |
374 | {"bri" , INST_TYPE_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8000000, OPCODE_MASK_H12, bri, branch_inst }, |
375 | {"brid" , INST_TYPE_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8100000, OPCODE_MASK_H12, brid, branch_inst }, |
376 | {"brlid" , INST_TYPE_RD_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8140000, OPCODE_MASK_H2, brlid, branch_inst }, |
377 | {"brai" , INST_TYPE_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8080000, OPCODE_MASK_H12, brai, branch_inst }, |
378 | {"braid" , INST_TYPE_IMM, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8180000, OPCODE_MASK_H12, braid, branch_inst }, |
379 | {"bralid" ,INST_TYPE_RD_IMM, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB81C0000, OPCODE_MASK_H2, bralid, branch_inst }, |
380 | {"brki" , INST_TYPE_RD_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB80C0000, OPCODE_MASK_H2, brki, branch_inst }, |
381 | {"beqi" , INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBC000000, OPCODE_MASK_H1, beqi, branch_inst }, |
382 | {"beqid" , INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBE000000, OPCODE_MASK_H1, beqid, branch_inst }, |
383 | {"bnei" , INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBC200000, OPCODE_MASK_H1, bnei, branch_inst }, |
384 | {"bneid" , INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBE200000, OPCODE_MASK_H1, bneid, branch_inst }, |
385 | {"blti" , INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBC400000, OPCODE_MASK_H1, blti, branch_inst }, |
386 | {"bltid" , INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBE400000, OPCODE_MASK_H1, bltid, branch_inst }, |
387 | {"blei" , INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBC600000, OPCODE_MASK_H1, blei, branch_inst }, |
388 | {"bleid" , INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBE600000, OPCODE_MASK_H1, bleid, branch_inst }, |
389 | {"bgti" , INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBC800000, OPCODE_MASK_H1, bgti, branch_inst }, |
390 | {"bgtid" , INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBE800000, OPCODE_MASK_H1, bgtid, branch_inst }, |
391 | {"bgei" , INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBCA00000, OPCODE_MASK_H1, bgei, branch_inst }, |
392 | {"bgeid" , INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBEA00000, OPCODE_MASK_H1, bgeid, branch_inst }, |
393 | {"lbu" , INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000000, OPCODE_MASK_H4, lbu, memory_load_inst }, |
394 | {"lhu" , INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000000, OPCODE_MASK_H4, lhu, memory_load_inst }, |
395 | {"lw" , INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000000, OPCODE_MASK_H4, lw, memory_load_inst }, |
396 | {"lwx" , INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000400, OPCODE_MASK_H4, lwx, memory_load_inst }, |
397 | {"sb" , INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000000, OPCODE_MASK_H4, sb, memory_store_inst }, |
398 | {"sh" , INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000000, OPCODE_MASK_H4, sh, memory_store_inst }, |
399 | {"sw" , INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000000, OPCODE_MASK_H4, sw, memory_store_inst }, |
400 | {"swx" , INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000400, OPCODE_MASK_H4, swx, memory_store_inst }, |
401 | {"lbui" , INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE0000000, OPCODE_MASK_H, lbui, memory_load_inst }, |
402 | {"lhui" , INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE4000000, OPCODE_MASK_H, lhui, memory_load_inst }, |
403 | {"lwi" , INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE8000000, OPCODE_MASK_H, lwi, memory_load_inst }, |
404 | {"sbi" , INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xF0000000, OPCODE_MASK_H, sbi, memory_store_inst }, |
405 | {"shi" , INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xF4000000, OPCODE_MASK_H, shi, memory_store_inst }, |
406 | {"swi" , INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xF8000000, OPCODE_MASK_H, swi, memory_store_inst }, |
407 | {"nop" , INST_TYPE_NONE, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000000, OPCODE_MASK_H1234, invalid_inst, logical_inst }, /* translates to or r0, r0, r0 */ |
408 | {"la" , INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* la translates to addik */ |
409 | {"tuqula" ,INST_TYPE_RD, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x3000002A, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* tuqula rd translates to addik rd, r0, 42 */ |
410 | {"not" , INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA800FFFF, OPCODE_MASK_H34, invalid_inst, logical_inst }, /* not translates to xori rd,ra,-1 */ |
411 | {"neg" , INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* neg translates to rsub rd, ra, r0 */ |
412 | {"rtb" , INST_TYPE_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB6000004, OPCODE_MASK_H1, invalid_inst, return_inst }, /* rtb translates to rts rd, 4 */ |
413 | {"sub" , INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* sub translates to rsub rd, rb, ra */ |
414 | {"lmi" , INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE8000000, OPCODE_MASK_H, invalid_inst, memory_load_inst }, |
415 | {"smi" , INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xF8000000, OPCODE_MASK_H, invalid_inst, memory_store_inst }, |
416 | {"msrset" ,INST_TYPE_RD_IMM15, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x94100000, OPCODE_MASK_H23N, msrset, special_inst }, |
417 | {"msrclr" ,INST_TYPE_RD_IMM15, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x94110000, OPCODE_MASK_H23N, msrclr, special_inst }, |
418 | {"fadd" , INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000000, OPCODE_MASK_H4, fadd, arithmetic_inst }, |
419 | {"frsub" , INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000080, OPCODE_MASK_H4, frsub, arithmetic_inst }, |
420 | {"fmul" , INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000100, OPCODE_MASK_H4, fmul, arithmetic_inst }, |
421 | {"fdiv" , INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000180, OPCODE_MASK_H4, fdiv, arithmetic_inst }, |
422 | {"fcmp.lt" , INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000210, OPCODE_MASK_H4, fcmp_lt, arithmetic_inst }, |
423 | {"fcmp.eq" , INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000220, OPCODE_MASK_H4, fcmp_eq, arithmetic_inst }, |
424 | {"fcmp.le" , INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000230, OPCODE_MASK_H4, fcmp_le, arithmetic_inst }, |
425 | {"fcmp.gt" , INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000240, OPCODE_MASK_H4, fcmp_gt, arithmetic_inst }, |
426 | {"fcmp.ne" , INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000250, OPCODE_MASK_H4, fcmp_ne, arithmetic_inst }, |
427 | {"fcmp.ge" , INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000260, OPCODE_MASK_H4, fcmp_ge, arithmetic_inst }, |
428 | {"fcmp.un" , INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000200, OPCODE_MASK_H4, fcmp_un, arithmetic_inst }, |
429 | {"flt" , INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000280, OPCODE_MASK_H4, flt, arithmetic_inst }, |
430 | {"fint" , INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000300, OPCODE_MASK_H4, fint, arithmetic_inst }, |
431 | {"fsqrt" , INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000380, OPCODE_MASK_H4, fsqrt, arithmetic_inst }, |
432 | {"tget" , INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C001000, OPCODE_MASK_H32, tget, anyware_inst }, |
433 | {"tcget" , INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C003000, OPCODE_MASK_H32, tcget, anyware_inst }, |
434 | {"tnget" , INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C005000, OPCODE_MASK_H32, tnget, anyware_inst }, |
435 | {"tncget" , INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C007000, OPCODE_MASK_H32, tncget, anyware_inst }, |
436 | {"tput" , INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C009000, OPCODE_MASK_H32, tput, anyware_inst }, |
437 | {"tcput" , INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00B000, OPCODE_MASK_H32, tcput, anyware_inst }, |
438 | {"tnput" , INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00D000, OPCODE_MASK_H32, tnput, anyware_inst }, |
439 | {"tncput" , INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00F000, OPCODE_MASK_H32, tncput, anyware_inst }, |
440 | |
441 | {"eget" , INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C000400, OPCODE_MASK_H32, eget, anyware_inst }, |
442 | {"ecget" , INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C002400, OPCODE_MASK_H32, ecget, anyware_inst }, |
443 | {"neget" , INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C004400, OPCODE_MASK_H32, neget, anyware_inst }, |
444 | {"necget" , INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C006400, OPCODE_MASK_H32, necget, anyware_inst }, |
445 | {"eput" , INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C008400, OPCODE_MASK_H32, eput, anyware_inst }, |
446 | {"ecput" , INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00A400, OPCODE_MASK_H32, ecput, anyware_inst }, |
447 | {"neput" , INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00C400, OPCODE_MASK_H32, neput, anyware_inst }, |
448 | {"necput" , INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00E400, OPCODE_MASK_H32, necput, anyware_inst }, |
449 | |
450 | {"teget" , INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C001400, OPCODE_MASK_H32, teget, anyware_inst }, |
451 | {"tecget" , INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C003400, OPCODE_MASK_H32, tecget, anyware_inst }, |
452 | {"tneget" , INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C005400, OPCODE_MASK_H32, tneget, anyware_inst }, |
453 | {"tnecget" , INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C007400, OPCODE_MASK_H32, tnecget, anyware_inst }, |
454 | {"teput" , INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C009400, OPCODE_MASK_H32, teput, anyware_inst }, |
455 | {"tecput" , INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00B400, OPCODE_MASK_H32, tecput, anyware_inst }, |
456 | {"tneput" , INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00D400, OPCODE_MASK_H32, tneput, anyware_inst }, |
457 | {"tnecput" , INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00F400, OPCODE_MASK_H32, tnecput, anyware_inst }, |
458 | |
459 | {"aget" , INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C000800, OPCODE_MASK_H32, aget, anyware_inst }, |
460 | {"caget" , INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C002800, OPCODE_MASK_H32, caget, anyware_inst }, |
461 | {"naget" , INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C004800, OPCODE_MASK_H32, naget, anyware_inst }, |
462 | {"ncaget" , INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C006800, OPCODE_MASK_H32, ncaget, anyware_inst }, |
463 | {"aput" , INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C008800, OPCODE_MASK_H32, aput, anyware_inst }, |
464 | {"caput" , INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00A800, OPCODE_MASK_H32, caput, anyware_inst }, |
465 | {"naput" , INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00C800, OPCODE_MASK_H32, naput, anyware_inst }, |
466 | {"ncaput" , INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00E800, OPCODE_MASK_H32, ncaput, anyware_inst }, |
467 | |
468 | {"taget" , INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C001800, OPCODE_MASK_H32, taget, anyware_inst }, |
469 | {"tcaget" , INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C003800, OPCODE_MASK_H32, tcaget, anyware_inst }, |
470 | {"tnaget" , INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C005800, OPCODE_MASK_H32, tnaget, anyware_inst }, |
471 | {"tncaget" , INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C007800, OPCODE_MASK_H32, tncaget, anyware_inst }, |
472 | {"taput" , INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C009800, OPCODE_MASK_H32, taput, anyware_inst }, |
473 | {"tcaput" , INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00B800, OPCODE_MASK_H32, tcaput, anyware_inst }, |
474 | {"tnaput" , INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00D800, OPCODE_MASK_H32, tnaput, anyware_inst }, |
475 | {"tncaput" , INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00F800, OPCODE_MASK_H32, tncaput, anyware_inst }, |
476 | |
477 | {"eaget" , INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C000C00, OPCODE_MASK_H32, eget, anyware_inst }, |
478 | {"ecaget" , INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C002C00, OPCODE_MASK_H32, ecget, anyware_inst }, |
479 | {"neaget" , INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C004C00, OPCODE_MASK_H32, neget, anyware_inst }, |
480 | {"necaget" , INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C006C00, OPCODE_MASK_H32, necget, anyware_inst }, |
481 | {"eaput" , INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C008C00, OPCODE_MASK_H32, eput, anyware_inst }, |
482 | {"ecaput" , INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00AC00, OPCODE_MASK_H32, ecput, anyware_inst }, |
483 | {"neaput" , INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00CC00, OPCODE_MASK_H32, neput, anyware_inst }, |
484 | {"necaput" , INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00EC00, OPCODE_MASK_H32, necput, anyware_inst }, |
485 | |
486 | {"teaget" , INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C001C00, OPCODE_MASK_H32, teaget, anyware_inst }, |
487 | {"tecaget" , INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C003C00, OPCODE_MASK_H32, tecaget, anyware_inst }, |
488 | {"tneaget" , INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C005C00, OPCODE_MASK_H32, tneaget, anyware_inst }, |
489 | {"tnecaget" , INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C007C00, OPCODE_MASK_H32, tnecaget, anyware_inst }, |
490 | {"teaput" , INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C009C00, OPCODE_MASK_H32, teaput, anyware_inst }, |
491 | {"tecaput" , INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00BC00, OPCODE_MASK_H32, tecaput, anyware_inst }, |
492 | {"tneaput" , INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00DC00, OPCODE_MASK_H32, tneaput, anyware_inst }, |
493 | {"tnecaput" , INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00FC00, OPCODE_MASK_H32, tnecaput, anyware_inst }, |
494 | |
495 | {"getd" , INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000000, OPCODE_MASK_H34C, getd, anyware_inst }, |
496 | {"tgetd" , INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000080, OPCODE_MASK_H34C, tgetd, anyware_inst }, |
497 | {"cgetd" , INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000100, OPCODE_MASK_H34C, cgetd, anyware_inst }, |
498 | {"tcgetd" , INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000180, OPCODE_MASK_H34C, tcgetd, anyware_inst }, |
499 | {"ngetd" , INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000200, OPCODE_MASK_H34C, ngetd, anyware_inst }, |
500 | {"tngetd" , INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000280, OPCODE_MASK_H34C, tngetd, anyware_inst }, |
501 | {"ncgetd" , INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000300, OPCODE_MASK_H34C, ncgetd, anyware_inst }, |
502 | {"tncgetd" , INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000380, OPCODE_MASK_H34C, tncgetd, anyware_inst }, |
503 | {"putd" , INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000400, OPCODE_MASK_H34C, putd, anyware_inst }, |
504 | {"tputd" , INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000480, OPCODE_MASK_H34C, tputd, anyware_inst }, |
505 | {"cputd" , INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000500, OPCODE_MASK_H34C, cputd, anyware_inst }, |
506 | {"tcputd" , INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000580, OPCODE_MASK_H34C, tcputd, anyware_inst }, |
507 | {"nputd" , INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000600, OPCODE_MASK_H34C, nputd, anyware_inst }, |
508 | {"tnputd" , INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000680, OPCODE_MASK_H34C, tnputd, anyware_inst }, |
509 | {"ncputd" , INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000700, OPCODE_MASK_H34C, ncputd, anyware_inst }, |
510 | {"tncputd" , INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000780, OPCODE_MASK_H34C, tncputd, anyware_inst }, |
511 | |
512 | {"egetd" , INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000020, OPCODE_MASK_H34C, egetd, anyware_inst }, |
513 | {"tegetd" , INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0000A0, OPCODE_MASK_H34C, tegetd, anyware_inst }, |
514 | {"ecgetd" , INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000120, OPCODE_MASK_H34C, ecgetd, anyware_inst }, |
515 | {"tecgetd" , INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0001A0, OPCODE_MASK_H34C, tecgetd, anyware_inst }, |
516 | {"negetd" , INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000220, OPCODE_MASK_H34C, negetd, anyware_inst }, |
517 | {"tnegetd" , INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0002A0, OPCODE_MASK_H34C, tnegetd, anyware_inst }, |
518 | {"necgetd" , INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000320, OPCODE_MASK_H34C, necgetd, anyware_inst }, |
519 | {"tnecgetd" , INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0003A0, OPCODE_MASK_H34C, tnecgetd, anyware_inst }, |
520 | {"eputd" , INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000420, OPCODE_MASK_H34C, eputd, anyware_inst }, |
521 | {"teputd" , INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0004A0, OPCODE_MASK_H34C, teputd, anyware_inst }, |
522 | {"ecputd" , INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000520, OPCODE_MASK_H34C, ecputd, anyware_inst }, |
523 | {"tecputd" , INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0005A0, OPCODE_MASK_H34C, tecputd, anyware_inst }, |
524 | {"neputd" , INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000620, OPCODE_MASK_H34C, neputd, anyware_inst }, |
525 | {"tneputd" , INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0006A0, OPCODE_MASK_H34C, tneputd, anyware_inst }, |
526 | {"necputd" , INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000720, OPCODE_MASK_H34C, necputd, anyware_inst }, |
527 | {"tnecputd" , INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0007A0, OPCODE_MASK_H34C, tnecputd, anyware_inst }, |
528 | |
529 | {"agetd" , INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000040, OPCODE_MASK_H34C, agetd, anyware_inst }, |
530 | {"tagetd" , INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0000C0, OPCODE_MASK_H34C, tagetd, anyware_inst }, |
531 | {"cagetd" , INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000140, OPCODE_MASK_H34C, cagetd, anyware_inst }, |
532 | {"tcagetd" , INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0001C0, OPCODE_MASK_H34C, tcagetd, anyware_inst }, |
533 | {"nagetd" , INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000240, OPCODE_MASK_H34C, nagetd, anyware_inst }, |
534 | {"tnagetd" , INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0002C0, OPCODE_MASK_H34C, tnagetd, anyware_inst }, |
535 | {"ncagetd" , INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000340, OPCODE_MASK_H34C, ncagetd, anyware_inst }, |
536 | {"tncagetd" , INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0003C0, OPCODE_MASK_H34C, tncagetd, anyware_inst }, |
537 | {"aputd" , INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000440, OPCODE_MASK_H34C, aputd, anyware_inst }, |
538 | {"taputd" , INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0004C0, OPCODE_MASK_H34C, taputd, anyware_inst }, |
539 | {"caputd" , INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000540, OPCODE_MASK_H34C, caputd, anyware_inst }, |
540 | {"tcaputd" , INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0005C0, OPCODE_MASK_H34C, tcaputd, anyware_inst }, |
541 | {"naputd" , INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000640, OPCODE_MASK_H34C, naputd, anyware_inst }, |
542 | {"tnaputd" , INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0006C0, OPCODE_MASK_H34C, tnaputd, anyware_inst }, |
543 | {"ncaputd" , INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000740, OPCODE_MASK_H34C, ncaputd, anyware_inst }, |
544 | {"tncaputd" , INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0007C0, OPCODE_MASK_H34C, tncaputd, anyware_inst }, |
545 | |
546 | {"eagetd" , INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000060, OPCODE_MASK_H34C, eagetd, anyware_inst }, |
547 | {"teagetd" , INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0000E0, OPCODE_MASK_H34C, teagetd, anyware_inst }, |
548 | {"ecagetd" , INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000160, OPCODE_MASK_H34C, ecagetd, anyware_inst }, |
549 | {"tecagetd" , INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0001E0, OPCODE_MASK_H34C, tecagetd, anyware_inst }, |
550 | {"neagetd" , INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000260, OPCODE_MASK_H34C, neagetd, anyware_inst }, |
551 | {"tneagetd" , INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0002E0, OPCODE_MASK_H34C, tneagetd, anyware_inst }, |
552 | {"necagetd" , INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000360, OPCODE_MASK_H34C, necagetd, anyware_inst }, |
553 | {"tnecagetd" , INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0003E0, OPCODE_MASK_H34C, tnecagetd, anyware_inst }, |
554 | {"eaputd" , INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000460, OPCODE_MASK_H34C, eaputd, anyware_inst }, |
555 | {"teaputd" , INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0004E0, OPCODE_MASK_H34C, teaputd, anyware_inst }, |
556 | {"ecaputd" , INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000560, OPCODE_MASK_H34C, ecaputd, anyware_inst }, |
557 | {"tecaputd" , INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0005E0, OPCODE_MASK_H34C, tecaputd, anyware_inst }, |
558 | {"neaputd" , INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000660, OPCODE_MASK_H34C, neaputd, anyware_inst }, |
559 | {"tneaputd" , INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0006E0, OPCODE_MASK_H34C, tneaputd, anyware_inst }, |
560 | {"necaputd" , INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000760, OPCODE_MASK_H34C, necaputd, anyware_inst }, |
561 | {"tnecaputd" , INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0007E0, OPCODE_MASK_H34C, tnecaputd, anyware_inst }, |
562 | {"" , 0, 0, 0, 0, 0, 0, 0, 0}, |
563 | }; |
564 | |
565 | /* prefix for register names */ |
566 | static const char register_prefix[] = "r" ; |
567 | static const char fsl_register_prefix[] = "rfsl" ; |
568 | static const char pvr_register_prefix[] = "rpvr" ; |
569 | |
570 | |
571 | /* #defines for valid immediate range */ |
572 | #define MIN_IMM ((int) 0x80000000) |
573 | #define MAX_IMM ((int) 0x7fffffff) |
574 | |
575 | #define MIN_IMM15 ((int) 0x0000) |
576 | #define MAX_IMM15 ((int) 0x7fff) |
577 | |
578 | #endif /* MICROBLAZE_OPC */ |
579 | |
580 | #include "disas/dis-asm.h" |
581 | |
582 | #define get_field_rd(instr) get_field(instr, RD_MASK, RD_LOW) |
583 | #define get_field_r1(instr) get_field(instr, RA_MASK, RA_LOW) |
584 | #define get_field_r2(instr) get_field(instr, RB_MASK, RB_LOW) |
585 | #define get_int_field_imm(instr) ((instr & IMM_MASK) >> IMM_LOW) |
586 | #define get_int_field_r1(instr) ((instr & RA_MASK) >> RA_LOW) |
587 | |
588 | /* Local function prototypes. */ |
589 | |
590 | static char * get_field (long instr, long mask, unsigned short low); |
591 | static char * get_field_imm (long instr); |
592 | static char * get_field_imm5 (long instr); |
593 | static char * get_field_rfsl (long instr); |
594 | static char * get_field_imm15 (long instr); |
595 | #if 0 |
596 | static char * get_field_unsigned_imm (long instr); |
597 | #endif |
598 | |
599 | static char * |
600 | get_field (long instr, long mask, unsigned short low) |
601 | { |
602 | char tmpstr[25]; |
603 | sprintf(tmpstr, "%s%d" , register_prefix, (int)((instr & mask) >> low)); |
604 | return(strdup(tmpstr)); |
605 | } |
606 | |
607 | static char * |
608 | get_field_imm (long instr) |
609 | { |
610 | char tmpstr[25]; |
611 | sprintf(tmpstr, "%d" , (short)((instr & IMM_MASK) >> IMM_LOW)); |
612 | return(strdup(tmpstr)); |
613 | } |
614 | |
615 | static char * |
616 | get_field_imm5 (long instr) |
617 | { |
618 | char tmpstr[25]; |
619 | sprintf(tmpstr, "%d" , (short)((instr & IMM5_MASK) >> IMM_LOW)); |
620 | return(strdup(tmpstr)); |
621 | } |
622 | |
623 | static char * |
624 | get_field_rfsl (long instr) |
625 | { |
626 | char tmpstr[25]; |
627 | sprintf(tmpstr, "%s%d" , fsl_register_prefix, (short)((instr & RFSL_MASK) >> IMM_LOW)); |
628 | return(strdup(tmpstr)); |
629 | } |
630 | |
631 | static char * |
632 | get_field_imm15 (long instr) |
633 | { |
634 | char tmpstr[25]; |
635 | sprintf(tmpstr, "%d" , (short)((instr & IMM15_MASK) >> IMM_LOW)); |
636 | return(strdup(tmpstr)); |
637 | } |
638 | |
639 | #if 0 |
640 | static char * |
641 | get_field_unsigned_imm (long instr) |
642 | { |
643 | char tmpstr[25]; |
644 | sprintf(tmpstr, "%d" , (int)((instr & IMM_MASK) >> IMM_LOW)); |
645 | return(strdup(tmpstr)); |
646 | } |
647 | #endif |
648 | |
649 | /* |
650 | char * |
651 | get_field_special (instr) |
652 | long instr; |
653 | { |
654 | char tmpstr[25]; |
655 | |
656 | sprintf(tmpstr, "%s%s", register_prefix, (((instr & IMM_MASK) >> IMM_LOW) & REG_MSR_MASK) == 0 ? "pc" : "msr"); |
657 | |
658 | return(strdup(tmpstr)); |
659 | } |
660 | */ |
661 | |
662 | static char * |
663 | get_field_special(long instr, const struct op_code_struct *op) |
664 | { |
665 | char tmpstr[25]; |
666 | char spr[6]; |
667 | |
668 | switch ( (((instr & IMM_MASK) >> IMM_LOW) ^ op->immval_mask) ) { |
669 | |
670 | case REG_MSR_MASK : |
671 | strcpy(spr, "msr" ); |
672 | break; |
673 | case REG_PC_MASK : |
674 | strcpy(spr, "pc" ); |
675 | break; |
676 | case REG_EAR_MASK : |
677 | strcpy(spr, "ear" ); |
678 | break; |
679 | case REG_ESR_MASK : |
680 | strcpy(spr, "esr" ); |
681 | break; |
682 | case REG_FSR_MASK : |
683 | strcpy(spr, "fsr" ); |
684 | break; |
685 | case REG_BTR_MASK : |
686 | strcpy(spr, "btr" ); |
687 | break; |
688 | case REG_EDR_MASK : |
689 | strcpy(spr, "edr" ); |
690 | break; |
691 | case REG_PID_MASK : |
692 | strcpy(spr, "pid" ); |
693 | break; |
694 | case REG_ZPR_MASK : |
695 | strcpy(spr, "zpr" ); |
696 | break; |
697 | case REG_TLBX_MASK : |
698 | strcpy(spr, "tlbx" ); |
699 | break; |
700 | case REG_TLBLO_MASK : |
701 | strcpy(spr, "tlblo" ); |
702 | break; |
703 | case REG_TLBHI_MASK : |
704 | strcpy(spr, "tlbhi" ); |
705 | break; |
706 | case REG_TLBSX_MASK : |
707 | strcpy(spr, "tlbsx" ); |
708 | break; |
709 | default : |
710 | { |
711 | if ( ((((instr & IMM_MASK) >> IMM_LOW) ^ op->immval_mask) & 0xE000) == REG_PVR_MASK) { |
712 | sprintf(tmpstr, "%s%u" , pvr_register_prefix, |
713 | (unsigned short)(((instr & IMM_MASK) >> IMM_LOW) ^ |
714 | op->immval_mask) ^ REG_PVR_MASK); |
715 | return(strdup(tmpstr)); |
716 | } else { |
717 | strcpy(spr, "pc" ); |
718 | } |
719 | } |
720 | break; |
721 | } |
722 | |
723 | sprintf(tmpstr, "%s%s" , register_prefix, spr); |
724 | return(strdup(tmpstr)); |
725 | } |
726 | |
727 | static unsigned long |
728 | read_insn_microblaze (bfd_vma memaddr, |
729 | struct disassemble_info *info, |
730 | const struct op_code_struct **opr) |
731 | { |
732 | unsigned char ibytes[4]; |
733 | int status; |
734 | const struct op_code_struct *op; |
735 | unsigned long inst; |
736 | |
737 | status = info->read_memory_func (memaddr, ibytes, 4, info); |
738 | |
739 | if (status != 0) |
740 | { |
741 | info->memory_error_func (status, memaddr, info); |
742 | return 0; |
743 | } |
744 | |
745 | if (info->endian == BFD_ENDIAN_BIG) |
746 | inst = ((unsigned)ibytes[0] << 24) | (ibytes[1] << 16) |
747 | | (ibytes[2] << 8) | ibytes[3]; |
748 | else if (info->endian == BFD_ENDIAN_LITTLE) |
749 | inst = ((unsigned)ibytes[3] << 24) | (ibytes[2] << 16) |
750 | | (ibytes[1] << 8) | ibytes[0]; |
751 | else |
752 | abort (); |
753 | |
754 | /* Just a linear search of the table. */ |
755 | for (op = opcodes; op->name != 0; op ++) |
756 | if (op->bit_sequence == (inst & op->opcode_mask)) |
757 | break; |
758 | |
759 | *opr = op; |
760 | return inst; |
761 | } |
762 | |
763 | |
764 | int |
765 | print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info) |
766 | { |
767 | fprintf_function fprintf_func = info->fprintf_func; |
768 | void * stream = info->stream; |
769 | unsigned long inst, prev_inst; |
770 | const struct op_code_struct *op, *pop; |
771 | int immval = 0; |
772 | bfd_boolean immfound = FALSE; |
773 | static bfd_vma prev_insn_addr = -1; /*init the prev insn addr */ |
774 | static int prev_insn_vma = -1; /*init the prev insn vma */ |
775 | int curr_insn_vma = info->buffer_vma; |
776 | |
777 | info->bytes_per_chunk = 4; |
778 | |
779 | inst = read_insn_microblaze (memaddr, info, &op); |
780 | if (inst == 0) { |
781 | return -1; |
782 | } |
783 | |
784 | if (prev_insn_vma == curr_insn_vma) { |
785 | if (memaddr-(info->bytes_per_chunk) == prev_insn_addr) { |
786 | prev_inst = read_insn_microblaze (prev_insn_addr, info, &pop); |
787 | if (prev_inst == 0) |
788 | return -1; |
789 | if (pop->instr == imm) { |
790 | immval = (get_int_field_imm(prev_inst) << 16) & 0xffff0000; |
791 | immfound = TRUE; |
792 | } |
793 | else { |
794 | immval = 0; |
795 | immfound = FALSE; |
796 | } |
797 | } |
798 | } |
799 | /* make curr insn as prev insn */ |
800 | prev_insn_addr = memaddr; |
801 | prev_insn_vma = curr_insn_vma; |
802 | |
803 | if (op->name == 0) { |
804 | fprintf_func (stream, ".short 0x%04lx" , inst); |
805 | } |
806 | else |
807 | { |
808 | fprintf_func (stream, "%s" , op->name); |
809 | |
810 | switch (op->inst_type) |
811 | { |
812 | case INST_TYPE_RD_R1_R2: |
813 | fprintf_func(stream, "\t%s, %s, %s" , get_field_rd(inst), get_field_r1(inst), get_field_r2(inst)); |
814 | break; |
815 | case INST_TYPE_RD_R1_IMM: |
816 | fprintf_func(stream, "\t%s, %s, %s" , get_field_rd(inst), get_field_r1(inst), get_field_imm(inst)); |
817 | if (info->print_address_func && get_int_field_r1(inst) == 0 && info->symbol_at_address_func) { |
818 | if (immfound) |
819 | immval |= (get_int_field_imm(inst) & 0x0000ffff); |
820 | else { |
821 | immval = get_int_field_imm(inst); |
822 | if (immval & 0x8000) |
823 | immval |= 0xFFFF0000; |
824 | } |
825 | if (immval > 0 && info->symbol_at_address_func(immval, info)) { |
826 | fprintf_func (stream, "\t// " ); |
827 | info->print_address_func (immval, info); |
828 | } |
829 | } |
830 | break; |
831 | case INST_TYPE_RD_R1_IMM5: |
832 | fprintf_func(stream, "\t%s, %s, %s" , get_field_rd(inst), get_field_r1(inst), get_field_imm5(inst)); |
833 | break; |
834 | case INST_TYPE_RD_RFSL: |
835 | fprintf_func(stream, "\t%s, %s" , get_field_rd(inst), get_field_rfsl(inst)); |
836 | break; |
837 | case INST_TYPE_R1_RFSL: |
838 | fprintf_func(stream, "\t%s, %s" , get_field_r1(inst), get_field_rfsl(inst)); |
839 | break; |
840 | case INST_TYPE_RD_SPECIAL: |
841 | fprintf_func(stream, "\t%s, %s" , get_field_rd(inst), get_field_special(inst, op)); |
842 | break; |
843 | case INST_TYPE_SPECIAL_R1: |
844 | fprintf_func(stream, "\t%s, %s" , get_field_special(inst, op), get_field_r1(inst)); |
845 | break; |
846 | case INST_TYPE_RD_R1: |
847 | fprintf_func(stream, "\t%s, %s" , get_field_rd(inst), get_field_r1(inst)); |
848 | break; |
849 | case INST_TYPE_R1_R2: |
850 | fprintf_func(stream, "\t%s, %s" , get_field_r1(inst), get_field_r2(inst)); |
851 | break; |
852 | case INST_TYPE_R1_IMM: |
853 | fprintf_func(stream, "\t%s, %s" , get_field_r1(inst), get_field_imm(inst)); |
854 | /* The non-pc relative instructions are returns, which shouldn't |
855 | have a label printed */ |
856 | if (info->print_address_func && op->inst_offset_type == INST_PC_OFFSET && info->symbol_at_address_func) { |
857 | if (immfound) |
858 | immval |= (get_int_field_imm(inst) & 0x0000ffff); |
859 | else { |
860 | immval = get_int_field_imm(inst); |
861 | if (immval & 0x8000) |
862 | immval |= 0xFFFF0000; |
863 | } |
864 | immval += memaddr; |
865 | if (immval > 0 && info->symbol_at_address_func(immval, info)) { |
866 | fprintf_func (stream, "\t// " ); |
867 | info->print_address_func (immval, info); |
868 | } else { |
869 | fprintf_func (stream, "\t\t// " ); |
870 | fprintf_func (stream, "%x" , immval); |
871 | } |
872 | } |
873 | break; |
874 | case INST_TYPE_RD_IMM: |
875 | fprintf_func(stream, "\t%s, %s" , get_field_rd(inst), get_field_imm(inst)); |
876 | if (info->print_address_func && info->symbol_at_address_func) { |
877 | if (immfound) |
878 | immval |= (get_int_field_imm(inst) & 0x0000ffff); |
879 | else { |
880 | immval = get_int_field_imm(inst); |
881 | if (immval & 0x8000) |
882 | immval |= 0xFFFF0000; |
883 | } |
884 | if (op->inst_offset_type == INST_PC_OFFSET) |
885 | immval += (int) memaddr; |
886 | if (info->symbol_at_address_func(immval, info)) { |
887 | fprintf_func (stream, "\t// " ); |
888 | info->print_address_func (immval, info); |
889 | } |
890 | } |
891 | break; |
892 | case INST_TYPE_IMM: |
893 | fprintf_func(stream, "\t%s" , get_field_imm(inst)); |
894 | if (info->print_address_func && info->symbol_at_address_func && op->instr != imm) { |
895 | if (immfound) |
896 | immval |= (get_int_field_imm(inst) & 0x0000ffff); |
897 | else { |
898 | immval = get_int_field_imm(inst); |
899 | if (immval & 0x8000) |
900 | immval |= 0xFFFF0000; |
901 | } |
902 | if (op->inst_offset_type == INST_PC_OFFSET) |
903 | immval += (int) memaddr; |
904 | if (immval > 0 && info->symbol_at_address_func(immval, info)) { |
905 | fprintf_func (stream, "\t// " ); |
906 | info->print_address_func (immval, info); |
907 | } else if (op->inst_offset_type == INST_PC_OFFSET) { |
908 | fprintf_func (stream, "\t\t// " ); |
909 | fprintf_func (stream, "%x" , immval); |
910 | } |
911 | } |
912 | break; |
913 | case INST_TYPE_RD_R2: |
914 | fprintf_func(stream, "\t%s, %s" , get_field_rd(inst), get_field_r2(inst)); |
915 | break; |
916 | case INST_TYPE_R2: |
917 | fprintf_func(stream, "\t%s" , get_field_r2(inst)); |
918 | break; |
919 | case INST_TYPE_R1: |
920 | fprintf_func(stream, "\t%s" , get_field_r1(inst)); |
921 | break; |
922 | case INST_TYPE_RD_R1_SPECIAL: |
923 | fprintf_func(stream, "\t%s, %s" , get_field_rd(inst), get_field_r2(inst)); |
924 | break; |
925 | case INST_TYPE_RD_IMM15: |
926 | fprintf_func(stream, "\t%s, %s" , get_field_rd(inst), get_field_imm15(inst)); |
927 | break; |
928 | /* For tuqula instruction */ |
929 | case INST_TYPE_RD: |
930 | fprintf_func(stream, "\t%s" , get_field_rd(inst)); |
931 | break; |
932 | case INST_TYPE_RFSL: |
933 | fprintf_func(stream, "\t%s" , get_field_rfsl(inst)); |
934 | break; |
935 | default: |
936 | /* if the disassembler lags the instruction set */ |
937 | fprintf_func (stream, "\tundecoded operands, inst is 0x%04lx" , inst); |
938 | break; |
939 | } |
940 | } |
941 | |
942 | /* Say how many bytes we consumed? */ |
943 | return 4; |
944 | } |
945 | |