1 | /* ppc-dis.c -- Disassemble PowerPC instructions |
2 | Copyright 1994, 1995, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007 |
3 | Free Software Foundation, Inc. |
4 | Written by Ian Lance Taylor, Cygnus Support |
5 | |
6 | This file is part of GDB, GAS, and the GNU binutils. |
7 | |
8 | GDB, GAS, and the GNU binutils are free software; you can redistribute |
9 | them and/or modify them under the terms of the GNU General Public |
10 | License as published by the Free Software Foundation; either version |
11 | 2, or (at your option) any later version. |
12 | |
13 | GDB, GAS, and the GNU binutils are distributed in the hope that they |
14 | will be useful, but WITHOUT ANY WARRANTY; without even the implied |
15 | warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See |
16 | the GNU General Public License for more details. |
17 | |
18 | You should have received a copy of the GNU General Public License |
19 | along with this file; see the file COPYING. If not, |
20 | see <http://www.gnu.org/licenses/>. */ |
21 | #include "qemu/osdep.h" |
22 | #include "disas/dis-asm.h" |
23 | #define BFD_DEFAULT_TARGET_SIZE 64 |
24 | |
25 | /* ppc.h -- Header file for PowerPC opcode table |
26 | Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, |
27 | 2007 Free Software Foundation, Inc. |
28 | Written by Ian Lance Taylor, Cygnus Support |
29 | |
30 | This file is part of GDB, GAS, and the GNU binutils. |
31 | |
32 | GDB, GAS, and the GNU binutils are free software; you can redistribute |
33 | them and/or modify them under the terms of the GNU General Public |
34 | License as published by the Free Software Foundation; either version |
35 | 1, or (at your option) any later version. |
36 | |
37 | GDB, GAS, and the GNU binutils are distributed in the hope that they |
38 | will be useful, but WITHOUT ANY WARRANTY; without even the implied |
39 | warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See |
40 | the GNU General Public License for more details. |
41 | |
42 | You should have received a copy of the GNU General Public License |
43 | along with this file; see the file COPYING. If not, |
44 | see <http://www.gnu.org/licenses/>. */ |
45 | |
46 | /* The opcode table is an array of struct powerpc_opcode. */ |
47 | |
48 | struct powerpc_opcode |
49 | { |
50 | /* The opcode name. */ |
51 | const char *name; |
52 | |
53 | /* The opcode itself. Those bits which will be filled in with |
54 | operands are zeroes. */ |
55 | unsigned long opcode; |
56 | |
57 | /* The opcode mask. This is used by the disassembler. This is a |
58 | mask containing ones indicating those bits which must match the |
59 | opcode field, and zeroes indicating those bits which need not |
60 | match (and are presumably filled in by operands). */ |
61 | unsigned long mask; |
62 | |
63 | /* One bit flags for the opcode. These are used to indicate which |
64 | specific processors support the instructions. The defined values |
65 | are listed below. */ |
66 | unsigned long flags; |
67 | |
68 | /* An array of operand codes. Each code is an index into the |
69 | operand table. They appear in the order which the operands must |
70 | appear in assembly code, and are terminated by a zero. */ |
71 | unsigned char operands[8]; |
72 | }; |
73 | |
74 | /* The table itself is sorted by major opcode number, and is otherwise |
75 | in the order in which the disassembler should consider |
76 | instructions. */ |
77 | extern const struct powerpc_opcode powerpc_opcodes[]; |
78 | extern const int powerpc_num_opcodes; |
79 | |
80 | /* Values defined for the flags field of a struct powerpc_opcode. */ |
81 | |
82 | /* Opcode is defined for the PowerPC architecture. */ |
83 | #define PPC_OPCODE_PPC 1 |
84 | |
85 | /* Opcode is defined for the POWER (RS/6000) architecture. */ |
86 | #define PPC_OPCODE_POWER 2 |
87 | |
88 | /* Opcode is defined for the POWER2 (Rios 2) architecture. */ |
89 | #define PPC_OPCODE_POWER2 4 |
90 | |
91 | /* Opcode is only defined on 32 bit architectures. */ |
92 | #define PPC_OPCODE_32 8 |
93 | |
94 | /* Opcode is only defined on 64 bit architectures. */ |
95 | #define PPC_OPCODE_64 0x10 |
96 | |
97 | /* Opcode is supported by the Motorola PowerPC 601 processor. The 601 |
98 | is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions, |
99 | but it also supports many additional POWER instructions. */ |
100 | #define PPC_OPCODE_601 0x20 |
101 | |
102 | /* Opcode is supported in both the Power and PowerPC architectures |
103 | (ie, compiler's -mcpu=common or assembler's -mcom). */ |
104 | #define PPC_OPCODE_COMMON 0x40 |
105 | |
106 | /* Opcode is supported for any Power or PowerPC platform (this is |
107 | for the assembler's -many option, and it eliminates duplicates). */ |
108 | #define PPC_OPCODE_ANY 0x80 |
109 | |
110 | /* Opcode is supported as part of the 64-bit bridge. */ |
111 | #define PPC_OPCODE_64_BRIDGE 0x100 |
112 | |
113 | /* Opcode is supported by Altivec Vector Unit */ |
114 | #define PPC_OPCODE_ALTIVEC 0x200 |
115 | |
116 | /* Opcode is supported by PowerPC 403 processor. */ |
117 | #define PPC_OPCODE_403 0x400 |
118 | |
119 | /* Opcode is supported by PowerPC BookE processor. */ |
120 | #define PPC_OPCODE_BOOKE 0x800 |
121 | |
122 | /* Opcode is only supported by 64-bit PowerPC BookE processor. */ |
123 | #define PPC_OPCODE_BOOKE64 0x1000 |
124 | |
125 | /* Opcode is supported by PowerPC 440 processor. */ |
126 | #define PPC_OPCODE_440 0x2000 |
127 | |
128 | /* Opcode is only supported by Power4 architecture. */ |
129 | #define PPC_OPCODE_POWER4 0x4000 |
130 | |
131 | /* Opcode isn't supported by Power4 architecture. */ |
132 | #define PPC_OPCODE_NOPOWER4 0x8000 |
133 | |
134 | /* Opcode is only supported by POWERPC Classic architecture. */ |
135 | #define PPC_OPCODE_CLASSIC 0x10000 |
136 | |
137 | /* Opcode is only supported by e500x2 Core. */ |
138 | #define PPC_OPCODE_SPE 0x20000 |
139 | |
140 | /* Opcode is supported by e500x2 Integer select APU. */ |
141 | #define PPC_OPCODE_ISEL 0x40000 |
142 | |
143 | /* Opcode is an e500 SPE floating point instruction. */ |
144 | #define PPC_OPCODE_EFS 0x80000 |
145 | |
146 | /* Opcode is supported by branch locking APU. */ |
147 | #define PPC_OPCODE_BRLOCK 0x100000 |
148 | |
149 | /* Opcode is supported by performance monitor APU. */ |
150 | #define PPC_OPCODE_PMR 0x200000 |
151 | |
152 | /* Opcode is supported by cache locking APU. */ |
153 | #define PPC_OPCODE_CACHELCK 0x400000 |
154 | |
155 | /* Opcode is supported by machine check APU. */ |
156 | #define PPC_OPCODE_RFMCI 0x800000 |
157 | |
158 | /* Opcode is only supported by Power5 architecture. */ |
159 | #define PPC_OPCODE_POWER5 0x1000000 |
160 | |
161 | /* Opcode is supported by PowerPC e300 family. */ |
162 | #define PPC_OPCODE_E300 0x2000000 |
163 | |
164 | /* Opcode is only supported by Power6 architecture. */ |
165 | #define PPC_OPCODE_POWER6 0x4000000 |
166 | |
167 | /* Opcode is only supported by PowerPC Cell family. */ |
168 | #define PPC_OPCODE_CELL 0x8000000 |
169 | |
170 | /* A macro to extract the major opcode from an instruction. */ |
171 | #define PPC_OP(i) (((i) >> 26) & 0x3f) |
172 | |
173 | /* The operands table is an array of struct powerpc_operand. */ |
174 | |
175 | struct powerpc_operand |
176 | { |
177 | /* A bitmask of bits in the operand. */ |
178 | unsigned int bitm; |
179 | |
180 | /* How far the operand is left shifted in the instruction. |
181 | -1 to indicate that BITM and SHIFT cannot be used to determine |
182 | where the operand goes in the insn. */ |
183 | int shift; |
184 | |
185 | /* Insertion function. This is used by the assembler. To insert an |
186 | operand value into an instruction, check this field. |
187 | |
188 | If it is NULL, execute |
189 | i |= (op & o->bitm) << o->shift; |
190 | (i is the instruction which we are filling in, o is a pointer to |
191 | this structure, and op is the operand value). |
192 | |
193 | If this field is not NULL, then simply call it with the |
194 | instruction and the operand value. It will return the new value |
195 | of the instruction. If the ERRMSG argument is not NULL, then if |
196 | the operand value is illegal, *ERRMSG will be set to a warning |
197 | string (the operand will be inserted in any case). If the |
198 | operand value is legal, *ERRMSG will be unchanged (most operands |
199 | can accept any value). */ |
200 | unsigned long (*insert) |
201 | (unsigned long instruction, long op, int dialect, const char **errmsg); |
202 | |
203 | /* Extraction function. This is used by the disassembler. To |
204 | extract this operand type from an instruction, check this field. |
205 | |
206 | If it is NULL, compute |
207 | op = (i >> o->shift) & o->bitm; |
208 | if ((o->flags & PPC_OPERAND_SIGNED) != 0) |
209 | sign_extend (op); |
210 | (i is the instruction, o is a pointer to this structure, and op |
211 | is the result). |
212 | |
213 | If this field is not NULL, then simply call it with the |
214 | instruction value. It will return the value of the operand. If |
215 | the INVALID argument is not NULL, *INVALID will be set to |
216 | non-zero if this operand type can not actually be extracted from |
217 | this operand (i.e., the instruction does not match). If the |
218 | operand is valid, *INVALID will not be changed. */ |
219 | long (*extract) (unsigned long instruction, int dialect, int *invalid); |
220 | |
221 | /* One bit syntax flags. */ |
222 | unsigned long flags; |
223 | }; |
224 | |
225 | /* Elements in the table are retrieved by indexing with values from |
226 | the operands field of the powerpc_opcodes table. */ |
227 | |
228 | extern const struct powerpc_operand powerpc_operands[]; |
229 | extern const unsigned int num_powerpc_operands; |
230 | |
231 | /* Values defined for the flags field of a struct powerpc_operand. */ |
232 | |
233 | /* This operand takes signed values. */ |
234 | #define PPC_OPERAND_SIGNED (0x1) |
235 | |
236 | /* This operand takes signed values, but also accepts a full positive |
237 | range of values when running in 32 bit mode. That is, if bits is |
238 | 16, it takes any value from -0x8000 to 0xffff. In 64 bit mode, |
239 | this flag is ignored. */ |
240 | #define PPC_OPERAND_SIGNOPT (0x2) |
241 | |
242 | /* This operand does not actually exist in the assembler input. This |
243 | is used to support extended mnemonics such as mr, for which two |
244 | operands fields are identical. The assembler should call the |
245 | insert function with any op value. The disassembler should call |
246 | the extract function, ignore the return value, and check the value |
247 | placed in the valid argument. */ |
248 | #define PPC_OPERAND_FAKE (0x4) |
249 | |
250 | /* The next operand should be wrapped in parentheses rather than |
251 | separated from this one by a comma. This is used for the load and |
252 | store instructions which want their operands to look like |
253 | reg,displacement(reg) |
254 | */ |
255 | #define PPC_OPERAND_PARENS (0x8) |
256 | |
257 | /* This operand may use the symbolic names for the CR fields, which |
258 | are |
259 | lt 0 gt 1 eq 2 so 3 un 3 |
260 | cr0 0 cr1 1 cr2 2 cr3 3 |
261 | cr4 4 cr5 5 cr6 6 cr7 7 |
262 | These may be combined arithmetically, as in cr2*4+gt. These are |
263 | only supported on the PowerPC, not the POWER. */ |
264 | #define PPC_OPERAND_CR (0x10) |
265 | |
266 | /* This operand names a register. The disassembler uses this to print |
267 | register names with a leading 'r'. */ |
268 | #define PPC_OPERAND_GPR (0x20) |
269 | |
270 | /* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0. */ |
271 | #define PPC_OPERAND_GPR_0 (0x40) |
272 | |
273 | /* This operand names a floating point register. The disassembler |
274 | prints these with a leading 'f'. */ |
275 | #define PPC_OPERAND_FPR (0x80) |
276 | |
277 | /* This operand is a relative branch displacement. The disassembler |
278 | prints these symbolically if possible. */ |
279 | #define PPC_OPERAND_RELATIVE (0x100) |
280 | |
281 | /* This operand is an absolute branch address. The disassembler |
282 | prints these symbolically if possible. */ |
283 | #define PPC_OPERAND_ABSOLUTE (0x200) |
284 | |
285 | /* This operand is optional, and is zero if omitted. This is used for |
286 | example, in the optional BF field in the comparison instructions. The |
287 | assembler must count the number of operands remaining on the line, |
288 | and the number of operands remaining for the opcode, and decide |
289 | whether this operand is present or not. The disassembler should |
290 | print this operand out only if it is not zero. */ |
291 | #define PPC_OPERAND_OPTIONAL (0x400) |
292 | |
293 | /* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand |
294 | is omitted, then for the next operand use this operand value plus |
295 | 1, ignoring the next operand field for the opcode. This wretched |
296 | hack is needed because the Power rotate instructions can take |
297 | either 4 or 5 operands. The disassembler should print this operand |
298 | out regardless of the PPC_OPERAND_OPTIONAL field. */ |
299 | #define PPC_OPERAND_NEXT (0x800) |
300 | |
301 | /* This operand should be regarded as a negative number for the |
302 | purposes of overflow checking (i.e., the normal most negative |
303 | number is disallowed and one more than the normal most positive |
304 | number is allowed). This flag will only be set for a signed |
305 | operand. */ |
306 | #define PPC_OPERAND_NEGATIVE (0x1000) |
307 | |
308 | /* This operand names a vector unit register. The disassembler |
309 | prints these with a leading 'v'. */ |
310 | #define PPC_OPERAND_VR (0x2000) |
311 | |
312 | /* This operand is for the DS field in a DS form instruction. */ |
313 | #define PPC_OPERAND_DS (0x4000) |
314 | |
315 | /* This operand is for the DQ field in a DQ form instruction. */ |
316 | #define PPC_OPERAND_DQ (0x8000) |
317 | |
318 | /* Valid range of operand is 0..n rather than 0..n-1. */ |
319 | #define PPC_OPERAND_PLUS1 (0x10000) |
320 | |
321 | /* The POWER and PowerPC assemblers use a few macros. We keep them |
322 | with the operands table for simplicity. The macro table is an |
323 | array of struct powerpc_macro. */ |
324 | |
325 | struct powerpc_macro |
326 | { |
327 | /* The macro name. */ |
328 | const char *name; |
329 | |
330 | /* The number of operands the macro takes. */ |
331 | unsigned int operands; |
332 | |
333 | /* One bit flags for the opcode. These are used to indicate which |
334 | specific processors support the instructions. The values are the |
335 | same as those for the struct powerpc_opcode flags field. */ |
336 | unsigned long flags; |
337 | |
338 | /* A format string to turn the macro into a normal instruction. |
339 | Each %N in the string is replaced with operand number N (zero |
340 | based). */ |
341 | const char *format; |
342 | }; |
343 | |
344 | extern const struct powerpc_macro powerpc_macros[]; |
345 | extern const int powerpc_num_macros; |
346 | |
347 | /* ppc-opc.c -- PowerPC opcode list |
348 | Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004, |
349 | 2005, 2006, 2007 Free Software Foundation, Inc. |
350 | Written by Ian Lance Taylor, Cygnus Support |
351 | |
352 | This file is part of GDB, GAS, and the GNU binutils. |
353 | |
354 | GDB, GAS, and the GNU binutils are free software; you can redistribute |
355 | them and/or modify them under the terms of the GNU General Public |
356 | License as published by the Free Software Foundation; either version |
357 | 2, or (at your option) any later version. |
358 | |
359 | GDB, GAS, and the GNU binutils are distributed in the hope that they |
360 | will be useful, but WITHOUT ANY WARRANTY; without even the implied |
361 | warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See |
362 | the GNU General Public License for more details. |
363 | |
364 | You should have received a copy of the GNU General Public License |
365 | along with this file; see the file COPYING. |
366 | If not, see <http://www.gnu.org/licenses/>. */ |
367 | |
368 | /* This file holds the PowerPC opcode table. The opcode table |
369 | includes almost all of the extended instruction mnemonics. This |
370 | permits the disassembler to use them, and simplifies the assembler |
371 | logic, at the cost of increasing the table size. The table is |
372 | strictly constant data, so the compiler should be able to put it in |
373 | the .text section. |
374 | |
375 | This file also holds the operand table. All knowledge about |
376 | inserting operands into instructions and vice-versa is kept in this |
377 | file. */ |
378 | |
379 | /* Local insertion and extraction functions. */ |
380 | |
381 | static unsigned long insert_bat (unsigned long, long, int, const char **); |
382 | static long extract_bat (unsigned long, int, int *); |
383 | static unsigned long insert_bba (unsigned long, long, int, const char **); |
384 | static long extract_bba (unsigned long, int, int *); |
385 | static unsigned long insert_bdm (unsigned long, long, int, const char **); |
386 | static long extract_bdm (unsigned long, int, int *); |
387 | static unsigned long insert_bdp (unsigned long, long, int, const char **); |
388 | static long extract_bdp (unsigned long, int, int *); |
389 | static unsigned long insert_bo (unsigned long, long, int, const char **); |
390 | static long extract_bo (unsigned long, int, int *); |
391 | static unsigned long insert_boe (unsigned long, long, int, const char **); |
392 | static long extract_boe (unsigned long, int, int *); |
393 | static unsigned long insert_fxm (unsigned long, long, int, const char **); |
394 | static long extract_fxm (unsigned long, int, int *); |
395 | static unsigned long insert_mbe (unsigned long, long, int, const char **); |
396 | static long extract_mbe (unsigned long, int, int *); |
397 | static unsigned long insert_mb6 (unsigned long, long, int, const char **); |
398 | static long extract_mb6 (unsigned long, int, int *); |
399 | static long extract_nb (unsigned long, int, int *); |
400 | static unsigned long insert_nsi (unsigned long, long, int, const char **); |
401 | static long extract_nsi (unsigned long, int, int *); |
402 | static unsigned long insert_ral (unsigned long, long, int, const char **); |
403 | static unsigned long insert_ram (unsigned long, long, int, const char **); |
404 | static unsigned long insert_raq (unsigned long, long, int, const char **); |
405 | static unsigned long insert_ras (unsigned long, long, int, const char **); |
406 | static unsigned long insert_rbs (unsigned long, long, int, const char **); |
407 | static long extract_rbs (unsigned long, int, int *); |
408 | static unsigned long insert_sh6 (unsigned long, long, int, const char **); |
409 | static long extract_sh6 (unsigned long, int, int *); |
410 | static unsigned long insert_spr (unsigned long, long, int, const char **); |
411 | static long extract_spr (unsigned long, int, int *); |
412 | static unsigned long insert_sprg (unsigned long, long, int, const char **); |
413 | static long extract_sprg (unsigned long, int, int *); |
414 | static unsigned long insert_tbr (unsigned long, long, int, const char **); |
415 | static long extract_tbr (unsigned long, int, int *); |
416 | |
417 | /* The operands table. |
418 | |
419 | The fields are bitm, shift, insert, extract, flags. |
420 | |
421 | We used to put parens around the various additions, like the one |
422 | for BA just below. However, that caused trouble with feeble |
423 | compilers with a limit on depth of a parenthesized expression, like |
424 | (reportedly) the compiler in Microsoft Developer Studio 5. So we |
425 | omit the parens, since the macros are never used in a context where |
426 | the addition will be ambiguous. */ |
427 | |
428 | const struct powerpc_operand powerpc_operands[] = |
429 | { |
430 | /* The zero index is used to indicate the end of the list of |
431 | operands. */ |
432 | #define UNUSED 0 |
433 | { 0, 0, NULL, NULL, 0 }, |
434 | |
435 | /* The BA field in an XL form instruction. */ |
436 | #define BA UNUSED + 1 |
437 | /* The BI field in a B form or XL form instruction. */ |
438 | #define BI BA |
439 | #define BI_MASK (0x1f << 16) |
440 | { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR }, |
441 | |
442 | /* The BA field in an XL form instruction when it must be the same |
443 | as the BT field in the same instruction. */ |
444 | #define BAT BA + 1 |
445 | { 0x1f, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE }, |
446 | |
447 | /* The BB field in an XL form instruction. */ |
448 | #define BB BAT + 1 |
449 | #define BB_MASK (0x1f << 11) |
450 | { 0x1f, 11, NULL, NULL, PPC_OPERAND_CR }, |
451 | |
452 | /* The BB field in an XL form instruction when it must be the same |
453 | as the BA field in the same instruction. */ |
454 | #define BBA BB + 1 |
455 | { 0x1f, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE }, |
456 | |
457 | /* The BD field in a B form instruction. The lower two bits are |
458 | forced to zero. */ |
459 | #define BD BBA + 1 |
460 | { 0xfffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, |
461 | |
462 | /* The BD field in a B form instruction when absolute addressing is |
463 | used. */ |
464 | #define BDA BD + 1 |
465 | { 0xfffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, |
466 | |
467 | /* The BD field in a B form instruction when the - modifier is used. |
468 | This sets the y bit of the BO field appropriately. */ |
469 | #define BDM BDA + 1 |
470 | { 0xfffc, 0, insert_bdm, extract_bdm, |
471 | PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, |
472 | |
473 | /* The BD field in a B form instruction when the - modifier is used |
474 | and absolute address is used. */ |
475 | #define BDMA BDM + 1 |
476 | { 0xfffc, 0, insert_bdm, extract_bdm, |
477 | PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, |
478 | |
479 | /* The BD field in a B form instruction when the + modifier is used. |
480 | This sets the y bit of the BO field appropriately. */ |
481 | #define BDP BDMA + 1 |
482 | { 0xfffc, 0, insert_bdp, extract_bdp, |
483 | PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, |
484 | |
485 | /* The BD field in a B form instruction when the + modifier is used |
486 | and absolute addressing is used. */ |
487 | #define BDPA BDP + 1 |
488 | { 0xfffc, 0, insert_bdp, extract_bdp, |
489 | PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, |
490 | |
491 | /* The BF field in an X or XL form instruction. */ |
492 | #define BF BDPA + 1 |
493 | /* The CRFD field in an X form instruction. */ |
494 | #define CRFD BF |
495 | { 0x7, 23, NULL, NULL, PPC_OPERAND_CR }, |
496 | |
497 | /* The BF field in an X or XL form instruction. */ |
498 | #define BFF BF + 1 |
499 | { 0x7, 23, NULL, NULL, 0 }, |
500 | |
501 | /* An optional BF field. This is used for comparison instructions, |
502 | in which an omitted BF field is taken as zero. */ |
503 | #define OBF BFF + 1 |
504 | { 0x7, 23, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL }, |
505 | |
506 | /* The BFA field in an X or XL form instruction. */ |
507 | #define BFA OBF + 1 |
508 | { 0x7, 18, NULL, NULL, PPC_OPERAND_CR }, |
509 | |
510 | /* The BO field in a B form instruction. Certain values are |
511 | illegal. */ |
512 | #define BO BFA + 1 |
513 | #define BO_MASK (0x1f << 21) |
514 | { 0x1f, 21, insert_bo, extract_bo, 0 }, |
515 | |
516 | /* The BO field in a B form instruction when the + or - modifier is |
517 | used. This is like the BO field, but it must be even. */ |
518 | #define BOE BO + 1 |
519 | { 0x1e, 21, insert_boe, extract_boe, 0 }, |
520 | |
521 | #define BH BOE + 1 |
522 | { 0x3, 11, NULL, NULL, PPC_OPERAND_OPTIONAL }, |
523 | |
524 | /* The BT field in an X or XL form instruction. */ |
525 | #define BT BH + 1 |
526 | { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR }, |
527 | |
528 | /* The condition register number portion of the BI field in a B form |
529 | or XL form instruction. This is used for the extended |
530 | conditional branch mnemonics, which set the lower two bits of the |
531 | BI field. This field is optional. */ |
532 | #define CR BT + 1 |
533 | { 0x7, 18, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL }, |
534 | |
535 | /* The CRB field in an X form instruction. */ |
536 | #define CRB CR + 1 |
537 | /* The MB field in an M form instruction. */ |
538 | #define MB CRB |
539 | #define MB_MASK (0x1f << 6) |
540 | { 0x1f, 6, NULL, NULL, 0 }, |
541 | |
542 | /* The CRFS field in an X form instruction. */ |
543 | #define CRFS CRB + 1 |
544 | { 0x7, 0, NULL, NULL, PPC_OPERAND_CR }, |
545 | |
546 | /* The CT field in an X form instruction. */ |
547 | #define CT CRFS + 1 |
548 | /* The MO field in an mbar instruction. */ |
549 | #define MO CT |
550 | { 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, |
551 | |
552 | /* The D field in a D form instruction. This is a displacement off |
553 | a register, and implies that the next operand is a register in |
554 | parentheses. */ |
555 | #define D CT + 1 |
556 | { 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, |
557 | |
558 | /* The DE field in a DE form instruction. This is like D, but is 12 |
559 | bits only. */ |
560 | #define DE D + 1 |
561 | { 0xfff, 4, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, |
562 | |
563 | /* The DES field in a DES form instruction. This is like DS, but is 14 |
564 | bits only (12 stored.) */ |
565 | #define DES DE + 1 |
566 | { 0x3ffc, 2, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, |
567 | |
568 | /* The DQ field in a DQ form instruction. This is like D, but the |
569 | lower four bits are forced to zero. */ |
570 | #define DQ DES + 1 |
571 | { 0xfff0, 0, NULL, NULL, |
572 | PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ }, |
573 | |
574 | /* The DS field in a DS form instruction. This is like D, but the |
575 | lower two bits are forced to zero. */ |
576 | #undef DS |
577 | #define DS DQ + 1 |
578 | { 0xfffc, 0, NULL, NULL, |
579 | PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS }, |
580 | |
581 | /* The E field in a wrteei instruction. */ |
582 | #define E DS + 1 |
583 | { 0x1, 15, NULL, NULL, 0 }, |
584 | |
585 | /* The FL1 field in a POWER SC form instruction. */ |
586 | #define FL1 E + 1 |
587 | /* The U field in an X form instruction. */ |
588 | #define U FL1 |
589 | { 0xf, 12, NULL, NULL, 0 }, |
590 | |
591 | /* The FL2 field in a POWER SC form instruction. */ |
592 | #define FL2 FL1 + 1 |
593 | { 0x7, 2, NULL, NULL, 0 }, |
594 | |
595 | /* The FLM field in an XFL form instruction. */ |
596 | #define FLM FL2 + 1 |
597 | { 0xff, 17, NULL, NULL, 0 }, |
598 | |
599 | /* The FRA field in an X or A form instruction. */ |
600 | #define FRA FLM + 1 |
601 | #define FRA_MASK (0x1f << 16) |
602 | { 0x1f, 16, NULL, NULL, PPC_OPERAND_FPR }, |
603 | |
604 | /* The FRB field in an X or A form instruction. */ |
605 | #define FRB FRA + 1 |
606 | #define FRB_MASK (0x1f << 11) |
607 | { 0x1f, 11, NULL, NULL, PPC_OPERAND_FPR }, |
608 | |
609 | /* The FRC field in an A form instruction. */ |
610 | #define FRC FRB + 1 |
611 | #define FRC_MASK (0x1f << 6) |
612 | { 0x1f, 6, NULL, NULL, PPC_OPERAND_FPR }, |
613 | |
614 | /* The FRS field in an X form instruction or the FRT field in a D, X |
615 | or A form instruction. */ |
616 | #define FRS FRC + 1 |
617 | #define FRT FRS |
618 | { 0x1f, 21, NULL, NULL, PPC_OPERAND_FPR }, |
619 | |
620 | /* The FXM field in an XFX instruction. */ |
621 | #define FXM FRS + 1 |
622 | { 0xff, 12, insert_fxm, extract_fxm, 0 }, |
623 | |
624 | /* Power4 version for mfcr. */ |
625 | #define FXM4 FXM + 1 |
626 | { 0xff, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL }, |
627 | |
628 | /* The L field in a D or X form instruction. */ |
629 | #define L FXM4 + 1 |
630 | { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, |
631 | |
632 | /* The LEV field in a POWER SVC form instruction. */ |
633 | #define SVC_LEV L + 1 |
634 | { 0x7f, 5, NULL, NULL, 0 }, |
635 | |
636 | /* The LEV field in an SC form instruction. */ |
637 | #define LEV SVC_LEV + 1 |
638 | { 0x7f, 5, NULL, NULL, PPC_OPERAND_OPTIONAL }, |
639 | |
640 | /* The LI field in an I form instruction. The lower two bits are |
641 | forced to zero. */ |
642 | #define LI LEV + 1 |
643 | { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, |
644 | |
645 | /* The LI field in an I form instruction when used as an absolute |
646 | address. */ |
647 | #define LIA LI + 1 |
648 | { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, |
649 | |
650 | /* The LS field in an X (sync) form instruction. */ |
651 | #define LS LIA + 1 |
652 | { 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, |
653 | |
654 | /* The ME field in an M form instruction. */ |
655 | #define ME LS + 1 |
656 | #define ME_MASK (0x1f << 1) |
657 | { 0x1f, 1, NULL, NULL, 0 }, |
658 | |
659 | /* The MB and ME fields in an M form instruction expressed a single |
660 | operand which is a bitmask indicating which bits to select. This |
661 | is a two operand form using PPC_OPERAND_NEXT. See the |
662 | description in opcode/ppc.h for what this means. */ |
663 | #define MBE ME + 1 |
664 | { 0x1f, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT }, |
665 | { -1, 0, insert_mbe, extract_mbe, 0 }, |
666 | |
667 | /* The MB or ME field in an MD or MDS form instruction. The high |
668 | bit is wrapped to the low end. */ |
669 | #define MB6 MBE + 2 |
670 | #define ME6 MB6 |
671 | #define MB6_MASK (0x3f << 5) |
672 | { 0x3f, 5, insert_mb6, extract_mb6, 0 }, |
673 | |
674 | /* The NB field in an X form instruction. The value 32 is stored as |
675 | 0. */ |
676 | #define NB MB6 + 1 |
677 | { 0x1f, 11, NULL, extract_nb, PPC_OPERAND_PLUS1 }, |
678 | |
679 | /* The NSI field in a D form instruction. This is the same as the |
680 | SI field, only negated. */ |
681 | #define NSI NB + 1 |
682 | { 0xffff, 0, insert_nsi, extract_nsi, |
683 | PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED }, |
684 | |
685 | /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */ |
686 | #define RA NSI + 1 |
687 | #define RA_MASK (0x1f << 16) |
688 | { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR }, |
689 | |
690 | /* As above, but 0 in the RA field means zero, not r0. */ |
691 | #define RA0 RA + 1 |
692 | { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR_0 }, |
693 | |
694 | /* The RA field in the DQ form lq instruction, which has special |
695 | value restrictions. */ |
696 | #define RAQ RA0 + 1 |
697 | { 0x1f, 16, insert_raq, NULL, PPC_OPERAND_GPR_0 }, |
698 | |
699 | /* The RA field in a D or X form instruction which is an updating |
700 | load, which means that the RA field may not be zero and may not |
701 | equal the RT field. */ |
702 | #define RAL RAQ + 1 |
703 | { 0x1f, 16, insert_ral, NULL, PPC_OPERAND_GPR_0 }, |
704 | |
705 | /* The RA field in an lmw instruction, which has special value |
706 | restrictions. */ |
707 | #define RAM RAL + 1 |
708 | { 0x1f, 16, insert_ram, NULL, PPC_OPERAND_GPR_0 }, |
709 | |
710 | /* The RA field in a D or X form instruction which is an updating |
711 | store or an updating floating point load, which means that the RA |
712 | field may not be zero. */ |
713 | #define RAS RAM + 1 |
714 | { 0x1f, 16, insert_ras, NULL, PPC_OPERAND_GPR_0 }, |
715 | |
716 | /* The RA field of the tlbwe instruction, which is optional. */ |
717 | #define RAOPT RAS + 1 |
718 | { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL }, |
719 | |
720 | /* The RB field in an X, XO, M, or MDS form instruction. */ |
721 | #define RB RAOPT + 1 |
722 | #define RB_MASK (0x1f << 11) |
723 | { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR }, |
724 | |
725 | /* The RB field in an X form instruction when it must be the same as |
726 | the RS field in the instruction. This is used for extended |
727 | mnemonics like mr. */ |
728 | #define RBS RB + 1 |
729 | { 0x1f, 11, insert_rbs, extract_rbs, PPC_OPERAND_FAKE }, |
730 | |
731 | /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form |
732 | instruction or the RT field in a D, DS, X, XFX or XO form |
733 | instruction. */ |
734 | #define RS RBS + 1 |
735 | #define RT RS |
736 | #define RT_MASK (0x1f << 21) |
737 | { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR }, |
738 | |
739 | /* The RS and RT fields of the DS form stq instruction, which have |
740 | special value restrictions. */ |
741 | #define RSQ RS + 1 |
742 | #define RTQ RSQ |
743 | { 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR_0 }, |
744 | |
745 | /* The RS field of the tlbwe instruction, which is optional. */ |
746 | #define RSO RSQ + 1 |
747 | #define RTO RSO |
748 | { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL }, |
749 | |
750 | /* The SH field in an X or M form instruction. */ |
751 | #define SH RSO + 1 |
752 | #define SH_MASK (0x1f << 11) |
753 | /* The other UIMM field in a EVX form instruction. */ |
754 | #define EVUIMM SH |
755 | { 0x1f, 11, NULL, NULL, 0 }, |
756 | |
757 | /* The SH field in an MD form instruction. This is split. */ |
758 | #define SH6 SH + 1 |
759 | #define SH6_MASK ((0x1f << 11) | (1 << 1)) |
760 | { 0x3f, -1, insert_sh6, extract_sh6, 0 }, |
761 | |
762 | /* The SH field of the tlbwe instruction, which is optional. */ |
763 | #define SHO SH6 + 1 |
764 | { 0x1f, 11, NULL, NULL, PPC_OPERAND_OPTIONAL }, |
765 | |
766 | /* The SI field in a D form instruction. */ |
767 | #define SI SHO + 1 |
768 | { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED }, |
769 | |
770 | /* The SI field in a D form instruction when we accept a wide range |
771 | of positive values. */ |
772 | #define SISIGNOPT SI + 1 |
773 | { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT }, |
774 | |
775 | /* The SPR field in an XFX form instruction. This is flipped--the |
776 | lower 5 bits are stored in the upper 5 and vice- versa. */ |
777 | #define SPR SISIGNOPT + 1 |
778 | #define PMR SPR |
779 | #define SPR_MASK (0x3ff << 11) |
780 | { 0x3ff, 11, insert_spr, extract_spr, 0 }, |
781 | |
782 | /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */ |
783 | #define SPRBAT SPR + 1 |
784 | #define SPRBAT_MASK (0x3 << 17) |
785 | { 0x3, 17, NULL, NULL, 0 }, |
786 | |
787 | /* The SPRG register number in an XFX form m[ft]sprg instruction. */ |
788 | #define SPRG SPRBAT + 1 |
789 | { 0x1f, 16, insert_sprg, extract_sprg, 0 }, |
790 | |
791 | /* The SR field in an X form instruction. */ |
792 | #define SR SPRG + 1 |
793 | { 0xf, 16, NULL, NULL, 0 }, |
794 | |
795 | /* The STRM field in an X AltiVec form instruction. */ |
796 | #define STRM SR + 1 |
797 | { 0x3, 21, NULL, NULL, 0 }, |
798 | |
799 | /* The SV field in a POWER SC form instruction. */ |
800 | #define SV STRM + 1 |
801 | { 0x3fff, 2, NULL, NULL, 0 }, |
802 | |
803 | /* The TBR field in an XFX form instruction. This is like the SPR |
804 | field, but it is optional. */ |
805 | #define TBR SV + 1 |
806 | { 0x3ff, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL }, |
807 | |
808 | /* The TO field in a D or X form instruction. */ |
809 | #define TO TBR + 1 |
810 | #define TO_MASK (0x1f << 21) |
811 | { 0x1f, 21, NULL, NULL, 0 }, |
812 | |
813 | /* The UI field in a D form instruction. */ |
814 | #define UI TO + 1 |
815 | { 0xffff, 0, NULL, NULL, 0 }, |
816 | |
817 | /* The VA field in a VA, VX or VXR form instruction. */ |
818 | #define VA UI + 1 |
819 | { 0x1f, 16, NULL, NULL, PPC_OPERAND_VR }, |
820 | |
821 | /* The VB field in a VA, VX or VXR form instruction. */ |
822 | #define VB VA + 1 |
823 | { 0x1f, 11, NULL, NULL, PPC_OPERAND_VR }, |
824 | |
825 | /* The VC field in a VA form instruction. */ |
826 | #define VC VB + 1 |
827 | { 0x1f, 6, NULL, NULL, PPC_OPERAND_VR }, |
828 | |
829 | /* The VD or VS field in a VA, VX, VXR or X form instruction. */ |
830 | #define VD VC + 1 |
831 | #define VS VD |
832 | { 0x1f, 21, NULL, NULL, PPC_OPERAND_VR }, |
833 | |
834 | /* The SIMM field in a VX form instruction. */ |
835 | #define SIMM VD + 1 |
836 | { 0x1f, 16, NULL, NULL, PPC_OPERAND_SIGNED}, |
837 | |
838 | /* The UIMM field in a VX form instruction, and TE in Z form. */ |
839 | #define UIMM SIMM + 1 |
840 | #define TE UIMM |
841 | { 0x1f, 16, NULL, NULL, 0 }, |
842 | |
843 | /* The SHB field in a VA form instruction. */ |
844 | #define SHB UIMM + 1 |
845 | { 0xf, 6, NULL, NULL, 0 }, |
846 | |
847 | /* The other UIMM field in a half word EVX form instruction. */ |
848 | #define EVUIMM_2 SHB + 1 |
849 | { 0x3e, 10, NULL, NULL, PPC_OPERAND_PARENS }, |
850 | |
851 | /* The other UIMM field in a word EVX form instruction. */ |
852 | #define EVUIMM_4 EVUIMM_2 + 1 |
853 | { 0x7c, 9, NULL, NULL, PPC_OPERAND_PARENS }, |
854 | |
855 | /* The other UIMM field in a double EVX form instruction. */ |
856 | #define EVUIMM_8 EVUIMM_4 + 1 |
857 | { 0xf8, 8, NULL, NULL, PPC_OPERAND_PARENS }, |
858 | |
859 | /* The WS field. */ |
860 | #define WS EVUIMM_8 + 1 |
861 | { 0x7, 11, NULL, NULL, 0 }, |
862 | |
863 | /* The L field in an mtmsrd or A form instruction or W in an X form. */ |
864 | #define A_L WS + 1 |
865 | #define W A_L |
866 | { 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL }, |
867 | |
868 | #define RMC A_L + 1 |
869 | { 0x3, 9, NULL, NULL, 0 }, |
870 | |
871 | #define R RMC + 1 |
872 | { 0x1, 16, NULL, NULL, 0 }, |
873 | |
874 | #define SP R + 1 |
875 | { 0x3, 19, NULL, NULL, 0 }, |
876 | |
877 | #define S SP + 1 |
878 | { 0x1, 20, NULL, NULL, 0 }, |
879 | |
880 | /* SH field starting at bit position 16. */ |
881 | #define SH16 S + 1 |
882 | /* The DCM and DGM fields in a Z form instruction. */ |
883 | #define DCM SH16 |
884 | #define DGM DCM |
885 | { 0x3f, 10, NULL, NULL, 0 }, |
886 | |
887 | /* The EH field in larx instruction. */ |
888 | #define EH SH16 + 1 |
889 | { 0x1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL }, |
890 | |
891 | /* The L field in an mtfsf or XFL form instruction. */ |
892 | #define XFL_L EH + 1 |
893 | { 0x1, 25, NULL, NULL, PPC_OPERAND_OPTIONAL}, |
894 | }; |
895 | |
896 | const unsigned int num_powerpc_operands = (sizeof (powerpc_operands) |
897 | / sizeof (powerpc_operands[0])); |
898 | |
899 | /* The functions used to insert and extract complicated operands. */ |
900 | |
901 | /* The BA field in an XL form instruction when it must be the same as |
902 | the BT field in the same instruction. This operand is marked FAKE. |
903 | The insertion function just copies the BT field into the BA field, |
904 | and the extraction function just checks that the fields are the |
905 | same. */ |
906 | |
907 | static unsigned long |
908 | insert_bat (unsigned long insn, |
909 | long value ATTRIBUTE_UNUSED, |
910 | int dialect ATTRIBUTE_UNUSED, |
911 | const char **errmsg ATTRIBUTE_UNUSED) |
912 | { |
913 | return insn | (((insn >> 21) & 0x1f) << 16); |
914 | } |
915 | |
916 | static long |
917 | (unsigned long insn, |
918 | int dialect ATTRIBUTE_UNUSED, |
919 | int *invalid) |
920 | { |
921 | if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f)) |
922 | *invalid = 1; |
923 | return 0; |
924 | } |
925 | |
926 | /* The BB field in an XL form instruction when it must be the same as |
927 | the BA field in the same instruction. This operand is marked FAKE. |
928 | The insertion function just copies the BA field into the BB field, |
929 | and the extraction function just checks that the fields are the |
930 | same. */ |
931 | |
932 | static unsigned long |
933 | insert_bba (unsigned long insn, |
934 | long value ATTRIBUTE_UNUSED, |
935 | int dialect ATTRIBUTE_UNUSED, |
936 | const char **errmsg ATTRIBUTE_UNUSED) |
937 | { |
938 | return insn | (((insn >> 16) & 0x1f) << 11); |
939 | } |
940 | |
941 | static long |
942 | (unsigned long insn, |
943 | int dialect ATTRIBUTE_UNUSED, |
944 | int *invalid) |
945 | { |
946 | if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f)) |
947 | *invalid = 1; |
948 | return 0; |
949 | } |
950 | |
951 | /* The BD field in a B form instruction when the - modifier is used. |
952 | This modifier means that the branch is not expected to be taken. |
953 | For chips built to versions of the architecture prior to version 2 |
954 | (ie. not Power4 compatible), we set the y bit of the BO field to 1 |
955 | if the offset is negative. When extracting, we require that the y |
956 | bit be 1 and that the offset be positive, since if the y bit is 0 |
957 | we just want to print the normal form of the instruction. |
958 | Power4 compatible targets use two bits, "a", and "t", instead of |
959 | the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable, |
960 | "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001 |
961 | in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000 |
962 | for branch on CTR. We only handle the taken/not-taken hint here. |
963 | Note that we don't relax the conditions tested here when |
964 | disassembling with -Many because insns using extract_bdm and |
965 | extract_bdp always occur in pairs. One or the other will always |
966 | be valid. */ |
967 | |
968 | static unsigned long |
969 | insert_bdm (unsigned long insn, |
970 | long value, |
971 | int dialect, |
972 | const char **errmsg ATTRIBUTE_UNUSED) |
973 | { |
974 | if ((dialect & PPC_OPCODE_POWER4) == 0) |
975 | { |
976 | if ((value & 0x8000) != 0) |
977 | insn |= 1 << 21; |
978 | } |
979 | else |
980 | { |
981 | if ((insn & (0x14 << 21)) == (0x04 << 21)) |
982 | insn |= 0x02 << 21; |
983 | else if ((insn & (0x14 << 21)) == (0x10 << 21)) |
984 | insn |= 0x08 << 21; |
985 | } |
986 | return insn | (value & 0xfffc); |
987 | } |
988 | |
989 | static long |
990 | (unsigned long insn, |
991 | int dialect, |
992 | int *invalid) |
993 | { |
994 | if ((dialect & PPC_OPCODE_POWER4) == 0) |
995 | { |
996 | if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0)) |
997 | *invalid = 1; |
998 | } |
999 | else |
1000 | { |
1001 | if ((insn & (0x17 << 21)) != (0x06 << 21) |
1002 | && (insn & (0x1d << 21)) != (0x18 << 21)) |
1003 | *invalid = 1; |
1004 | } |
1005 | |
1006 | return ((insn & 0xfffc) ^ 0x8000) - 0x8000; |
1007 | } |
1008 | |
1009 | /* The BD field in a B form instruction when the + modifier is used. |
1010 | This is like BDM, above, except that the branch is expected to be |
1011 | taken. */ |
1012 | |
1013 | static unsigned long |
1014 | insert_bdp (unsigned long insn, |
1015 | long value, |
1016 | int dialect, |
1017 | const char **errmsg ATTRIBUTE_UNUSED) |
1018 | { |
1019 | if ((dialect & PPC_OPCODE_POWER4) == 0) |
1020 | { |
1021 | if ((value & 0x8000) == 0) |
1022 | insn |= 1 << 21; |
1023 | } |
1024 | else |
1025 | { |
1026 | if ((insn & (0x14 << 21)) == (0x04 << 21)) |
1027 | insn |= 0x03 << 21; |
1028 | else if ((insn & (0x14 << 21)) == (0x10 << 21)) |
1029 | insn |= 0x09 << 21; |
1030 | } |
1031 | return insn | (value & 0xfffc); |
1032 | } |
1033 | |
1034 | static long |
1035 | (unsigned long insn, |
1036 | int dialect, |
1037 | int *invalid) |
1038 | { |
1039 | if ((dialect & PPC_OPCODE_POWER4) == 0) |
1040 | { |
1041 | if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0)) |
1042 | *invalid = 1; |
1043 | } |
1044 | else |
1045 | { |
1046 | if ((insn & (0x17 << 21)) != (0x07 << 21) |
1047 | && (insn & (0x1d << 21)) != (0x19 << 21)) |
1048 | *invalid = 1; |
1049 | } |
1050 | |
1051 | return ((insn & 0xfffc) ^ 0x8000) - 0x8000; |
1052 | } |
1053 | |
1054 | /* Check for legal values of a BO field. */ |
1055 | |
1056 | static int |
1057 | valid_bo (long value, int dialect, int ) |
1058 | { |
1059 | if ((dialect & PPC_OPCODE_POWER4) == 0) |
1060 | { |
1061 | int valid; |
1062 | /* Certain encodings have bits that are required to be zero. |
1063 | These are (z must be zero, y may be anything): |
1064 | 001zy |
1065 | 011zy |
1066 | 1z00y |
1067 | 1z01y |
1068 | 1z1zz |
1069 | */ |
1070 | switch (value & 0x14) |
1071 | { |
1072 | default: |
1073 | case 0: |
1074 | valid = 1; |
1075 | break; |
1076 | case 0x4: |
1077 | valid = (value & 0x2) == 0; |
1078 | break; |
1079 | case 0x10: |
1080 | valid = (value & 0x8) == 0; |
1081 | break; |
1082 | case 0x14: |
1083 | valid = value == 0x14; |
1084 | break; |
1085 | } |
1086 | /* When disassembling with -Many, accept power4 encodings too. */ |
1087 | if (valid |
1088 | || (dialect & PPC_OPCODE_ANY) == 0 |
1089 | || !extract) |
1090 | return valid; |
1091 | } |
1092 | |
1093 | /* Certain encodings have bits that are required to be zero. |
1094 | These are (z must be zero, a & t may be anything): |
1095 | 0000z |
1096 | 0001z |
1097 | 0100z |
1098 | 0101z |
1099 | 001at |
1100 | 011at |
1101 | 1a00t |
1102 | 1a01t |
1103 | 1z1zz |
1104 | */ |
1105 | if ((value & 0x14) == 0) |
1106 | return (value & 0x1) == 0; |
1107 | else if ((value & 0x14) == 0x14) |
1108 | return value == 0x14; |
1109 | else |
1110 | return 1; |
1111 | } |
1112 | |
1113 | /* The BO field in a B form instruction. Warn about attempts to set |
1114 | the field to an illegal value. */ |
1115 | |
1116 | static unsigned long |
1117 | insert_bo (unsigned long insn, |
1118 | long value, |
1119 | int dialect, |
1120 | const char **errmsg) |
1121 | { |
1122 | if (!valid_bo (value, dialect, 0)) |
1123 | *errmsg = "invalid conditional option" ; |
1124 | return insn | ((value & 0x1f) << 21); |
1125 | } |
1126 | |
1127 | static long |
1128 | (unsigned long insn, |
1129 | int dialect, |
1130 | int *invalid) |
1131 | { |
1132 | long value; |
1133 | |
1134 | value = (insn >> 21) & 0x1f; |
1135 | if (!valid_bo (value, dialect, 1)) |
1136 | *invalid = 1; |
1137 | return value; |
1138 | } |
1139 | |
1140 | /* The BO field in a B form instruction when the + or - modifier is |
1141 | used. This is like the BO field, but it must be even. When |
1142 | extracting it, we force it to be even. */ |
1143 | |
1144 | static unsigned long |
1145 | insert_boe (unsigned long insn, |
1146 | long value, |
1147 | int dialect, |
1148 | const char **errmsg) |
1149 | { |
1150 | if (!valid_bo (value, dialect, 0)) |
1151 | *errmsg = "invalid conditional option" ; |
1152 | else if ((value & 1) != 0) |
1153 | *errmsg = "attempt to set y bit when using + or - modifier" ; |
1154 | |
1155 | return insn | ((value & 0x1f) << 21); |
1156 | } |
1157 | |
1158 | static long |
1159 | (unsigned long insn, |
1160 | int dialect, |
1161 | int *invalid) |
1162 | { |
1163 | long value; |
1164 | |
1165 | value = (insn >> 21) & 0x1f; |
1166 | if (!valid_bo (value, dialect, 1)) |
1167 | *invalid = 1; |
1168 | return value & 0x1e; |
1169 | } |
1170 | |
1171 | /* FXM mask in mfcr and mtcrf instructions. */ |
1172 | |
1173 | static unsigned long |
1174 | insert_fxm (unsigned long insn, |
1175 | long value, |
1176 | int dialect, |
1177 | const char **errmsg) |
1178 | { |
1179 | /* If we're handling the mfocrf and mtocrf insns ensure that exactly |
1180 | one bit of the mask field is set. */ |
1181 | if ((insn & (1 << 20)) != 0) |
1182 | { |
1183 | if (value == 0 || (value & -value) != value) |
1184 | { |
1185 | *errmsg = "invalid mask field" ; |
1186 | value = 0; |
1187 | } |
1188 | } |
1189 | |
1190 | /* If the optional field on mfcr is missing that means we want to use |
1191 | the old form of the instruction that moves the whole cr. In that |
1192 | case we'll have VALUE zero. There doesn't seem to be a way to |
1193 | distinguish this from the case where someone writes mfcr %r3,0. */ |
1194 | else if (value == 0) |
1195 | ; |
1196 | |
1197 | /* If only one bit of the FXM field is set, we can use the new form |
1198 | of the instruction, which is faster. Unlike the Power4 branch hint |
1199 | encoding, this is not backward compatible. Do not generate the |
1200 | new form unless -mpower4 has been given, or -many and the two |
1201 | operand form of mfcr was used. */ |
1202 | else if ((value & -value) == value |
1203 | && ((dialect & PPC_OPCODE_POWER4) != 0 |
1204 | || ((dialect & PPC_OPCODE_ANY) != 0 |
1205 | && (insn & (0x3ff << 1)) == 19 << 1))) |
1206 | insn |= 1 << 20; |
1207 | |
1208 | /* Any other value on mfcr is an error. */ |
1209 | else if ((insn & (0x3ff << 1)) == 19 << 1) |
1210 | { |
1211 | *errmsg = "ignoring invalid mfcr mask" ; |
1212 | value = 0; |
1213 | } |
1214 | |
1215 | return insn | ((value & 0xff) << 12); |
1216 | } |
1217 | |
1218 | static long |
1219 | (unsigned long insn, |
1220 | int dialect ATTRIBUTE_UNUSED, |
1221 | int *invalid) |
1222 | { |
1223 | long mask = (insn >> 12) & 0xff; |
1224 | |
1225 | /* Is this a Power4 insn? */ |
1226 | if ((insn & (1 << 20)) != 0) |
1227 | { |
1228 | /* Exactly one bit of MASK should be set. */ |
1229 | if (mask == 0 || (mask & -mask) != mask) |
1230 | *invalid = 1; |
1231 | } |
1232 | |
1233 | /* Check that non-power4 form of mfcr has a zero MASK. */ |
1234 | else if ((insn & (0x3ff << 1)) == 19 << 1) |
1235 | { |
1236 | if (mask != 0) |
1237 | *invalid = 1; |
1238 | } |
1239 | |
1240 | return mask; |
1241 | } |
1242 | |
1243 | /* The MB and ME fields in an M form instruction expressed as a single |
1244 | operand which is itself a bitmask. The extraction function always |
1245 | marks it as invalid, since we never want to recognize an |
1246 | instruction which uses a field of this type. */ |
1247 | |
1248 | static unsigned long |
1249 | insert_mbe (unsigned long insn, |
1250 | long value, |
1251 | int dialect ATTRIBUTE_UNUSED, |
1252 | const char **errmsg) |
1253 | { |
1254 | unsigned long uval, mask; |
1255 | int mb, me, mx, count, last; |
1256 | |
1257 | uval = value; |
1258 | |
1259 | if (uval == 0) |
1260 | { |
1261 | *errmsg = "illegal bitmask" ; |
1262 | return insn; |
1263 | } |
1264 | |
1265 | mb = 0; |
1266 | me = 32; |
1267 | if ((uval & 1) != 0) |
1268 | last = 1; |
1269 | else |
1270 | last = 0; |
1271 | count = 0; |
1272 | |
1273 | /* mb: location of last 0->1 transition */ |
1274 | /* me: location of last 1->0 transition */ |
1275 | /* count: # transitions */ |
1276 | |
1277 | for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1) |
1278 | { |
1279 | if ((uval & mask) && !last) |
1280 | { |
1281 | ++count; |
1282 | mb = mx; |
1283 | last = 1; |
1284 | } |
1285 | else if (!(uval & mask) && last) |
1286 | { |
1287 | ++count; |
1288 | me = mx; |
1289 | last = 0; |
1290 | } |
1291 | } |
1292 | if (me == 0) |
1293 | me = 32; |
1294 | |
1295 | if (count != 2 && (count != 0 || ! last)) |
1296 | *errmsg = "illegal bitmask" ; |
1297 | |
1298 | return insn | (mb << 6) | ((me - 1) << 1); |
1299 | } |
1300 | |
1301 | static long |
1302 | (unsigned long insn, |
1303 | int dialect ATTRIBUTE_UNUSED, |
1304 | int *invalid) |
1305 | { |
1306 | long ret; |
1307 | int mb, me; |
1308 | int i; |
1309 | |
1310 | *invalid = 1; |
1311 | |
1312 | mb = (insn >> 6) & 0x1f; |
1313 | me = (insn >> 1) & 0x1f; |
1314 | if (mb < me + 1) |
1315 | { |
1316 | ret = 0; |
1317 | for (i = mb; i <= me; i++) |
1318 | ret |= 1L << (31 - i); |
1319 | } |
1320 | else if (mb == me + 1) |
1321 | ret = ~0; |
1322 | else /* (mb > me + 1) */ |
1323 | { |
1324 | ret = ~0; |
1325 | for (i = me + 1; i < mb; i++) |
1326 | ret &= ~(1L << (31 - i)); |
1327 | } |
1328 | return ret; |
1329 | } |
1330 | |
1331 | /* The MB or ME field in an MD or MDS form instruction. The high bit |
1332 | is wrapped to the low end. */ |
1333 | |
1334 | static unsigned long |
1335 | insert_mb6 (unsigned long insn, |
1336 | long value, |
1337 | int dialect ATTRIBUTE_UNUSED, |
1338 | const char **errmsg ATTRIBUTE_UNUSED) |
1339 | { |
1340 | return insn | ((value & 0x1f) << 6) | (value & 0x20); |
1341 | } |
1342 | |
1343 | static long |
1344 | (unsigned long insn, |
1345 | int dialect ATTRIBUTE_UNUSED, |
1346 | int *invalid ATTRIBUTE_UNUSED) |
1347 | { |
1348 | return ((insn >> 6) & 0x1f) | (insn & 0x20); |
1349 | } |
1350 | |
1351 | /* The NB field in an X form instruction. The value 32 is stored as |
1352 | 0. */ |
1353 | |
1354 | static long |
1355 | (unsigned long insn, |
1356 | int dialect ATTRIBUTE_UNUSED, |
1357 | int *invalid ATTRIBUTE_UNUSED) |
1358 | { |
1359 | long ret; |
1360 | |
1361 | ret = (insn >> 11) & 0x1f; |
1362 | if (ret == 0) |
1363 | ret = 32; |
1364 | return ret; |
1365 | } |
1366 | |
1367 | /* The NSI field in a D form instruction. This is the same as the SI |
1368 | field, only negated. The extraction function always marks it as |
1369 | invalid, since we never want to recognize an instruction which uses |
1370 | a field of this type. */ |
1371 | |
1372 | static unsigned long |
1373 | insert_nsi (unsigned long insn, |
1374 | long value, |
1375 | int dialect ATTRIBUTE_UNUSED, |
1376 | const char **errmsg ATTRIBUTE_UNUSED) |
1377 | { |
1378 | return insn | (-value & 0xffff); |
1379 | } |
1380 | |
1381 | static long |
1382 | (unsigned long insn, |
1383 | int dialect ATTRIBUTE_UNUSED, |
1384 | int *invalid) |
1385 | { |
1386 | *invalid = 1; |
1387 | return -(((insn & 0xffff) ^ 0x8000) - 0x8000); |
1388 | } |
1389 | |
1390 | /* The RA field in a D or X form instruction which is an updating |
1391 | load, which means that the RA field may not be zero and may not |
1392 | equal the RT field. */ |
1393 | |
1394 | static unsigned long |
1395 | insert_ral (unsigned long insn, |
1396 | long value, |
1397 | int dialect ATTRIBUTE_UNUSED, |
1398 | const char **errmsg) |
1399 | { |
1400 | if (value == 0 |
1401 | || (unsigned long) value == ((insn >> 21) & 0x1f)) |
1402 | *errmsg = "invalid register operand when updating" ; |
1403 | return insn | ((value & 0x1f) << 16); |
1404 | } |
1405 | |
1406 | /* The RA field in an lmw instruction, which has special value |
1407 | restrictions. */ |
1408 | |
1409 | static unsigned long |
1410 | insert_ram (unsigned long insn, |
1411 | long value, |
1412 | int dialect ATTRIBUTE_UNUSED, |
1413 | const char **errmsg) |
1414 | { |
1415 | if ((unsigned long) value >= ((insn >> 21) & 0x1f)) |
1416 | *errmsg = "index register in load range" ; |
1417 | return insn | ((value & 0x1f) << 16); |
1418 | } |
1419 | |
1420 | /* The RA field in the DQ form lq instruction, which has special |
1421 | value restrictions. */ |
1422 | |
1423 | static unsigned long |
1424 | insert_raq (unsigned long insn, |
1425 | long value, |
1426 | int dialect ATTRIBUTE_UNUSED, |
1427 | const char **errmsg) |
1428 | { |
1429 | long rtvalue = (insn & RT_MASK) >> 21; |
1430 | |
1431 | if (value == rtvalue) |
1432 | *errmsg = "source and target register operands must be different" ; |
1433 | return insn | ((value & 0x1f) << 16); |
1434 | } |
1435 | |
1436 | /* The RA field in a D or X form instruction which is an updating |
1437 | store or an updating floating point load, which means that the RA |
1438 | field may not be zero. */ |
1439 | |
1440 | static unsigned long |
1441 | insert_ras (unsigned long insn, |
1442 | long value, |
1443 | int dialect ATTRIBUTE_UNUSED, |
1444 | const char **errmsg) |
1445 | { |
1446 | if (value == 0) |
1447 | *errmsg = "invalid register operand when updating" ; |
1448 | return insn | ((value & 0x1f) << 16); |
1449 | } |
1450 | |
1451 | /* The RB field in an X form instruction when it must be the same as |
1452 | the RS field in the instruction. This is used for extended |
1453 | mnemonics like mr. This operand is marked FAKE. The insertion |
1454 | function just copies the BT field into the BA field, and the |
1455 | extraction function just checks that the fields are the same. */ |
1456 | |
1457 | static unsigned long |
1458 | insert_rbs (unsigned long insn, |
1459 | long value ATTRIBUTE_UNUSED, |
1460 | int dialect ATTRIBUTE_UNUSED, |
1461 | const char **errmsg ATTRIBUTE_UNUSED) |
1462 | { |
1463 | return insn | (((insn >> 21) & 0x1f) << 11); |
1464 | } |
1465 | |
1466 | static long |
1467 | (unsigned long insn, |
1468 | int dialect ATTRIBUTE_UNUSED, |
1469 | int *invalid) |
1470 | { |
1471 | if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f)) |
1472 | *invalid = 1; |
1473 | return 0; |
1474 | } |
1475 | |
1476 | /* The SH field in an MD form instruction. This is split. */ |
1477 | |
1478 | static unsigned long |
1479 | insert_sh6 (unsigned long insn, |
1480 | long value, |
1481 | int dialect ATTRIBUTE_UNUSED, |
1482 | const char **errmsg ATTRIBUTE_UNUSED) |
1483 | { |
1484 | return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4); |
1485 | } |
1486 | |
1487 | static long |
1488 | (unsigned long insn, |
1489 | int dialect ATTRIBUTE_UNUSED, |
1490 | int *invalid ATTRIBUTE_UNUSED) |
1491 | { |
1492 | return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20); |
1493 | } |
1494 | |
1495 | /* The SPR field in an XFX form instruction. This is flipped--the |
1496 | lower 5 bits are stored in the upper 5 and vice- versa. */ |
1497 | |
1498 | static unsigned long |
1499 | insert_spr (unsigned long insn, |
1500 | long value, |
1501 | int dialect ATTRIBUTE_UNUSED, |
1502 | const char **errmsg ATTRIBUTE_UNUSED) |
1503 | { |
1504 | return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6); |
1505 | } |
1506 | |
1507 | static long |
1508 | (unsigned long insn, |
1509 | int dialect ATTRIBUTE_UNUSED, |
1510 | int *invalid ATTRIBUTE_UNUSED) |
1511 | { |
1512 | return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0); |
1513 | } |
1514 | |
1515 | /* Some dialects have 8 SPRG registers instead of the standard 4. */ |
1516 | |
1517 | static unsigned long |
1518 | insert_sprg (unsigned long insn, |
1519 | long value, |
1520 | int dialect, |
1521 | const char **errmsg) |
1522 | { |
1523 | /* This check uses PPC_OPCODE_403 because PPC405 is later defined |
1524 | as a synonym. If ever a 405 specific dialect is added this |
1525 | check should use that instead. */ |
1526 | if (value > 7 |
1527 | || (value > 3 |
1528 | && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_403)) == 0)) |
1529 | *errmsg = "invalid sprg number" ; |
1530 | |
1531 | /* If this is mfsprg4..7 then use spr 260..263 which can be read in |
1532 | user mode. Anything else must use spr 272..279. */ |
1533 | if (value <= 3 || (insn & 0x100) != 0) |
1534 | value |= 0x10; |
1535 | |
1536 | return insn | ((value & 0x17) << 16); |
1537 | } |
1538 | |
1539 | static long |
1540 | (unsigned long insn, |
1541 | int dialect, |
1542 | int *invalid) |
1543 | { |
1544 | unsigned long val = (insn >> 16) & 0x1f; |
1545 | |
1546 | /* mfsprg can use 260..263 and 272..279. mtsprg only uses spr 272..279 |
1547 | If not BOOKE or 405, then both use only 272..275. */ |
1548 | if (val <= 3 |
1549 | || (val < 0x10 && (insn & 0x100) != 0) |
1550 | || (val - 0x10 > 3 |
1551 | && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_403)) == 0)) |
1552 | *invalid = 1; |
1553 | return val & 7; |
1554 | } |
1555 | |
1556 | /* The TBR field in an XFX instruction. This is just like SPR, but it |
1557 | is optional. When TBR is omitted, it must be inserted as 268 (the |
1558 | magic number of the TB register). These functions treat 0 |
1559 | (indicating an omitted optional operand) as 268. This means that |
1560 | ``mftb 4,0'' is not handled correctly. This does not matter very |
1561 | much, since the architecture manual does not define mftb as |
1562 | accepting any values other than 268 or 269. */ |
1563 | |
1564 | #define TB (268) |
1565 | |
1566 | static unsigned long |
1567 | insert_tbr (unsigned long insn, |
1568 | long value, |
1569 | int dialect ATTRIBUTE_UNUSED, |
1570 | const char **errmsg ATTRIBUTE_UNUSED) |
1571 | { |
1572 | if (value == 0) |
1573 | value = TB; |
1574 | return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6); |
1575 | } |
1576 | |
1577 | static long |
1578 | (unsigned long insn, |
1579 | int dialect ATTRIBUTE_UNUSED, |
1580 | int *invalid ATTRIBUTE_UNUSED) |
1581 | { |
1582 | long ret; |
1583 | |
1584 | ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0); |
1585 | if (ret == TB) |
1586 | ret = 0; |
1587 | return ret; |
1588 | } |
1589 | |
1590 | /* Macros used to form opcodes. */ |
1591 | |
1592 | /* The main opcode. */ |
1593 | #define OP(x) ((((unsigned long)(x)) & 0x3f) << 26) |
1594 | #define OP_MASK OP (0x3f) |
1595 | |
1596 | /* The main opcode combined with a trap code in the TO field of a D |
1597 | form instruction. Used for extended mnemonics for the trap |
1598 | instructions. */ |
1599 | #define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21)) |
1600 | #define OPTO_MASK (OP_MASK | TO_MASK) |
1601 | |
1602 | /* The main opcode combined with a comparison size bit in the L field |
1603 | of a D form or X form instruction. Used for extended mnemonics for |
1604 | the comparison instructions. */ |
1605 | #define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21)) |
1606 | #define OPL_MASK OPL (0x3f,1) |
1607 | |
1608 | /* An A form instruction. */ |
1609 | #define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1)) |
1610 | #define A_MASK A (0x3f, 0x1f, 1) |
1611 | |
1612 | /* An A_MASK with the FRB field fixed. */ |
1613 | #define AFRB_MASK (A_MASK | FRB_MASK) |
1614 | |
1615 | /* An A_MASK with the FRC field fixed. */ |
1616 | #define AFRC_MASK (A_MASK | FRC_MASK) |
1617 | |
1618 | /* An A_MASK with the FRA and FRC fields fixed. */ |
1619 | #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK) |
1620 | |
1621 | /* An AFRAFRC_MASK, but with L bit clear. */ |
1622 | #define AFRALFRC_MASK (AFRAFRC_MASK & ~((unsigned long) 1 << 16)) |
1623 | |
1624 | /* A B form instruction. */ |
1625 | #define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1)) |
1626 | #define B_MASK B (0x3f, 1, 1) |
1627 | |
1628 | /* A B form instruction setting the BO field. */ |
1629 | #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21)) |
1630 | #define BBO_MASK BBO (0x3f, 0x1f, 1, 1) |
1631 | |
1632 | /* A BBO_MASK with the y bit of the BO field removed. This permits |
1633 | matching a conditional branch regardless of the setting of the y |
1634 | bit. Similarly for the 'at' bits used for power4 branch hints. */ |
1635 | #define Y_MASK (((unsigned long) 1) << 21) |
1636 | #define AT1_MASK (((unsigned long) 3) << 21) |
1637 | #define AT2_MASK (((unsigned long) 9) << 21) |
1638 | #define BBOY_MASK (BBO_MASK &~ Y_MASK) |
1639 | #define BBOAT_MASK (BBO_MASK &~ AT1_MASK) |
1640 | |
1641 | /* A B form instruction setting the BO field and the condition bits of |
1642 | the BI field. */ |
1643 | #define BBOCB(op, bo, cb, aa, lk) \ |
1644 | (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16)) |
1645 | #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1) |
1646 | |
1647 | /* A BBOCB_MASK with the y bit of the BO field removed. */ |
1648 | #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK) |
1649 | #define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK) |
1650 | #define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK) |
1651 | |
1652 | /* A BBOYCB_MASK in which the BI field is fixed. */ |
1653 | #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK) |
1654 | #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK) |
1655 | |
1656 | /* A Context form instruction. */ |
1657 | #define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7)) |
1658 | #define CTX_MASK CTX(0x3f, 0x7) |
1659 | |
1660 | /* A User Context form instruction. */ |
1661 | #define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f)) |
1662 | #define UCTX_MASK UCTX(0x3f, 0x1f) |
1663 | |
1664 | /* The main opcode mask with the RA field clear. */ |
1665 | #define DRA_MASK (OP_MASK | RA_MASK) |
1666 | |
1667 | /* A DS form instruction. */ |
1668 | #define DSO(op, xop) (OP (op) | ((xop) & 0x3)) |
1669 | #define DS_MASK DSO (0x3f, 3) |
1670 | |
1671 | /* A DE form instruction. */ |
1672 | #define DEO(op, xop) (OP (op) | ((xop) & 0xf)) |
1673 | #define DE_MASK DEO (0x3e, 0xf) |
1674 | |
1675 | /* An EVSEL form instruction. */ |
1676 | #define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3) |
1677 | #define EVSEL_MASK EVSEL(0x3f, 0xff) |
1678 | |
1679 | /* An M form instruction. */ |
1680 | #define M(op, rc) (OP (op) | ((rc) & 1)) |
1681 | #define M_MASK M (0x3f, 1) |
1682 | |
1683 | /* An M form instruction with the ME field specified. */ |
1684 | #define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1)) |
1685 | |
1686 | /* An M_MASK with the MB and ME fields fixed. */ |
1687 | #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK) |
1688 | |
1689 | /* An M_MASK with the SH and ME fields fixed. */ |
1690 | #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK) |
1691 | |
1692 | /* An MD form instruction. */ |
1693 | #define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1)) |
1694 | #define MD_MASK MD (0x3f, 0x7, 1) |
1695 | |
1696 | /* An MD_MASK with the MB field fixed. */ |
1697 | #define MDMB_MASK (MD_MASK | MB6_MASK) |
1698 | |
1699 | /* An MD_MASK with the SH field fixed. */ |
1700 | #define MDSH_MASK (MD_MASK | SH6_MASK) |
1701 | |
1702 | /* An MDS form instruction. */ |
1703 | #define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1)) |
1704 | #define MDS_MASK MDS (0x3f, 0xf, 1) |
1705 | |
1706 | /* An MDS_MASK with the MB field fixed. */ |
1707 | #define MDSMB_MASK (MDS_MASK | MB6_MASK) |
1708 | |
1709 | /* An SC form instruction. */ |
1710 | #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1)) |
1711 | #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1) |
1712 | |
1713 | /* A VX form instruction. */ |
1714 | #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff)) |
1715 | |
1716 | /* The mask for an VX form instruction. */ |
1717 | #define VX_MASK VX(0x3f, 0x7ff) |
1718 | |
1719 | /* A VA form instruction. */ |
1720 | #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f)) |
1721 | |
1722 | /* The mask for a VA form instruction. */ |
1723 | #define VXA_MASK VXA(0x3f, 0x3f) |
1724 | |
1725 | /* A VXR form instruction. */ |
1726 | #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff)) |
1727 | |
1728 | /* The mask for a VXR form instruction. */ |
1729 | #define VXR_MASK VXR(0x3f, 0x3ff, 1) |
1730 | |
1731 | /* An X form instruction. */ |
1732 | #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1)) |
1733 | |
1734 | /* A Z form instruction. */ |
1735 | #define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1)) |
1736 | |
1737 | /* An X form instruction with the RC bit specified. */ |
1738 | #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1)) |
1739 | |
1740 | /* A Z form instruction with the RC bit specified. */ |
1741 | #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1)) |
1742 | |
1743 | /* The mask for an X form instruction. */ |
1744 | #define X_MASK XRC (0x3f, 0x3ff, 1) |
1745 | |
1746 | /* The mask for a Z form instruction. */ |
1747 | #define Z_MASK ZRC (0x3f, 0x1ff, 1) |
1748 | #define Z2_MASK ZRC (0x3f, 0xff, 1) |
1749 | |
1750 | /* An X_MASK with the RA field fixed. */ |
1751 | #define XRA_MASK (X_MASK | RA_MASK) |
1752 | |
1753 | /* An XRA_MASK with the W field clear. */ |
1754 | #define XWRA_MASK (XRA_MASK & ~((unsigned long) 1 << 16)) |
1755 | |
1756 | /* An X_MASK with the RB field fixed. */ |
1757 | #define XRB_MASK (X_MASK | RB_MASK) |
1758 | |
1759 | /* An X_MASK with the RT field fixed. */ |
1760 | #define XRT_MASK (X_MASK | RT_MASK) |
1761 | |
1762 | /* An XRT_MASK mask with the L bits clear. */ |
1763 | #define XLRT_MASK (XRT_MASK & ~((unsigned long) 0x3 << 21)) |
1764 | |
1765 | /* An X_MASK with the RA and RB fields fixed. */ |
1766 | #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK) |
1767 | |
1768 | /* An X form instruction with the RA field fixed. */ |
1769 | #define XRA(op, xop, ra) (X((op), (xop)) | (((ra) << 16) & XRA_MASK)) |
1770 | |
1771 | /* An XRARB_MASK, but with the L bit clear. */ |
1772 | #define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16)) |
1773 | |
1774 | /* An X_MASK with the RT and RA fields fixed. */ |
1775 | #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK) |
1776 | |
1777 | /* An XRTRA_MASK, but with L bit clear. */ |
1778 | #define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21)) |
1779 | |
1780 | /* An X form instruction with the L bit specified. */ |
1781 | #define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21)) |
1782 | |
1783 | /* The mask for an X form comparison instruction. */ |
1784 | #define XCMP_MASK (X_MASK | (((unsigned long)1) << 22)) |
1785 | |
1786 | /* The mask for an X form comparison instruction with the L field |
1787 | fixed. */ |
1788 | #define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21)) |
1789 | |
1790 | /* An X form trap instruction with the TO field specified. */ |
1791 | #define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21)) |
1792 | #define XTO_MASK (X_MASK | TO_MASK) |
1793 | |
1794 | /* An X form tlb instruction with the SH field specified. */ |
1795 | #define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11)) |
1796 | #define XTLB_MASK (X_MASK | SH_MASK) |
1797 | |
1798 | /* An X form sync instruction. */ |
1799 | #define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21)) |
1800 | |
1801 | /* An X form sync instruction with everything filled in except the LS field. */ |
1802 | #define XSYNC_MASK (0xff9fffff) |
1803 | |
1804 | /* An X_MASK, but with the EH bit clear. */ |
1805 | #define XEH_MASK (X_MASK & ~((unsigned long )1)) |
1806 | |
1807 | /* An X form AltiVec dss instruction. */ |
1808 | #define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25)) |
1809 | #define XDSS_MASK XDSS(0x3f, 0x3ff, 1) |
1810 | |
1811 | /* An XFL form instruction. */ |
1812 | #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1)) |
1813 | #define XFL_MASK XFL (0x3f, 0x3ff, 1) |
1814 | |
1815 | /* An X form isel instruction. */ |
1816 | #define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1)) |
1817 | #define XISEL_MASK XISEL(0x3f, 0x1f) |
1818 | |
1819 | /* An XL form instruction with the LK field set to 0. */ |
1820 | #define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1)) |
1821 | |
1822 | /* An XL form instruction which uses the LK field. */ |
1823 | #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1)) |
1824 | |
1825 | /* The mask for an XL form instruction. */ |
1826 | #define XL_MASK XLLK (0x3f, 0x3ff, 1) |
1827 | |
1828 | /* An XL form instruction which explicitly sets the BO field. */ |
1829 | #define XLO(op, bo, xop, lk) \ |
1830 | (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21)) |
1831 | #define XLO_MASK (XL_MASK | BO_MASK) |
1832 | |
1833 | /* An XL form instruction which explicitly sets the y bit of the BO |
1834 | field. */ |
1835 | #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21)) |
1836 | #define XLYLK_MASK (XL_MASK | Y_MASK) |
1837 | |
1838 | /* An XL form instruction which sets the BO field and the condition |
1839 | bits of the BI field. */ |
1840 | #define XLOCB(op, bo, cb, xop, lk) \ |
1841 | (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16)) |
1842 | #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1) |
1843 | |
1844 | /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */ |
1845 | #define XLBB_MASK (XL_MASK | BB_MASK) |
1846 | #define XLYBB_MASK (XLYLK_MASK | BB_MASK) |
1847 | #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK) |
1848 | |
1849 | /* A mask for branch instructions using the BH field. */ |
1850 | #define XLBH_MASK (XL_MASK | (0x1c << 11)) |
1851 | |
1852 | /* An XL_MASK with the BO and BB fields fixed. */ |
1853 | #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK) |
1854 | |
1855 | /* An XL_MASK with the BO, BI and BB fields fixed. */ |
1856 | #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK) |
1857 | |
1858 | /* An XO form instruction. */ |
1859 | #define XO(op, xop, oe, rc) \ |
1860 | (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1)) |
1861 | #define XO_MASK XO (0x3f, 0x1ff, 1, 1) |
1862 | |
1863 | /* An XO_MASK with the RB field fixed. */ |
1864 | #define XORB_MASK (XO_MASK | RB_MASK) |
1865 | |
1866 | /* An XS form instruction. */ |
1867 | #define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1)) |
1868 | #define XS_MASK XS (0x3f, 0x1ff, 1) |
1869 | |
1870 | /* A mask for the FXM version of an XFX form instruction. */ |
1871 | #define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20)) |
1872 | |
1873 | /* An XFX form instruction with the FXM field filled in. */ |
1874 | #define XFXM(op, xop, fxm, p4) \ |
1875 | (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \ |
1876 | | ((unsigned long)(p4) << 20)) |
1877 | |
1878 | /* An XFX form instruction with the SPR field filled in. */ |
1879 | #define XSPR(op, xop, spr) \ |
1880 | (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6)) |
1881 | #define XSPR_MASK (X_MASK | SPR_MASK) |
1882 | |
1883 | /* An XFX form instruction with the SPR field filled in except for the |
1884 | SPRBAT field. */ |
1885 | #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK) |
1886 | |
1887 | /* An XFX form instruction with the SPR field filled in except for the |
1888 | SPRG field. */ |
1889 | #define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16)) |
1890 | |
1891 | /* An X form instruction with everything filled in except the E field. */ |
1892 | #define XE_MASK (0xffff7fff) |
1893 | |
1894 | /* An X form user context instruction. */ |
1895 | #define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f)) |
1896 | #define XUC_MASK XUC(0x3f, 0x1f) |
1897 | |
1898 | /* The BO encodings used in extended conditional branch mnemonics. */ |
1899 | #define BODNZF (0x0) |
1900 | #define BODNZFP (0x1) |
1901 | #define BODZF (0x2) |
1902 | #define BODZFP (0x3) |
1903 | #define BODNZT (0x8) |
1904 | #define BODNZTP (0x9) |
1905 | #define BODZT (0xa) |
1906 | #define BODZTP (0xb) |
1907 | |
1908 | #define BOF (0x4) |
1909 | #define BOFP (0x5) |
1910 | #define BOFM4 (0x6) |
1911 | #define BOFP4 (0x7) |
1912 | #define BOT (0xc) |
1913 | #define BOTP (0xd) |
1914 | #define BOTM4 (0xe) |
1915 | #define BOTP4 (0xf) |
1916 | |
1917 | #define BODNZ (0x10) |
1918 | #define BODNZP (0x11) |
1919 | #define BODZ (0x12) |
1920 | #define BODZP (0x13) |
1921 | #define BODNZM4 (0x18) |
1922 | #define BODNZP4 (0x19) |
1923 | #define BODZM4 (0x1a) |
1924 | #define BODZP4 (0x1b) |
1925 | |
1926 | #define BOU (0x14) |
1927 | |
1928 | /* The BI condition bit encodings used in extended conditional branch |
1929 | mnemonics. */ |
1930 | #define CBLT (0) |
1931 | #define CBGT (1) |
1932 | #define CBEQ (2) |
1933 | #define CBSO (3) |
1934 | |
1935 | /* The TO encodings used in extended trap mnemonics. */ |
1936 | #define TOLGT (0x1) |
1937 | #define TOLLT (0x2) |
1938 | #define TOEQ (0x4) |
1939 | #define TOLGE (0x5) |
1940 | #define TOLNL (0x5) |
1941 | #define TOLLE (0x6) |
1942 | #define TOLNG (0x6) |
1943 | #define TOGT (0x8) |
1944 | #define TOGE (0xc) |
1945 | #define TONL (0xc) |
1946 | #define TOLT (0x10) |
1947 | #define TOLE (0x14) |
1948 | #define TONG (0x14) |
1949 | #define TONE (0x18) |
1950 | #define TOU (0x1f) |
1951 | |
1952 | /* Smaller names for the flags so each entry in the opcodes table will |
1953 | fit on a single line. */ |
1954 | #undef PPC |
1955 | #define PPC PPC_OPCODE_PPC |
1956 | #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON |
1957 | #define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM |
1958 | #define POWER4 PPC_OPCODE_POWER4 |
1959 | #define POWER5 PPC_OPCODE_POWER5 |
1960 | #define POWER6 PPC_OPCODE_POWER6 |
1961 | /* Documentation purposes only; we don't actually check the isa for disas. */ |
1962 | #define POWER7 PPC_OPCODE_POWER6 |
1963 | #define POWER9 PPC_OPCODE_POWER6 |
1964 | #define CELL PPC_OPCODE_CELL |
1965 | #define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC |
1966 | #define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC |
1967 | #define PPC403 PPC_OPCODE_403 |
1968 | #define PPC405 PPC403 |
1969 | #define PPC440 PPC_OPCODE_440 |
1970 | #define PPC750 PPC |
1971 | #define PPC860 PPC |
1972 | #define PPCVEC PPC_OPCODE_ALTIVEC |
1973 | #define POWER PPC_OPCODE_POWER |
1974 | #define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2 |
1975 | #define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 |
1976 | #define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_32 |
1977 | #define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON |
1978 | #define COM32 PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_32 |
1979 | #define M601 PPC_OPCODE_POWER | PPC_OPCODE_601 |
1980 | #define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON |
1981 | #define MFDEC1 PPC_OPCODE_POWER |
1982 | #define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE |
1983 | #define BOOKE PPC_OPCODE_BOOKE |
1984 | #define BOOKE64 PPC_OPCODE_BOOKE64 |
1985 | #define CLASSIC PPC_OPCODE_CLASSIC |
1986 | #define PPCE300 PPC_OPCODE_E300 |
1987 | #define PPCSPE PPC_OPCODE_SPE |
1988 | #define PPCISEL PPC_OPCODE_ISEL |
1989 | #define PPCEFS PPC_OPCODE_EFS |
1990 | #define PPCBRLK PPC_OPCODE_BRLOCK |
1991 | #define PPCPMR PPC_OPCODE_PMR |
1992 | #define PPCCHLK PPC_OPCODE_CACHELCK |
1993 | #define PPCCHLK64 PPC_OPCODE_CACHELCK | PPC_OPCODE_BOOKE64 |
1994 | #define PPCRFMCI PPC_OPCODE_RFMCI |
1995 | |
1996 | /* The opcode table. |
1997 | |
1998 | The format of the opcode table is: |
1999 | |
2000 | NAME OPCODE MASK FLAGS { OPERANDS } |
2001 | |
2002 | NAME is the name of the instruction. |
2003 | OPCODE is the instruction opcode. |
2004 | MASK is the opcode mask; this is used to tell the disassembler |
2005 | which bits in the actual opcode must match OPCODE. |
2006 | FLAGS are flags indicated what processors support the instruction. |
2007 | OPERANDS is the list of operands. |
2008 | |
2009 | The disassembler reads the table in order and prints the first |
2010 | instruction which matches, so this table is sorted to put more |
2011 | specific instructions before more general instructions. It is also |
2012 | sorted by major opcode. */ |
2013 | |
2014 | const struct powerpc_opcode powerpc_opcodes[] = { |
2015 | { "attn" , X(0,256), X_MASK, POWER4, { 0 } }, |
2016 | { "tdlgti" , OPTO(2,TOLGT), OPTO_MASK, PPC64, { RA, SI } }, |
2017 | { "tdllti" , OPTO(2,TOLLT), OPTO_MASK, PPC64, { RA, SI } }, |
2018 | { "tdeqi" , OPTO(2,TOEQ), OPTO_MASK, PPC64, { RA, SI } }, |
2019 | { "tdlgei" , OPTO(2,TOLGE), OPTO_MASK, PPC64, { RA, SI } }, |
2020 | { "tdlnli" , OPTO(2,TOLNL), OPTO_MASK, PPC64, { RA, SI } }, |
2021 | { "tdllei" , OPTO(2,TOLLE), OPTO_MASK, PPC64, { RA, SI } }, |
2022 | { "tdlngi" , OPTO(2,TOLNG), OPTO_MASK, PPC64, { RA, SI } }, |
2023 | { "tdgti" , OPTO(2,TOGT), OPTO_MASK, PPC64, { RA, SI } }, |
2024 | { "tdgei" , OPTO(2,TOGE), OPTO_MASK, PPC64, { RA, SI } }, |
2025 | { "tdnli" , OPTO(2,TONL), OPTO_MASK, PPC64, { RA, SI } }, |
2026 | { "tdlti" , OPTO(2,TOLT), OPTO_MASK, PPC64, { RA, SI } }, |
2027 | { "tdlei" , OPTO(2,TOLE), OPTO_MASK, PPC64, { RA, SI } }, |
2028 | { "tdngi" , OPTO(2,TONG), OPTO_MASK, PPC64, { RA, SI } }, |
2029 | { "tdnei" , OPTO(2,TONE), OPTO_MASK, PPC64, { RA, SI } }, |
2030 | { "tdi" , OP(2), OP_MASK, PPC64, { TO, RA, SI } }, |
2031 | |
2032 | { "twlgti" , OPTO(3,TOLGT), OPTO_MASK, PPCCOM, { RA, SI } }, |
2033 | { "tlgti" , OPTO(3,TOLGT), OPTO_MASK, PWRCOM, { RA, SI } }, |
2034 | { "twllti" , OPTO(3,TOLLT), OPTO_MASK, PPCCOM, { RA, SI } }, |
2035 | { "tllti" , OPTO(3,TOLLT), OPTO_MASK, PWRCOM, { RA, SI } }, |
2036 | { "tweqi" , OPTO(3,TOEQ), OPTO_MASK, PPCCOM, { RA, SI } }, |
2037 | { "teqi" , OPTO(3,TOEQ), OPTO_MASK, PWRCOM, { RA, SI } }, |
2038 | { "twlgei" , OPTO(3,TOLGE), OPTO_MASK, PPCCOM, { RA, SI } }, |
2039 | { "tlgei" , OPTO(3,TOLGE), OPTO_MASK, PWRCOM, { RA, SI } }, |
2040 | { "twlnli" , OPTO(3,TOLNL), OPTO_MASK, PPCCOM, { RA, SI } }, |
2041 | { "tlnli" , OPTO(3,TOLNL), OPTO_MASK, PWRCOM, { RA, SI } }, |
2042 | { "twllei" , OPTO(3,TOLLE), OPTO_MASK, PPCCOM, { RA, SI } }, |
2043 | { "tllei" , OPTO(3,TOLLE), OPTO_MASK, PWRCOM, { RA, SI } }, |
2044 | { "twlngi" , OPTO(3,TOLNG), OPTO_MASK, PPCCOM, { RA, SI } }, |
2045 | { "tlngi" , OPTO(3,TOLNG), OPTO_MASK, PWRCOM, { RA, SI } }, |
2046 | { "twgti" , OPTO(3,TOGT), OPTO_MASK, PPCCOM, { RA, SI } }, |
2047 | { "tgti" , OPTO(3,TOGT), OPTO_MASK, PWRCOM, { RA, SI } }, |
2048 | { "twgei" , OPTO(3,TOGE), OPTO_MASK, PPCCOM, { RA, SI } }, |
2049 | { "tgei" , OPTO(3,TOGE), OPTO_MASK, PWRCOM, { RA, SI } }, |
2050 | { "twnli" , OPTO(3,TONL), OPTO_MASK, PPCCOM, { RA, SI } }, |
2051 | { "tnli" , OPTO(3,TONL), OPTO_MASK, PWRCOM, { RA, SI } }, |
2052 | { "twlti" , OPTO(3,TOLT), OPTO_MASK, PPCCOM, { RA, SI } }, |
2053 | { "tlti" , OPTO(3,TOLT), OPTO_MASK, PWRCOM, { RA, SI } }, |
2054 | { "twlei" , OPTO(3,TOLE), OPTO_MASK, PPCCOM, { RA, SI } }, |
2055 | { "tlei" , OPTO(3,TOLE), OPTO_MASK, PWRCOM, { RA, SI } }, |
2056 | { "twngi" , OPTO(3,TONG), OPTO_MASK, PPCCOM, { RA, SI } }, |
2057 | { "tngi" , OPTO(3,TONG), OPTO_MASK, PWRCOM, { RA, SI } }, |
2058 | { "twnei" , OPTO(3,TONE), OPTO_MASK, PPCCOM, { RA, SI } }, |
2059 | { "tnei" , OPTO(3,TONE), OPTO_MASK, PWRCOM, { RA, SI } }, |
2060 | { "twi" , OP(3), OP_MASK, PPCCOM, { TO, RA, SI } }, |
2061 | { "ti" , OP(3), OP_MASK, PWRCOM, { TO, RA, SI } }, |
2062 | |
2063 | { "macchw" , XO(4,172,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2064 | { "macchw." , XO(4,172,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2065 | { "macchwo" , XO(4,172,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2066 | { "macchwo." , XO(4,172,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2067 | { "macchws" , XO(4,236,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2068 | { "macchws." , XO(4,236,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2069 | { "macchwso" , XO(4,236,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2070 | { "macchwso." , XO(4,236,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2071 | { "macchwsu" , XO(4,204,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2072 | { "macchwsu." , XO(4,204,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2073 | { "macchwsuo" , XO(4,204,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2074 | { "macchwsuo." , XO(4,204,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2075 | { "macchwu" , XO(4,140,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2076 | { "macchwu." , XO(4,140,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2077 | { "macchwuo" , XO(4,140,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2078 | { "macchwuo." , XO(4,140,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2079 | { "machhw" , XO(4,44,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2080 | { "machhw." , XO(4,44,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2081 | { "machhwo" , XO(4,44,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2082 | { "machhwo." , XO(4,44,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2083 | { "machhws" , XO(4,108,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2084 | { "machhws." , XO(4,108,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2085 | { "machhwso" , XO(4,108,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2086 | { "machhwso." , XO(4,108,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2087 | { "machhwsu" , XO(4,76,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2088 | { "machhwsu." , XO(4,76,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2089 | { "machhwsuo" , XO(4,76,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2090 | { "machhwsuo." , XO(4,76,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2091 | { "machhwu" , XO(4,12,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2092 | { "machhwu." , XO(4,12,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2093 | { "machhwuo" , XO(4,12,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2094 | { "machhwuo." , XO(4,12,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2095 | { "maclhw" , XO(4,428,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2096 | { "maclhw." , XO(4,428,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2097 | { "maclhwo" , XO(4,428,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2098 | { "maclhwo." , XO(4,428,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2099 | { "maclhws" , XO(4,492,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2100 | { "maclhws." , XO(4,492,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2101 | { "maclhwso" , XO(4,492,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2102 | { "maclhwso." , XO(4,492,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2103 | { "maclhwsu" , XO(4,460,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2104 | { "maclhwsu." , XO(4,460,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2105 | { "maclhwsuo" , XO(4,460,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2106 | { "maclhwsuo." , XO(4,460,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2107 | { "maclhwu" , XO(4,396,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2108 | { "maclhwu." , XO(4,396,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2109 | { "maclhwuo" , XO(4,396,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2110 | { "maclhwuo." , XO(4,396,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2111 | { "mulchw" , XRC(4,168,0), X_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2112 | { "mulchw." , XRC(4,168,1), X_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2113 | { "mulchwu" , XRC(4,136,0), X_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2114 | { "mulchwu." , XRC(4,136,1), X_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2115 | { "mulhhw" , XRC(4,40,0), X_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2116 | { "mulhhw." , XRC(4,40,1), X_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2117 | { "mulhhwu" , XRC(4,8,0), X_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2118 | { "mulhhwu." , XRC(4,8,1), X_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2119 | { "mullhw" , XRC(4,424,0), X_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2120 | { "mullhw." , XRC(4,424,1), X_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2121 | { "mullhwu" , XRC(4,392,0), X_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2122 | { "mullhwu." , XRC(4,392,1), X_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2123 | { "nmacchw" , XO(4,174,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2124 | { "nmacchw." , XO(4,174,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2125 | { "nmacchwo" , XO(4,174,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2126 | { "nmacchwo." , XO(4,174,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2127 | { "nmacchws" , XO(4,238,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2128 | { "nmacchws." , XO(4,238,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2129 | { "nmacchwso" , XO(4,238,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2130 | { "nmacchwso." , XO(4,238,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2131 | { "nmachhw" , XO(4,46,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2132 | { "nmachhw." , XO(4,46,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2133 | { "nmachhwo" , XO(4,46,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2134 | { "nmachhwo." , XO(4,46,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2135 | { "nmachhws" , XO(4,110,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2136 | { "nmachhws." , XO(4,110,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2137 | { "nmachhwso" , XO(4,110,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2138 | { "nmachhwso." , XO(4,110,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2139 | { "nmaclhw" , XO(4,430,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2140 | { "nmaclhw." , XO(4,430,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2141 | { "nmaclhwo" , XO(4,430,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2142 | { "nmaclhwo." , XO(4,430,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2143 | { "nmaclhws" , XO(4,494,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2144 | { "nmaclhws." , XO(4,494,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2145 | { "nmaclhwso" , XO(4,494,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2146 | { "nmaclhwso." , XO(4,494,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2147 | { "mfvscr" , VX(4, 1540), VX_MASK, PPCVEC, { VD } }, |
2148 | { "mtvscr" , VX(4, 1604), VX_MASK, PPCVEC, { VB } }, |
2149 | |
2150 | /* Double-precision opcodes. */ |
2151 | /* Some of these conflict with AltiVec, so move them before, since |
2152 | PPCVEC includes the PPC_OPCODE_PPC set. */ |
2153 | { "efscfd" , VX(4, 719), VX_MASK, PPCEFS, { RS, RB } }, |
2154 | { "efdabs" , VX(4, 740), VX_MASK, PPCEFS, { RS, RA } }, |
2155 | { "efdnabs" , VX(4, 741), VX_MASK, PPCEFS, { RS, RA } }, |
2156 | { "efdneg" , VX(4, 742), VX_MASK, PPCEFS, { RS, RA } }, |
2157 | { "efdadd" , VX(4, 736), VX_MASK, PPCEFS, { RS, RA, RB } }, |
2158 | { "efdsub" , VX(4, 737), VX_MASK, PPCEFS, { RS, RA, RB } }, |
2159 | { "efdmul" , VX(4, 744), VX_MASK, PPCEFS, { RS, RA, RB } }, |
2160 | { "efddiv" , VX(4, 745), VX_MASK, PPCEFS, { RS, RA, RB } }, |
2161 | { "efdcmpgt" , VX(4, 748), VX_MASK, PPCEFS, { CRFD, RA, RB } }, |
2162 | { "efdcmplt" , VX(4, 749), VX_MASK, PPCEFS, { CRFD, RA, RB } }, |
2163 | { "efdcmpeq" , VX(4, 750), VX_MASK, PPCEFS, { CRFD, RA, RB } }, |
2164 | { "efdtstgt" , VX(4, 764), VX_MASK, PPCEFS, { CRFD, RA, RB } }, |
2165 | { "efdtstlt" , VX(4, 765), VX_MASK, PPCEFS, { CRFD, RA, RB } }, |
2166 | { "efdtsteq" , VX(4, 766), VX_MASK, PPCEFS, { CRFD, RA, RB } }, |
2167 | { "efdcfsi" , VX(4, 753), VX_MASK, PPCEFS, { RS, RB } }, |
2168 | { "efdcfsid" , VX(4, 739), VX_MASK, PPCEFS, { RS, RB } }, |
2169 | { "efdcfui" , VX(4, 752), VX_MASK, PPCEFS, { RS, RB } }, |
2170 | { "efdcfuid" , VX(4, 738), VX_MASK, PPCEFS, { RS, RB } }, |
2171 | { "efdcfsf" , VX(4, 755), VX_MASK, PPCEFS, { RS, RB } }, |
2172 | { "efdcfuf" , VX(4, 754), VX_MASK, PPCEFS, { RS, RB } }, |
2173 | { "efdctsi" , VX(4, 757), VX_MASK, PPCEFS, { RS, RB } }, |
2174 | { "efdctsidz" ,VX(4, 747), VX_MASK, PPCEFS, { RS, RB } }, |
2175 | { "efdctsiz" , VX(4, 762), VX_MASK, PPCEFS, { RS, RB } }, |
2176 | { "efdctui" , VX(4, 756), VX_MASK, PPCEFS, { RS, RB } }, |
2177 | { "efdctuidz" ,VX(4, 746), VX_MASK, PPCEFS, { RS, RB } }, |
2178 | { "efdctuiz" , VX(4, 760), VX_MASK, PPCEFS, { RS, RB } }, |
2179 | { "efdctsf" , VX(4, 759), VX_MASK, PPCEFS, { RS, RB } }, |
2180 | { "efdctuf" , VX(4, 758), VX_MASK, PPCEFS, { RS, RB } }, |
2181 | { "efdcfs" , VX(4, 751), VX_MASK, PPCEFS, { RS, RB } }, |
2182 | /* End of double-precision opcodes. */ |
2183 | |
2184 | { "vaddcuw" , VX(4, 384), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2185 | { "vaddfp" , VX(4, 10), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2186 | { "vaddsbs" , VX(4, 768), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2187 | { "vaddshs" , VX(4, 832), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2188 | { "vaddsws" , VX(4, 896), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2189 | { "vaddubm" , VX(4, 0), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2190 | { "vaddubs" , VX(4, 512), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2191 | { "vadduhm" , VX(4, 64), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2192 | { "vadduhs" , VX(4, 576), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2193 | { "vadduwm" , VX(4, 128), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2194 | { "vadduws" , VX(4, 640), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2195 | { "vand" , VX(4, 1028), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2196 | { "vandc" , VX(4, 1092), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2197 | { "vavgsb" , VX(4, 1282), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2198 | { "vavgsh" , VX(4, 1346), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2199 | { "vavgsw" , VX(4, 1410), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2200 | { "vavgub" , VX(4, 1026), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2201 | { "vavguh" , VX(4, 1090), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2202 | { "vavguw" , VX(4, 1154), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2203 | { "vcfsx" , VX(4, 842), VX_MASK, PPCVEC, { VD, VB, UIMM } }, |
2204 | { "vcfux" , VX(4, 778), VX_MASK, PPCVEC, { VD, VB, UIMM } }, |
2205 | { "vcmpbfp" , VXR(4, 966, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
2206 | { "vcmpbfp." , VXR(4, 966, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
2207 | { "vcmpeqfp" , VXR(4, 198, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
2208 | { "vcmpeqfp." , VXR(4, 198, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
2209 | { "vcmpequb" , VXR(4, 6, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
2210 | { "vcmpequb." , VXR(4, 6, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
2211 | { "vcmpequh" , VXR(4, 70, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
2212 | { "vcmpequh." , VXR(4, 70, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
2213 | { "vcmpequw" , VXR(4, 134, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
2214 | { "vcmpequw." , VXR(4, 134, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
2215 | { "vcmpgefp" , VXR(4, 454, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
2216 | { "vcmpgefp." , VXR(4, 454, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
2217 | { "vcmpgtfp" , VXR(4, 710, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
2218 | { "vcmpgtfp." , VXR(4, 710, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
2219 | { "vcmpgtsb" , VXR(4, 774, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
2220 | { "vcmpgtsb." , VXR(4, 774, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
2221 | { "vcmpgtsh" , VXR(4, 838, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
2222 | { "vcmpgtsh." , VXR(4, 838, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
2223 | { "vcmpgtsw" , VXR(4, 902, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
2224 | { "vcmpgtsw." , VXR(4, 902, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
2225 | { "vcmpgtub" , VXR(4, 518, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
2226 | { "vcmpgtub." , VXR(4, 518, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
2227 | { "vcmpgtuh" , VXR(4, 582, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
2228 | { "vcmpgtuh." , VXR(4, 582, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
2229 | { "vcmpgtuw" , VXR(4, 646, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
2230 | { "vcmpgtuw." , VXR(4, 646, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
2231 | { "vctsxs" , VX(4, 970), VX_MASK, PPCVEC, { VD, VB, UIMM } }, |
2232 | { "vctuxs" , VX(4, 906), VX_MASK, PPCVEC, { VD, VB, UIMM } }, |
2233 | { "vexptefp" , VX(4, 394), VX_MASK, PPCVEC, { VD, VB } }, |
2234 | { "vlogefp" , VX(4, 458), VX_MASK, PPCVEC, { VD, VB } }, |
2235 | { "vmaddfp" , VXA(4, 46), VXA_MASK, PPCVEC, { VD, VA, VC, VB } }, |
2236 | { "vmaxfp" , VX(4, 1034), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2237 | { "vmaxsb" , VX(4, 258), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2238 | { "vmaxsh" , VX(4, 322), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2239 | { "vmaxsw" , VX(4, 386), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2240 | { "vmaxub" , VX(4, 2), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2241 | { "vmaxuh" , VX(4, 66), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2242 | { "vmaxuw" , VX(4, 130), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2243 | { "vmhaddshs" , VXA(4, 32), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, |
2244 | { "vmhraddshs" , VXA(4, 33), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, |
2245 | { "vminfp" , VX(4, 1098), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2246 | { "vminsb" , VX(4, 770), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2247 | { "vminsh" , VX(4, 834), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2248 | { "vminsw" , VX(4, 898), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2249 | { "vminub" , VX(4, 514), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2250 | { "vminuh" , VX(4, 578), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2251 | { "vminuw" , VX(4, 642), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2252 | { "vmladduhm" , VXA(4, 34), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, |
2253 | { "vmrghb" , VX(4, 12), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2254 | { "vmrghh" , VX(4, 76), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2255 | { "vmrghw" , VX(4, 140), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2256 | { "vmrglb" , VX(4, 268), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2257 | { "vmrglh" , VX(4, 332), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2258 | { "vmrglw" , VX(4, 396), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2259 | { "vmsummbm" , VXA(4, 37), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, |
2260 | { "vmsumshm" , VXA(4, 40), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, |
2261 | { "vmsumshs" , VXA(4, 41), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, |
2262 | { "vmsumubm" , VXA(4, 36), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, |
2263 | { "vmsumuhm" , VXA(4, 38), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, |
2264 | { "vmsumuhs" , VXA(4, 39), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, |
2265 | { "vmulesb" , VX(4, 776), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2266 | { "vmulesh" , VX(4, 840), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2267 | { "vmuleub" , VX(4, 520), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2268 | { "vmuleuh" , VX(4, 584), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2269 | { "vmulosb" , VX(4, 264), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2270 | { "vmulosh" , VX(4, 328), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2271 | { "vmuloub" , VX(4, 8), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2272 | { "vmulouh" , VX(4, 72), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2273 | { "vnmsubfp" , VXA(4, 47), VXA_MASK, PPCVEC, { VD, VA, VC, VB } }, |
2274 | { "vnor" , VX(4, 1284), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2275 | { "vor" , VX(4, 1156), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2276 | { "vperm" , VXA(4, 43), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, |
2277 | { "vpkpx" , VX(4, 782), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2278 | { "vpkshss" , VX(4, 398), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2279 | { "vpkshus" , VX(4, 270), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2280 | { "vpkswss" , VX(4, 462), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2281 | { "vpkswus" , VX(4, 334), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2282 | { "vpkuhum" , VX(4, 14), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2283 | { "vpkuhus" , VX(4, 142), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2284 | { "vpkuwum" , VX(4, 78), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2285 | { "vpkuwus" , VX(4, 206), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2286 | { "vrefp" , VX(4, 266), VX_MASK, PPCVEC, { VD, VB } }, |
2287 | { "vrfim" , VX(4, 714), VX_MASK, PPCVEC, { VD, VB } }, |
2288 | { "vrfin" , VX(4, 522), VX_MASK, PPCVEC, { VD, VB } }, |
2289 | { "vrfip" , VX(4, 650), VX_MASK, PPCVEC, { VD, VB } }, |
2290 | { "vrfiz" , VX(4, 586), VX_MASK, PPCVEC, { VD, VB } }, |
2291 | { "vrlb" , VX(4, 4), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2292 | { "vrlh" , VX(4, 68), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2293 | { "vrlw" , VX(4, 132), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2294 | { "vrsqrtefp" , VX(4, 330), VX_MASK, PPCVEC, { VD, VB } }, |
2295 | { "vrldmi" , VX(4, 197), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2296 | { "vrldnm" , VX(4, 453), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2297 | { "vrlwmi" , VX(4, 133), VX_MASK, PPCVEC, { VD, VA, VB} }, |
2298 | { "vrlwnm" , VX(4, 389), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2299 | { "vsel" , VXA(4, 42), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, |
2300 | { "vsl" , VX(4, 452), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2301 | { "vslb" , VX(4, 260), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2302 | { "vsldoi" , VXA(4, 44), VXA_MASK, PPCVEC, { VD, VA, VB, SHB } }, |
2303 | { "vslh" , VX(4, 324), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2304 | { "vslo" , VX(4, 1036), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2305 | { "vslw" , VX(4, 388), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2306 | { "vspltb" , VX(4, 524), VX_MASK, PPCVEC, { VD, VB, UIMM } }, |
2307 | { "vsplth" , VX(4, 588), VX_MASK, PPCVEC, { VD, VB, UIMM } }, |
2308 | { "vspltisb" , VX(4, 780), VX_MASK, PPCVEC, { VD, SIMM } }, |
2309 | { "vspltish" , VX(4, 844), VX_MASK, PPCVEC, { VD, SIMM } }, |
2310 | { "vspltisw" , VX(4, 908), VX_MASK, PPCVEC, { VD, SIMM } }, |
2311 | { "vspltw" , VX(4, 652), VX_MASK, PPCVEC, { VD, VB, UIMM } }, |
2312 | { "vsr" , VX(4, 708), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2313 | { "vsrab" , VX(4, 772), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2314 | { "vsrah" , VX(4, 836), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2315 | { "vsraw" , VX(4, 900), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2316 | { "vsrb" , VX(4, 516), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2317 | { "vsrh" , VX(4, 580), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2318 | { "vsro" , VX(4, 1100), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2319 | { "vsrw" , VX(4, 644), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2320 | { "vsubcuw" , VX(4, 1408), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2321 | { "vsubfp" , VX(4, 74), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2322 | { "vsubsbs" , VX(4, 1792), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2323 | { "vsubshs" , VX(4, 1856), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2324 | { "vsubsws" , VX(4, 1920), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2325 | { "vsububm" , VX(4, 1024), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2326 | { "vsububs" , VX(4, 1536), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2327 | { "vsubuhm" , VX(4, 1088), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2328 | { "vsubuhs" , VX(4, 1600), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2329 | { "vsubuwm" , VX(4, 1152), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2330 | { "vsubuws" , VX(4, 1664), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2331 | { "vsumsws" , VX(4, 1928), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2332 | { "vsum2sws" , VX(4, 1672), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2333 | { "vsum4sbs" , VX(4, 1800), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2334 | { "vsum4shs" , VX(4, 1608), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2335 | { "vsum4ubs" , VX(4, 1544), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2336 | { "vupkhpx" , VX(4, 846), VX_MASK, PPCVEC, { VD, VB } }, |
2337 | { "vupkhsb" , VX(4, 526), VX_MASK, PPCVEC, { VD, VB } }, |
2338 | { "vupkhsh" , VX(4, 590), VX_MASK, PPCVEC, { VD, VB } }, |
2339 | { "vupklpx" , VX(4, 974), VX_MASK, PPCVEC, { VD, VB } }, |
2340 | { "vupklsb" , VX(4, 654), VX_MASK, PPCVEC, { VD, VB } }, |
2341 | { "vupklsh" , VX(4, 718), VX_MASK, PPCVEC, { VD, VB } }, |
2342 | { "vxor" , VX(4, 1220), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2343 | |
2344 | { "evaddw" , VX(4, 512), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2345 | { "evaddiw" , VX(4, 514), VX_MASK, PPCSPE, { RS, RB, UIMM } }, |
2346 | { "evsubfw" , VX(4, 516), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2347 | { "evsubw" , VX(4, 516), VX_MASK, PPCSPE, { RS, RB, RA } }, |
2348 | { "evsubifw" , VX(4, 518), VX_MASK, PPCSPE, { RS, UIMM, RB } }, |
2349 | { "evsubiw" , VX(4, 518), VX_MASK, PPCSPE, { RS, RB, UIMM } }, |
2350 | { "evabs" , VX(4, 520), VX_MASK, PPCSPE, { RS, RA } }, |
2351 | { "evneg" , VX(4, 521), VX_MASK, PPCSPE, { RS, RA } }, |
2352 | { "evextsb" , VX(4, 522), VX_MASK, PPCSPE, { RS, RA } }, |
2353 | { "evextsh" , VX(4, 523), VX_MASK, PPCSPE, { RS, RA } }, |
2354 | { "evrndw" , VX(4, 524), VX_MASK, PPCSPE, { RS, RA } }, |
2355 | { "evcntlzw" , VX(4, 525), VX_MASK, PPCSPE, { RS, RA } }, |
2356 | { "evcntlsw" , VX(4, 526), VX_MASK, PPCSPE, { RS, RA } }, |
2357 | |
2358 | { "brinc" , VX(4, 527), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2359 | |
2360 | { "evand" , VX(4, 529), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2361 | { "evandc" , VX(4, 530), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2362 | { "evmr" , VX(4, 535), VX_MASK, PPCSPE, { RS, RA, BBA } }, |
2363 | { "evor" , VX(4, 535), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2364 | { "evorc" , VX(4, 539), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2365 | { "evxor" , VX(4, 534), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2366 | { "eveqv" , VX(4, 537), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2367 | { "evnand" , VX(4, 542), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2368 | { "evnot" , VX(4, 536), VX_MASK, PPCSPE, { RS, RA, BBA } }, |
2369 | { "evnor" , VX(4, 536), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2370 | |
2371 | { "evrlw" , VX(4, 552), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2372 | { "evrlwi" , VX(4, 554), VX_MASK, PPCSPE, { RS, RA, EVUIMM } }, |
2373 | { "evslw" , VX(4, 548), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2374 | { "evslwi" , VX(4, 550), VX_MASK, PPCSPE, { RS, RA, EVUIMM } }, |
2375 | { "evsrws" , VX(4, 545), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2376 | { "evsrwu" , VX(4, 544), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2377 | { "evsrwis" , VX(4, 547), VX_MASK, PPCSPE, { RS, RA, EVUIMM } }, |
2378 | { "evsrwiu" , VX(4, 546), VX_MASK, PPCSPE, { RS, RA, EVUIMM } }, |
2379 | { "evsplati" , VX(4, 553), VX_MASK, PPCSPE, { RS, SIMM } }, |
2380 | { "evsplatfi" , VX(4, 555), VX_MASK, PPCSPE, { RS, SIMM } }, |
2381 | { "evmergehi" , VX(4, 556), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2382 | { "evmergelo" , VX(4, 557), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2383 | { "evmergehilo" ,VX(4,558), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2384 | { "evmergelohi" ,VX(4,559), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2385 | |
2386 | { "evcmpgts" , VX(4, 561), VX_MASK, PPCSPE, { CRFD, RA, RB } }, |
2387 | { "evcmpgtu" , VX(4, 560), VX_MASK, PPCSPE, { CRFD, RA, RB } }, |
2388 | { "evcmplts" , VX(4, 563), VX_MASK, PPCSPE, { CRFD, RA, RB } }, |
2389 | { "evcmpltu" , VX(4, 562), VX_MASK, PPCSPE, { CRFD, RA, RB } }, |
2390 | { "evcmpeq" , VX(4, 564), VX_MASK, PPCSPE, { CRFD, RA, RB } }, |
2391 | { "evsel" , EVSEL(4,79),EVSEL_MASK, PPCSPE, { RS, RA, RB, CRFS } }, |
2392 | |
2393 | { "evldd" , VX(4, 769), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } }, |
2394 | { "evlddx" , VX(4, 768), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2395 | { "evldw" , VX(4, 771), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } }, |
2396 | { "evldwx" , VX(4, 770), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2397 | { "evldh" , VX(4, 773), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } }, |
2398 | { "evldhx" , VX(4, 772), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2399 | { "evlwhe" , VX(4, 785), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, |
2400 | { "evlwhex" , VX(4, 784), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2401 | { "evlwhou" , VX(4, 789), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, |
2402 | { "evlwhoux" , VX(4, 788), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2403 | { "evlwhos" , VX(4, 791), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, |
2404 | { "evlwhosx" , VX(4, 790), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2405 | { "evlwwsplat" ,VX(4, 793), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, |
2406 | { "evlwwsplatx" ,VX(4, 792), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2407 | { "evlwhsplat" ,VX(4, 797), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, |
2408 | { "evlwhsplatx" ,VX(4, 796), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2409 | { "evlhhesplat" ,VX(4, 777), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } }, |
2410 | { "evlhhesplatx" ,VX(4, 776), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2411 | { "evlhhousplat" ,VX(4, 781), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } }, |
2412 | { "evlhhousplatx" ,VX(4, 780), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2413 | { "evlhhossplat" ,VX(4, 783), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } }, |
2414 | { "evlhhossplatx" ,VX(4, 782), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2415 | |
2416 | { "evstdd" , VX(4, 801), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } }, |
2417 | { "evstddx" , VX(4, 800), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2418 | { "evstdw" , VX(4, 803), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } }, |
2419 | { "evstdwx" , VX(4, 802), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2420 | { "evstdh" , VX(4, 805), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } }, |
2421 | { "evstdhx" , VX(4, 804), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2422 | { "evstwwe" , VX(4, 825), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, |
2423 | { "evstwwex" , VX(4, 824), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2424 | { "evstwwo" , VX(4, 829), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, |
2425 | { "evstwwox" , VX(4, 828), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2426 | { "evstwhe" , VX(4, 817), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, |
2427 | { "evstwhex" , VX(4, 816), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2428 | { "evstwho" , VX(4, 821), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, |
2429 | { "evstwhox" , VX(4, 820), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2430 | |
2431 | { "evfsabs" , VX(4, 644), VX_MASK, PPCSPE, { RS, RA } }, |
2432 | { "evfsnabs" , VX(4, 645), VX_MASK, PPCSPE, { RS, RA } }, |
2433 | { "evfsneg" , VX(4, 646), VX_MASK, PPCSPE, { RS, RA } }, |
2434 | { "evfsadd" , VX(4, 640), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2435 | { "evfssub" , VX(4, 641), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2436 | { "evfsmul" , VX(4, 648), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2437 | { "evfsdiv" , VX(4, 649), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2438 | { "evfscmpgt" , VX(4, 652), VX_MASK, PPCSPE, { CRFD, RA, RB } }, |
2439 | { "evfscmplt" , VX(4, 653), VX_MASK, PPCSPE, { CRFD, RA, RB } }, |
2440 | { "evfscmpeq" , VX(4, 654), VX_MASK, PPCSPE, { CRFD, RA, RB } }, |
2441 | { "evfststgt" , VX(4, 668), VX_MASK, PPCSPE, { CRFD, RA, RB } }, |
2442 | { "evfststlt" , VX(4, 669), VX_MASK, PPCSPE, { CRFD, RA, RB } }, |
2443 | { "evfststeq" , VX(4, 670), VX_MASK, PPCSPE, { CRFD, RA, RB } }, |
2444 | { "evfscfui" , VX(4, 656), VX_MASK, PPCSPE, { RS, RB } }, |
2445 | { "evfsctuiz" , VX(4, 664), VX_MASK, PPCSPE, { RS, RB } }, |
2446 | { "evfscfsi" , VX(4, 657), VX_MASK, PPCSPE, { RS, RB } }, |
2447 | { "evfscfuf" , VX(4, 658), VX_MASK, PPCSPE, { RS, RB } }, |
2448 | { "evfscfsf" , VX(4, 659), VX_MASK, PPCSPE, { RS, RB } }, |
2449 | { "evfsctui" , VX(4, 660), VX_MASK, PPCSPE, { RS, RB } }, |
2450 | { "evfsctsi" , VX(4, 661), VX_MASK, PPCSPE, { RS, RB } }, |
2451 | { "evfsctsiz" , VX(4, 666), VX_MASK, PPCSPE, { RS, RB } }, |
2452 | { "evfsctuf" , VX(4, 662), VX_MASK, PPCSPE, { RS, RB } }, |
2453 | { "evfsctsf" , VX(4, 663), VX_MASK, PPCSPE, { RS, RB } }, |
2454 | |
2455 | { "efsabs" , VX(4, 708), VX_MASK, PPCEFS, { RS, RA } }, |
2456 | { "efsnabs" , VX(4, 709), VX_MASK, PPCEFS, { RS, RA } }, |
2457 | { "efsneg" , VX(4, 710), VX_MASK, PPCEFS, { RS, RA } }, |
2458 | { "efsadd" , VX(4, 704), VX_MASK, PPCEFS, { RS, RA, RB } }, |
2459 | { "efssub" , VX(4, 705), VX_MASK, PPCEFS, { RS, RA, RB } }, |
2460 | { "efsmul" , VX(4, 712), VX_MASK, PPCEFS, { RS, RA, RB } }, |
2461 | { "efsdiv" , VX(4, 713), VX_MASK, PPCEFS, { RS, RA, RB } }, |
2462 | { "efscmpgt" , VX(4, 716), VX_MASK, PPCEFS, { CRFD, RA, RB } }, |
2463 | { "efscmplt" , VX(4, 717), VX_MASK, PPCEFS, { CRFD, RA, RB } }, |
2464 | { "efscmpeq" , VX(4, 718), VX_MASK, PPCEFS, { CRFD, RA, RB } }, |
2465 | { "efststgt" , VX(4, 732), VX_MASK, PPCEFS, { CRFD, RA, RB } }, |
2466 | { "efststlt" , VX(4, 733), VX_MASK, PPCEFS, { CRFD, RA, RB } }, |
2467 | { "efststeq" , VX(4, 734), VX_MASK, PPCEFS, { CRFD, RA, RB } }, |
2468 | { "efscfui" , VX(4, 720), VX_MASK, PPCEFS, { RS, RB } }, |
2469 | { "efsctuiz" , VX(4, 728), VX_MASK, PPCEFS, { RS, RB } }, |
2470 | { "efscfsi" , VX(4, 721), VX_MASK, PPCEFS, { RS, RB } }, |
2471 | { "efscfuf" , VX(4, 722), VX_MASK, PPCEFS, { RS, RB } }, |
2472 | { "efscfsf" , VX(4, 723), VX_MASK, PPCEFS, { RS, RB } }, |
2473 | { "efsctui" , VX(4, 724), VX_MASK, PPCEFS, { RS, RB } }, |
2474 | { "efsctsi" , VX(4, 725), VX_MASK, PPCEFS, { RS, RB } }, |
2475 | { "efsctsiz" , VX(4, 730), VX_MASK, PPCEFS, { RS, RB } }, |
2476 | { "efsctuf" , VX(4, 726), VX_MASK, PPCEFS, { RS, RB } }, |
2477 | { "efsctsf" , VX(4, 727), VX_MASK, PPCEFS, { RS, RB } }, |
2478 | |
2479 | { "evmhossf" , VX(4, 1031), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2480 | { "evmhossfa" , VX(4, 1063), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2481 | { "evmhosmf" , VX(4, 1039), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2482 | { "evmhosmfa" , VX(4, 1071), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2483 | { "evmhosmi" , VX(4, 1037), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2484 | { "evmhosmia" , VX(4, 1069), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2485 | { "evmhoumi" , VX(4, 1036), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2486 | { "evmhoumia" , VX(4, 1068), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2487 | { "evmhessf" , VX(4, 1027), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2488 | { "evmhessfa" , VX(4, 1059), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2489 | { "evmhesmf" , VX(4, 1035), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2490 | { "evmhesmfa" , VX(4, 1067), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2491 | { "evmhesmi" , VX(4, 1033), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2492 | { "evmhesmia" , VX(4, 1065), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2493 | { "evmheumi" , VX(4, 1032), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2494 | { "evmheumia" , VX(4, 1064), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2495 | |
2496 | { "evmhossfaaw" ,VX(4, 1287), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2497 | { "evmhossiaaw" ,VX(4, 1285), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2498 | { "evmhosmfaaw" ,VX(4, 1295), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2499 | { "evmhosmiaaw" ,VX(4, 1293), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2500 | { "evmhousiaaw" ,VX(4, 1284), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2501 | { "evmhoumiaaw" ,VX(4, 1292), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2502 | { "evmhessfaaw" ,VX(4, 1283), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2503 | { "evmhessiaaw" ,VX(4, 1281), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2504 | { "evmhesmfaaw" ,VX(4, 1291), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2505 | { "evmhesmiaaw" ,VX(4, 1289), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2506 | { "evmheusiaaw" ,VX(4, 1280), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2507 | { "evmheumiaaw" ,VX(4, 1288), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2508 | |
2509 | { "evmhossfanw" ,VX(4, 1415), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2510 | { "evmhossianw" ,VX(4, 1413), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2511 | { "evmhosmfanw" ,VX(4, 1423), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2512 | { "evmhosmianw" ,VX(4, 1421), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2513 | { "evmhousianw" ,VX(4, 1412), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2514 | { "evmhoumianw" ,VX(4, 1420), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2515 | { "evmhessfanw" ,VX(4, 1411), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2516 | { "evmhessianw" ,VX(4, 1409), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2517 | { "evmhesmfanw" ,VX(4, 1419), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2518 | { "evmhesmianw" ,VX(4, 1417), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2519 | { "evmheusianw" ,VX(4, 1408), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2520 | { "evmheumianw" ,VX(4, 1416), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2521 | |
2522 | { "evmhogsmfaa" ,VX(4, 1327), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2523 | { "evmhogsmiaa" ,VX(4, 1325), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2524 | { "evmhogumiaa" ,VX(4, 1324), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2525 | { "evmhegsmfaa" ,VX(4, 1323), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2526 | { "evmhegsmiaa" ,VX(4, 1321), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2527 | { "evmhegumiaa" ,VX(4, 1320), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2528 | |
2529 | { "evmhogsmfan" ,VX(4, 1455), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2530 | { "evmhogsmian" ,VX(4, 1453), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2531 | { "evmhogumian" ,VX(4, 1452), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2532 | { "evmhegsmfan" ,VX(4, 1451), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2533 | { "evmhegsmian" ,VX(4, 1449), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2534 | { "evmhegumian" ,VX(4, 1448), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2535 | |
2536 | { "evmwhssf" , VX(4, 1095), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2537 | { "evmwhssfa" , VX(4, 1127), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2538 | { "evmwhsmf" , VX(4, 1103), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2539 | { "evmwhsmfa" , VX(4, 1135), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2540 | { "evmwhsmi" , VX(4, 1101), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2541 | { "evmwhsmia" , VX(4, 1133), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2542 | { "evmwhumi" , VX(4, 1100), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2543 | { "evmwhumia" , VX(4, 1132), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2544 | |
2545 | { "evmwlumi" , VX(4, 1096), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2546 | { "evmwlumia" , VX(4, 1128), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2547 | |
2548 | { "evmwlssiaaw" ,VX(4, 1345), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2549 | { "evmwlsmiaaw" ,VX(4, 1353), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2550 | { "evmwlusiaaw" ,VX(4, 1344), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2551 | { "evmwlumiaaw" ,VX(4, 1352), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2552 | |
2553 | { "evmwlssianw" ,VX(4, 1473), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2554 | { "evmwlsmianw" ,VX(4, 1481), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2555 | { "evmwlusianw" ,VX(4, 1472), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2556 | { "evmwlumianw" ,VX(4, 1480), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2557 | |
2558 | { "evmwssf" , VX(4, 1107), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2559 | { "evmwssfa" , VX(4, 1139), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2560 | { "evmwsmf" , VX(4, 1115), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2561 | { "evmwsmfa" , VX(4, 1147), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2562 | { "evmwsmi" , VX(4, 1113), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2563 | { "evmwsmia" , VX(4, 1145), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2564 | { "evmwumi" , VX(4, 1112), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2565 | { "evmwumia" , VX(4, 1144), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2566 | |
2567 | { "evmwssfaa" , VX(4, 1363), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2568 | { "evmwsmfaa" , VX(4, 1371), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2569 | { "evmwsmiaa" , VX(4, 1369), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2570 | { "evmwumiaa" , VX(4, 1368), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2571 | |
2572 | { "evmwssfan" , VX(4, 1491), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2573 | { "evmwsmfan" , VX(4, 1499), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2574 | { "evmwsmian" , VX(4, 1497), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2575 | { "evmwumian" , VX(4, 1496), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2576 | |
2577 | { "evaddssiaaw" ,VX(4, 1217), VX_MASK, PPCSPE, { RS, RA } }, |
2578 | { "evaddsmiaaw" ,VX(4, 1225), VX_MASK, PPCSPE, { RS, RA } }, |
2579 | { "evaddusiaaw" ,VX(4, 1216), VX_MASK, PPCSPE, { RS, RA } }, |
2580 | { "evaddumiaaw" ,VX(4, 1224), VX_MASK, PPCSPE, { RS, RA } }, |
2581 | |
2582 | { "evsubfssiaaw" ,VX(4, 1219), VX_MASK, PPCSPE, { RS, RA } }, |
2583 | { "evsubfsmiaaw" ,VX(4, 1227), VX_MASK, PPCSPE, { RS, RA } }, |
2584 | { "evsubfusiaaw" ,VX(4, 1218), VX_MASK, PPCSPE, { RS, RA } }, |
2585 | { "evsubfumiaaw" ,VX(4, 1226), VX_MASK, PPCSPE, { RS, RA } }, |
2586 | |
2587 | { "evmra" , VX(4, 1220), VX_MASK, PPCSPE, { RS, RA } }, |
2588 | |
2589 | { "evdivws" , VX(4, 1222), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2590 | { "evdivwu" , VX(4, 1223), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2591 | |
2592 | { "mulli" , OP(7), OP_MASK, PPCCOM, { RT, RA, SI } }, |
2593 | { "muli" , OP(7), OP_MASK, PWRCOM, { RT, RA, SI } }, |
2594 | |
2595 | { "subfic" , OP(8), OP_MASK, PPCCOM, { RT, RA, SI } }, |
2596 | { "sfi" , OP(8), OP_MASK, PWRCOM, { RT, RA, SI } }, |
2597 | |
2598 | { "dozi" , OP(9), OP_MASK, M601, { RT, RA, SI } }, |
2599 | |
2600 | { "bce" , B(9,0,0), B_MASK, BOOKE64, { BO, BI, BD } }, |
2601 | { "bcel" , B(9,0,1), B_MASK, BOOKE64, { BO, BI, BD } }, |
2602 | { "bcea" , B(9,1,0), B_MASK, BOOKE64, { BO, BI, BDA } }, |
2603 | { "bcela" , B(9,1,1), B_MASK, BOOKE64, { BO, BI, BDA } }, |
2604 | |
2605 | { "cmplwi" , OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } }, |
2606 | { "cmpldi" , OPL(10,1), OPL_MASK, PPC64, { OBF, RA, UI } }, |
2607 | { "cmpli" , OP(10), OP_MASK, PPC, { BF, L, RA, UI } }, |
2608 | { "cmpli" , OP(10), OP_MASK, PWRCOM, { BF, RA, UI } }, |
2609 | |
2610 | { "cmpwi" , OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } }, |
2611 | { "cmpdi" , OPL(11,1), OPL_MASK, PPC64, { OBF, RA, SI } }, |
2612 | { "cmpi" , OP(11), OP_MASK, PPC, { BF, L, RA, SI } }, |
2613 | { "cmpi" , OP(11), OP_MASK, PWRCOM, { BF, RA, SI } }, |
2614 | |
2615 | { "addic" , OP(12), OP_MASK, PPCCOM, { RT, RA, SI } }, |
2616 | { "ai" , OP(12), OP_MASK, PWRCOM, { RT, RA, SI } }, |
2617 | { "subic" , OP(12), OP_MASK, PPCCOM, { RT, RA, NSI } }, |
2618 | |
2619 | { "addic." , OP(13), OP_MASK, PPCCOM, { RT, RA, SI } }, |
2620 | { "ai." , OP(13), OP_MASK, PWRCOM, { RT, RA, SI } }, |
2621 | { "subic." , OP(13), OP_MASK, PPCCOM, { RT, RA, NSI } }, |
2622 | |
2623 | { "li" , OP(14), DRA_MASK, PPCCOM, { RT, SI } }, |
2624 | { "lil" , OP(14), DRA_MASK, PWRCOM, { RT, SI } }, |
2625 | { "addi" , OP(14), OP_MASK, PPCCOM, { RT, RA0, SI } }, |
2626 | { "cal" , OP(14), OP_MASK, PWRCOM, { RT, D, RA0 } }, |
2627 | { "subi" , OP(14), OP_MASK, PPCCOM, { RT, RA0, NSI } }, |
2628 | { "la" , OP(14), OP_MASK, PPCCOM, { RT, D, RA0 } }, |
2629 | |
2630 | { "lis" , OP(15), DRA_MASK, PPCCOM, { RT, SISIGNOPT } }, |
2631 | { "liu" , OP(15), DRA_MASK, PWRCOM, { RT, SISIGNOPT } }, |
2632 | { "addis" , OP(15), OP_MASK, PPCCOM, { RT,RA0,SISIGNOPT } }, |
2633 | { "cau" , OP(15), OP_MASK, PWRCOM, { RT,RA0,SISIGNOPT } }, |
2634 | { "subis" , OP(15), OP_MASK, PPCCOM, { RT, RA0, NSI } }, |
2635 | |
2636 | { "bdnz-" , BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } }, |
2637 | { "bdnz+" , BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } }, |
2638 | { "bdnz" , BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BD } }, |
2639 | { "bdn" , BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, { BD } }, |
2640 | { "bdnzl-" , BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } }, |
2641 | { "bdnzl+" , BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } }, |
2642 | { "bdnzl" , BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BD } }, |
2643 | { "bdnl" , BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, { BD } }, |
2644 | { "bdnza-" , BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } }, |
2645 | { "bdnza+" , BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } }, |
2646 | { "bdnza" , BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDA } }, |
2647 | { "bdna" , BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, { BDA } }, |
2648 | { "bdnzla-" , BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } }, |
2649 | { "bdnzla+" , BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } }, |
2650 | { "bdnzla" , BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDA } }, |
2651 | { "bdnla" , BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, { BDA } }, |
2652 | { "bdz-" , BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } }, |
2653 | { "bdz+" , BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } }, |
2654 | { "bdz" , BBO(16,BODZ,0,0), BBOATBI_MASK, COM, { BD } }, |
2655 | { "bdzl-" , BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } }, |
2656 | { "bdzl+" , BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } }, |
2657 | { "bdzl" , BBO(16,BODZ,0,1), BBOATBI_MASK, COM, { BD } }, |
2658 | { "bdza-" , BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } }, |
2659 | { "bdza+" , BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } }, |
2660 | { "bdza" , BBO(16,BODZ,1,0), BBOATBI_MASK, COM, { BDA } }, |
2661 | { "bdzla-" , BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } }, |
2662 | { "bdzla+" , BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } }, |
2663 | { "bdzla" , BBO(16,BODZ,1,1), BBOATBI_MASK, COM, { BDA } }, |
2664 | { "blt-" , BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
2665 | { "blt+" , BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
2666 | { "blt" , BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } }, |
2667 | { "bltl-" , BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
2668 | { "bltl+" , BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
2669 | { "bltl" , BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } }, |
2670 | { "blta-" , BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
2671 | { "blta+" , BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
2672 | { "blta" , BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, |
2673 | { "bltla-" , BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
2674 | { "bltla+" , BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
2675 | { "bltla" , BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, |
2676 | { "bgt-" , BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
2677 | { "bgt+" , BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
2678 | { "bgt" , BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } }, |
2679 | { "bgtl-" , BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
2680 | { "bgtl+" , BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
2681 | { "bgtl" , BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } }, |
2682 | { "bgta-" , BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
2683 | { "bgta+" , BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
2684 | { "bgta" , BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, |
2685 | { "bgtla-" , BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
2686 | { "bgtla+" , BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
2687 | { "bgtla" , BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, |
2688 | { "beq-" , BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
2689 | { "beq+" , BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
2690 | { "beq" , BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } }, |
2691 | { "beql-" , BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
2692 | { "beql+" , BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
2693 | { "beql" , BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } }, |
2694 | { "beqa-" , BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
2695 | { "beqa+" , BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
2696 | { "beqa" , BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } }, |
2697 | { "beqla-" , BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
2698 | { "beqla+" , BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
2699 | { "beqla" , BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } }, |
2700 | { "bso-" , BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
2701 | { "bso+" , BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
2702 | { "bso" , BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } }, |
2703 | { "bsol-" , BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
2704 | { "bsol+" , BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
2705 | { "bsol" , BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } }, |
2706 | { "bsoa-" , BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
2707 | { "bsoa+" , BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
2708 | { "bsoa" , BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } }, |
2709 | { "bsola-" , BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
2710 | { "bsola+" , BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
2711 | { "bsola" , BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } }, |
2712 | { "bun-" , BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
2713 | { "bun+" , BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
2714 | { "bun" , BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } }, |
2715 | { "bunl-" , BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
2716 | { "bunl+" , BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
2717 | { "bunl" , BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } }, |
2718 | { "buna-" , BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
2719 | { "buna+" , BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
2720 | { "buna" , BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } }, |
2721 | { "bunla-" , BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
2722 | { "bunla+" , BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
2723 | { "bunla" , BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } }, |
2724 | { "bge-" , BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
2725 | { "bge+" , BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
2726 | { "bge" , BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } }, |
2727 | { "bgel-" , BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
2728 | { "bgel+" , BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
2729 | { "bgel" , BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } }, |
2730 | { "bgea-" , BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
2731 | { "bgea+" , BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
2732 | { "bgea" , BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, |
2733 | { "bgela-" , BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
2734 | { "bgela+" , BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
2735 | { "bgela" , BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, |
2736 | { "bnl-" , BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
2737 | { "bnl+" , BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
2738 | { "bnl" , BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } }, |
2739 | { "bnll-" , BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
2740 | { "bnll+" , BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
2741 | { "bnll" , BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } }, |
2742 | { "bnla-" , BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
2743 | { "bnla+" , BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
2744 | { "bnla" , BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, |
2745 | { "bnlla-" , BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
2746 | { "bnlla+" , BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
2747 | { "bnlla" , BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, |
2748 | { "ble-" , BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
2749 | { "ble+" , BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
2750 | { "ble" , BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } }, |
2751 | { "blel-" , BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
2752 | { "blel+" , BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
2753 | { "blel" , BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } }, |
2754 | { "blea-" , BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
2755 | { "blea+" , BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
2756 | { "blea" , BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, |
2757 | { "blela-" , BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
2758 | { "blela+" , BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
2759 | { "blela" , BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, |
2760 | { "bng-" , BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
2761 | { "bng+" , BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
2762 | { "bng" , BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } }, |
2763 | { "bngl-" , BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
2764 | { "bngl+" , BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
2765 | { "bngl" , BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } }, |
2766 | { "bnga-" , BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
2767 | { "bnga+" , BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
2768 | { "bnga" , BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, |
2769 | { "bngla-" , BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
2770 | { "bngla+" , BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
2771 | { "bngla" , BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, |
2772 | { "bne-" , BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
2773 | { "bne+" , BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
2774 | { "bne" , BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } }, |
2775 | { "bnel-" , BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
2776 | { "bnel+" , BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
2777 | { "bnel" , BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } }, |
2778 | { "bnea-" , BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
2779 | { "bnea+" , BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
2780 | { "bnea" , BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } }, |
2781 | { "bnela-" , BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
2782 | { "bnela+" , BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
2783 | { "bnela" , BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } }, |
2784 | { "bns-" , BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
2785 | { "bns+" , BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
2786 | { "bns" , BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } }, |
2787 | { "bnsl-" , BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
2788 | { "bnsl+" , BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
2789 | { "bnsl" , BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } }, |
2790 | { "bnsa-" , BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
2791 | { "bnsa+" , BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
2792 | { "bnsa" , BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } }, |
2793 | { "bnsla-" , BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
2794 | { "bnsla+" , BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
2795 | { "bnsla" , BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } }, |
2796 | { "bnu-" , BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
2797 | { "bnu+" , BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
2798 | { "bnu" , BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } }, |
2799 | { "bnul-" , BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
2800 | { "bnul+" , BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
2801 | { "bnul" , BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } }, |
2802 | { "bnua-" , BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
2803 | { "bnua+" , BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
2804 | { "bnua" , BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } }, |
2805 | { "bnula-" , BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
2806 | { "bnula+" , BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
2807 | { "bnula" , BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } }, |
2808 | { "bdnzt-" , BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } }, |
2809 | { "bdnzt+" , BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } }, |
2810 | { "bdnzt" , BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } }, |
2811 | { "bdnztl-" , BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } }, |
2812 | { "bdnztl+" , BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } }, |
2813 | { "bdnztl" , BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } }, |
2814 | { "bdnzta-" , BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } }, |
2815 | { "bdnzta+" , BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } }, |
2816 | { "bdnzta" , BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } }, |
2817 | { "bdnztla-" ,BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } }, |
2818 | { "bdnztla+" ,BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } }, |
2819 | { "bdnztla" , BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } }, |
2820 | { "bdnzf-" , BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } }, |
2821 | { "bdnzf+" , BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } }, |
2822 | { "bdnzf" , BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } }, |
2823 | { "bdnzfl-" , BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } }, |
2824 | { "bdnzfl+" , BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } }, |
2825 | { "bdnzfl" , BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } }, |
2826 | { "bdnzfa-" , BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } }, |
2827 | { "bdnzfa+" , BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } }, |
2828 | { "bdnzfa" , BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } }, |
2829 | { "bdnzfla-" ,BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } }, |
2830 | { "bdnzfla+" ,BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } }, |
2831 | { "bdnzfla" , BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } }, |
2832 | { "bt-" , BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } }, |
2833 | { "bt+" , BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } }, |
2834 | { "bt" , BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BD } }, |
2835 | { "bbt" , BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, { BI, BD } }, |
2836 | { "btl-" , BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } }, |
2837 | { "btl+" , BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } }, |
2838 | { "btl" , BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BD } }, |
2839 | { "bbtl" , BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, { BI, BD } }, |
2840 | { "bta-" , BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } }, |
2841 | { "bta+" , BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } }, |
2842 | { "bta" , BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } }, |
2843 | { "bbta" , BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } }, |
2844 | { "btla-" , BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } }, |
2845 | { "btla+" , BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } }, |
2846 | { "btla" , BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } }, |
2847 | { "bbtla" , BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } }, |
2848 | { "bf-" , BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } }, |
2849 | { "bf+" , BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } }, |
2850 | { "bf" , BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BD } }, |
2851 | { "bbf" , BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, { BI, BD } }, |
2852 | { "bfl-" , BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } }, |
2853 | { "bfl+" , BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } }, |
2854 | { "bfl" , BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BD } }, |
2855 | { "bbfl" , BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, { BI, BD } }, |
2856 | { "bfa-" , BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } }, |
2857 | { "bfa+" , BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } }, |
2858 | { "bfa" , BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } }, |
2859 | { "bbfa" , BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } }, |
2860 | { "bfla-" , BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } }, |
2861 | { "bfla+" , BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } }, |
2862 | { "bfla" , BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } }, |
2863 | { "bbfla" , BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } }, |
2864 | { "bdzt-" , BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } }, |
2865 | { "bdzt+" , BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } }, |
2866 | { "bdzt" , BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } }, |
2867 | { "bdztl-" , BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } }, |
2868 | { "bdztl+" , BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } }, |
2869 | { "bdztl" , BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } }, |
2870 | { "bdzta-" , BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } }, |
2871 | { "bdzta+" , BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } }, |
2872 | { "bdzta" , BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } }, |
2873 | { "bdztla-" , BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } }, |
2874 | { "bdztla+" , BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } }, |
2875 | { "bdztla" , BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } }, |
2876 | { "bdzf-" , BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } }, |
2877 | { "bdzf+" , BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } }, |
2878 | { "bdzf" , BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } }, |
2879 | { "bdzfl-" , BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } }, |
2880 | { "bdzfl+" , BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } }, |
2881 | { "bdzfl" , BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } }, |
2882 | { "bdzfa-" , BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } }, |
2883 | { "bdzfa+" , BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } }, |
2884 | { "bdzfa" , BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } }, |
2885 | { "bdzfla-" , BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } }, |
2886 | { "bdzfla+" , BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } }, |
2887 | { "bdzfla" , BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } }, |
2888 | { "bc-" , B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDM } }, |
2889 | { "bc+" , B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDP } }, |
2890 | { "bc" , B(16,0,0), B_MASK, COM, { BO, BI, BD } }, |
2891 | { "bcl-" , B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDM } }, |
2892 | { "bcl+" , B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDP } }, |
2893 | { "bcl" , B(16,0,1), B_MASK, COM, { BO, BI, BD } }, |
2894 | { "bca-" , B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDMA } }, |
2895 | { "bca+" , B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDPA } }, |
2896 | { "bca" , B(16,1,0), B_MASK, COM, { BO, BI, BDA } }, |
2897 | { "bcla-" , B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDMA } }, |
2898 | { "bcla+" , B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDPA } }, |
2899 | { "bcla" , B(16,1,1), B_MASK, COM, { BO, BI, BDA } }, |
2900 | |
2901 | { "sc" , SC(17,1,0), SC_MASK, PPC, { LEV } }, |
2902 | { "svc" , SC(17,0,0), SC_MASK, POWER, { SVC_LEV, FL1, FL2 } }, |
2903 | { "svcl" , SC(17,0,1), SC_MASK, POWER, { SVC_LEV, FL1, FL2 } }, |
2904 | { "svca" , SC(17,1,0), SC_MASK, PWRCOM, { SV } }, |
2905 | { "svcla" , SC(17,1,1), SC_MASK, POWER, { SV } }, |
2906 | |
2907 | { "b" , B(18,0,0), B_MASK, COM, { LI } }, |
2908 | { "bl" , B(18,0,1), B_MASK, COM, { LI } }, |
2909 | { "ba" , B(18,1,0), B_MASK, COM, { LIA } }, |
2910 | { "bla" , B(18,1,1), B_MASK, COM, { LIA } }, |
2911 | |
2912 | { "mcrf" , XL(19,0), XLBB_MASK|(3 << 21)|(3 << 16), COM, { BF, BFA } }, |
2913 | |
2914 | { "blr" , XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } }, |
2915 | { "br" , XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, { 0 } }, |
2916 | { "blrl" , XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } }, |
2917 | { "brl" , XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, { 0 } }, |
2918 | { "bdnzlr" , XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } }, |
2919 | { "bdnzlr-" , XLO(19,BODNZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } }, |
2920 | { "bdnzlr-" , XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } }, |
2921 | { "bdnzlr+" , XLO(19,BODNZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } }, |
2922 | { "bdnzlr+" , XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } }, |
2923 | { "bdnzlrl" , XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } }, |
2924 | { "bdnzlrl-" ,XLO(19,BODNZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } }, |
2925 | { "bdnzlrl-" ,XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } }, |
2926 | { "bdnzlrl+" ,XLO(19,BODNZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } }, |
2927 | { "bdnzlrl+" ,XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } }, |
2928 | { "bdzlr" , XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } }, |
2929 | { "bdzlr-" , XLO(19,BODZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } }, |
2930 | { "bdzlr-" , XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } }, |
2931 | { "bdzlr+" , XLO(19,BODZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } }, |
2932 | { "bdzlr+" , XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } }, |
2933 | { "bdzlrl" , XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } }, |
2934 | { "bdzlrl-" , XLO(19,BODZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } }, |
2935 | { "bdzlrl-" , XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } }, |
2936 | { "bdzlrl+" , XLO(19,BODZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } }, |
2937 | { "bdzlrl+" , XLO(19,BODZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } }, |
2938 | { "bltlr" , XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
2939 | { "bltlr-" , XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
2940 | { "bltlr-" , XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
2941 | { "bltlr+" , XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
2942 | { "bltlr+" , XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
2943 | { "bltr" , XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, |
2944 | { "bltlrl" , XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
2945 | { "bltlrl-" , XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
2946 | { "bltlrl-" , XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
2947 | { "bltlrl+" , XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
2948 | { "bltlrl+" , XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
2949 | { "bltrl" , XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, |
2950 | { "bgtlr" , XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
2951 | { "bgtlr-" , XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
2952 | { "bgtlr-" , XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
2953 | { "bgtlr+" , XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
2954 | { "bgtlr+" , XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
2955 | { "bgtr" , XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, |
2956 | { "bgtlrl" , XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
2957 | { "bgtlrl-" , XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
2958 | { "bgtlrl-" , XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
2959 | { "bgtlrl+" , XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
2960 | { "bgtlrl+" , XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
2961 | { "bgtrl" , XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, |
2962 | { "beqlr" , XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
2963 | { "beqlr-" , XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
2964 | { "beqlr-" , XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
2965 | { "beqlr+" , XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
2966 | { "beqlr+" , XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
2967 | { "beqr" , XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, |
2968 | { "beqlrl" , XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
2969 | { "beqlrl-" , XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
2970 | { "beqlrl-" , XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
2971 | { "beqlrl+" , XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
2972 | { "beqlrl+" , XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
2973 | { "beqrl" , XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, |
2974 | { "bsolr" , XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
2975 | { "bsolr-" , XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
2976 | { "bsolr-" , XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
2977 | { "bsolr+" , XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
2978 | { "bsolr+" , XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
2979 | { "bsor" , XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, |
2980 | { "bsolrl" , XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
2981 | { "bsolrl-" , XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
2982 | { "bsolrl-" , XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
2983 | { "bsolrl+" , XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
2984 | { "bsolrl+" , XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
2985 | { "bsorl" , XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, |
2986 | { "bunlr" , XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
2987 | { "bunlr-" , XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
2988 | { "bunlr-" , XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
2989 | { "bunlr+" , XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
2990 | { "bunlr+" , XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
2991 | { "bunlrl" , XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
2992 | { "bunlrl-" , XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
2993 | { "bunlrl-" , XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
2994 | { "bunlrl+" , XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
2995 | { "bunlrl+" , XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
2996 | { "bgelr" , XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
2997 | { "bgelr-" , XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
2998 | { "bgelr-" , XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
2999 | { "bgelr+" , XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3000 | { "bgelr+" , XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3001 | { "bger" , XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, |
3002 | { "bgelrl" , XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3003 | { "bgelrl-" , XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3004 | { "bgelrl-" , XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3005 | { "bgelrl+" , XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3006 | { "bgelrl+" , XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3007 | { "bgerl" , XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, |
3008 | { "bnllr" , XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3009 | { "bnllr-" , XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3010 | { "bnllr-" , XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3011 | { "bnllr+" , XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3012 | { "bnllr+" , XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3013 | { "bnlr" , XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, |
3014 | { "bnllrl" , XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3015 | { "bnllrl-" , XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3016 | { "bnllrl-" , XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3017 | { "bnllrl+" , XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3018 | { "bnllrl+" , XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3019 | { "bnlrl" , XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, |
3020 | { "blelr" , XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3021 | { "blelr-" , XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3022 | { "blelr-" , XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3023 | { "blelr+" , XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3024 | { "blelr+" , XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3025 | { "bler" , XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, |
3026 | { "blelrl" , XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3027 | { "blelrl-" , XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3028 | { "blelrl-" , XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3029 | { "blelrl+" , XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3030 | { "blelrl+" , XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3031 | { "blerl" , XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, |
3032 | { "bnglr" , XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3033 | { "bnglr-" , XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3034 | { "bnglr-" , XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3035 | { "bnglr+" , XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3036 | { "bnglr+" , XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3037 | { "bngr" , XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, |
3038 | { "bnglrl" , XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3039 | { "bnglrl-" , XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3040 | { "bnglrl-" , XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3041 | { "bnglrl+" , XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3042 | { "bnglrl+" , XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3043 | { "bngrl" , XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, |
3044 | { "bnelr" , XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3045 | { "bnelr-" , XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3046 | { "bnelr-" , XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3047 | { "bnelr+" , XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3048 | { "bnelr+" , XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3049 | { "bner" , XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, |
3050 | { "bnelrl" , XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3051 | { "bnelrl-" , XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3052 | { "bnelrl-" , XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3053 | { "bnelrl+" , XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3054 | { "bnelrl+" , XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3055 | { "bnerl" , XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, |
3056 | { "bnslr" , XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3057 | { "bnslr-" , XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3058 | { "bnslr-" , XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3059 | { "bnslr+" , XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3060 | { "bnslr+" , XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3061 | { "bnsr" , XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, |
3062 | { "bnslrl" , XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3063 | { "bnslrl-" , XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3064 | { "bnslrl-" , XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3065 | { "bnslrl+" , XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3066 | { "bnslrl+" , XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3067 | { "bnsrl" , XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, |
3068 | { "bnulr" , XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3069 | { "bnulr-" , XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3070 | { "bnulr-" , XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3071 | { "bnulr+" , XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3072 | { "bnulr+" , XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3073 | { "bnulrl" , XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3074 | { "bnulrl-" , XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3075 | { "bnulrl-" , XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3076 | { "bnulrl+" , XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3077 | { "bnulrl+" , XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3078 | { "btlr" , XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, { BI } }, |
3079 | { "btlr-" , XLO(19,BOT,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, |
3080 | { "btlr-" , XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4, { BI } }, |
3081 | { "btlr+" , XLO(19,BOTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, |
3082 | { "btlr+" , XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4, { BI } }, |
3083 | { "bbtr" , XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, { BI } }, |
3084 | { "btlrl" , XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, { BI } }, |
3085 | { "btlrl-" , XLO(19,BOT,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, |
3086 | { "btlrl-" , XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4, { BI } }, |
3087 | { "btlrl+" , XLO(19,BOTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, |
3088 | { "btlrl+" , XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4, { BI } }, |
3089 | { "bbtrl" , XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, { BI } }, |
3090 | { "bflr" , XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, { BI } }, |
3091 | { "bflr-" , XLO(19,BOF,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, |
3092 | { "bflr-" , XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4, { BI } }, |
3093 | { "bflr+" , XLO(19,BOFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, |
3094 | { "bflr+" , XLO(19,BOFP4,16,0), XLBOBB_MASK, POWER4, { BI } }, |
3095 | { "bbfr" , XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, { BI } }, |
3096 | { "bflrl" , XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, { BI } }, |
3097 | { "bflrl-" , XLO(19,BOF,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, |
3098 | { "bflrl-" , XLO(19,BOFM4,16,1), XLBOBB_MASK, POWER4, { BI } }, |
3099 | { "bflrl+" , XLO(19,BOFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, |
3100 | { "bflrl+" , XLO(19,BOFP4,16,1), XLBOBB_MASK, POWER4, { BI } }, |
3101 | { "bbfrl" , XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, { BI } }, |
3102 | { "bdnztlr" , XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, { BI } }, |
3103 | { "bdnztlr-" ,XLO(19,BODNZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, |
3104 | { "bdnztlr+" ,XLO(19,BODNZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, |
3105 | { "bdnztlrl" ,XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, { BI } }, |
3106 | { "bdnztlrl-" ,XLO(19,BODNZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, |
3107 | { "bdnztlrl+" ,XLO(19,BODNZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, |
3108 | { "bdnzflr" , XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, { BI } }, |
3109 | { "bdnzflr-" ,XLO(19,BODNZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, |
3110 | { "bdnzflr+" ,XLO(19,BODNZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, |
3111 | { "bdnzflrl" ,XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, { BI } }, |
3112 | { "bdnzflrl-" ,XLO(19,BODNZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, |
3113 | { "bdnzflrl+" ,XLO(19,BODNZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, |
3114 | { "bdztlr" , XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, { BI } }, |
3115 | { "bdztlr-" , XLO(19,BODZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, |
3116 | { "bdztlr+" , XLO(19,BODZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, |
3117 | { "bdztlrl" , XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, { BI } }, |
3118 | { "bdztlrl-" ,XLO(19,BODZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, |
3119 | { "bdztlrl+" ,XLO(19,BODZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, |
3120 | { "bdzflr" , XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, { BI } }, |
3121 | { "bdzflr-" , XLO(19,BODZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, |
3122 | { "bdzflr+" , XLO(19,BODZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, |
3123 | { "bdzflrl" , XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, { BI } }, |
3124 | { "bdzflrl-" ,XLO(19,BODZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, |
3125 | { "bdzflrl+" ,XLO(19,BODZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, |
3126 | { "bclr+" , XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } }, |
3127 | { "bclrl+" , XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } }, |
3128 | { "bclr-" , XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } }, |
3129 | { "bclrl-" , XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } }, |
3130 | { "bclr" , XLLK(19,16,0), XLBH_MASK, PPCCOM, { BO, BI, BH } }, |
3131 | { "bclrl" , XLLK(19,16,1), XLBH_MASK, PPCCOM, { BO, BI, BH } }, |
3132 | { "bcr" , XLLK(19,16,0), XLBB_MASK, PWRCOM, { BO, BI } }, |
3133 | { "bcrl" , XLLK(19,16,1), XLBB_MASK, PWRCOM, { BO, BI } }, |
3134 | { "bclre" , XLLK(19,17,0), XLBB_MASK, BOOKE64, { BO, BI } }, |
3135 | { "bclrel" , XLLK(19,17,1), XLBB_MASK, BOOKE64, { BO, BI } }, |
3136 | |
3137 | { "rfid" , XL(19,18), 0xffffffff, PPC64, { 0 } }, |
3138 | |
3139 | { "crnot" , XL(19,33), XL_MASK, PPCCOM, { BT, BA, BBA } }, |
3140 | { "crnor" , XL(19,33), XL_MASK, COM, { BT, BA, BB } }, |
3141 | { "rfmci" , X(19,38), 0xffffffff, PPCRFMCI, { 0 } }, |
3142 | |
3143 | { "rfi" , XL(19,50), 0xffffffff, COM, { 0 } }, |
3144 | { "rfci" , XL(19,51), 0xffffffff, PPC403 | BOOKE, { 0 } }, |
3145 | |
3146 | { "rfsvc" , XL(19,82), 0xffffffff, POWER, { 0 } }, |
3147 | |
3148 | { "crandc" , XL(19,129), XL_MASK, COM, { BT, BA, BB } }, |
3149 | |
3150 | { "isync" , XL(19,150), 0xffffffff, PPCCOM, { 0 } }, |
3151 | { "ics" , XL(19,150), 0xffffffff, PWRCOM, { 0 } }, |
3152 | |
3153 | { "crclr" , XL(19,193), XL_MASK, PPCCOM, { BT, BAT, BBA } }, |
3154 | { "crxor" , XL(19,193), XL_MASK, COM, { BT, BA, BB } }, |
3155 | |
3156 | { "crnand" , XL(19,225), XL_MASK, COM, { BT, BA, BB } }, |
3157 | |
3158 | { "crand" , XL(19,257), XL_MASK, COM, { BT, BA, BB } }, |
3159 | |
3160 | { "hrfid" , XL(19,274), 0xffffffff, POWER5 | CELL, { 0 } }, |
3161 | |
3162 | { "crset" , XL(19,289), XL_MASK, PPCCOM, { BT, BAT, BBA } }, |
3163 | { "creqv" , XL(19,289), XL_MASK, COM, { BT, BA, BB } }, |
3164 | |
3165 | { "doze" , XL(19,402), 0xffffffff, POWER6, { 0 } }, |
3166 | |
3167 | { "crorc" , XL(19,417), XL_MASK, COM, { BT, BA, BB } }, |
3168 | |
3169 | { "nap" , XL(19,434), 0xffffffff, POWER6, { 0 } }, |
3170 | |
3171 | { "crmove" , XL(19,449), XL_MASK, PPCCOM, { BT, BA, BBA } }, |
3172 | { "cror" , XL(19,449), XL_MASK, COM, { BT, BA, BB } }, |
3173 | |
3174 | { "sleep" , XL(19,466), 0xffffffff, POWER6, { 0 } }, |
3175 | { "rvwinkle" , XL(19,498), 0xffffffff, POWER6, { 0 } }, |
3176 | |
3177 | { "bctr" , XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, { 0 } }, |
3178 | { "bctrl" , XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, { 0 } }, |
3179 | { "bltctr" , XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3180 | { "bltctr-" , XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3181 | { "bltctr-" , XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3182 | { "bltctr+" , XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3183 | { "bltctr+" , XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3184 | { "bltctrl" , XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3185 | { "bltctrl-" ,XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3186 | { "bltctrl-" ,XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3187 | { "bltctrl+" ,XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3188 | { "bltctrl+" ,XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3189 | { "bgtctr" , XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3190 | { "bgtctr-" , XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3191 | { "bgtctr-" , XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3192 | { "bgtctr+" , XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3193 | { "bgtctr+" , XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3194 | { "bgtctrl" , XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3195 | { "bgtctrl-" ,XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3196 | { "bgtctrl-" ,XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3197 | { "bgtctrl+" ,XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3198 | { "bgtctrl+" ,XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3199 | { "beqctr" , XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3200 | { "beqctr-" , XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3201 | { "beqctr-" , XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3202 | { "beqctr+" , XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3203 | { "beqctr+" , XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3204 | { "beqctrl" , XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3205 | { "beqctrl-" ,XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3206 | { "beqctrl-" ,XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3207 | { "beqctrl+" ,XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3208 | { "beqctrl+" ,XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3209 | { "bsoctr" , XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3210 | { "bsoctr-" , XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3211 | { "bsoctr-" , XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3212 | { "bsoctr+" , XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3213 | { "bsoctr+" , XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3214 | { "bsoctrl" , XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3215 | { "bsoctrl-" ,XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3216 | { "bsoctrl-" ,XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3217 | { "bsoctrl+" ,XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3218 | { "bsoctrl+" ,XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3219 | { "bunctr" , XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3220 | { "bunctr-" , XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3221 | { "bunctr-" , XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3222 | { "bunctr+" , XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3223 | { "bunctr+" , XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3224 | { "bunctrl" , XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3225 | { "bunctrl-" ,XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3226 | { "bunctrl-" ,XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3227 | { "bunctrl+" ,XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3228 | { "bunctrl+" ,XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3229 | { "bgectr" , XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3230 | { "bgectr-" , XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3231 | { "bgectr-" , XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3232 | { "bgectr+" , XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3233 | { "bgectr+" , XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3234 | { "bgectrl" , XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3235 | { "bgectrl-" ,XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3236 | { "bgectrl-" ,XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3237 | { "bgectrl+" ,XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3238 | { "bgectrl+" ,XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3239 | { "bnlctr" , XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3240 | { "bnlctr-" , XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3241 | { "bnlctr-" , XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3242 | { "bnlctr+" , XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3243 | { "bnlctr+" , XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3244 | { "bnlctrl" , XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3245 | { "bnlctrl-" ,XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3246 | { "bnlctrl-" ,XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3247 | { "bnlctrl+" ,XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3248 | { "bnlctrl+" ,XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3249 | { "blectr" , XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3250 | { "blectr-" , XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3251 | { "blectr-" , XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3252 | { "blectr+" , XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3253 | { "blectr+" , XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3254 | { "blectrl" , XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3255 | { "blectrl-" ,XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3256 | { "blectrl-" ,XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3257 | { "blectrl+" ,XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3258 | { "blectrl+" ,XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3259 | { "bngctr" , XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3260 | { "bngctr-" , XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3261 | { "bngctr-" , XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3262 | { "bngctr+" , XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3263 | { "bngctr+" , XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3264 | { "bngctrl" , XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3265 | { "bngctrl-" ,XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3266 | { "bngctrl-" ,XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3267 | { "bngctrl+" ,XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3268 | { "bngctrl+" ,XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3269 | { "bnectr" , XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3270 | { "bnectr-" , XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3271 | { "bnectr-" , XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3272 | { "bnectr+" , XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3273 | { "bnectr+" , XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3274 | { "bnectrl" , XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3275 | { "bnectrl-" ,XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3276 | { "bnectrl-" ,XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3277 | { "bnectrl+" ,XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3278 | { "bnectrl+" ,XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3279 | { "bnsctr" , XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3280 | { "bnsctr-" , XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3281 | { "bnsctr-" , XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3282 | { "bnsctr+" , XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3283 | { "bnsctr+" , XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3284 | { "bnsctrl" , XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3285 | { "bnsctrl-" ,XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3286 | { "bnsctrl-" ,XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3287 | { "bnsctrl+" ,XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3288 | { "bnsctrl+" ,XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3289 | { "bnuctr" , XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3290 | { "bnuctr-" , XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3291 | { "bnuctr-" , XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3292 | { "bnuctr+" , XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3293 | { "bnuctr+" , XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3294 | { "bnuctrl" , XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3295 | { "bnuctrl-" ,XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3296 | { "bnuctrl-" ,XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3297 | { "bnuctrl+" ,XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3298 | { "bnuctrl+" ,XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3299 | { "btctr" , XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, { BI } }, |
3300 | { "btctr-" , XLO(19,BOT,528,0), XLBOBB_MASK, NOPOWER4, { BI } }, |
3301 | { "btctr-" , XLO(19,BOTM4,528,0), XLBOBB_MASK, POWER4, { BI } }, |
3302 | { "btctr+" , XLO(19,BOTP,528,0), XLBOBB_MASK, NOPOWER4, { BI } }, |
3303 | { "btctr+" , XLO(19,BOTP4,528,0), XLBOBB_MASK, POWER4, { BI } }, |
3304 | { "btctrl" , XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, { BI } }, |
3305 | { "btctrl-" , XLO(19,BOT,528,1), XLBOBB_MASK, NOPOWER4, { BI } }, |
3306 | { "btctrl-" , XLO(19,BOTM4,528,1), XLBOBB_MASK, POWER4, { BI } }, |
3307 | { "btctrl+" , XLO(19,BOTP,528,1), XLBOBB_MASK, NOPOWER4, { BI } }, |
3308 | { "btctrl+" , XLO(19,BOTP4,528,1), XLBOBB_MASK, POWER4, { BI } }, |
3309 | { "bfctr" , XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, { BI } }, |
3310 | { "bfctr-" , XLO(19,BOF,528,0), XLBOBB_MASK, NOPOWER4, { BI } }, |
3311 | { "bfctr-" , XLO(19,BOFM4,528,0), XLBOBB_MASK, POWER4, { BI } }, |
3312 | { "bfctr+" , XLO(19,BOFP,528,0), XLBOBB_MASK, NOPOWER4, { BI } }, |
3313 | { "bfctr+" , XLO(19,BOFP4,528,0), XLBOBB_MASK, POWER4, { BI } }, |
3314 | { "bfctrl" , XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, { BI } }, |
3315 | { "bfctrl-" , XLO(19,BOF,528,1), XLBOBB_MASK, NOPOWER4, { BI } }, |
3316 | { "bfctrl-" , XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, { BI } }, |
3317 | { "bfctrl+" , XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, { BI } }, |
3318 | { "bfctrl+" , XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, { BI } }, |
3319 | { "bcctr-" , XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } }, |
3320 | { "bcctr+" , XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } }, |
3321 | { "bcctrl-" , XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } }, |
3322 | { "bcctrl+" , XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } }, |
3323 | { "bcctr" , XLLK(19,528,0), XLBH_MASK, PPCCOM, { BO, BI, BH } }, |
3324 | { "bcctrl" , XLLK(19,528,1), XLBH_MASK, PPCCOM, { BO, BI, BH } }, |
3325 | { "bcc" , XLLK(19,528,0), XLBB_MASK, PWRCOM, { BO, BI } }, |
3326 | { "bccl" , XLLK(19,528,1), XLBB_MASK, PWRCOM, { BO, BI } }, |
3327 | { "bcctre" , XLLK(19,529,0), XLBB_MASK, BOOKE64, { BO, BI } }, |
3328 | { "bcctrel" , XLLK(19,529,1), XLBB_MASK, BOOKE64, { BO, BI } }, |
3329 | |
3330 | { "rlwimi" , M(20,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } }, |
3331 | { "rlimi" , M(20,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } }, |
3332 | |
3333 | { "rlwimi." , M(20,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } }, |
3334 | { "rlimi." , M(20,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } }, |
3335 | |
3336 | { "rotlwi" , MME(21,31,0), MMBME_MASK, PPCCOM, { RA, RS, SH } }, |
3337 | { "clrlwi" , MME(21,31,0), MSHME_MASK, PPCCOM, { RA, RS, MB } }, |
3338 | { "rlwinm" , M(21,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } }, |
3339 | { "rlinm" , M(21,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } }, |
3340 | { "rotlwi." , MME(21,31,1), MMBME_MASK, PPCCOM, { RA,RS,SH } }, |
3341 | { "clrlwi." , MME(21,31,1), MSHME_MASK, PPCCOM, { RA, RS, MB } }, |
3342 | { "rlwinm." , M(21,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } }, |
3343 | { "rlinm." , M(21,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } }, |
3344 | |
3345 | { "rlmi" , M(22,0), M_MASK, M601, { RA,RS,RB,MBE,ME } }, |
3346 | { "rlmi." , M(22,1), M_MASK, M601, { RA,RS,RB,MBE,ME } }, |
3347 | |
3348 | { "be" , B(22,0,0), B_MASK, BOOKE64, { LI } }, |
3349 | { "bel" , B(22,0,1), B_MASK, BOOKE64, { LI } }, |
3350 | { "bea" , B(22,1,0), B_MASK, BOOKE64, { LIA } }, |
3351 | { "bela" , B(22,1,1), B_MASK, BOOKE64, { LIA } }, |
3352 | |
3353 | { "rotlw" , MME(23,31,0), MMBME_MASK, PPCCOM, { RA, RS, RB } }, |
3354 | { "rlwnm" , M(23,0), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } }, |
3355 | { "rlnm" , M(23,0), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } }, |
3356 | { "rotlw." , MME(23,31,1), MMBME_MASK, PPCCOM, { RA, RS, RB } }, |
3357 | { "rlwnm." , M(23,1), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } }, |
3358 | { "rlnm." , M(23,1), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } }, |
3359 | |
3360 | { "nop" , OP(24), 0xffffffff, PPCCOM, { 0 } }, |
3361 | { "ori" , OP(24), OP_MASK, PPCCOM, { RA, RS, UI } }, |
3362 | { "oril" , OP(24), OP_MASK, PWRCOM, { RA, RS, UI } }, |
3363 | |
3364 | { "oris" , OP(25), OP_MASK, PPCCOM, { RA, RS, UI } }, |
3365 | { "oriu" , OP(25), OP_MASK, PWRCOM, { RA, RS, UI } }, |
3366 | |
3367 | { "xori" , OP(26), OP_MASK, PPCCOM, { RA, RS, UI } }, |
3368 | { "xoril" , OP(26), OP_MASK, PWRCOM, { RA, RS, UI } }, |
3369 | |
3370 | { "xoris" , OP(27), OP_MASK, PPCCOM, { RA, RS, UI } }, |
3371 | { "xoriu" , OP(27), OP_MASK, PWRCOM, { RA, RS, UI } }, |
3372 | |
3373 | { "andi." , OP(28), OP_MASK, PPCCOM, { RA, RS, UI } }, |
3374 | { "andil." , OP(28), OP_MASK, PWRCOM, { RA, RS, UI } }, |
3375 | |
3376 | { "andis." , OP(29), OP_MASK, PPCCOM, { RA, RS, UI } }, |
3377 | { "andiu." , OP(29), OP_MASK, PWRCOM, { RA, RS, UI } }, |
3378 | |
3379 | { "rotldi" , MD(30,0,0), MDMB_MASK, PPC64, { RA, RS, SH6 } }, |
3380 | { "clrldi" , MD(30,0,0), MDSH_MASK, PPC64, { RA, RS, MB6 } }, |
3381 | { "rldicl" , MD(30,0,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, |
3382 | { "rotldi." , MD(30,0,1), MDMB_MASK, PPC64, { RA, RS, SH6 } }, |
3383 | { "clrldi." , MD(30,0,1), MDSH_MASK, PPC64, { RA, RS, MB6 } }, |
3384 | { "rldicl." , MD(30,0,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, |
3385 | |
3386 | { "rldicr" , MD(30,1,0), MD_MASK, PPC64, { RA, RS, SH6, ME6 } }, |
3387 | { "rldicr." , MD(30,1,1), MD_MASK, PPC64, { RA, RS, SH6, ME6 } }, |
3388 | |
3389 | { "rldic" , MD(30,2,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, |
3390 | { "rldic." , MD(30,2,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, |
3391 | |
3392 | { "rldimi" , MD(30,3,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, |
3393 | { "rldimi." , MD(30,3,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, |
3394 | |
3395 | { "rotld" , MDS(30,8,0), MDSMB_MASK, PPC64, { RA, RS, RB } }, |
3396 | { "rldcl" , MDS(30,8,0), MDS_MASK, PPC64, { RA, RS, RB, MB6 } }, |
3397 | { "rotld." , MDS(30,8,1), MDSMB_MASK, PPC64, { RA, RS, RB } }, |
3398 | { "rldcl." , MDS(30,8,1), MDS_MASK, PPC64, { RA, RS, RB, MB6 } }, |
3399 | |
3400 | { "rldcr" , MDS(30,9,0), MDS_MASK, PPC64, { RA, RS, RB, ME6 } }, |
3401 | { "rldcr." , MDS(30,9,1), MDS_MASK, PPC64, { RA, RS, RB, ME6 } }, |
3402 | |
3403 | { "cmpw" , XOPL(31,0,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } }, |
3404 | { "cmpd" , XOPL(31,0,1), XCMPL_MASK, PPC64, { OBF, RA, RB } }, |
3405 | { "cmp" , X(31,0), XCMP_MASK, PPC, { BF, L, RA, RB } }, |
3406 | { "cmp" , X(31,0), XCMPL_MASK, PWRCOM, { BF, RA, RB } }, |
3407 | |
3408 | { "twlgt" , XTO(31,4,TOLGT), XTO_MASK, PPCCOM, { RA, RB } }, |
3409 | { "tlgt" , XTO(31,4,TOLGT), XTO_MASK, PWRCOM, { RA, RB } }, |
3410 | { "twllt" , XTO(31,4,TOLLT), XTO_MASK, PPCCOM, { RA, RB } }, |
3411 | { "tllt" , XTO(31,4,TOLLT), XTO_MASK, PWRCOM, { RA, RB } }, |
3412 | { "tweq" , XTO(31,4,TOEQ), XTO_MASK, PPCCOM, { RA, RB } }, |
3413 | { "teq" , XTO(31,4,TOEQ), XTO_MASK, PWRCOM, { RA, RB } }, |
3414 | { "twlge" , XTO(31,4,TOLGE), XTO_MASK, PPCCOM, { RA, RB } }, |
3415 | { "tlge" , XTO(31,4,TOLGE), XTO_MASK, PWRCOM, { RA, RB } }, |
3416 | { "twlnl" , XTO(31,4,TOLNL), XTO_MASK, PPCCOM, { RA, RB } }, |
3417 | { "tlnl" , XTO(31,4,TOLNL), XTO_MASK, PWRCOM, { RA, RB } }, |
3418 | { "twlle" , XTO(31,4,TOLLE), XTO_MASK, PPCCOM, { RA, RB } }, |
3419 | { "tlle" , XTO(31,4,TOLLE), XTO_MASK, PWRCOM, { RA, RB } }, |
3420 | { "twlng" , XTO(31,4,TOLNG), XTO_MASK, PPCCOM, { RA, RB } }, |
3421 | { "tlng" , XTO(31,4,TOLNG), XTO_MASK, PWRCOM, { RA, RB } }, |
3422 | { "twgt" , XTO(31,4,TOGT), XTO_MASK, PPCCOM, { RA, RB } }, |
3423 | { "tgt" , XTO(31,4,TOGT), XTO_MASK, PWRCOM, { RA, RB } }, |
3424 | { "twge" , XTO(31,4,TOGE), XTO_MASK, PPCCOM, { RA, RB } }, |
3425 | { "tge" , XTO(31,4,TOGE), XTO_MASK, PWRCOM, { RA, RB } }, |
3426 | { "twnl" , XTO(31,4,TONL), XTO_MASK, PPCCOM, { RA, RB } }, |
3427 | { "tnl" , XTO(31,4,TONL), XTO_MASK, PWRCOM, { RA, RB } }, |
3428 | { "twlt" , XTO(31,4,TOLT), XTO_MASK, PPCCOM, { RA, RB } }, |
3429 | { "tlt" , XTO(31,4,TOLT), XTO_MASK, PWRCOM, { RA, RB } }, |
3430 | { "twle" , XTO(31,4,TOLE), XTO_MASK, PPCCOM, { RA, RB } }, |
3431 | { "tle" , XTO(31,4,TOLE), XTO_MASK, PWRCOM, { RA, RB } }, |
3432 | { "twng" , XTO(31,4,TONG), XTO_MASK, PPCCOM, { RA, RB } }, |
3433 | { "tng" , XTO(31,4,TONG), XTO_MASK, PWRCOM, { RA, RB } }, |
3434 | { "twne" , XTO(31,4,TONE), XTO_MASK, PPCCOM, { RA, RB } }, |
3435 | { "tne" , XTO(31,4,TONE), XTO_MASK, PWRCOM, { RA, RB } }, |
3436 | { "trap" , XTO(31,4,TOU), 0xffffffff, PPCCOM, { 0 } }, |
3437 | { "tw" , X(31,4), X_MASK, PPCCOM, { TO, RA, RB } }, |
3438 | { "t" , X(31,4), X_MASK, PWRCOM, { TO, RA, RB } }, |
3439 | |
3440 | { "subfc" , XO(31,8,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, |
3441 | { "sf" , XO(31,8,0,0), XO_MASK, PWRCOM, { RT, RA, RB } }, |
3442 | { "subc" , XO(31,8,0,0), XO_MASK, PPC, { RT, RB, RA } }, |
3443 | { "subfc." , XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RA, RB } }, |
3444 | { "sf." , XO(31,8,0,1), XO_MASK, PWRCOM, { RT, RA, RB } }, |
3445 | { "subc." , XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RB, RA } }, |
3446 | { "subfco" , XO(31,8,1,0), XO_MASK, PPCCOM, { RT, RA, RB } }, |
3447 | { "sfo" , XO(31,8,1,0), XO_MASK, PWRCOM, { RT, RA, RB } }, |
3448 | { "subco" , XO(31,8,1,0), XO_MASK, PPC, { RT, RB, RA } }, |
3449 | { "subfco." , XO(31,8,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, |
3450 | { "sfo." , XO(31,8,1,1), XO_MASK, PWRCOM, { RT, RA, RB } }, |
3451 | { "subco." , XO(31,8,1,1), XO_MASK, PPC, { RT, RB, RA } }, |
3452 | |
3453 | { "mulhdu" , XO(31,9,0,0), XO_MASK, PPC64, { RT, RA, RB } }, |
3454 | { "mulhdu." , XO(31,9,0,1), XO_MASK, PPC64, { RT, RA, RB } }, |
3455 | |
3456 | { "addc" , XO(31,10,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, |
3457 | { "a" , XO(31,10,0,0), XO_MASK, PWRCOM, { RT, RA, RB } }, |
3458 | { "addc." , XO(31,10,0,1), XO_MASK, PPCCOM, { RT, RA, RB } }, |
3459 | { "a." , XO(31,10,0,1), XO_MASK, PWRCOM, { RT, RA, RB } }, |
3460 | { "addco" , XO(31,10,1,0), XO_MASK, PPCCOM, { RT, RA, RB } }, |
3461 | { "ao" , XO(31,10,1,0), XO_MASK, PWRCOM, { RT, RA, RB } }, |
3462 | { "addco." , XO(31,10,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, |
3463 | { "ao." , XO(31,10,1,1), XO_MASK, PWRCOM, { RT, RA, RB } }, |
3464 | |
3465 | { "mulhwu" , XO(31,11,0,0), XO_MASK, PPC, { RT, RA, RB } }, |
3466 | { "mulhwu." , XO(31,11,0,1), XO_MASK, PPC, { RT, RA, RB } }, |
3467 | |
3468 | { "isellt" , X(31,15), X_MASK, PPCISEL, { RT, RA, RB } }, |
3469 | { "iselgt" , X(31,47), X_MASK, PPCISEL, { RT, RA, RB } }, |
3470 | { "iseleq" , X(31,79), X_MASK, PPCISEL, { RT, RA, RB } }, |
3471 | { "isel" , XISEL(31,15), XISEL_MASK, PPCISEL, { RT, RA, RB, CRB } }, |
3472 | |
3473 | { "mfocrf" , XFXM(31,19,0,1), XFXFXM_MASK, COM, { RT, FXM } }, |
3474 | { "mfcr" , X(31,19), XRARB_MASK, NOPOWER4 | COM, { RT } }, |
3475 | { "mfcr" , X(31,19), XFXFXM_MASK, POWER4, { RT, FXM4 } }, |
3476 | |
3477 | { "lwarx" , X(31,20), XEH_MASK, PPC, { RT, RA0, RB, EH } }, |
3478 | |
3479 | { "ldx" , X(31,21), X_MASK, PPC64, { RT, RA0, RB } }, |
3480 | |
3481 | { "icbt" , X(31,22), X_MASK, BOOKE|PPCE300, { CT, RA, RB } }, |
3482 | { "icbt" , X(31,262), XRT_MASK, PPC403, { RA, RB } }, |
3483 | |
3484 | { "lwzx" , X(31,23), X_MASK, PPCCOM, { RT, RA0, RB } }, |
3485 | { "lx" , X(31,23), X_MASK, PWRCOM, { RT, RA, RB } }, |
3486 | |
3487 | { "slw" , XRC(31,24,0), X_MASK, PPCCOM, { RA, RS, RB } }, |
3488 | { "sl" , XRC(31,24,0), X_MASK, PWRCOM, { RA, RS, RB } }, |
3489 | { "slw." , XRC(31,24,1), X_MASK, PPCCOM, { RA, RS, RB } }, |
3490 | { "sl." , XRC(31,24,1), X_MASK, PWRCOM, { RA, RS, RB } }, |
3491 | |
3492 | { "cntlzw" , XRC(31,26,0), XRB_MASK, PPCCOM, { RA, RS } }, |
3493 | { "cntlz" , XRC(31,26,0), XRB_MASK, PWRCOM, { RA, RS } }, |
3494 | { "cntlzw." , XRC(31,26,1), XRB_MASK, PPCCOM, { RA, RS } }, |
3495 | { "cntlz." , XRC(31,26,1), XRB_MASK, PWRCOM, { RA, RS } }, |
3496 | |
3497 | { "sld" , XRC(31,27,0), X_MASK, PPC64, { RA, RS, RB } }, |
3498 | { "sld." , XRC(31,27,1), X_MASK, PPC64, { RA, RS, RB } }, |
3499 | |
3500 | { "and" , XRC(31,28,0), X_MASK, COM, { RA, RS, RB } }, |
3501 | { "and." , XRC(31,28,1), X_MASK, COM, { RA, RS, RB } }, |
3502 | |
3503 | { "maskg" , XRC(31,29,0), X_MASK, M601, { RA, RS, RB } }, |
3504 | { "maskg." , XRC(31,29,1), X_MASK, M601, { RA, RS, RB } }, |
3505 | |
3506 | { "icbte" , X(31,30), X_MASK, BOOKE64, { CT, RA, RB } }, |
3507 | |
3508 | { "lwzxe" , X(31,31), X_MASK, BOOKE64, { RT, RA0, RB } }, |
3509 | |
3510 | { "cmplw" , XOPL(31,32,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } }, |
3511 | { "cmpld" , XOPL(31,32,1), XCMPL_MASK, PPC64, { OBF, RA, RB } }, |
3512 | { "cmpl" , X(31,32), XCMP_MASK, PPC, { BF, L, RA, RB } }, |
3513 | { "cmpl" , X(31,32), XCMPL_MASK, PWRCOM, { BF, RA, RB } }, |
3514 | |
3515 | { "subf" , XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } }, |
3516 | { "sub" , XO(31,40,0,0), XO_MASK, PPC, { RT, RB, RA } }, |
3517 | { "subf." , XO(31,40,0,1), XO_MASK, PPC, { RT, RA, RB } }, |
3518 | { "sub." , XO(31,40,0,1), XO_MASK, PPC, { RT, RB, RA } }, |
3519 | { "subfo" , XO(31,40,1,0), XO_MASK, PPC, { RT, RA, RB } }, |
3520 | { "subo" , XO(31,40,1,0), XO_MASK, PPC, { RT, RB, RA } }, |
3521 | { "subfo." , XO(31,40,1,1), XO_MASK, PPC, { RT, RA, RB } }, |
3522 | { "subo." , XO(31,40,1,1), XO_MASK, PPC, { RT, RB, RA } }, |
3523 | |
3524 | { "ldux" , X(31,53), X_MASK, PPC64, { RT, RAL, RB } }, |
3525 | |
3526 | { "dcbst" , X(31,54), XRT_MASK, PPC, { RA, RB } }, |
3527 | |
3528 | { "lwzux" , X(31,55), X_MASK, PPCCOM, { RT, RAL, RB } }, |
3529 | { "lux" , X(31,55), X_MASK, PWRCOM, { RT, RA, RB } }, |
3530 | |
3531 | { "dcbste" , X(31,62), XRT_MASK, BOOKE64, { RA, RB } }, |
3532 | |
3533 | { "lwzuxe" , X(31,63), X_MASK, BOOKE64, { RT, RAL, RB } }, |
3534 | |
3535 | { "cntlzd" , XRC(31,58,0), XRB_MASK, PPC64, { RA, RS } }, |
3536 | { "cntlzd." , XRC(31,58,1), XRB_MASK, PPC64, { RA, RS } }, |
3537 | |
3538 | { "andc" , XRC(31,60,0), X_MASK, COM, { RA, RS, RB } }, |
3539 | { "andc." , XRC(31,60,1), X_MASK, COM, { RA, RS, RB } }, |
3540 | |
3541 | { "tdlgt" , XTO(31,68,TOLGT), XTO_MASK, PPC64, { RA, RB } }, |
3542 | { "tdllt" , XTO(31,68,TOLLT), XTO_MASK, PPC64, { RA, RB } }, |
3543 | { "tdeq" , XTO(31,68,TOEQ), XTO_MASK, PPC64, { RA, RB } }, |
3544 | { "tdlge" , XTO(31,68,TOLGE), XTO_MASK, PPC64, { RA, RB } }, |
3545 | { "tdlnl" , XTO(31,68,TOLNL), XTO_MASK, PPC64, { RA, RB } }, |
3546 | { "tdlle" , XTO(31,68,TOLLE), XTO_MASK, PPC64, { RA, RB } }, |
3547 | { "tdlng" , XTO(31,68,TOLNG), XTO_MASK, PPC64, { RA, RB } }, |
3548 | { "tdgt" , XTO(31,68,TOGT), XTO_MASK, PPC64, { RA, RB } }, |
3549 | { "tdge" , XTO(31,68,TOGE), XTO_MASK, PPC64, { RA, RB } }, |
3550 | { "tdnl" , XTO(31,68,TONL), XTO_MASK, PPC64, { RA, RB } }, |
3551 | { "tdlt" , XTO(31,68,TOLT), XTO_MASK, PPC64, { RA, RB } }, |
3552 | { "tdle" , XTO(31,68,TOLE), XTO_MASK, PPC64, { RA, RB } }, |
3553 | { "tdng" , XTO(31,68,TONG), XTO_MASK, PPC64, { RA, RB } }, |
3554 | { "tdne" , XTO(31,68,TONE), XTO_MASK, PPC64, { RA, RB } }, |
3555 | { "td" , X(31,68), X_MASK, PPC64, { TO, RA, RB } }, |
3556 | |
3557 | { "mulhd" , XO(31,73,0,0), XO_MASK, PPC64, { RT, RA, RB } }, |
3558 | { "mulhd." , XO(31,73,0,1), XO_MASK, PPC64, { RT, RA, RB } }, |
3559 | |
3560 | { "mulhw" , XO(31,75,0,0), XO_MASK, PPC, { RT, RA, RB } }, |
3561 | { "mulhw." , XO(31,75,0,1), XO_MASK, PPC, { RT, RA, RB } }, |
3562 | |
3563 | { "dlmzb" , XRC(31,78,0), X_MASK, PPC403|PPC440, { RA, RS, RB } }, |
3564 | { "dlmzb." , XRC(31,78,1), X_MASK, PPC403|PPC440, { RA, RS, RB } }, |
3565 | |
3566 | { "mtsrd" , X(31,82), XRB_MASK|(1<<20), PPC64, { SR, RS } }, |
3567 | |
3568 | { "mfmsr" , X(31,83), XRARB_MASK, COM, { RT } }, |
3569 | |
3570 | { "ldarx" , X(31,84), XEH_MASK, PPC64, { RT, RA0, RB, EH } }, |
3571 | |
3572 | { "dcbfl" , XOPL(31,86,1), XRT_MASK, POWER5, { RA, RB } }, |
3573 | { "dcbf" , X(31,86), XLRT_MASK, PPC, { RA, RB, L } }, |
3574 | |
3575 | { "lbzx" , X(31,87), X_MASK, COM, { RT, RA0, RB } }, |
3576 | |
3577 | { "dcbfe" , X(31,94), XRT_MASK, BOOKE64, { RA, RB } }, |
3578 | |
3579 | { "lbzxe" , X(31,95), X_MASK, BOOKE64, { RT, RA0, RB } }, |
3580 | |
3581 | { "neg" , XO(31,104,0,0), XORB_MASK, COM, { RT, RA } }, |
3582 | { "neg." , XO(31,104,0,1), XORB_MASK, COM, { RT, RA } }, |
3583 | { "nego" , XO(31,104,1,0), XORB_MASK, COM, { RT, RA } }, |
3584 | { "nego." , XO(31,104,1,1), XORB_MASK, COM, { RT, RA } }, |
3585 | |
3586 | { "mul" , XO(31,107,0,0), XO_MASK, M601, { RT, RA, RB } }, |
3587 | { "mul." , XO(31,107,0,1), XO_MASK, M601, { RT, RA, RB } }, |
3588 | { "mulo" , XO(31,107,1,0), XO_MASK, M601, { RT, RA, RB } }, |
3589 | { "mulo." , XO(31,107,1,1), XO_MASK, M601, { RT, RA, RB } }, |
3590 | |
3591 | { "mtsrdin" , X(31,114), XRA_MASK, PPC64, { RS, RB } }, |
3592 | |
3593 | { "clf" , X(31,118), XTO_MASK, POWER, { RA, RB } }, |
3594 | |
3595 | { "lbzux" , X(31,119), X_MASK, COM, { RT, RAL, RB } }, |
3596 | |
3597 | { "popcntb" , X(31,122), XRB_MASK, POWER5, { RA, RS } }, |
3598 | { "popcntw" , X(31,378), XRB_MASK, POWER7, { RA, RS } }, |
3599 | { "popcntd" , X(31,506), XRB_MASK, POWER7, { RA, RS } }, |
3600 | |
3601 | { "cnttzw" , XRC(31,538,0), XRB_MASK, POWER9, { RA, RS } }, |
3602 | { "cnttzw." , XRC(31,538,1), XRB_MASK, POWER9, { RA, RS } }, |
3603 | { "cnttzd" , XRC(31,570,0), XRB_MASK, POWER9, { RA, RS } }, |
3604 | { "cnttzd." , XRC(31,570,1), XRB_MASK, POWER9, { RA, RS } }, |
3605 | |
3606 | { "not" , XRC(31,124,0), X_MASK, COM, { RA, RS, RBS } }, |
3607 | { "nor" , XRC(31,124,0), X_MASK, COM, { RA, RS, RB } }, |
3608 | { "not." , XRC(31,124,1), X_MASK, COM, { RA, RS, RBS } }, |
3609 | { "nor." , XRC(31,124,1), X_MASK, COM, { RA, RS, RB } }, |
3610 | |
3611 | { "lwarxe" , X(31,126), X_MASK, BOOKE64, { RT, RA0, RB } }, |
3612 | |
3613 | { "lbzuxe" , X(31,127), X_MASK, BOOKE64, { RT, RAL, RB } }, |
3614 | |
3615 | { "wrtee" , X(31,131), XRARB_MASK, PPC403 | BOOKE, { RS } }, |
3616 | |
3617 | { "dcbtstls" ,X(31,134), X_MASK, PPCCHLK, { CT, RA, RB }}, |
3618 | |
3619 | { "subfe" , XO(31,136,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, |
3620 | { "sfe" , XO(31,136,0,0), XO_MASK, PWRCOM, { RT, RA, RB } }, |
3621 | { "subfe." , XO(31,136,0,1), XO_MASK, PPCCOM, { RT, RA, RB } }, |
3622 | { "sfe." , XO(31,136,0,1), XO_MASK, PWRCOM, { RT, RA, RB } }, |
3623 | { "subfeo" , XO(31,136,1,0), XO_MASK, PPCCOM, { RT, RA, RB } }, |
3624 | { "sfeo" , XO(31,136,1,0), XO_MASK, PWRCOM, { RT, RA, RB } }, |
3625 | { "subfeo." , XO(31,136,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, |
3626 | { "sfeo." , XO(31,136,1,1), XO_MASK, PWRCOM, { RT, RA, RB } }, |
3627 | |
3628 | { "adde" , XO(31,138,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, |
3629 | { "ae" , XO(31,138,0,0), XO_MASK, PWRCOM, { RT, RA, RB } }, |
3630 | { "adde." , XO(31,138,0,1), XO_MASK, PPCCOM, { RT, RA, RB } }, |
3631 | { "ae." , XO(31,138,0,1), XO_MASK, PWRCOM, { RT, RA, RB } }, |
3632 | { "addeo" , XO(31,138,1,0), XO_MASK, PPCCOM, { RT, RA, RB } }, |
3633 | { "aeo" , XO(31,138,1,0), XO_MASK, PWRCOM, { RT, RA, RB } }, |
3634 | { "addeo." , XO(31,138,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, |
3635 | { "aeo." , XO(31,138,1,1), XO_MASK, PWRCOM, { RT, RA, RB } }, |
3636 | |
3637 | { "dcbtstlse" ,X(31,142),X_MASK, PPCCHLK64, { CT, RA, RB }}, |
3638 | |
3639 | { "mtocrf" , XFXM(31,144,0,1), XFXFXM_MASK, COM, { FXM, RS } }, |
3640 | { "mtcr" , XFXM(31,144,0xff,0), XRARB_MASK, COM, { RS }}, |
3641 | { "mtcrf" , X(31,144), XFXFXM_MASK, COM, { FXM, RS } }, |
3642 | |
3643 | { "mtmsr" , X(31,146), XRARB_MASK, COM, { RS } }, |
3644 | |
3645 | { "stdx" , X(31,149), X_MASK, PPC64, { RS, RA0, RB } }, |
3646 | |
3647 | { "stwcx." , XRC(31,150,1), X_MASK, PPC, { RS, RA0, RB } }, |
3648 | |
3649 | { "stwx" , X(31,151), X_MASK, PPCCOM, { RS, RA0, RB } }, |
3650 | { "stx" , X(31,151), X_MASK, PWRCOM, { RS, RA, RB } }, |
3651 | |
3652 | { "stwcxe." , XRC(31,158,1), X_MASK, BOOKE64, { RS, RA0, RB } }, |
3653 | |
3654 | { "stwxe" , X(31,159), X_MASK, BOOKE64, { RS, RA0, RB } }, |
3655 | |
3656 | { "slq" , XRC(31,152,0), X_MASK, M601, { RA, RS, RB } }, |
3657 | { "slq." , XRC(31,152,1), X_MASK, M601, { RA, RS, RB } }, |
3658 | |
3659 | { "sle" , XRC(31,153,0), X_MASK, M601, { RA, RS, RB } }, |
3660 | { "sle." , XRC(31,153,1), X_MASK, M601, { RA, RS, RB } }, |
3661 | |
3662 | { "prtyw" , X(31,154), XRB_MASK, POWER6, { RA, RS } }, |
3663 | |
3664 | { "wrteei" , X(31,163), XE_MASK, PPC403 | BOOKE, { E } }, |
3665 | |
3666 | { "dcbtls" , X(31,166), X_MASK, PPCCHLK, { CT, RA, RB }}, |
3667 | { "dcbtlse" , X(31,174), X_MASK, PPCCHLK64, { CT, RA, RB }}, |
3668 | |
3669 | { "mtmsrd" , X(31,178), XRLARB_MASK, PPC64, { RS, A_L } }, |
3670 | |
3671 | { "stdux" , X(31,181), X_MASK, PPC64, { RS, RAS, RB } }, |
3672 | |
3673 | { "stwux" , X(31,183), X_MASK, PPCCOM, { RS, RAS, RB } }, |
3674 | { "stux" , X(31,183), X_MASK, PWRCOM, { RS, RA0, RB } }, |
3675 | |
3676 | { "sliq" , XRC(31,184,0), X_MASK, M601, { RA, RS, SH } }, |
3677 | { "sliq." , XRC(31,184,1), X_MASK, M601, { RA, RS, SH } }, |
3678 | |
3679 | { "prtyd" , X(31,186), XRB_MASK, POWER6, { RA, RS } }, |
3680 | |
3681 | { "stwuxe" , X(31,191), X_MASK, BOOKE64, { RS, RAS, RB } }, |
3682 | |
3683 | { "subfze" , XO(31,200,0,0), XORB_MASK, PPCCOM, { RT, RA } }, |
3684 | { "sfze" , XO(31,200,0,0), XORB_MASK, PWRCOM, { RT, RA } }, |
3685 | { "subfze." , XO(31,200,0,1), XORB_MASK, PPCCOM, { RT, RA } }, |
3686 | { "sfze." , XO(31,200,0,1), XORB_MASK, PWRCOM, { RT, RA } }, |
3687 | { "subfzeo" , XO(31,200,1,0), XORB_MASK, PPCCOM, { RT, RA } }, |
3688 | { "sfzeo" , XO(31,200,1,0), XORB_MASK, PWRCOM, { RT, RA } }, |
3689 | { "subfzeo." ,XO(31,200,1,1), XORB_MASK, PPCCOM, { RT, RA } }, |
3690 | { "sfzeo." , XO(31,200,1,1), XORB_MASK, PWRCOM, { RT, RA } }, |
3691 | |
3692 | { "addze" , XO(31,202,0,0), XORB_MASK, PPCCOM, { RT, RA } }, |
3693 | { "aze" , XO(31,202,0,0), XORB_MASK, PWRCOM, { RT, RA } }, |
3694 | { "addze." , XO(31,202,0,1), XORB_MASK, PPCCOM, { RT, RA } }, |
3695 | { "aze." , XO(31,202,0,1), XORB_MASK, PWRCOM, { RT, RA } }, |
3696 | { "addzeo" , XO(31,202,1,0), XORB_MASK, PPCCOM, { RT, RA } }, |
3697 | { "azeo" , XO(31,202,1,0), XORB_MASK, PWRCOM, { RT, RA } }, |
3698 | { "addzeo." , XO(31,202,1,1), XORB_MASK, PPCCOM, { RT, RA } }, |
3699 | { "azeo." , XO(31,202,1,1), XORB_MASK, PWRCOM, { RT, RA } }, |
3700 | |
3701 | { "mtsr" , X(31,210), XRB_MASK|(1<<20), COM32, { SR, RS } }, |
3702 | |
3703 | { "stdcx." , XRC(31,214,1), X_MASK, PPC64, { RS, RA0, RB } }, |
3704 | |
3705 | { "stbx" , X(31,215), X_MASK, COM, { RS, RA0, RB } }, |
3706 | |
3707 | { "sllq" , XRC(31,216,0), X_MASK, M601, { RA, RS, RB } }, |
3708 | { "sllq." , XRC(31,216,1), X_MASK, M601, { RA, RS, RB } }, |
3709 | |
3710 | { "sleq" , XRC(31,217,0), X_MASK, M601, { RA, RS, RB } }, |
3711 | { "sleq." , XRC(31,217,1), X_MASK, M601, { RA, RS, RB } }, |
3712 | |
3713 | { "stbxe" , X(31,223), X_MASK, BOOKE64, { RS, RA0, RB } }, |
3714 | |
3715 | { "icblc" , X(31,230), X_MASK, PPCCHLK, { CT, RA, RB }}, |
3716 | |
3717 | { "subfme" , XO(31,232,0,0), XORB_MASK, PPCCOM, { RT, RA } }, |
3718 | { "sfme" , XO(31,232,0,0), XORB_MASK, PWRCOM, { RT, RA } }, |
3719 | { "subfme." , XO(31,232,0,1), XORB_MASK, PPCCOM, { RT, RA } }, |
3720 | { "sfme." , XO(31,232,0,1), XORB_MASK, PWRCOM, { RT, RA } }, |
3721 | { "subfmeo" , XO(31,232,1,0), XORB_MASK, PPCCOM, { RT, RA } }, |
3722 | { "sfmeo" , XO(31,232,1,0), XORB_MASK, PWRCOM, { RT, RA } }, |
3723 | { "subfmeo." ,XO(31,232,1,1), XORB_MASK, PPCCOM, { RT, RA } }, |
3724 | { "sfmeo." , XO(31,232,1,1), XORB_MASK, PWRCOM, { RT, RA } }, |
3725 | |
3726 | { "mulld" , XO(31,233,0,0), XO_MASK, PPC64, { RT, RA, RB } }, |
3727 | { "mulld." , XO(31,233,0,1), XO_MASK, PPC64, { RT, RA, RB } }, |
3728 | { "mulldo" , XO(31,233,1,0), XO_MASK, PPC64, { RT, RA, RB } }, |
3729 | { "mulldo." , XO(31,233,1,1), XO_MASK, PPC64, { RT, RA, RB } }, |
3730 | |
3731 | { "addme" , XO(31,234,0,0), XORB_MASK, PPCCOM, { RT, RA } }, |
3732 | { "ame" , XO(31,234,0,0), XORB_MASK, PWRCOM, { RT, RA } }, |
3733 | { "addme." , XO(31,234,0,1), XORB_MASK, PPCCOM, { RT, RA } }, |
3734 | { "ame." , XO(31,234,0,1), XORB_MASK, PWRCOM, { RT, RA } }, |
3735 | { "addmeo" , XO(31,234,1,0), XORB_MASK, PPCCOM, { RT, RA } }, |
3736 | { "ameo" , XO(31,234,1,0), XORB_MASK, PWRCOM, { RT, RA } }, |
3737 | { "addmeo." , XO(31,234,1,1), XORB_MASK, PPCCOM, { RT, RA } }, |
3738 | { "ameo." , XO(31,234,1,1), XORB_MASK, PWRCOM, { RT, RA } }, |
3739 | |
3740 | { "addex" , XO(31,170,0,0), XO_MASK, POWER9, { RT, RA, RB } }, |
3741 | |
3742 | { "mullw" , XO(31,235,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, |
3743 | { "muls" , XO(31,235,0,0), XO_MASK, PWRCOM, { RT, RA, RB } }, |
3744 | { "mullw." , XO(31,235,0,1), XO_MASK, PPCCOM, { RT, RA, RB } }, |
3745 | { "muls." , XO(31,235,0,1), XO_MASK, PWRCOM, { RT, RA, RB } }, |
3746 | { "mullwo" , XO(31,235,1,0), XO_MASK, PPCCOM, { RT, RA, RB } }, |
3747 | { "mulso" , XO(31,235,1,0), XO_MASK, PWRCOM, { RT, RA, RB } }, |
3748 | { "mullwo." , XO(31,235,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, |
3749 | { "mulso." , XO(31,235,1,1), XO_MASK, PWRCOM, { RT, RA, RB } }, |
3750 | |
3751 | { "icblce" , X(31,238), X_MASK, PPCCHLK64, { CT, RA, RB }}, |
3752 | { "mtsrin" , X(31,242), XRA_MASK, PPC32, { RS, RB } }, |
3753 | { "mtsri" , X(31,242), XRA_MASK, POWER32, { RS, RB } }, |
3754 | |
3755 | { "dcbtst" , X(31,246), X_MASK, PPC, { CT, RA, RB } }, |
3756 | |
3757 | { "stbux" , X(31,247), X_MASK, COM, { RS, RAS, RB } }, |
3758 | |
3759 | { "slliq" , XRC(31,248,0), X_MASK, M601, { RA, RS, SH } }, |
3760 | { "slliq." , XRC(31,248,1), X_MASK, M601, { RA, RS, SH } }, |
3761 | |
3762 | { "dcbtste" , X(31,253), X_MASK, BOOKE64, { CT, RA, RB } }, |
3763 | |
3764 | { "stbuxe" , X(31,255), X_MASK, BOOKE64, { RS, RAS, RB } }, |
3765 | |
3766 | { "mfdcrx" , X(31,259), X_MASK, BOOKE, { RS, RA } }, |
3767 | |
3768 | { "doz" , XO(31,264,0,0), XO_MASK, M601, { RT, RA, RB } }, |
3769 | { "doz." , XO(31,264,0,1), XO_MASK, M601, { RT, RA, RB } }, |
3770 | { "dozo" , XO(31,264,1,0), XO_MASK, M601, { RT, RA, RB } }, |
3771 | { "dozo." , XO(31,264,1,1), XO_MASK, M601, { RT, RA, RB } }, |
3772 | |
3773 | { "add" , XO(31,266,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, |
3774 | { "cax" , XO(31,266,0,0), XO_MASK, PWRCOM, { RT, RA, RB } }, |
3775 | { "add." , XO(31,266,0,1), XO_MASK, PPCCOM, { RT, RA, RB } }, |
3776 | { "cax." , XO(31,266,0,1), XO_MASK, PWRCOM, { RT, RA, RB } }, |
3777 | { "addo" , XO(31,266,1,0), XO_MASK, PPCCOM, { RT, RA, RB } }, |
3778 | { "caxo" , XO(31,266,1,0), XO_MASK, PWRCOM, { RT, RA, RB } }, |
3779 | { "addo." , XO(31,266,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, |
3780 | { "caxo." , XO(31,266,1,1), XO_MASK, PWRCOM, { RT, RA, RB } }, |
3781 | |
3782 | { "tlbiel" , X(31,274), XRTLRA_MASK, POWER4, { RB, L } }, |
3783 | |
3784 | { "mfapidi" , X(31,275), X_MASK, BOOKE, { RT, RA } }, |
3785 | |
3786 | { "lscbx" , XRC(31,277,0), X_MASK, M601, { RT, RA, RB } }, |
3787 | { "lscbx." , XRC(31,277,1), X_MASK, M601, { RT, RA, RB } }, |
3788 | |
3789 | { "dcbt" , X(31,278), X_MASK, PPC, { CT, RA, RB } }, |
3790 | |
3791 | { "lhzx" , X(31,279), X_MASK, COM, { RT, RA0, RB } }, |
3792 | |
3793 | { "eqv" , XRC(31,284,0), X_MASK, COM, { RA, RS, RB } }, |
3794 | { "eqv." , XRC(31,284,1), X_MASK, COM, { RA, RS, RB } }, |
3795 | |
3796 | { "dcbte" , X(31,286), X_MASK, BOOKE64, { CT, RA, RB } }, |
3797 | |
3798 | { "lhzxe" , X(31,287), X_MASK, BOOKE64, { RT, RA0, RB } }, |
3799 | |
3800 | { "tlbie" , X(31,306), XRTLRA_MASK, PPC, { RB, L } }, |
3801 | { "tlbi" , X(31,306), XRT_MASK, POWER, { RA0, RB } }, |
3802 | |
3803 | { "eciwx" , X(31,310), X_MASK, PPC, { RT, RA, RB } }, |
3804 | |
3805 | { "lhzux" , X(31,311), X_MASK, COM, { RT, RAL, RB } }, |
3806 | |
3807 | { "xor" , XRC(31,316,0), X_MASK, COM, { RA, RS, RB } }, |
3808 | { "xor." , XRC(31,316,1), X_MASK, COM, { RA, RS, RB } }, |
3809 | |
3810 | { "lhzuxe" , X(31,319), X_MASK, BOOKE64, { RT, RAL, RB } }, |
3811 | |
3812 | { "mfexisr" , XSPR(31,323,64), XSPR_MASK, PPC403, { RT } }, |
3813 | { "mfexier" , XSPR(31,323,66), XSPR_MASK, PPC403, { RT } }, |
3814 | { "mfbr0" , XSPR(31,323,128), XSPR_MASK, PPC403, { RT } }, |
3815 | { "mfbr1" , XSPR(31,323,129), XSPR_MASK, PPC403, { RT } }, |
3816 | { "mfbr2" , XSPR(31,323,130), XSPR_MASK, PPC403, { RT } }, |
3817 | { "mfbr3" , XSPR(31,323,131), XSPR_MASK, PPC403, { RT } }, |
3818 | { "mfbr4" , XSPR(31,323,132), XSPR_MASK, PPC403, { RT } }, |
3819 | { "mfbr5" , XSPR(31,323,133), XSPR_MASK, PPC403, { RT } }, |
3820 | { "mfbr6" , XSPR(31,323,134), XSPR_MASK, PPC403, { RT } }, |
3821 | { "mfbr7" , XSPR(31,323,135), XSPR_MASK, PPC403, { RT } }, |
3822 | { "mfbear" , XSPR(31,323,144), XSPR_MASK, PPC403, { RT } }, |
3823 | { "mfbesr" , XSPR(31,323,145), XSPR_MASK, PPC403, { RT } }, |
3824 | { "mfiocr" , XSPR(31,323,160), XSPR_MASK, PPC403, { RT } }, |
3825 | { "mfdmacr0" , XSPR(31,323,192), XSPR_MASK, PPC403, { RT } }, |
3826 | { "mfdmact0" , XSPR(31,323,193), XSPR_MASK, PPC403, { RT } }, |
3827 | { "mfdmada0" , XSPR(31,323,194), XSPR_MASK, PPC403, { RT } }, |
3828 | { "mfdmasa0" , XSPR(31,323,195), XSPR_MASK, PPC403, { RT } }, |
3829 | { "mfdmacc0" , XSPR(31,323,196), XSPR_MASK, PPC403, { RT } }, |
3830 | { "mfdmacr1" , XSPR(31,323,200), XSPR_MASK, PPC403, { RT } }, |
3831 | { "mfdmact1" , XSPR(31,323,201), XSPR_MASK, PPC403, { RT } }, |
3832 | { "mfdmada1" , XSPR(31,323,202), XSPR_MASK, PPC403, { RT } }, |
3833 | { "mfdmasa1" , XSPR(31,323,203), XSPR_MASK, PPC403, { RT } }, |
3834 | { "mfdmacc1" , XSPR(31,323,204), XSPR_MASK, PPC403, { RT } }, |
3835 | { "mfdmacr2" , XSPR(31,323,208), XSPR_MASK, PPC403, { RT } }, |
3836 | { "mfdmact2" , XSPR(31,323,209), XSPR_MASK, PPC403, { RT } }, |
3837 | { "mfdmada2" , XSPR(31,323,210), XSPR_MASK, PPC403, { RT } }, |
3838 | { "mfdmasa2" , XSPR(31,323,211), XSPR_MASK, PPC403, { RT } }, |
3839 | { "mfdmacc2" , XSPR(31,323,212), XSPR_MASK, PPC403, { RT } }, |
3840 | { "mfdmacr3" , XSPR(31,323,216), XSPR_MASK, PPC403, { RT } }, |
3841 | { "mfdmact3" , XSPR(31,323,217), XSPR_MASK, PPC403, { RT } }, |
3842 | { "mfdmada3" , XSPR(31,323,218), XSPR_MASK, PPC403, { RT } }, |
3843 | { "mfdmasa3" , XSPR(31,323,219), XSPR_MASK, PPC403, { RT } }, |
3844 | { "mfdmacc3" , XSPR(31,323,220), XSPR_MASK, PPC403, { RT } }, |
3845 | { "mfdmasr" , XSPR(31,323,224), XSPR_MASK, PPC403, { RT } }, |
3846 | { "mfdcr" , X(31,323), X_MASK, PPC403 | BOOKE, { RT, SPR } }, |
3847 | |
3848 | { "div" , XO(31,331,0,0), XO_MASK, M601, { RT, RA, RB } }, |
3849 | { "div." , XO(31,331,0,1), XO_MASK, M601, { RT, RA, RB } }, |
3850 | { "divo" , XO(31,331,1,0), XO_MASK, M601, { RT, RA, RB } }, |
3851 | { "divo." , XO(31,331,1,1), XO_MASK, M601, { RT, RA, RB } }, |
3852 | |
3853 | { "mfpmr" , X(31,334), X_MASK, PPCPMR, { RT, PMR }}, |
3854 | |
3855 | { "mfmq" , XSPR(31,339,0), XSPR_MASK, M601, { RT } }, |
3856 | { "mfxer" , XSPR(31,339,1), XSPR_MASK, COM, { RT } }, |
3857 | { "mfrtcu" , XSPR(31,339,4), XSPR_MASK, COM, { RT } }, |
3858 | { "mfrtcl" , XSPR(31,339,5), XSPR_MASK, COM, { RT } }, |
3859 | { "mfdec" , XSPR(31,339,6), XSPR_MASK, MFDEC1, { RT } }, |
3860 | { "mfdec" , XSPR(31,339,22), XSPR_MASK, MFDEC2, { RT } }, |
3861 | { "mflr" , XSPR(31,339,8), XSPR_MASK, COM, { RT } }, |
3862 | { "mfctr" , XSPR(31,339,9), XSPR_MASK, COM, { RT } }, |
3863 | { "mftid" , XSPR(31,339,17), XSPR_MASK, POWER, { RT } }, |
3864 | { "mfdsisr" , XSPR(31,339,18), XSPR_MASK, COM, { RT } }, |
3865 | { "mfdar" , XSPR(31,339,19), XSPR_MASK, COM, { RT } }, |
3866 | { "mfsdr0" , XSPR(31,339,24), XSPR_MASK, POWER, { RT } }, |
3867 | { "mfsdr1" , XSPR(31,339,25), XSPR_MASK, COM, { RT } }, |
3868 | { "mfsrr0" , XSPR(31,339,26), XSPR_MASK, COM, { RT } }, |
3869 | { "mfsrr1" , XSPR(31,339,27), XSPR_MASK, COM, { RT } }, |
3870 | { "mfcfar" , XSPR(31,339,28), XSPR_MASK, POWER6, { RT } }, |
3871 | { "mfpid" , XSPR(31,339,48), XSPR_MASK, BOOKE, { RT } }, |
3872 | { "mfpid" , XSPR(31,339,945), XSPR_MASK, PPC403, { RT } }, |
3873 | { "mfcsrr0" , XSPR(31,339,58), XSPR_MASK, BOOKE, { RT } }, |
3874 | { "mfcsrr1" , XSPR(31,339,59), XSPR_MASK, BOOKE, { RT } }, |
3875 | { "mfdear" , XSPR(31,339,61), XSPR_MASK, BOOKE, { RT } }, |
3876 | { "mfdear" , XSPR(31,339,981), XSPR_MASK, PPC403, { RT } }, |
3877 | { "mfesr" , XSPR(31,339,62), XSPR_MASK, BOOKE, { RT } }, |
3878 | { "mfesr" , XSPR(31,339,980), XSPR_MASK, PPC403, { RT } }, |
3879 | { "mfivpr" , XSPR(31,339,63), XSPR_MASK, BOOKE, { RT } }, |
3880 | { "mfcmpa" , XSPR(31,339,144), XSPR_MASK, PPC860, { RT } }, |
3881 | { "mfcmpb" , XSPR(31,339,145), XSPR_MASK, PPC860, { RT } }, |
3882 | { "mfcmpc" , XSPR(31,339,146), XSPR_MASK, PPC860, { RT } }, |
3883 | { "mfcmpd" , XSPR(31,339,147), XSPR_MASK, PPC860, { RT } }, |
3884 | { "mficr" , XSPR(31,339,148), XSPR_MASK, PPC860, { RT } }, |
3885 | { "mfder" , XSPR(31,339,149), XSPR_MASK, PPC860, { RT } }, |
3886 | { "mfcounta" , XSPR(31,339,150), XSPR_MASK, PPC860, { RT } }, |
3887 | { "mfcountb" , XSPR(31,339,151), XSPR_MASK, PPC860, { RT } }, |
3888 | { "mfcmpe" , XSPR(31,339,152), XSPR_MASK, PPC860, { RT } }, |
3889 | { "mfcmpf" , XSPR(31,339,153), XSPR_MASK, PPC860, { RT } }, |
3890 | { "mfcmpg" , XSPR(31,339,154), XSPR_MASK, PPC860, { RT } }, |
3891 | { "mfcmph" , XSPR(31,339,155), XSPR_MASK, PPC860, { RT } }, |
3892 | { "mflctrl1" , XSPR(31,339,156), XSPR_MASK, PPC860, { RT } }, |
3893 | { "mflctrl2" , XSPR(31,339,157), XSPR_MASK, PPC860, { RT } }, |
3894 | { "mfictrl" , XSPR(31,339,158), XSPR_MASK, PPC860, { RT } }, |
3895 | { "mfbar" , XSPR(31,339,159), XSPR_MASK, PPC860, { RT } }, |
3896 | { "mfvrsave" , XSPR(31,339,256), XSPR_MASK, PPCVEC, { RT } }, |
3897 | { "mfusprg0" , XSPR(31,339,256), XSPR_MASK, BOOKE, { RT } }, |
3898 | { "mftb" , X(31,371), X_MASK, CLASSIC, { RT, TBR } }, |
3899 | { "mftb" , XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } }, |
3900 | { "mftbl" , XSPR(31,371,268), XSPR_MASK, CLASSIC, { RT } }, |
3901 | { "mftbl" , XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } }, |
3902 | { "mftbu" , XSPR(31,371,269), XSPR_MASK, CLASSIC, { RT } }, |
3903 | { "mftbu" , XSPR(31,339,269), XSPR_MASK, BOOKE, { RT } }, |
3904 | { "mfsprg" , XSPR(31,339,256), XSPRG_MASK, PPC, { RT, SPRG } }, |
3905 | { "mfsprg0" , XSPR(31,339,272), XSPR_MASK, PPC, { RT } }, |
3906 | { "mfsprg1" , XSPR(31,339,273), XSPR_MASK, PPC, { RT } }, |
3907 | { "mfsprg2" , XSPR(31,339,274), XSPR_MASK, PPC, { RT } }, |
3908 | { "mfsprg3" , XSPR(31,339,275), XSPR_MASK, PPC, { RT } }, |
3909 | { "mfsprg4" , XSPR(31,339,260), XSPR_MASK, PPC405 | BOOKE, { RT } }, |
3910 | { "mfsprg5" , XSPR(31,339,261), XSPR_MASK, PPC405 | BOOKE, { RT } }, |
3911 | { "mfsprg6" , XSPR(31,339,262), XSPR_MASK, PPC405 | BOOKE, { RT } }, |
3912 | { "mfsprg7" , XSPR(31,339,263), XSPR_MASK, PPC405 | BOOKE, { RT } }, |
3913 | { "mfasr" , XSPR(31,339,280), XSPR_MASK, PPC64, { RT } }, |
3914 | { "mfear" , XSPR(31,339,282), XSPR_MASK, PPC, { RT } }, |
3915 | { "mfpir" , XSPR(31,339,286), XSPR_MASK, BOOKE, { RT } }, |
3916 | { "mfpvr" , XSPR(31,339,287), XSPR_MASK, PPC, { RT } }, |
3917 | { "mfdbsr" , XSPR(31,339,304), XSPR_MASK, BOOKE, { RT } }, |
3918 | { "mfdbsr" , XSPR(31,339,1008), XSPR_MASK, PPC403, { RT } }, |
3919 | { "mfdbcr0" , XSPR(31,339,308), XSPR_MASK, BOOKE, { RT } }, |
3920 | { "mfdbcr0" , XSPR(31,339,1010), XSPR_MASK, PPC405, { RT } }, |
3921 | { "mfdbcr1" , XSPR(31,339,309), XSPR_MASK, BOOKE, { RT } }, |
3922 | { "mfdbcr1" , XSPR(31,339,957), XSPR_MASK, PPC405, { RT } }, |
3923 | { "mfdbcr2" , XSPR(31,339,310), XSPR_MASK, BOOKE, { RT } }, |
3924 | { "mfiac1" , XSPR(31,339,312), XSPR_MASK, BOOKE, { RT } }, |
3925 | { "mfiac1" , XSPR(31,339,1012), XSPR_MASK, PPC403, { RT } }, |
3926 | { "mfiac2" , XSPR(31,339,313), XSPR_MASK, BOOKE, { RT } }, |
3927 | { "mfiac2" , XSPR(31,339,1013), XSPR_MASK, PPC403, { RT } }, |
3928 | { "mfiac3" , XSPR(31,339,314), XSPR_MASK, BOOKE, { RT } }, |
3929 | { "mfiac3" , XSPR(31,339,948), XSPR_MASK, PPC405, { RT } }, |
3930 | { "mfiac4" , XSPR(31,339,315), XSPR_MASK, BOOKE, { RT } }, |
3931 | { "mfiac4" , XSPR(31,339,949), XSPR_MASK, PPC405, { RT } }, |
3932 | { "mfdac1" , XSPR(31,339,316), XSPR_MASK, BOOKE, { RT } }, |
3933 | { "mfdac1" , XSPR(31,339,1014), XSPR_MASK, PPC403, { RT } }, |
3934 | { "mfdac2" , XSPR(31,339,317), XSPR_MASK, BOOKE, { RT } }, |
3935 | { "mfdac2" , XSPR(31,339,1015), XSPR_MASK, PPC403, { RT } }, |
3936 | { "mfdvc1" , XSPR(31,339,318), XSPR_MASK, BOOKE, { RT } }, |
3937 | { "mfdvc1" , XSPR(31,339,950), XSPR_MASK, PPC405, { RT } }, |
3938 | { "mfdvc2" , XSPR(31,339,319), XSPR_MASK, BOOKE, { RT } }, |
3939 | { "mfdvc2" , XSPR(31,339,951), XSPR_MASK, PPC405, { RT } }, |
3940 | { "mftsr" , XSPR(31,339,336), XSPR_MASK, BOOKE, { RT } }, |
3941 | { "mftsr" , XSPR(31,339,984), XSPR_MASK, PPC403, { RT } }, |
3942 | { "mftcr" , XSPR(31,339,340), XSPR_MASK, BOOKE, { RT } }, |
3943 | { "mftcr" , XSPR(31,339,986), XSPR_MASK, PPC403, { RT } }, |
3944 | { "mfivor0" , XSPR(31,339,400), XSPR_MASK, BOOKE, { RT } }, |
3945 | { "mfivor1" , XSPR(31,339,401), XSPR_MASK, BOOKE, { RT } }, |
3946 | { "mfivor2" , XSPR(31,339,402), XSPR_MASK, BOOKE, { RT } }, |
3947 | { "mfivor3" , XSPR(31,339,403), XSPR_MASK, BOOKE, { RT } }, |
3948 | { "mfivor4" , XSPR(31,339,404), XSPR_MASK, BOOKE, { RT } }, |
3949 | { "mfivor5" , XSPR(31,339,405), XSPR_MASK, BOOKE, { RT } }, |
3950 | { "mfivor6" , XSPR(31,339,406), XSPR_MASK, BOOKE, { RT } }, |
3951 | { "mfivor7" , XSPR(31,339,407), XSPR_MASK, BOOKE, { RT } }, |
3952 | { "mfivor8" , XSPR(31,339,408), XSPR_MASK, BOOKE, { RT } }, |
3953 | { "mfivor9" , XSPR(31,339,409), XSPR_MASK, BOOKE, { RT } }, |
3954 | { "mfivor10" , XSPR(31,339,410), XSPR_MASK, BOOKE, { RT } }, |
3955 | { "mfivor11" , XSPR(31,339,411), XSPR_MASK, BOOKE, { RT } }, |
3956 | { "mfivor12" , XSPR(31,339,412), XSPR_MASK, BOOKE, { RT } }, |
3957 | { "mfivor13" , XSPR(31,339,413), XSPR_MASK, BOOKE, { RT } }, |
3958 | { "mfivor14" , XSPR(31,339,414), XSPR_MASK, BOOKE, { RT } }, |
3959 | { "mfivor15" , XSPR(31,339,415), XSPR_MASK, BOOKE, { RT } }, |
3960 | { "mfspefscr" , XSPR(31,339,512), XSPR_MASK, PPCSPE, { RT } }, |
3961 | { "mfbbear" , XSPR(31,339,513), XSPR_MASK, PPCBRLK, { RT } }, |
3962 | { "mfbbtar" , XSPR(31,339,514), XSPR_MASK, PPCBRLK, { RT } }, |
3963 | { "mfivor32" , XSPR(31,339,528), XSPR_MASK, PPCSPE, { RT } }, |
3964 | { "mfivor33" , XSPR(31,339,529), XSPR_MASK, PPCSPE, { RT } }, |
3965 | { "mfivor34" , XSPR(31,339,530), XSPR_MASK, PPCSPE, { RT } }, |
3966 | { "mfivor35" , XSPR(31,339,531), XSPR_MASK, PPCPMR, { RT } }, |
3967 | { "mfibatu" , XSPR(31,339,528), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, |
3968 | { "mfibatl" , XSPR(31,339,529), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, |
3969 | { "mfdbatu" , XSPR(31,339,536), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, |
3970 | { "mfdbatl" , XSPR(31,339,537), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, |
3971 | { "mfic_cst" , XSPR(31,339,560), XSPR_MASK, PPC860, { RT } }, |
3972 | { "mfic_adr" , XSPR(31,339,561), XSPR_MASK, PPC860, { RT } }, |
3973 | { "mfic_dat" , XSPR(31,339,562), XSPR_MASK, PPC860, { RT } }, |
3974 | { "mfdc_cst" , XSPR(31,339,568), XSPR_MASK, PPC860, { RT } }, |
3975 | { "mfdc_adr" , XSPR(31,339,569), XSPR_MASK, PPC860, { RT } }, |
3976 | { "mfmcsrr0" , XSPR(31,339,570), XSPR_MASK, PPCRFMCI, { RT } }, |
3977 | { "mfdc_dat" , XSPR(31,339,570), XSPR_MASK, PPC860, { RT } }, |
3978 | { "mfmcsrr1" , XSPR(31,339,571), XSPR_MASK, PPCRFMCI, { RT } }, |
3979 | { "mfmcsr" , XSPR(31,339,572), XSPR_MASK, PPCRFMCI, { RT } }, |
3980 | { "mfmcar" , XSPR(31,339,573), XSPR_MASK, PPCRFMCI, { RT } }, |
3981 | { "mfdpdr" , XSPR(31,339,630), XSPR_MASK, PPC860, { RT } }, |
3982 | { "mfdpir" , XSPR(31,339,631), XSPR_MASK, PPC860, { RT } }, |
3983 | { "mfimmr" , XSPR(31,339,638), XSPR_MASK, PPC860, { RT } }, |
3984 | { "mfmi_ctr" , XSPR(31,339,784), XSPR_MASK, PPC860, { RT } }, |
3985 | { "mfmi_ap" , XSPR(31,339,786), XSPR_MASK, PPC860, { RT } }, |
3986 | { "mfmi_epn" , XSPR(31,339,787), XSPR_MASK, PPC860, { RT } }, |
3987 | { "mfmi_twc" , XSPR(31,339,789), XSPR_MASK, PPC860, { RT } }, |
3988 | { "mfmi_rpn" , XSPR(31,339,790), XSPR_MASK, PPC860, { RT } }, |
3989 | { "mfmd_ctr" , XSPR(31,339,792), XSPR_MASK, PPC860, { RT } }, |
3990 | { "mfm_casid" , XSPR(31,339,793), XSPR_MASK, PPC860, { RT } }, |
3991 | { "mfmd_ap" , XSPR(31,339,794), XSPR_MASK, PPC860, { RT } }, |
3992 | { "mfmd_epn" , XSPR(31,339,795), XSPR_MASK, PPC860, { RT } }, |
3993 | { "mfmd_twb" , XSPR(31,339,796), XSPR_MASK, PPC860, { RT } }, |
3994 | { "mfmd_twc" , XSPR(31,339,797), XSPR_MASK, PPC860, { RT } }, |
3995 | { "mfmd_rpn" , XSPR(31,339,798), XSPR_MASK, PPC860, { RT } }, |
3996 | { "mfm_tw" , XSPR(31,339,799), XSPR_MASK, PPC860, { RT } }, |
3997 | { "mfmi_dbcam" , XSPR(31,339,816), XSPR_MASK, PPC860, { RT } }, |
3998 | { "mfmi_dbram0" ,XSPR(31,339,817), XSPR_MASK, PPC860, { RT } }, |
3999 | { "mfmi_dbram1" ,XSPR(31,339,818), XSPR_MASK, PPC860, { RT } }, |
4000 | { "mfmd_dbcam" , XSPR(31,339,824), XSPR_MASK, PPC860, { RT } }, |
4001 | { "mfmd_dbram0" ,XSPR(31,339,825), XSPR_MASK, PPC860, { RT } }, |
4002 | { "mfmd_dbram1" ,XSPR(31,339,826), XSPR_MASK, PPC860, { RT } }, |
4003 | { "mfummcr0" , XSPR(31,339,936), XSPR_MASK, PPC750, { RT } }, |
4004 | { "mfupmc1" , XSPR(31,339,937), XSPR_MASK, PPC750, { RT } }, |
4005 | { "mfupmc2" , XSPR(31,339,938), XSPR_MASK, PPC750, { RT } }, |
4006 | { "mfusia" , XSPR(31,339,939), XSPR_MASK, PPC750, { RT } }, |
4007 | { "mfummcr1" , XSPR(31,339,940), XSPR_MASK, PPC750, { RT } }, |
4008 | { "mfupmc3" , XSPR(31,339,941), XSPR_MASK, PPC750, { RT } }, |
4009 | { "mfupmc4" , XSPR(31,339,942), XSPR_MASK, PPC750, { RT } }, |
4010 | { "mfzpr" , XSPR(31,339,944), XSPR_MASK, PPC403, { RT } }, |
4011 | { "mfccr0" , XSPR(31,339,947), XSPR_MASK, PPC405, { RT } }, |
4012 | { "mfmmcr0" , XSPR(31,339,952), XSPR_MASK, PPC750, { RT } }, |
4013 | { "mfpmc1" , XSPR(31,339,953), XSPR_MASK, PPC750, { RT } }, |
4014 | { "mfsgr" , XSPR(31,339,953), XSPR_MASK, PPC403, { RT } }, |
4015 | { "mfpmc2" , XSPR(31,339,954), XSPR_MASK, PPC750, { RT } }, |
4016 | { "mfdcwr" , XSPR(31,339,954), XSPR_MASK, PPC403, { RT } }, |
4017 | { "mfsia" , XSPR(31,339,955), XSPR_MASK, PPC750, { RT } }, |
4018 | { "mfsler" , XSPR(31,339,955), XSPR_MASK, PPC405, { RT } }, |
4019 | { "mfmmcr1" , XSPR(31,339,956), XSPR_MASK, PPC750, { RT } }, |
4020 | { "mfsu0r" , XSPR(31,339,956), XSPR_MASK, PPC405, { RT } }, |
4021 | { "mfpmc3" , XSPR(31,339,957), XSPR_MASK, PPC750, { RT } }, |
4022 | { "mfpmc4" , XSPR(31,339,958), XSPR_MASK, PPC750, { RT } }, |
4023 | { "mficdbdr" , XSPR(31,339,979), XSPR_MASK, PPC403, { RT } }, |
4024 | { "mfevpr" , XSPR(31,339,982), XSPR_MASK, PPC403, { RT } }, |
4025 | { "mfcdbcr" , XSPR(31,339,983), XSPR_MASK, PPC403, { RT } }, |
4026 | { "mfpit" , XSPR(31,339,987), XSPR_MASK, PPC403, { RT } }, |
4027 | { "mftbhi" , XSPR(31,339,988), XSPR_MASK, PPC403, { RT } }, |
4028 | { "mftblo" , XSPR(31,339,989), XSPR_MASK, PPC403, { RT } }, |
4029 | { "mfsrr2" , XSPR(31,339,990), XSPR_MASK, PPC403, { RT } }, |
4030 | { "mfsrr3" , XSPR(31,339,991), XSPR_MASK, PPC403, { RT } }, |
4031 | { "mfl2cr" , XSPR(31,339,1017), XSPR_MASK, PPC750, { RT } }, |
4032 | { "mfdccr" , XSPR(31,339,1018), XSPR_MASK, PPC403, { RT } }, |
4033 | { "mficcr" , XSPR(31,339,1019), XSPR_MASK, PPC403, { RT } }, |
4034 | { "mfictc" , XSPR(31,339,1019), XSPR_MASK, PPC750, { RT } }, |
4035 | { "mfpbl1" , XSPR(31,339,1020), XSPR_MASK, PPC403, { RT } }, |
4036 | { "mfthrm1" , XSPR(31,339,1020), XSPR_MASK, PPC750, { RT } }, |
4037 | { "mfpbu1" , XSPR(31,339,1021), XSPR_MASK, PPC403, { RT } }, |
4038 | { "mfthrm2" , XSPR(31,339,1021), XSPR_MASK, PPC750, { RT } }, |
4039 | { "mfpbl2" , XSPR(31,339,1022), XSPR_MASK, PPC403, { RT } }, |
4040 | { "mfthrm3" , XSPR(31,339,1022), XSPR_MASK, PPC750, { RT } }, |
4041 | { "mfpbu2" , XSPR(31,339,1023), XSPR_MASK, PPC403, { RT } }, |
4042 | { "mfspr" , X(31,339), X_MASK, COM, { RT, SPR } }, |
4043 | |
4044 | { "lwax" , X(31,341), X_MASK, PPC64, { RT, RA0, RB } }, |
4045 | |
4046 | { "dst" , XDSS(31,342,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } }, |
4047 | { "dstt" , XDSS(31,342,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } }, |
4048 | |
4049 | { "lhax" , X(31,343), X_MASK, COM, { RT, RA0, RB } }, |
4050 | |
4051 | { "lhaxe" , X(31,351), X_MASK, BOOKE64, { RT, RA0, RB } }, |
4052 | |
4053 | { "dstst" , XDSS(31,374,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } }, |
4054 | { "dststt" , XDSS(31,374,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } }, |
4055 | |
4056 | { "dccci" , X(31,454), XRT_MASK, PPC403|PPC440, { RA, RB } }, |
4057 | |
4058 | { "abs" , XO(31,360,0,0), XORB_MASK, M601, { RT, RA } }, |
4059 | { "abs." , XO(31,360,0,1), XORB_MASK, M601, { RT, RA } }, |
4060 | { "abso" , XO(31,360,1,0), XORB_MASK, M601, { RT, RA } }, |
4061 | { "abso." , XO(31,360,1,1), XORB_MASK, M601, { RT, RA } }, |
4062 | |
4063 | { "divs" , XO(31,363,0,0), XO_MASK, M601, { RT, RA, RB } }, |
4064 | { "divs." , XO(31,363,0,1), XO_MASK, M601, { RT, RA, RB } }, |
4065 | { "divso" , XO(31,363,1,0), XO_MASK, M601, { RT, RA, RB } }, |
4066 | { "divso." , XO(31,363,1,1), XO_MASK, M601, { RT, RA, RB } }, |
4067 | |
4068 | { "tlbia" , X(31,370), 0xffffffff, PPC, { 0 } }, |
4069 | |
4070 | { "lwaux" , X(31,373), X_MASK, PPC64, { RT, RAL, RB } }, |
4071 | |
4072 | { "lhaux" , X(31,375), X_MASK, COM, { RT, RAL, RB } }, |
4073 | |
4074 | { "lhauxe" , X(31,383), X_MASK, BOOKE64, { RT, RAL, RB } }, |
4075 | |
4076 | { "mtdcrx" , X(31,387), X_MASK, BOOKE, { RA, RS } }, |
4077 | |
4078 | { "dcblc" , X(31,390), X_MASK, PPCCHLK, { CT, RA, RB }}, |
4079 | |
4080 | { "subfe64" , XO(31,392,0,0), XO_MASK, BOOKE64, { RT, RA, RB } }, |
4081 | { "subfe64o" ,XO(31,392,1,0), XO_MASK, BOOKE64, { RT, RA, RB } }, |
4082 | |
4083 | { "adde64" , XO(31,394,0,0), XO_MASK, BOOKE64, { RT, RA, RB } }, |
4084 | { "adde64o" , XO(31,394,1,0), XO_MASK, BOOKE64, { RT, RA, RB } }, |
4085 | |
4086 | { "dcblce" , X(31,398), X_MASK, PPCCHLK64, { CT, RA, RB }}, |
4087 | |
4088 | { "slbmte" , X(31,402), XRA_MASK, PPC64, { RS, RB } }, |
4089 | |
4090 | { "sthx" , X(31,407), X_MASK, COM, { RS, RA0, RB } }, |
4091 | |
4092 | { "cmpb" , X(31,508), X_MASK, POWER6, { RA, RS, RB } }, |
4093 | |
4094 | { "lfqx" , X(31,791), X_MASK, POWER2, { FRT, RA, RB } }, |
4095 | |
4096 | { "lfdpx" , X(31,791), X_MASK, POWER6, { FRT, RA, RB } }, |
4097 | |
4098 | { "lfqux" , X(31,823), X_MASK, POWER2, { FRT, RA, RB } }, |
4099 | |
4100 | { "stfqx" , X(31,919), X_MASK, POWER2, { FRS, RA, RB } }, |
4101 | |
4102 | { "stfdpx" , X(31,919), X_MASK, POWER6, { FRS, RA, RB } }, |
4103 | |
4104 | { "stfqux" , X(31,951), X_MASK, POWER2, { FRS, RA, RB } }, |
4105 | |
4106 | { "orc" , XRC(31,412,0), X_MASK, COM, { RA, RS, RB } }, |
4107 | { "orc." , XRC(31,412,1), X_MASK, COM, { RA, RS, RB } }, |
4108 | |
4109 | { "sradi" , XS(31,413,0), XS_MASK, PPC64, { RA, RS, SH6 } }, |
4110 | { "sradi." , XS(31,413,1), XS_MASK, PPC64, { RA, RS, SH6 } }, |
4111 | |
4112 | { "sthxe" , X(31,415), X_MASK, BOOKE64, { RS, RA0, RB } }, |
4113 | |
4114 | { "slbie" , X(31,434), XRTRA_MASK, PPC64, { RB } }, |
4115 | |
4116 | { "ecowx" , X(31,438), X_MASK, PPC, { RT, RA, RB } }, |
4117 | |
4118 | { "sthux" , X(31,439), X_MASK, COM, { RS, RAS, RB } }, |
4119 | |
4120 | { "sthuxe" , X(31,447), X_MASK, BOOKE64, { RS, RAS, RB } }, |
4121 | |
4122 | { "cctpl" , 0x7c210b78, 0xffffffff, CELL, { 0 }}, |
4123 | { "cctpm" , 0x7c421378, 0xffffffff, CELL, { 0 }}, |
4124 | { "cctph" , 0x7c631b78, 0xffffffff, CELL, { 0 }}, |
4125 | { "db8cyc" , 0x7f9ce378, 0xffffffff, CELL, { 0 }}, |
4126 | { "db10cyc" , 0x7fbdeb78, 0xffffffff, CELL, { 0 }}, |
4127 | { "db12cyc" , 0x7fdef378, 0xffffffff, CELL, { 0 }}, |
4128 | { "db16cyc" , 0x7ffffb78, 0xffffffff, CELL, { 0 }}, |
4129 | { "mr" , XRC(31,444,0), X_MASK, COM, { RA, RS, RBS } }, |
4130 | { "or" , XRC(31,444,0), X_MASK, COM, { RA, RS, RB } }, |
4131 | { "mr." , XRC(31,444,1), X_MASK, COM, { RA, RS, RBS } }, |
4132 | { "or." , XRC(31,444,1), X_MASK, COM, { RA, RS, RB } }, |
4133 | |
4134 | { "mtexisr" , XSPR(31,451,64), XSPR_MASK, PPC403, { RS } }, |
4135 | { "mtexier" , XSPR(31,451,66), XSPR_MASK, PPC403, { RS } }, |
4136 | { "mtbr0" , XSPR(31,451,128), XSPR_MASK, PPC403, { RS } }, |
4137 | { "mtbr1" , XSPR(31,451,129), XSPR_MASK, PPC403, { RS } }, |
4138 | { "mtbr2" , XSPR(31,451,130), XSPR_MASK, PPC403, { RS } }, |
4139 | { "mtbr3" , XSPR(31,451,131), XSPR_MASK, PPC403, { RS } }, |
4140 | { "mtbr4" , XSPR(31,451,132), XSPR_MASK, PPC403, { RS } }, |
4141 | { "mtbr5" , XSPR(31,451,133), XSPR_MASK, PPC403, { RS } }, |
4142 | { "mtbr6" , XSPR(31,451,134), XSPR_MASK, PPC403, { RS } }, |
4143 | { "mtbr7" , XSPR(31,451,135), XSPR_MASK, PPC403, { RS } }, |
4144 | { "mtbear" , XSPR(31,451,144), XSPR_MASK, PPC403, { RS } }, |
4145 | { "mtbesr" , XSPR(31,451,145), XSPR_MASK, PPC403, { RS } }, |
4146 | { "mtiocr" , XSPR(31,451,160), XSPR_MASK, PPC403, { RS } }, |
4147 | { "mtdmacr0" , XSPR(31,451,192), XSPR_MASK, PPC403, { RS } }, |
4148 | { "mtdmact0" , XSPR(31,451,193), XSPR_MASK, PPC403, { RS } }, |
4149 | { "mtdmada0" , XSPR(31,451,194), XSPR_MASK, PPC403, { RS } }, |
4150 | { "mtdmasa0" , XSPR(31,451,195), XSPR_MASK, PPC403, { RS } }, |
4151 | { "mtdmacc0" , XSPR(31,451,196), XSPR_MASK, PPC403, { RS } }, |
4152 | { "mtdmacr1" , XSPR(31,451,200), XSPR_MASK, PPC403, { RS } }, |
4153 | { "mtdmact1" , XSPR(31,451,201), XSPR_MASK, PPC403, { RS } }, |
4154 | { "mtdmada1" , XSPR(31,451,202), XSPR_MASK, PPC403, { RS } }, |
4155 | { "mtdmasa1" , XSPR(31,451,203), XSPR_MASK, PPC403, { RS } }, |
4156 | { "mtdmacc1" , XSPR(31,451,204), XSPR_MASK, PPC403, { RS } }, |
4157 | { "mtdmacr2" , XSPR(31,451,208), XSPR_MASK, PPC403, { RS } }, |
4158 | { "mtdmact2" , XSPR(31,451,209), XSPR_MASK, PPC403, { RS } }, |
4159 | { "mtdmada2" , XSPR(31,451,210), XSPR_MASK, PPC403, { RS } }, |
4160 | { "mtdmasa2" , XSPR(31,451,211), XSPR_MASK, PPC403, { RS } }, |
4161 | { "mtdmacc2" , XSPR(31,451,212), XSPR_MASK, PPC403, { RS } }, |
4162 | { "mtdmacr3" , XSPR(31,451,216), XSPR_MASK, PPC403, { RS } }, |
4163 | { "mtdmact3" , XSPR(31,451,217), XSPR_MASK, PPC403, { RS } }, |
4164 | { "mtdmada3" , XSPR(31,451,218), XSPR_MASK, PPC403, { RS } }, |
4165 | { "mtdmasa3" , XSPR(31,451,219), XSPR_MASK, PPC403, { RS } }, |
4166 | { "mtdmacc3" , XSPR(31,451,220), XSPR_MASK, PPC403, { RS } }, |
4167 | { "mtdmasr" , XSPR(31,451,224), XSPR_MASK, PPC403, { RS } }, |
4168 | { "mtdcr" , X(31,451), X_MASK, PPC403 | BOOKE, { SPR, RS } }, |
4169 | |
4170 | { "subfze64" ,XO(31,456,0,0), XORB_MASK, BOOKE64, { RT, RA } }, |
4171 | { "subfze64o" ,XO(31,456,1,0), XORB_MASK, BOOKE64, { RT, RA } }, |
4172 | |
4173 | { "divdu" , XO(31,457,0,0), XO_MASK, PPC64, { RT, RA, RB } }, |
4174 | { "divdu." , XO(31,457,0,1), XO_MASK, PPC64, { RT, RA, RB } }, |
4175 | { "divduo" , XO(31,457,1,0), XO_MASK, PPC64, { RT, RA, RB } }, |
4176 | { "divduo." , XO(31,457,1,1), XO_MASK, PPC64, { RT, RA, RB } }, |
4177 | |
4178 | { "addze64" , XO(31,458,0,0), XORB_MASK, BOOKE64, { RT, RA } }, |
4179 | { "addze64o" ,XO(31,458,1,0), XORB_MASK, BOOKE64, { RT, RA } }, |
4180 | |
4181 | { "divwu" , XO(31,459,0,0), XO_MASK, PPC, { RT, RA, RB } }, |
4182 | { "divwu." , XO(31,459,0,1), XO_MASK, PPC, { RT, RA, RB } }, |
4183 | { "divwuo" , XO(31,459,1,0), XO_MASK, PPC, { RT, RA, RB } }, |
4184 | { "divwuo." , XO(31,459,1,1), XO_MASK, PPC, { RT, RA, RB } }, |
4185 | |
4186 | { "mtmq" , XSPR(31,467,0), XSPR_MASK, M601, { RS } }, |
4187 | { "mtxer" , XSPR(31,467,1), XSPR_MASK, COM, { RS } }, |
4188 | { "mtlr" , XSPR(31,467,8), XSPR_MASK, COM, { RS } }, |
4189 | { "mtctr" , XSPR(31,467,9), XSPR_MASK, COM, { RS } }, |
4190 | { "mttid" , XSPR(31,467,17), XSPR_MASK, POWER, { RS } }, |
4191 | { "mtdsisr" , XSPR(31,467,18), XSPR_MASK, COM, { RS } }, |
4192 | { "mtdar" , XSPR(31,467,19), XSPR_MASK, COM, { RS } }, |
4193 | { "mtrtcu" , XSPR(31,467,20), XSPR_MASK, COM, { RS } }, |
4194 | { "mtrtcl" , XSPR(31,467,21), XSPR_MASK, COM, { RS } }, |
4195 | { "mtdec" , XSPR(31,467,22), XSPR_MASK, COM, { RS } }, |
4196 | { "mtsdr0" , XSPR(31,467,24), XSPR_MASK, POWER, { RS } }, |
4197 | { "mtsdr1" , XSPR(31,467,25), XSPR_MASK, COM, { RS } }, |
4198 | { "mtsrr0" , XSPR(31,467,26), XSPR_MASK, COM, { RS } }, |
4199 | { "mtsrr1" , XSPR(31,467,27), XSPR_MASK, COM, { RS } }, |
4200 | { "mtcfar" , XSPR(31,467,28), XSPR_MASK, POWER6, { RS } }, |
4201 | { "mtpid" , XSPR(31,467,48), XSPR_MASK, BOOKE, { RS } }, |
4202 | { "mtpid" , XSPR(31,467,945), XSPR_MASK, PPC403, { RS } }, |
4203 | { "mtdecar" , XSPR(31,467,54), XSPR_MASK, BOOKE, { RS } }, |
4204 | { "mtcsrr0" , XSPR(31,467,58), XSPR_MASK, BOOKE, { RS } }, |
4205 | { "mtcsrr1" , XSPR(31,467,59), XSPR_MASK, BOOKE, { RS } }, |
4206 | { "mtdear" , XSPR(31,467,61), XSPR_MASK, BOOKE, { RS } }, |
4207 | { "mtdear" , XSPR(31,467,981), XSPR_MASK, PPC403, { RS } }, |
4208 | { "mtesr" , XSPR(31,467,62), XSPR_MASK, BOOKE, { RS } }, |
4209 | { "mtesr" , XSPR(31,467,980), XSPR_MASK, PPC403, { RS } }, |
4210 | { "mtivpr" , XSPR(31,467,63), XSPR_MASK, BOOKE, { RS } }, |
4211 | { "mtcmpa" , XSPR(31,467,144), XSPR_MASK, PPC860, { RS } }, |
4212 | { "mtcmpb" , XSPR(31,467,145), XSPR_MASK, PPC860, { RS } }, |
4213 | { "mtcmpc" , XSPR(31,467,146), XSPR_MASK, PPC860, { RS } }, |
4214 | { "mtcmpd" , XSPR(31,467,147), XSPR_MASK, PPC860, { RS } }, |
4215 | { "mticr" , XSPR(31,467,148), XSPR_MASK, PPC860, { RS } }, |
4216 | { "mtder" , XSPR(31,467,149), XSPR_MASK, PPC860, { RS } }, |
4217 | { "mtcounta" , XSPR(31,467,150), XSPR_MASK, PPC860, { RS } }, |
4218 | { "mtcountb" , XSPR(31,467,151), XSPR_MASK, PPC860, { RS } }, |
4219 | { "mtcmpe" , XSPR(31,467,152), XSPR_MASK, PPC860, { RS } }, |
4220 | { "mtcmpf" , XSPR(31,467,153), XSPR_MASK, PPC860, { RS } }, |
4221 | { "mtcmpg" , XSPR(31,467,154), XSPR_MASK, PPC860, { RS } }, |
4222 | { "mtcmph" , XSPR(31,467,155), XSPR_MASK, PPC860, { RS } }, |
4223 | { "mtlctrl1" , XSPR(31,467,156), XSPR_MASK, PPC860, { RS } }, |
4224 | { "mtlctrl2" , XSPR(31,467,157), XSPR_MASK, PPC860, { RS } }, |
4225 | { "mtictrl" , XSPR(31,467,158), XSPR_MASK, PPC860, { RS } }, |
4226 | { "mtbar" , XSPR(31,467,159), XSPR_MASK, PPC860, { RS } }, |
4227 | { "mtvrsave" , XSPR(31,467,256), XSPR_MASK, PPCVEC, { RS } }, |
4228 | { "mtusprg0" , XSPR(31,467,256), XSPR_MASK, BOOKE, { RS } }, |
4229 | { "mtsprg" , XSPR(31,467,256), XSPRG_MASK,PPC, { SPRG, RS } }, |
4230 | { "mtsprg0" , XSPR(31,467,272), XSPR_MASK, PPC, { RS } }, |
4231 | { "mtsprg1" , XSPR(31,467,273), XSPR_MASK, PPC, { RS } }, |
4232 | { "mtsprg2" , XSPR(31,467,274), XSPR_MASK, PPC, { RS } }, |
4233 | { "mtsprg3" , XSPR(31,467,275), XSPR_MASK, PPC, { RS } }, |
4234 | { "mtsprg4" , XSPR(31,467,276), XSPR_MASK, PPC405 | BOOKE, { RS } }, |
4235 | { "mtsprg5" , XSPR(31,467,277), XSPR_MASK, PPC405 | BOOKE, { RS } }, |
4236 | { "mtsprg6" , XSPR(31,467,278), XSPR_MASK, PPC405 | BOOKE, { RS } }, |
4237 | { "mtsprg7" , XSPR(31,467,279), XSPR_MASK, PPC405 | BOOKE, { RS } }, |
4238 | { "mtasr" , XSPR(31,467,280), XSPR_MASK, PPC64, { RS } }, |
4239 | { "mtear" , XSPR(31,467,282), XSPR_MASK, PPC, { RS } }, |
4240 | { "mttbl" , XSPR(31,467,284), XSPR_MASK, PPC, { RS } }, |
4241 | { "mttbu" , XSPR(31,467,285), XSPR_MASK, PPC, { RS } }, |
4242 | { "mtdbsr" , XSPR(31,467,304), XSPR_MASK, BOOKE, { RS } }, |
4243 | { "mtdbsr" , XSPR(31,467,1008), XSPR_MASK, PPC403, { RS } }, |
4244 | { "mtdbcr0" , XSPR(31,467,308), XSPR_MASK, BOOKE, { RS } }, |
4245 | { "mtdbcr0" , XSPR(31,467,1010), XSPR_MASK, PPC405, { RS } }, |
4246 | { "mtdbcr1" , XSPR(31,467,309), XSPR_MASK, BOOKE, { RS } }, |
4247 | { "mtdbcr1" , XSPR(31,467,957), XSPR_MASK, PPC405, { RS } }, |
4248 | { "mtdbcr2" , XSPR(31,467,310), XSPR_MASK, BOOKE, { RS } }, |
4249 | { "mtiac1" , XSPR(31,467,312), XSPR_MASK, BOOKE, { RS } }, |
4250 | { "mtiac1" , XSPR(31,467,1012), XSPR_MASK, PPC403, { RS } }, |
4251 | { "mtiac2" , XSPR(31,467,313), XSPR_MASK, BOOKE, { RS } }, |
4252 | { "mtiac2" , XSPR(31,467,1013), XSPR_MASK, PPC403, { RS } }, |
4253 | { "mtiac3" , XSPR(31,467,314), XSPR_MASK, BOOKE, { RS } }, |
4254 | { "mtiac3" , XSPR(31,467,948), XSPR_MASK, PPC405, { RS } }, |
4255 | { "mtiac4" , XSPR(31,467,315), XSPR_MASK, BOOKE, { RS } }, |
4256 | { "mtiac4" , XSPR(31,467,949), XSPR_MASK, PPC405, { RS } }, |
4257 | { "mtdac1" , XSPR(31,467,316), XSPR_MASK, BOOKE, { RS } }, |
4258 | { "mtdac1" , XSPR(31,467,1014), XSPR_MASK, PPC403, { RS } }, |
4259 | { "mtdac2" , XSPR(31,467,317), XSPR_MASK, BOOKE, { RS } }, |
4260 | { "mtdac2" , XSPR(31,467,1015), XSPR_MASK, PPC403, { RS } }, |
4261 | { "mtdvc1" , XSPR(31,467,318), XSPR_MASK, BOOKE, { RS } }, |
4262 | { "mtdvc1" , XSPR(31,467,950), XSPR_MASK, PPC405, { RS } }, |
4263 | { "mtdvc2" , XSPR(31,467,319), XSPR_MASK, BOOKE, { RS } }, |
4264 | { "mtdvc2" , XSPR(31,467,951), XSPR_MASK, PPC405, { RS } }, |
4265 | { "mttsr" , XSPR(31,467,336), XSPR_MASK, BOOKE, { RS } }, |
4266 | { "mttsr" , XSPR(31,467,984), XSPR_MASK, PPC403, { RS } }, |
4267 | { "mttcr" , XSPR(31,467,340), XSPR_MASK, BOOKE, { RS } }, |
4268 | { "mttcr" , XSPR(31,467,986), XSPR_MASK, PPC403, { RS } }, |
4269 | { "mtivor0" , XSPR(31,467,400), XSPR_MASK, BOOKE, { RS } }, |
4270 | { "mtivor1" , XSPR(31,467,401), XSPR_MASK, BOOKE, { RS } }, |
4271 | { "mtivor2" , XSPR(31,467,402), XSPR_MASK, BOOKE, { RS } }, |
4272 | { "mtivor3" , XSPR(31,467,403), XSPR_MASK, BOOKE, { RS } }, |
4273 | { "mtivor4" , XSPR(31,467,404), XSPR_MASK, BOOKE, { RS } }, |
4274 | { "mtivor5" , XSPR(31,467,405), XSPR_MASK, BOOKE, { RS } }, |
4275 | { "mtivor6" , XSPR(31,467,406), XSPR_MASK, BOOKE, { RS } }, |
4276 | { "mtivor7" , XSPR(31,467,407), XSPR_MASK, BOOKE, { RS } }, |
4277 | { "mtivor8" , XSPR(31,467,408), XSPR_MASK, BOOKE, { RS } }, |
4278 | { "mtivor9" , XSPR(31,467,409), XSPR_MASK, BOOKE, { RS } }, |
4279 | { "mtivor10" , XSPR(31,467,410), XSPR_MASK, BOOKE, { RS } }, |
4280 | { "mtivor11" , XSPR(31,467,411), XSPR_MASK, BOOKE, { RS } }, |
4281 | { "mtivor12" , XSPR(31,467,412), XSPR_MASK, BOOKE, { RS } }, |
4282 | { "mtivor13" , XSPR(31,467,413), XSPR_MASK, BOOKE, { RS } }, |
4283 | { "mtivor14" , XSPR(31,467,414), XSPR_MASK, BOOKE, { RS } }, |
4284 | { "mtivor15" , XSPR(31,467,415), XSPR_MASK, BOOKE, { RS } }, |
4285 | { "mtspefscr" , XSPR(31,467,512), XSPR_MASK, PPCSPE, { RS } }, |
4286 | { "mtbbear" , XSPR(31,467,513), XSPR_MASK, PPCBRLK, { RS } }, |
4287 | { "mtbbtar" , XSPR(31,467,514), XSPR_MASK, PPCBRLK, { RS } }, |
4288 | { "mtivor32" , XSPR(31,467,528), XSPR_MASK, PPCSPE, { RS } }, |
4289 | { "mtivor33" , XSPR(31,467,529), XSPR_MASK, PPCSPE, { RS } }, |
4290 | { "mtivor34" , XSPR(31,467,530), XSPR_MASK, PPCSPE, { RS } }, |
4291 | { "mtivor35" , XSPR(31,467,531), XSPR_MASK, PPCPMR, { RS } }, |
4292 | { "mtibatu" , XSPR(31,467,528), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, |
4293 | { "mtibatl" , XSPR(31,467,529), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, |
4294 | { "mtdbatu" , XSPR(31,467,536), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, |
4295 | { "mtdbatl" , XSPR(31,467,537), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, |
4296 | { "mtmcsrr0" , XSPR(31,467,570), XSPR_MASK, PPCRFMCI, { RS } }, |
4297 | { "mtmcsrr1" , XSPR(31,467,571), XSPR_MASK, PPCRFMCI, { RS } }, |
4298 | { "mtmcsr" , XSPR(31,467,572), XSPR_MASK, PPCRFMCI, { RS } }, |
4299 | { "mtummcr0" , XSPR(31,467,936), XSPR_MASK, PPC750, { RS } }, |
4300 | { "mtupmc1" , XSPR(31,467,937), XSPR_MASK, PPC750, { RS } }, |
4301 | { "mtupmc2" , XSPR(31,467,938), XSPR_MASK, PPC750, { RS } }, |
4302 | { "mtusia" , XSPR(31,467,939), XSPR_MASK, PPC750, { RS } }, |
4303 | { "mtummcr1" , XSPR(31,467,940), XSPR_MASK, PPC750, { RS } }, |
4304 | { "mtupmc3" , XSPR(31,467,941), XSPR_MASK, PPC750, { RS } }, |
4305 | { "mtupmc4" , XSPR(31,467,942), XSPR_MASK, PPC750, { RS } }, |
4306 | { "mtzpr" , XSPR(31,467,944), XSPR_MASK, PPC403, { RS } }, |
4307 | { "mtccr0" , XSPR(31,467,947), XSPR_MASK, PPC405, { RS } }, |
4308 | { "mtmmcr0" , XSPR(31,467,952), XSPR_MASK, PPC750, { RS } }, |
4309 | { "mtsgr" , XSPR(31,467,953), XSPR_MASK, PPC403, { RS } }, |
4310 | { "mtpmc1" , XSPR(31,467,953), XSPR_MASK, PPC750, { RS } }, |
4311 | { "mtdcwr" , XSPR(31,467,954), XSPR_MASK, PPC403, { RS } }, |
4312 | { "mtpmc2" , XSPR(31,467,954), XSPR_MASK, PPC750, { RS } }, |
4313 | { "mtsler" , XSPR(31,467,955), XSPR_MASK, PPC405, { RS } }, |
4314 | { "mtsia" , XSPR(31,467,955), XSPR_MASK, PPC750, { RS } }, |
4315 | { "mtsu0r" , XSPR(31,467,956), XSPR_MASK, PPC405, { RS } }, |
4316 | { "mtmmcr1" , XSPR(31,467,956), XSPR_MASK, PPC750, { RS } }, |
4317 | { "mtpmc3" , XSPR(31,467,957), XSPR_MASK, PPC750, { RS } }, |
4318 | { "mtpmc4" , XSPR(31,467,958), XSPR_MASK, PPC750, { RS } }, |
4319 | { "mticdbdr" , XSPR(31,467,979), XSPR_MASK, PPC403, { RS } }, |
4320 | { "mtevpr" , XSPR(31,467,982), XSPR_MASK, PPC403, { RS } }, |
4321 | { "mtcdbcr" , XSPR(31,467,983), XSPR_MASK, PPC403, { RS } }, |
4322 | { "mtpit" , XSPR(31,467,987), XSPR_MASK, PPC403, { RS } }, |
4323 | { "mttbhi" , XSPR(31,467,988), XSPR_MASK, PPC403, { RS } }, |
4324 | { "mttblo" , XSPR(31,467,989), XSPR_MASK, PPC403, { RS } }, |
4325 | { "mtsrr2" , XSPR(31,467,990), XSPR_MASK, PPC403, { RS } }, |
4326 | { "mtsrr3" , XSPR(31,467,991), XSPR_MASK, PPC403, { RS } }, |
4327 | { "mtl2cr" , XSPR(31,467,1017), XSPR_MASK, PPC750, { RS } }, |
4328 | { "mtdccr" , XSPR(31,467,1018), XSPR_MASK, PPC403, { RS } }, |
4329 | { "mticcr" , XSPR(31,467,1019), XSPR_MASK, PPC403, { RS } }, |
4330 | { "mtictc" , XSPR(31,467,1019), XSPR_MASK, PPC750, { RS } }, |
4331 | { "mtpbl1" , XSPR(31,467,1020), XSPR_MASK, PPC403, { RS } }, |
4332 | { "mtthrm1" , XSPR(31,467,1020), XSPR_MASK, PPC750, { RS } }, |
4333 | { "mtpbu1" , XSPR(31,467,1021), XSPR_MASK, PPC403, { RS } }, |
4334 | { "mtthrm2" , XSPR(31,467,1021), XSPR_MASK, PPC750, { RS } }, |
4335 | { "mtpbl2" , XSPR(31,467,1022), XSPR_MASK, PPC403, { RS } }, |
4336 | { "mtthrm3" , XSPR(31,467,1022), XSPR_MASK, PPC750, { RS } }, |
4337 | { "mtpbu2" , XSPR(31,467,1023), XSPR_MASK, PPC403, { RS } }, |
4338 | { "mtspr" , X(31,467), X_MASK, COM, { SPR, RS } }, |
4339 | |
4340 | { "dcbi" , X(31,470), XRT_MASK, PPC, { RA, RB } }, |
4341 | |
4342 | { "nand" , XRC(31,476,0), X_MASK, COM, { RA, RS, RB } }, |
4343 | { "nand." , XRC(31,476,1), X_MASK, COM, { RA, RS, RB } }, |
4344 | |
4345 | { "dcbie" , X(31,478), XRT_MASK, BOOKE64, { RA, RB } }, |
4346 | |
4347 | { "dcread" , X(31,486), X_MASK, PPC403|PPC440, { RT, RA, RB }}, |
4348 | |
4349 | { "mtpmr" , X(31,462), X_MASK, PPCPMR, { PMR, RS }}, |
4350 | |
4351 | { "icbtls" , X(31,486), X_MASK, PPCCHLK, { CT, RA, RB }}, |
4352 | |
4353 | { "nabs" , XO(31,488,0,0), XORB_MASK, M601, { RT, RA } }, |
4354 | { "subfme64" ,XO(31,488,0,0), XORB_MASK, BOOKE64, { RT, RA } }, |
4355 | { "nabs." , XO(31,488,0,1), XORB_MASK, M601, { RT, RA } }, |
4356 | { "nabso" , XO(31,488,1,0), XORB_MASK, M601, { RT, RA } }, |
4357 | { "subfme64o" ,XO(31,488,1,0), XORB_MASK, BOOKE64, { RT, RA } }, |
4358 | { "nabso." , XO(31,488,1,1), XORB_MASK, M601, { RT, RA } }, |
4359 | |
4360 | { "divd" , XO(31,489,0,0), XO_MASK, PPC64, { RT, RA, RB } }, |
4361 | { "divd." , XO(31,489,0,1), XO_MASK, PPC64, { RT, RA, RB } }, |
4362 | { "divdo" , XO(31,489,1,0), XO_MASK, PPC64, { RT, RA, RB } }, |
4363 | { "divdo." , XO(31,489,1,1), XO_MASK, PPC64, { RT, RA, RB } }, |
4364 | |
4365 | { "addme64" , XO(31,490,0,0), XORB_MASK, BOOKE64, { RT, RA } }, |
4366 | { "addme64o" ,XO(31,490,1,0), XORB_MASK, BOOKE64, { RT, RA } }, |
4367 | |
4368 | { "divw" , XO(31,491,0,0), XO_MASK, PPC, { RT, RA, RB } }, |
4369 | { "divw." , XO(31,491,0,1), XO_MASK, PPC, { RT, RA, RB } }, |
4370 | { "divwo" , XO(31,491,1,0), XO_MASK, PPC, { RT, RA, RB } }, |
4371 | { "divwo." , XO(31,491,1,1), XO_MASK, PPC, { RT, RA, RB } }, |
4372 | |
4373 | { "icbtlse" , X(31,494), X_MASK, PPCCHLK64, { CT, RA, RB }}, |
4374 | |
4375 | { "slbia" , X(31,498), 0xffffffff, PPC64, { 0 } }, |
4376 | |
4377 | { "cli" , X(31,502), XRB_MASK, POWER, { RT, RA } }, |
4378 | |
4379 | { "stdcxe." , XRC(31,511,1), X_MASK, BOOKE64, { RS, RA, RB } }, |
4380 | |
4381 | { "mcrxr" , X(31,512), XRARB_MASK|(3<<21), COM, { BF } }, |
4382 | |
4383 | { "bblels" , X(31,518), X_MASK, PPCBRLK, { 0 }}, |
4384 | { "mcrxr64" , X(31,544), XRARB_MASK|(3<<21), BOOKE64, { BF } }, |
4385 | |
4386 | { "clcs" , X(31,531), XRB_MASK, M601, { RT, RA } }, |
4387 | |
4388 | { "ldbrx" , X(31,532), X_MASK, CELL, { RT, RA0, RB } }, |
4389 | |
4390 | { "lswx" , X(31,533), X_MASK, PPCCOM, { RT, RA0, RB } }, |
4391 | { "lsx" , X(31,533), X_MASK, PWRCOM, { RT, RA, RB } }, |
4392 | |
4393 | { "lwbrx" , X(31,534), X_MASK, PPCCOM, { RT, RA0, RB } }, |
4394 | { "lbrx" , X(31,534), X_MASK, PWRCOM, { RT, RA, RB } }, |
4395 | |
4396 | { "lfsx" , X(31,535), X_MASK, COM, { FRT, RA0, RB } }, |
4397 | |
4398 | { "srw" , XRC(31,536,0), X_MASK, PPCCOM, { RA, RS, RB } }, |
4399 | { "sr" , XRC(31,536,0), X_MASK, PWRCOM, { RA, RS, RB } }, |
4400 | { "srw." , XRC(31,536,1), X_MASK, PPCCOM, { RA, RS, RB } }, |
4401 | { "sr." , XRC(31,536,1), X_MASK, PWRCOM, { RA, RS, RB } }, |
4402 | |
4403 | { "rrib" , XRC(31,537,0), X_MASK, M601, { RA, RS, RB } }, |
4404 | { "rrib." , XRC(31,537,1), X_MASK, M601, { RA, RS, RB } }, |
4405 | |
4406 | { "srd" , XRC(31,539,0), X_MASK, PPC64, { RA, RS, RB } }, |
4407 | { "srd." , XRC(31,539,1), X_MASK, PPC64, { RA, RS, RB } }, |
4408 | |
4409 | { "maskir" , XRC(31,541,0), X_MASK, M601, { RA, RS, RB } }, |
4410 | { "maskir." , XRC(31,541,1), X_MASK, M601, { RA, RS, RB } }, |
4411 | |
4412 | { "lwbrxe" , X(31,542), X_MASK, BOOKE64, { RT, RA0, RB } }, |
4413 | |
4414 | { "lfsxe" , X(31,543), X_MASK, BOOKE64, { FRT, RA0, RB } }, |
4415 | |
4416 | { "bbelr" , X(31,550), X_MASK, PPCBRLK, { 0 }}, |
4417 | |
4418 | { "tlbsync" , X(31,566), 0xffffffff, PPC, { 0 } }, |
4419 | |
4420 | { "lfsux" , X(31,567), X_MASK, COM, { FRT, RAS, RB } }, |
4421 | |
4422 | { "lfsuxe" , X(31,575), X_MASK, BOOKE64, { FRT, RAS, RB } }, |
4423 | |
4424 | { "mfsr" , X(31,595), XRB_MASK|(1<<20), COM32, { RT, SR } }, |
4425 | |
4426 | { "lswi" , X(31,597), X_MASK, PPCCOM, { RT, RA0, NB } }, |
4427 | { "lsi" , X(31,597), X_MASK, PWRCOM, { RT, RA0, NB } }, |
4428 | |
4429 | { "lwsync" , XSYNC(31,598,1), 0xffffffff, PPC, { 0 } }, |
4430 | { "ptesync" , XSYNC(31,598,2), 0xffffffff, PPC64, { 0 } }, |
4431 | { "msync" , X(31,598), 0xffffffff, BOOKE, { 0 } }, |
4432 | { "sync" , X(31,598), XSYNC_MASK, PPCCOM, { LS } }, |
4433 | { "dcs" , X(31,598), 0xffffffff, PWRCOM, { 0 } }, |
4434 | |
4435 | { "lfdx" , X(31,599), X_MASK, COM, { FRT, RA0, RB } }, |
4436 | |
4437 | { "lfdxe" , X(31,607), X_MASK, BOOKE64, { FRT, RA0, RB } }, |
4438 | |
4439 | { "mffgpr" , XRC(31,607,0), XRA_MASK, POWER6, { FRT, RB } }, |
4440 | |
4441 | { "mfsri" , X(31,627), X_MASK, PWRCOM, { RT, RA, RB } }, |
4442 | |
4443 | { "dclst" , X(31,630), XRB_MASK, PWRCOM, { RS, RA } }, |
4444 | |
4445 | { "lfdux" , X(31,631), X_MASK, COM, { FRT, RAS, RB } }, |
4446 | |
4447 | { "lfduxe" , X(31,639), X_MASK, BOOKE64, { FRT, RAS, RB } }, |
4448 | |
4449 | { "mfsrin" , X(31,659), XRA_MASK, PPC32, { RT, RB } }, |
4450 | |
4451 | { "stdbrx" , X(31,660), X_MASK, CELL, { RS, RA0, RB } }, |
4452 | |
4453 | { "stswx" , X(31,661), X_MASK, PPCCOM, { RS, RA0, RB } }, |
4454 | { "stsx" , X(31,661), X_MASK, PWRCOM, { RS, RA0, RB } }, |
4455 | |
4456 | { "stwbrx" , X(31,662), X_MASK, PPCCOM, { RS, RA0, RB } }, |
4457 | { "stbrx" , X(31,662), X_MASK, PWRCOM, { RS, RA0, RB } }, |
4458 | |
4459 | { "stfsx" , X(31,663), X_MASK, COM, { FRS, RA0, RB } }, |
4460 | |
4461 | { "srq" , XRC(31,664,0), X_MASK, M601, { RA, RS, RB } }, |
4462 | { "srq." , XRC(31,664,1), X_MASK, M601, { RA, RS, RB } }, |
4463 | |
4464 | { "sre" , XRC(31,665,0), X_MASK, M601, { RA, RS, RB } }, |
4465 | { "sre." , XRC(31,665,1), X_MASK, M601, { RA, RS, RB } }, |
4466 | |
4467 | { "stwbrxe" , X(31,670), X_MASK, BOOKE64, { RS, RA0, RB } }, |
4468 | |
4469 | { "stfsxe" , X(31,671), X_MASK, BOOKE64, { FRS, RA0, RB } }, |
4470 | |
4471 | { "stfsux" , X(31,695), X_MASK, COM, { FRS, RAS, RB } }, |
4472 | |
4473 | { "sriq" , XRC(31,696,0), X_MASK, M601, { RA, RS, SH } }, |
4474 | { "sriq." , XRC(31,696,1), X_MASK, M601, { RA, RS, SH } }, |
4475 | |
4476 | { "stfsuxe" , X(31,703), X_MASK, BOOKE64, { FRS, RAS, RB } }, |
4477 | |
4478 | { "stswi" , X(31,725), X_MASK, PPCCOM, { RS, RA0, NB } }, |
4479 | { "stsi" , X(31,725), X_MASK, PWRCOM, { RS, RA0, NB } }, |
4480 | |
4481 | { "stfdx" , X(31,727), X_MASK, COM, { FRS, RA0, RB } }, |
4482 | |
4483 | { "srlq" , XRC(31,728,0), X_MASK, M601, { RA, RS, RB } }, |
4484 | { "srlq." , XRC(31,728,1), X_MASK, M601, { RA, RS, RB } }, |
4485 | |
4486 | { "sreq" , XRC(31,729,0), X_MASK, M601, { RA, RS, RB } }, |
4487 | { "sreq." , XRC(31,729,1), X_MASK, M601, { RA, RS, RB } }, |
4488 | |
4489 | { "stfdxe" , X(31,735), X_MASK, BOOKE64, { FRS, RA0, RB } }, |
4490 | |
4491 | { "mftgpr" , XRC(31,735,0), XRA_MASK, POWER6, { RT, FRB } }, |
4492 | |
4493 | { "dcba" , X(31,758), XRT_MASK, PPC405 | BOOKE, { RA, RB } }, |
4494 | |
4495 | { "stfdux" , X(31,759), X_MASK, COM, { FRS, RAS, RB } }, |
4496 | |
4497 | { "srliq" , XRC(31,760,0), X_MASK, M601, { RA, RS, SH } }, |
4498 | { "srliq." , XRC(31,760,1), X_MASK, M601, { RA, RS, SH } }, |
4499 | |
4500 | { "dcbae" , X(31,766), XRT_MASK, BOOKE64, { RA, RB } }, |
4501 | |
4502 | { "stfduxe" , X(31,767), X_MASK, BOOKE64, { FRS, RAS, RB } }, |
4503 | |
4504 | { "tlbivax" , X(31,786), XRT_MASK, BOOKE, { RA, RB } }, |
4505 | { "tlbivaxe" ,X(31,787), XRT_MASK, BOOKE64, { RA, RB } }, |
4506 | |
4507 | { "lwzcix" , X(31,789), X_MASK, POWER6, { RT, RA0, RB } }, |
4508 | |
4509 | { "lhbrx" , X(31,790), X_MASK, COM, { RT, RA0, RB } }, |
4510 | |
4511 | { "sraw" , XRC(31,792,0), X_MASK, PPCCOM, { RA, RS, RB } }, |
4512 | { "sra" , XRC(31,792,0), X_MASK, PWRCOM, { RA, RS, RB } }, |
4513 | { "sraw." , XRC(31,792,1), X_MASK, PPCCOM, { RA, RS, RB } }, |
4514 | { "sra." , XRC(31,792,1), X_MASK, PWRCOM, { RA, RS, RB } }, |
4515 | |
4516 | { "srad" , XRC(31,794,0), X_MASK, PPC64, { RA, RS, RB } }, |
4517 | { "srad." , XRC(31,794,1), X_MASK, PPC64, { RA, RS, RB } }, |
4518 | |
4519 | { "lhbrxe" , X(31,798), X_MASK, BOOKE64, { RT, RA0, RB } }, |
4520 | |
4521 | { "ldxe" , X(31,799), X_MASK, BOOKE64, { RT, RA0, RB } }, |
4522 | { "lduxe" , X(31,831), X_MASK, BOOKE64, { RT, RA0, RB } }, |
4523 | |
4524 | { "rac" , X(31,818), X_MASK, PWRCOM, { RT, RA, RB } }, |
4525 | |
4526 | { "lhzcix" , X(31,821), X_MASK, POWER6, { RT, RA0, RB } }, |
4527 | |
4528 | { "dss" , XDSS(31,822,0), XDSS_MASK, PPCVEC, { STRM } }, |
4529 | { "dssall" , XDSS(31,822,1), XDSS_MASK, PPCVEC, { 0 } }, |
4530 | |
4531 | { "srawi" , XRC(31,824,0), X_MASK, PPCCOM, { RA, RS, SH } }, |
4532 | { "srai" , XRC(31,824,0), X_MASK, PWRCOM, { RA, RS, SH } }, |
4533 | { "srawi." , XRC(31,824,1), X_MASK, PPCCOM, { RA, RS, SH } }, |
4534 | { "srai." , XRC(31,824,1), X_MASK, PWRCOM, { RA, RS, SH } }, |
4535 | |
4536 | { "slbmfev" , X(31,851), XRA_MASK, PPC64, { RT, RB } }, |
4537 | |
4538 | { "lbzcix" , X(31,853), X_MASK, POWER6, { RT, RA0, RB } }, |
4539 | |
4540 | { "mbar" , X(31,854), X_MASK, BOOKE, { MO } }, |
4541 | { "eieio" , X(31,854), 0xffffffff, PPC, { 0 } }, |
4542 | |
4543 | { "lfiwax" , X(31,855), X_MASK, POWER6, { FRT, RA0, RB } }, |
4544 | |
4545 | { "ldcix" , X(31,885), X_MASK, POWER6, { RT, RA0, RB } }, |
4546 | |
4547 | { "tlbsx" , XRC(31,914,0), X_MASK, PPC403|BOOKE, { RTO, RA, RB } }, |
4548 | { "tlbsx." , XRC(31,914,1), X_MASK, PPC403|BOOKE, { RTO, RA, RB } }, |
4549 | { "tlbsxe" , XRC(31,915,0), X_MASK, BOOKE64, { RTO, RA, RB } }, |
4550 | { "tlbsxe." , XRC(31,915,1), X_MASK, BOOKE64, { RTO, RA, RB } }, |
4551 | |
4552 | { "slbmfee" , X(31,915), XRA_MASK, PPC64, { RT, RB } }, |
4553 | |
4554 | { "stwcix" , X(31,917), X_MASK, POWER6, { RS, RA0, RB } }, |
4555 | |
4556 | { "sthbrx" , X(31,918), X_MASK, COM, { RS, RA0, RB } }, |
4557 | |
4558 | { "sraq" , XRC(31,920,0), X_MASK, M601, { RA, RS, RB } }, |
4559 | { "sraq." , XRC(31,920,1), X_MASK, M601, { RA, RS, RB } }, |
4560 | |
4561 | { "srea" , XRC(31,921,0), X_MASK, M601, { RA, RS, RB } }, |
4562 | { "srea." , XRC(31,921,1), X_MASK, M601, { RA, RS, RB } }, |
4563 | |
4564 | { "extsh" , XRC(31,922,0), XRB_MASK, PPCCOM, { RA, RS } }, |
4565 | { "exts" , XRC(31,922,0), XRB_MASK, PWRCOM, { RA, RS } }, |
4566 | { "extsh." , XRC(31,922,1), XRB_MASK, PPCCOM, { RA, RS } }, |
4567 | { "exts." , XRC(31,922,1), XRB_MASK, PWRCOM, { RA, RS } }, |
4568 | |
4569 | { "sthbrxe" , X(31,926), X_MASK, BOOKE64, { RS, RA0, RB } }, |
4570 | |
4571 | { "stdxe" , X(31,927), X_MASK, BOOKE64, { RS, RA0, RB } }, |
4572 | |
4573 | { "tlbrehi" , XTLB(31,946,0), XTLB_MASK, PPC403, { RT, RA } }, |
4574 | { "tlbrelo" , XTLB(31,946,1), XTLB_MASK, PPC403, { RT, RA } }, |
4575 | { "tlbre" , X(31,946), X_MASK, PPC403|BOOKE, { RSO, RAOPT, SHO } }, |
4576 | |
4577 | { "sthcix" , X(31,949), X_MASK, POWER6, { RS, RA0, RB } }, |
4578 | |
4579 | { "sraiq" , XRC(31,952,0), X_MASK, M601, { RA, RS, SH } }, |
4580 | { "sraiq." , XRC(31,952,1), X_MASK, M601, { RA, RS, SH } }, |
4581 | |
4582 | { "extsb" , XRC(31,954,0), XRB_MASK, PPC, { RA, RS} }, |
4583 | { "extsb." , XRC(31,954,1), XRB_MASK, PPC, { RA, RS} }, |
4584 | |
4585 | { "stduxe" , X(31,959), X_MASK, BOOKE64, { RS, RAS, RB } }, |
4586 | |
4587 | { "iccci" , X(31,966), XRT_MASK, PPC403|PPC440, { RA, RB } }, |
4588 | |
4589 | { "tlbwehi" , XTLB(31,978,0), XTLB_MASK, PPC403, { RT, RA } }, |
4590 | { "tlbwelo" , XTLB(31,978,1), XTLB_MASK, PPC403, { RT, RA } }, |
4591 | { "tlbwe" , X(31,978), X_MASK, PPC403|BOOKE, { RSO, RAOPT, SHO } }, |
4592 | { "tlbld" , X(31,978), XRTRA_MASK, PPC, { RB } }, |
4593 | |
4594 | { "stbcix" , X(31,981), X_MASK, POWER6, { RS, RA0, RB } }, |
4595 | |
4596 | { "icbi" , X(31,982), XRT_MASK, PPC, { RA, RB } }, |
4597 | |
4598 | { "stfiwx" , X(31,983), X_MASK, PPC, { FRS, RA0, RB } }, |
4599 | |
4600 | { "extsw" , XRC(31,986,0), XRB_MASK, PPC64 | BOOKE64,{ RA, RS } }, |
4601 | { "extsw." , XRC(31,986,1), XRB_MASK, PPC64, { RA, RS } }, |
4602 | |
4603 | { "icread" , X(31,998), XRT_MASK, PPC403|PPC440, { RA, RB } }, |
4604 | |
4605 | { "icbie" , X(31,990), XRT_MASK, BOOKE64, { RA, RB } }, |
4606 | { "stfiwxe" , X(31,991), X_MASK, BOOKE64, { FRS, RA0, RB } }, |
4607 | |
4608 | { "tlbli" , X(31,1010), XRTRA_MASK, PPC, { RB } }, |
4609 | |
4610 | { "stdcix" , X(31,1013), X_MASK, POWER6, { RS, RA0, RB } }, |
4611 | |
4612 | { "dcbzl" , XOPL(31,1014,1), XRT_MASK,POWER4, { RA, RB } }, |
4613 | { "dcbz" , X(31,1014), XRT_MASK, PPC, { RA, RB } }, |
4614 | { "dclz" , X(31,1014), XRT_MASK, PPC, { RA, RB } }, |
4615 | |
4616 | { "dcbze" , X(31,1022), XRT_MASK, BOOKE64, { RA, RB } }, |
4617 | |
4618 | { "lvebx" , X(31, 7), X_MASK, PPCVEC, { VD, RA, RB } }, |
4619 | { "lvehx" , X(31, 39), X_MASK, PPCVEC, { VD, RA, RB } }, |
4620 | { "lvewx" , X(31, 71), X_MASK, PPCVEC, { VD, RA, RB } }, |
4621 | { "lvsl" , X(31, 6), X_MASK, PPCVEC, { VD, RA, RB } }, |
4622 | { "lvsr" , X(31, 38), X_MASK, PPCVEC, { VD, RA, RB } }, |
4623 | { "lvx" , X(31, 103), X_MASK, PPCVEC, { VD, RA, RB } }, |
4624 | { "lvxl" , X(31, 359), X_MASK, PPCVEC, { VD, RA, RB } }, |
4625 | { "stvebx" , X(31, 135), X_MASK, PPCVEC, { VS, RA, RB } }, |
4626 | { "stvehx" , X(31, 167), X_MASK, PPCVEC, { VS, RA, RB } }, |
4627 | { "stvewx" , X(31, 199), X_MASK, PPCVEC, { VS, RA, RB } }, |
4628 | { "stvx" , X(31, 231), X_MASK, PPCVEC, { VS, RA, RB } }, |
4629 | { "stvxl" , X(31, 487), X_MASK, PPCVEC, { VS, RA, RB } }, |
4630 | |
4631 | /* New load/store left/right index vector instructions that are in the Cell only. */ |
4632 | { "lvlx" , X(31, 519), X_MASK, CELL, { VD, RA0, RB } }, |
4633 | { "lvlxl" , X(31, 775), X_MASK, CELL, { VD, RA0, RB } }, |
4634 | { "lvrx" , X(31, 551), X_MASK, CELL, { VD, RA0, RB } }, |
4635 | { "lvrxl" , X(31, 807), X_MASK, CELL, { VD, RA0, RB } }, |
4636 | { "stvlx" , X(31, 647), X_MASK, CELL, { VS, RA0, RB } }, |
4637 | { "stvlxl" , X(31, 903), X_MASK, CELL, { VS, RA0, RB } }, |
4638 | { "stvrx" , X(31, 679), X_MASK, CELL, { VS, RA0, RB } }, |
4639 | { "stvrxl" , X(31, 935), X_MASK, CELL, { VS, RA0, RB } }, |
4640 | |
4641 | { "lwz" , OP(32), OP_MASK, PPCCOM, { RT, D, RA0 } }, |
4642 | { "l" , OP(32), OP_MASK, PWRCOM, { RT, D, RA0 } }, |
4643 | |
4644 | { "lwzu" , OP(33), OP_MASK, PPCCOM, { RT, D, RAL } }, |
4645 | { "lu" , OP(33), OP_MASK, PWRCOM, { RT, D, RA0 } }, |
4646 | |
4647 | { "lbz" , OP(34), OP_MASK, COM, { RT, D, RA0 } }, |
4648 | |
4649 | { "lbzu" , OP(35), OP_MASK, COM, { RT, D, RAL } }, |
4650 | |
4651 | { "stw" , OP(36), OP_MASK, PPCCOM, { RS, D, RA0 } }, |
4652 | { "st" , OP(36), OP_MASK, PWRCOM, { RS, D, RA0 } }, |
4653 | |
4654 | { "stwu" , OP(37), OP_MASK, PPCCOM, { RS, D, RAS } }, |
4655 | { "stu" , OP(37), OP_MASK, PWRCOM, { RS, D, RA0 } }, |
4656 | |
4657 | { "stb" , OP(38), OP_MASK, COM, { RS, D, RA0 } }, |
4658 | |
4659 | { "stbu" , OP(39), OP_MASK, COM, { RS, D, RAS } }, |
4660 | |
4661 | { "lhz" , OP(40), OP_MASK, COM, { RT, D, RA0 } }, |
4662 | |
4663 | { "lhzu" , OP(41), OP_MASK, COM, { RT, D, RAL } }, |
4664 | |
4665 | { "lha" , OP(42), OP_MASK, COM, { RT, D, RA0 } }, |
4666 | |
4667 | { "lhau" , OP(43), OP_MASK, COM, { RT, D, RAL } }, |
4668 | |
4669 | { "sth" , OP(44), OP_MASK, COM, { RS, D, RA0 } }, |
4670 | |
4671 | { "sthu" , OP(45), OP_MASK, COM, { RS, D, RAS } }, |
4672 | |
4673 | { "lmw" , OP(46), OP_MASK, PPCCOM, { RT, D, RAM } }, |
4674 | { "lm" , OP(46), OP_MASK, PWRCOM, { RT, D, RA0 } }, |
4675 | |
4676 | { "stmw" , OP(47), OP_MASK, PPCCOM, { RS, D, RA0 } }, |
4677 | { "stm" , OP(47), OP_MASK, PWRCOM, { RS, D, RA0 } }, |
4678 | |
4679 | { "lfs" , OP(48), OP_MASK, COM, { FRT, D, RA0 } }, |
4680 | |
4681 | { "lfsu" , OP(49), OP_MASK, COM, { FRT, D, RAS } }, |
4682 | |
4683 | { "lfd" , OP(50), OP_MASK, COM, { FRT, D, RA0 } }, |
4684 | |
4685 | { "lfdu" , OP(51), OP_MASK, COM, { FRT, D, RAS } }, |
4686 | |
4687 | { "stfs" , OP(52), OP_MASK, COM, { FRS, D, RA0 } }, |
4688 | |
4689 | { "stfsu" , OP(53), OP_MASK, COM, { FRS, D, RAS } }, |
4690 | |
4691 | { "stfd" , OP(54), OP_MASK, COM, { FRS, D, RA0 } }, |
4692 | |
4693 | { "stfdu" , OP(55), OP_MASK, COM, { FRS, D, RAS } }, |
4694 | |
4695 | { "lq" , OP(56), OP_MASK, POWER4, { RTQ, DQ, RAQ } }, |
4696 | |
4697 | { "lfq" , OP(56), OP_MASK, POWER2, { FRT, D, RA0 } }, |
4698 | |
4699 | { "lfqu" , OP(57), OP_MASK, POWER2, { FRT, D, RA0 } }, |
4700 | |
4701 | { "lfdp" , OP(57), OP_MASK, POWER6, { FRT, D, RA0 } }, |
4702 | |
4703 | { "lbze" , DEO(58,0), DE_MASK, BOOKE64, { RT, DE, RA0 } }, |
4704 | { "lbzue" , DEO(58,1), DE_MASK, BOOKE64, { RT, DE, RAL } }, |
4705 | { "lhze" , DEO(58,2), DE_MASK, BOOKE64, { RT, DE, RA0 } }, |
4706 | { "lhzue" , DEO(58,3), DE_MASK, BOOKE64, { RT, DE, RAL } }, |
4707 | { "lhae" , DEO(58,4), DE_MASK, BOOKE64, { RT, DE, RA0 } }, |
4708 | { "lhaue" , DEO(58,5), DE_MASK, BOOKE64, { RT, DE, RAL } }, |
4709 | { "lwze" , DEO(58,6), DE_MASK, BOOKE64, { RT, DE, RA0 } }, |
4710 | { "lwzue" , DEO(58,7), DE_MASK, BOOKE64, { RT, DE, RAL } }, |
4711 | { "stbe" , DEO(58,8), DE_MASK, BOOKE64, { RS, DE, RA0 } }, |
4712 | { "stbue" , DEO(58,9), DE_MASK, BOOKE64, { RS, DE, RAS } }, |
4713 | { "sthe" , DEO(58,10), DE_MASK, BOOKE64, { RS, DE, RA0 } }, |
4714 | { "sthue" , DEO(58,11), DE_MASK, BOOKE64, { RS, DE, RAS } }, |
4715 | { "stwe" , DEO(58,14), DE_MASK, BOOKE64, { RS, DE, RA0 } }, |
4716 | { "stwue" , DEO(58,15), DE_MASK, BOOKE64, { RS, DE, RAS } }, |
4717 | |
4718 | { "ld" , DSO(58,0), DS_MASK, PPC64, { RT, DS, RA0 } }, |
4719 | |
4720 | { "ldu" , DSO(58,1), DS_MASK, PPC64, { RT, DS, RAL } }, |
4721 | |
4722 | { "lwa" , DSO(58,2), DS_MASK, PPC64, { RT, DS, RA0 } }, |
4723 | |
4724 | { "dadd" , XRC(59,2,0), X_MASK, POWER6, { FRT, FRA, FRB } }, |
4725 | { "dadd." , XRC(59,2,1), X_MASK, POWER6, { FRT, FRA, FRB } }, |
4726 | |
4727 | { "dqua" , ZRC(59,3,0), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } }, |
4728 | { "dqua." , ZRC(59,3,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } }, |
4729 | |
4730 | { "fdivs" , A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, |
4731 | { "fdivs." , A(59,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } }, |
4732 | |
4733 | { "fsubs" , A(59,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, |
4734 | { "fsubs." , A(59,20,1), AFRC_MASK, PPC, { FRT, FRA, FRB } }, |
4735 | |
4736 | { "fadds" , A(59,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, |
4737 | { "fadds." , A(59,21,1), AFRC_MASK, PPC, { FRT, FRA, FRB } }, |
4738 | |
4739 | { "fsqrts" , A(59,22,0), AFRAFRC_MASK, PPC, { FRT, FRB } }, |
4740 | { "fsqrts." , A(59,22,1), AFRAFRC_MASK, PPC, { FRT, FRB } }, |
4741 | |
4742 | { "fres" , A(59,24,0), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } }, |
4743 | { "fres." , A(59,24,1), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } }, |
4744 | |
4745 | { "fmuls" , A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } }, |
4746 | { "fmuls." , A(59,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } }, |
4747 | |
4748 | { "frsqrtes" , A(59,26,0), AFRALFRC_MASK,POWER5, { FRT, FRB, A_L } }, |
4749 | { "frsqrtes." ,A(59,26,1), AFRALFRC_MASK,POWER5, { FRT, FRB, A_L } }, |
4750 | |
4751 | { "fmsubs" , A(59,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, |
4752 | { "fmsubs." , A(59,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, |
4753 | |
4754 | { "fmadds" , A(59,29,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, |
4755 | { "fmadds." , A(59,29,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, |
4756 | |
4757 | { "fnmsubs" , A(59,30,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, |
4758 | { "fnmsubs." ,A(59,30,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, |
4759 | |
4760 | { "fnmadds" , A(59,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, |
4761 | { "fnmadds." ,A(59,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, |
4762 | |
4763 | { "dmul" , XRC(59,34,0), X_MASK, POWER6, { FRT, FRA, FRB } }, |
4764 | { "dmul." , XRC(59,34,1), X_MASK, POWER6, { FRT, FRA, FRB } }, |
4765 | |
4766 | { "drrnd" , ZRC(59,35,0), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } }, |
4767 | { "drrnd." , ZRC(59,35,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } }, |
4768 | |
4769 | { "dscli" , ZRC(59,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, |
4770 | { "dscli." , ZRC(59,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } }, |
4771 | |
4772 | { "dquai" , ZRC(59,67,0), Z2_MASK, POWER6, { TE, FRT, FRB, RMC } }, |
4773 | { "dquai." , ZRC(59,67,1), Z2_MASK, POWER6, { TE, FRT, FRB, RMC } }, |
4774 | |
4775 | { "dscri" , ZRC(59,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, |
4776 | { "dscri." , ZRC(59,98,1), Z_MASK, POWER6, { FRT, FRA, SH16 } }, |
4777 | |
4778 | { "drintx" , ZRC(59,99,0), Z2_MASK, POWER6, { R, FRT, FRB, RMC } }, |
4779 | { "drintx." , ZRC(59,99,1), Z2_MASK, POWER6, { R, FRT, FRB, RMC } }, |
4780 | |
4781 | { "dcmpo" , X(59,130), X_MASK, POWER6, { BF, FRA, FRB } }, |
4782 | |
4783 | { "dtstex" , X(59,162), X_MASK, POWER6, { BF, FRA, FRB } }, |
4784 | { "dtstdc" , Z(59,194), Z_MASK, POWER6, { BF, FRA, DCM } }, |
4785 | { "dtstdg" , Z(59,226), Z_MASK, POWER6, { BF, FRA, DGM } }, |
4786 | |
4787 | { "drintn" , ZRC(59,227,0), Z2_MASK, POWER6, { R, FRT, FRB, RMC } }, |
4788 | { "drintn." , ZRC(59,227,1), Z2_MASK, POWER6, { R, FRT, FRB, RMC } }, |
4789 | |
4790 | { "dctdp" , XRC(59,258,0), X_MASK, POWER6, { FRT, FRB } }, |
4791 | { "dctdp." , XRC(59,258,1), X_MASK, POWER6, { FRT, FRB } }, |
4792 | |
4793 | { "dctfix" , XRC(59,290,0), X_MASK, POWER6, { FRT, FRB } }, |
4794 | { "dctfix." , XRC(59,290,1), X_MASK, POWER6, { FRT, FRB } }, |
4795 | |
4796 | { "ddedpd" , XRC(59,322,0), X_MASK, POWER6, { SP, FRT, FRB } }, |
4797 | { "ddedpd." , XRC(59,322,1), X_MASK, POWER6, { SP, FRT, FRB } }, |
4798 | |
4799 | { "dxex" , XRC(59,354,0), X_MASK, POWER6, { FRT, FRB } }, |
4800 | { "dxex." , XRC(59,354,1), X_MASK, POWER6, { FRT, FRB } }, |
4801 | |
4802 | { "dsub" , XRC(59,514,0), X_MASK, POWER6, { FRT, FRA, FRB } }, |
4803 | { "dsub." , XRC(59,514,1), X_MASK, POWER6, { FRT, FRA, FRB } }, |
4804 | |
4805 | { "ddiv" , XRC(59,546,0), X_MASK, POWER6, { FRT, FRA, FRB } }, |
4806 | { "ddiv." , XRC(59,546,1), X_MASK, POWER6, { FRT, FRA, FRB } }, |
4807 | |
4808 | { "dcmpu" , X(59,642), X_MASK, POWER6, { BF, FRA, FRB } }, |
4809 | |
4810 | { "dtstsf" , X(59,674), X_MASK, POWER6, { BF, FRA, FRB } }, |
4811 | |
4812 | { "drsp" , XRC(59,770,0), X_MASK, POWER6, { FRT, FRB } }, |
4813 | { "drsp." , XRC(59,770,1), X_MASK, POWER6, { FRT, FRB } }, |
4814 | |
4815 | { "dcffix" , XRC(59,802,0), X_MASK, POWER6, { FRT, FRB } }, |
4816 | { "dcffix." , XRC(59,802,1), X_MASK, POWER6, { FRT, FRB } }, |
4817 | |
4818 | { "denbcd" , XRC(59,834,0), X_MASK, POWER6, { S, FRT, FRB } }, |
4819 | { "denbcd." , XRC(59,834,1), X_MASK, POWER6, { S, FRT, FRB } }, |
4820 | |
4821 | { "diex" , XRC(59,866,0), X_MASK, POWER6, { FRT, FRA, FRB } }, |
4822 | { "diex." , XRC(59,866,1), X_MASK, POWER6, { FRT, FRA, FRB } }, |
4823 | |
4824 | { "stfq" , OP(60), OP_MASK, POWER2, { FRS, D, RA } }, |
4825 | |
4826 | { "stfqu" , OP(61), OP_MASK, POWER2, { FRS, D, RA } }, |
4827 | |
4828 | { "stfdp" , OP(61), OP_MASK, POWER6, { FRT, D, RA0 } }, |
4829 | |
4830 | { "lde" , DEO(62,0), DE_MASK, BOOKE64, { RT, DES, RA0 } }, |
4831 | { "ldue" , DEO(62,1), DE_MASK, BOOKE64, { RT, DES, RA0 } }, |
4832 | { "lfse" , DEO(62,4), DE_MASK, BOOKE64, { FRT, DES, RA0 } }, |
4833 | { "lfsue" , DEO(62,5), DE_MASK, BOOKE64, { FRT, DES, RAS } }, |
4834 | { "lfde" , DEO(62,6), DE_MASK, BOOKE64, { FRT, DES, RA0 } }, |
4835 | { "lfdue" , DEO(62,7), DE_MASK, BOOKE64, { FRT, DES, RAS } }, |
4836 | { "stde" , DEO(62,8), DE_MASK, BOOKE64, { RS, DES, RA0 } }, |
4837 | { "stdue" , DEO(62,9), DE_MASK, BOOKE64, { RS, DES, RAS } }, |
4838 | { "stfse" , DEO(62,12), DE_MASK, BOOKE64, { FRS, DES, RA0 } }, |
4839 | { "stfsue" , DEO(62,13), DE_MASK, BOOKE64, { FRS, DES, RAS } }, |
4840 | { "stfde" , DEO(62,14), DE_MASK, BOOKE64, { FRS, DES, RA0 } }, |
4841 | { "stfdue" , DEO(62,15), DE_MASK, BOOKE64, { FRS, DES, RAS } }, |
4842 | |
4843 | { "std" , DSO(62,0), DS_MASK, PPC64, { RS, DS, RA0 } }, |
4844 | |
4845 | { "stdu" , DSO(62,1), DS_MASK, PPC64, { RS, DS, RAS } }, |
4846 | |
4847 | { "stq" , DSO(62,2), DS_MASK, POWER4, { RSQ, DS, RA0 } }, |
4848 | |
4849 | { "fcmpu" , X(63,0), X_MASK|(3<<21), COM, { BF, FRA, FRB } }, |
4850 | |
4851 | { "daddq" , XRC(63,2,0), X_MASK, POWER6, { FRT, FRA, FRB } }, |
4852 | { "daddq." , XRC(63,2,1), X_MASK, POWER6, { FRT, FRA, FRB } }, |
4853 | |
4854 | { "dquaq" , ZRC(63,3,0), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } }, |
4855 | { "dquaq." , ZRC(63,3,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } }, |
4856 | |
4857 | { "fcpsgn" , XRC(63,8,0), X_MASK, POWER6, { FRT, FRA, FRB } }, |
4858 | { "fcpsgn." , XRC(63,8,1), X_MASK, POWER6, { FRT, FRA, FRB } }, |
4859 | |
4860 | { "frsp" , XRC(63,12,0), XRA_MASK, COM, { FRT, FRB } }, |
4861 | { "frsp." , XRC(63,12,1), XRA_MASK, COM, { FRT, FRB } }, |
4862 | |
4863 | { "fctiw" , XRC(63,14,0), XRA_MASK, PPCCOM, { FRT, FRB } }, |
4864 | { "fcir" , XRC(63,14,0), XRA_MASK, POWER2, { FRT, FRB } }, |
4865 | { "fctiw." , XRC(63,14,1), XRA_MASK, PPCCOM, { FRT, FRB } }, |
4866 | { "fcir." , XRC(63,14,1), XRA_MASK, POWER2, { FRT, FRB } }, |
4867 | |
4868 | { "fctiwz" , XRC(63,15,0), XRA_MASK, PPCCOM, { FRT, FRB } }, |
4869 | { "fcirz" , XRC(63,15,0), XRA_MASK, POWER2, { FRT, FRB } }, |
4870 | { "fctiwz." , XRC(63,15,1), XRA_MASK, PPCCOM, { FRT, FRB } }, |
4871 | { "fcirz." , XRC(63,15,1), XRA_MASK, POWER2, { FRT, FRB } }, |
4872 | |
4873 | { "fdiv" , A(63,18,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, |
4874 | { "fd" , A(63,18,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } }, |
4875 | { "fdiv." , A(63,18,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, |
4876 | { "fd." , A(63,18,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } }, |
4877 | |
4878 | { "fsub" , A(63,20,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, |
4879 | { "fs" , A(63,20,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } }, |
4880 | { "fsub." , A(63,20,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, |
4881 | { "fs." , A(63,20,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } }, |
4882 | |
4883 | { "fadd" , A(63,21,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, |
4884 | { "fa" , A(63,21,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } }, |
4885 | { "fadd." , A(63,21,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, |
4886 | { "fa." , A(63,21,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } }, |
4887 | |
4888 | { "fsqrt" , A(63,22,0), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } }, |
4889 | { "fsqrt." , A(63,22,1), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } }, |
4890 | |
4891 | { "fsel" , A(63,23,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, |
4892 | { "fsel." , A(63,23,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, |
4893 | |
4894 | { "fre" , A(63,24,0), AFRALFRC_MASK, POWER5, { FRT, FRB, A_L } }, |
4895 | { "fre." , A(63,24,1), AFRALFRC_MASK, POWER5, { FRT, FRB, A_L } }, |
4896 | |
4897 | { "fmul" , A(63,25,0), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } }, |
4898 | { "fm" , A(63,25,0), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } }, |
4899 | { "fmul." , A(63,25,1), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } }, |
4900 | { "fm." , A(63,25,1), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } }, |
4901 | |
4902 | { "frsqrte" , A(63,26,0), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } }, |
4903 | { "frsqrte." ,A(63,26,1), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } }, |
4904 | |
4905 | { "fmsub" , A(63,28,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, |
4906 | { "fms" , A(63,28,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, |
4907 | { "fmsub." , A(63,28,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, |
4908 | { "fms." , A(63,28,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, |
4909 | |
4910 | { "fmadd" , A(63,29,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, |
4911 | { "fma" , A(63,29,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, |
4912 | { "fmadd." , A(63,29,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, |
4913 | { "fma." , A(63,29,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, |
4914 | |
4915 | { "fnmsub" , A(63,30,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, |
4916 | { "fnms" , A(63,30,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, |
4917 | { "fnmsub." , A(63,30,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, |
4918 | { "fnms." , A(63,30,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, |
4919 | |
4920 | { "fnmadd" , A(63,31,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, |
4921 | { "fnma" , A(63,31,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, |
4922 | { "fnmadd." , A(63,31,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, |
4923 | { "fnma." , A(63,31,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, |
4924 | |
4925 | { "fcmpo" , X(63,32), X_MASK|(3<<21), COM, { BF, FRA, FRB } }, |
4926 | |
4927 | { "dmulq" , XRC(63,34,0), X_MASK, POWER6, { FRT, FRA, FRB } }, |
4928 | { "dmulq." , XRC(63,34,1), X_MASK, POWER6, { FRT, FRA, FRB } }, |
4929 | |
4930 | { "drrndq" , ZRC(63,35,0), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } }, |
4931 | { "drrndq." , ZRC(63,35,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } }, |
4932 | |
4933 | { "mtfsb1" , XRC(63,38,0), XRARB_MASK, COM, { BT } }, |
4934 | { "mtfsb1." , XRC(63,38,1), XRARB_MASK, COM, { BT } }, |
4935 | |
4936 | { "fneg" , XRC(63,40,0), XRA_MASK, COM, { FRT, FRB } }, |
4937 | { "fneg." , XRC(63,40,1), XRA_MASK, COM, { FRT, FRB } }, |
4938 | |
4939 | { "mcrfs" , X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } }, |
4940 | |
4941 | { "dscliq" , ZRC(63,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, |
4942 | { "dscliq." , ZRC(63,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } }, |
4943 | |
4944 | { "dquaiq" , ZRC(63,67,0), Z2_MASK, POWER6, { TE, FRT, FRB, RMC } }, |
4945 | { "dquaiq." , ZRC(63,67,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } }, |
4946 | |
4947 | { "mtfsb0" , XRC(63,70,0), XRARB_MASK, COM, { BT } }, |
4948 | { "mtfsb0." , XRC(63,70,1), XRARB_MASK, COM, { BT } }, |
4949 | |
4950 | { "fmr" , XRC(63,72,0), XRA_MASK, COM, { FRT, FRB } }, |
4951 | { "fmr." , XRC(63,72,1), XRA_MASK, COM, { FRT, FRB } }, |
4952 | |
4953 | { "dscriq" , ZRC(63,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, |
4954 | { "dscriq." , ZRC(63,98,1), Z_MASK, POWER6, { FRT, FRA, SH16 } }, |
4955 | |
4956 | { "drintxq" , ZRC(63,99,0), Z2_MASK, POWER6, { R, FRT, FRB, RMC } }, |
4957 | { "drintxq." ,ZRC(63,99,1), Z2_MASK, POWER6, { R, FRT, FRB, RMC } }, |
4958 | |
4959 | { "dcmpoq" , X(63,130), X_MASK, POWER6, { BF, FRA, FRB } }, |
4960 | |
4961 | { "mtfsfi" , XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), COM, { BFF, U, W } }, |
4962 | { "mtfsfi." , XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), COM, { BFF, U, W } }, |
4963 | |
4964 | { "fnabs" , XRC(63,136,0), XRA_MASK, COM, { FRT, FRB } }, |
4965 | { "fnabs." , XRC(63,136,1), XRA_MASK, COM, { FRT, FRB } }, |
4966 | |
4967 | { "dtstexq" , X(63,162), X_MASK, POWER6, { BF, FRA, FRB } }, |
4968 | { "dtstdcq" , Z(63,194), Z_MASK, POWER6, { BF, FRA, DCM } }, |
4969 | { "dtstdgq" , Z(63,226), Z_MASK, POWER6, { BF, FRA, DGM } }, |
4970 | |
4971 | { "drintnq" , ZRC(63,227,0), Z2_MASK, POWER6, { R, FRT, FRB, RMC } }, |
4972 | { "drintnq." ,ZRC(63,227,1), Z2_MASK, POWER6, { R, FRT, FRB, RMC } }, |
4973 | |
4974 | { "dctqpq" , XRC(63,258,0), X_MASK, POWER6, { FRT, FRB } }, |
4975 | { "dctqpq." , XRC(63,258,1), X_MASK, POWER6, { FRT, FRB } }, |
4976 | |
4977 | { "fabs" , XRC(63,264,0), XRA_MASK, COM, { FRT, FRB } }, |
4978 | { "fabs." , XRC(63,264,1), XRA_MASK, COM, { FRT, FRB } }, |
4979 | |
4980 | { "dctfixq" , XRC(63,290,0), X_MASK, POWER6, { FRT, FRB } }, |
4981 | { "dctfixq." ,XRC(63,290,1), X_MASK, POWER6, { FRT, FRB } }, |
4982 | |
4983 | { "ddedpdq" , XRC(63,322,0), X_MASK, POWER6, { SP, FRT, FRB } }, |
4984 | { "ddedpdq." ,XRC(63,322,1), X_MASK, POWER6, { SP, FRT, FRB } }, |
4985 | |
4986 | { "dxexq" , XRC(63,354,0), X_MASK, POWER6, { FRT, FRB } }, |
4987 | { "dxexq." , XRC(63,354,1), X_MASK, POWER6, { FRT, FRB } }, |
4988 | |
4989 | { "frin" , XRC(63,392,0), XRA_MASK, POWER5, { FRT, FRB } }, |
4990 | { "frin." , XRC(63,392,1), XRA_MASK, POWER5, { FRT, FRB } }, |
4991 | { "friz" , XRC(63,424,0), XRA_MASK, POWER5, { FRT, FRB } }, |
4992 | { "friz." , XRC(63,424,1), XRA_MASK, POWER5, { FRT, FRB } }, |
4993 | { "frip" , XRC(63,456,0), XRA_MASK, POWER5, { FRT, FRB } }, |
4994 | { "frip." , XRC(63,456,1), XRA_MASK, POWER5, { FRT, FRB } }, |
4995 | { "frim" , XRC(63,488,0), XRA_MASK, POWER5, { FRT, FRB } }, |
4996 | { "frim." , XRC(63,488,1), XRA_MASK, POWER5, { FRT, FRB } }, |
4997 | |
4998 | { "dsubq" , XRC(63,514,0), X_MASK, POWER6, { FRT, FRA, FRB } }, |
4999 | { "dsubq." , XRC(63,514,1), X_MASK, POWER6, { FRT, FRA, FRB } }, |
5000 | |
5001 | { "ddivq" , XRC(63,546,0), X_MASK, POWER6, { FRT, FRA, FRB } }, |
5002 | { "ddivq." , XRC(63,546,1), X_MASK, POWER6, { FRT, FRA, FRB } }, |
5003 | |
5004 | { "mffsl" , XRA(63,583,12), XRARB_MASK, POWER9, { FRT } }, |
5005 | |
5006 | { "mffs" , XRC(63,583,0), XRARB_MASK, COM, { FRT } }, |
5007 | { "mffs." , XRC(63,583,1), XRARB_MASK, COM, { FRT } }, |
5008 | |
5009 | { "dcmpuq" , X(63,642), X_MASK, POWER6, { BF, FRA, FRB } }, |
5010 | |
5011 | { "dtstsfq" , X(63,674), X_MASK, POWER6, { BF, FRA, FRB } }, |
5012 | |
5013 | { "mtfsf" , XFL(63,711,0), XFL_MASK, COM, { FLM, FRB, XFL_L, W } }, |
5014 | { "mtfsf." , XFL(63,711,1), XFL_MASK, COM, { FLM, FRB, XFL_L, W } }, |
5015 | |
5016 | { "drdpq" , XRC(63,770,0), X_MASK, POWER6, { FRT, FRB } }, |
5017 | { "drdpq." , XRC(63,770,1), X_MASK, POWER6, { FRT, FRB } }, |
5018 | |
5019 | { "dcffixq" , XRC(63,802,0), X_MASK, POWER6, { FRT, FRB } }, |
5020 | { "dcffixq." ,XRC(63,802,1), X_MASK, POWER6, { FRT, FRB } }, |
5021 | |
5022 | { "fctid" , XRC(63,814,0), XRA_MASK, PPC64, { FRT, FRB } }, |
5023 | { "fctid." , XRC(63,814,1), XRA_MASK, PPC64, { FRT, FRB } }, |
5024 | |
5025 | { "fctidz" , XRC(63,815,0), XRA_MASK, PPC64, { FRT, FRB } }, |
5026 | { "fctidz." , XRC(63,815,1), XRA_MASK, PPC64, { FRT, FRB } }, |
5027 | |
5028 | { "denbcdq" , XRC(63,834,0), X_MASK, POWER6, { S, FRT, FRB } }, |
5029 | { "denbcdq." ,XRC(63,834,1), X_MASK, POWER6, { S, FRT, FRB } }, |
5030 | |
5031 | { "fcfid" , XRC(63,846,0), XRA_MASK, PPC64, { FRT, FRB } }, |
5032 | { "fcfid." , XRC(63,846,1), XRA_MASK, PPC64, { FRT, FRB } }, |
5033 | |
5034 | { "diexq" , XRC(63,866,0), X_MASK, POWER6, { FRT, FRA, FRB } }, |
5035 | { "diexq." , XRC(63,866,1), X_MASK, POWER6, { FRT, FRA, FRB } }, |
5036 | |
5037 | }; |
5038 | |
5039 | const int powerpc_num_opcodes = |
5040 | sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]); |
5041 | |
5042 | /* The macro table. This is only used by the assembler. */ |
5043 | |
5044 | /* The expressions of the form (-x ! 31) & (x | 31) have the value 0 |
5045 | when x=0; 32-x when x is between 1 and 31; are negative if x is |
5046 | negative; and are 32 or more otherwise. This is what you want |
5047 | when, for instance, you are emulating a right shift by a |
5048 | rotate-left-and-mask, because the underlying instructions support |
5049 | shifts of size 0 but not shifts of size 32. By comparison, when |
5050 | extracting x bits from some word you want to use just 32-x, because |
5051 | the underlying instructions don't support extracting 0 bits but do |
5052 | support extracting the whole word (32 bits in this case). */ |
5053 | |
5054 | const struct powerpc_macro powerpc_macros[] = { |
5055 | { "extldi" , 4, PPC64, "rldicr %0,%1,%3,(%2)-1" }, |
5056 | { "extldi." , 4, PPC64, "rldicr. %0,%1,%3,(%2)-1" }, |
5057 | { "extrdi" , 4, PPC64, "rldicl %0,%1,(%2)+(%3),64-(%2)" }, |
5058 | { "extrdi." , 4, PPC64, "rldicl. %0,%1,(%2)+(%3),64-(%2)" }, |
5059 | { "insrdi" , 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3" }, |
5060 | { "insrdi." , 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3" }, |
5061 | { "rotrdi" , 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0" }, |
5062 | { "rotrdi." , 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0" }, |
5063 | { "sldi" , 3, PPC64, "rldicr %0,%1,%2,63-(%2)" }, |
5064 | { "sldi." , 3, PPC64, "rldicr. %0,%1,%2,63-(%2)" }, |
5065 | { "srdi" , 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2" }, |
5066 | { "srdi." , 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2" }, |
5067 | { "clrrdi" , 3, PPC64, "rldicr %0,%1,0,63-(%2)" }, |
5068 | { "clrrdi." , 3, PPC64, "rldicr. %0,%1,0,63-(%2)" }, |
5069 | { "clrlsldi" ,4, PPC64, "rldic %0,%1,%3,(%2)-(%3)" }, |
5070 | { "clrlsldi." ,4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)" }, |
5071 | |
5072 | { "extlwi" , 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1" }, |
5073 | { "extlwi." , 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1" }, |
5074 | { "extrwi" , 4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" }, |
5075 | { "extrwi." , 4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" }, |
5076 | { "inslwi" , 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1" }, |
5077 | { "inslwi." , 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1" }, |
5078 | { "insrwi" , 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" }, |
5079 | { "insrwi." , 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" }, |
5080 | { "rotrwi" , 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31" }, |
5081 | { "rotrwi." , 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31" }, |
5082 | { "slwi" , 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)" }, |
5083 | { "sli" , 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)" }, |
5084 | { "slwi." , 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)" }, |
5085 | { "sli." , 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)" }, |
5086 | { "srwi" , 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" }, |
5087 | { "sri" , 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" }, |
5088 | { "srwi." , 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" }, |
5089 | { "sri." , 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" }, |
5090 | { "clrrwi" , 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)" }, |
5091 | { "clrrwi." , 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)" }, |
5092 | { "clrlslwi" ,4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" }, |
5093 | { "clrlslwi." ,4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" }, |
5094 | }; |
5095 | |
5096 | const int powerpc_num_macros = |
5097 | sizeof (powerpc_macros) / sizeof (powerpc_macros[0]); |
5098 | |
5099 | |
5100 | /* This file provides several disassembler functions, all of which use |
5101 | the disassembler interface defined in dis-asm.h. Several functions |
5102 | are provided because this file handles disassembly for the PowerPC |
5103 | in both big and little endian mode and also for the POWER (RS/6000) |
5104 | chip. */ |
5105 | |
5106 | static int print_insn_powerpc (bfd_vma, struct disassemble_info *, int, int); |
5107 | |
5108 | /* Determine which set of machines to disassemble for. PPC403/601 or |
5109 | BookE. For convenience, also disassemble instructions supported |
5110 | by the AltiVec vector unit. */ |
5111 | |
5112 | static int |
5113 | powerpc_dialect (struct disassemble_info *info) |
5114 | { |
5115 | int dialect = PPC_OPCODE_PPC; |
5116 | |
5117 | if (BFD_DEFAULT_TARGET_SIZE == 64) |
5118 | dialect |= PPC_OPCODE_64; |
5119 | |
5120 | if (info->disassembler_options |
5121 | && strstr (info->disassembler_options, "booke" ) != NULL) |
5122 | dialect |= PPC_OPCODE_BOOKE | PPC_OPCODE_BOOKE64; |
5123 | else if ((info->mach == bfd_mach_ppc_e500) |
5124 | || (info->disassembler_options |
5125 | && strstr (info->disassembler_options, "e500" ) != NULL)) |
5126 | dialect |= (PPC_OPCODE_BOOKE |
5127 | | PPC_OPCODE_SPE | PPC_OPCODE_ISEL |
5128 | | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK |
5129 | | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK |
5130 | | PPC_OPCODE_RFMCI); |
5131 | else if (info->disassembler_options |
5132 | && strstr (info->disassembler_options, "efs" ) != NULL) |
5133 | dialect |= PPC_OPCODE_EFS; |
5134 | else if (info->disassembler_options |
5135 | && strstr (info->disassembler_options, "e300" ) != NULL) |
5136 | dialect |= PPC_OPCODE_E300 | PPC_OPCODE_CLASSIC | PPC_OPCODE_COMMON; |
5137 | else if (info->disassembler_options |
5138 | && strstr (info->disassembler_options, "440" ) != NULL) |
5139 | dialect |= PPC_OPCODE_BOOKE | PPC_OPCODE_32 |
5140 | | PPC_OPCODE_440 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI; |
5141 | else |
5142 | dialect |= (PPC_OPCODE_403 | PPC_OPCODE_601 | PPC_OPCODE_CLASSIC |
5143 | | PPC_OPCODE_COMMON | PPC_OPCODE_ALTIVEC); |
5144 | |
5145 | if (info->disassembler_options |
5146 | && strstr (info->disassembler_options, "power4" ) != NULL) |
5147 | dialect |= PPC_OPCODE_POWER4; |
5148 | |
5149 | if (info->disassembler_options |
5150 | && strstr (info->disassembler_options, "power5" ) != NULL) |
5151 | dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5; |
5152 | |
5153 | if (info->disassembler_options |
5154 | && strstr (info->disassembler_options, "cell" ) != NULL) |
5155 | dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC; |
5156 | |
5157 | if (info->disassembler_options |
5158 | && strstr (info->disassembler_options, "power6" ) != NULL) |
5159 | dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC; |
5160 | |
5161 | if (info->disassembler_options |
5162 | && strstr (info->disassembler_options, "any" ) != NULL) |
5163 | dialect |= PPC_OPCODE_ANY; |
5164 | |
5165 | if (info->disassembler_options) |
5166 | { |
5167 | if (strstr (info->disassembler_options, "32" ) != NULL) |
5168 | dialect &= ~PPC_OPCODE_64; |
5169 | else if (strstr (info->disassembler_options, "64" ) != NULL) |
5170 | dialect |= PPC_OPCODE_64; |
5171 | } |
5172 | |
5173 | info->private_data = (char *) 0 + dialect; |
5174 | return dialect; |
5175 | } |
5176 | |
5177 | /* QEMU default */ |
5178 | int |
5179 | print_insn_ppc (bfd_vma memaddr, struct disassemble_info *info) |
5180 | { |
5181 | int dialect = (char *) info->private_data - (char *) 0; |
5182 | return print_insn_powerpc (memaddr, info, info->endian == BFD_ENDIAN_BIG, |
5183 | dialect); |
5184 | } |
5185 | |
5186 | /* Print a big endian PowerPC instruction. */ |
5187 | |
5188 | int |
5189 | print_insn_big_powerpc (bfd_vma memaddr, struct disassemble_info *info) |
5190 | { |
5191 | int dialect = (char *) info->private_data - (char *) 0; |
5192 | return print_insn_powerpc (memaddr, info, 1, dialect); |
5193 | } |
5194 | |
5195 | /* Print a little endian PowerPC instruction. */ |
5196 | |
5197 | int |
5198 | print_insn_little_powerpc (bfd_vma memaddr, struct disassemble_info *info) |
5199 | { |
5200 | int dialect = (char *) info->private_data - (char *) 0; |
5201 | return print_insn_powerpc (memaddr, info, 0, dialect); |
5202 | } |
5203 | |
5204 | /* Print a POWER (RS/6000) instruction. */ |
5205 | |
5206 | int |
5207 | print_insn_rs6000 (bfd_vma memaddr, struct disassemble_info *info) |
5208 | { |
5209 | return print_insn_powerpc (memaddr, info, 1, PPC_OPCODE_POWER); |
5210 | } |
5211 | |
5212 | /* Extract the operand value from the PowerPC or POWER instruction. */ |
5213 | |
5214 | static long |
5215 | operand_value_powerpc (const struct powerpc_operand *operand, |
5216 | unsigned long insn, int dialect) |
5217 | { |
5218 | long value; |
5219 | int invalid; |
5220 | /* Extract the value from the instruction. */ |
5221 | if (operand->extract) |
5222 | value = (*operand->extract) (insn, dialect, &invalid); |
5223 | else |
5224 | { |
5225 | value = (insn >> operand->shift) & operand->bitm; |
5226 | if ((operand->flags & PPC_OPERAND_SIGNED) != 0) |
5227 | { |
5228 | /* BITM is always some number of zeros followed by some |
5229 | number of ones, followed by some numer of zeros. */ |
5230 | unsigned long top = operand->bitm; |
5231 | /* top & -top gives the rightmost 1 bit, so this |
5232 | fills in any trailing zeros. */ |
5233 | top |= (top & -top) - 1; |
5234 | top &= ~(top >> 1); |
5235 | value = (value ^ top) - top; |
5236 | } |
5237 | } |
5238 | |
5239 | return value; |
5240 | } |
5241 | |
5242 | /* Determine whether the optional operand(s) should be printed. */ |
5243 | |
5244 | static int |
5245 | skip_optional_operands (const unsigned char *opindex, |
5246 | unsigned long insn, int dialect) |
5247 | { |
5248 | const struct powerpc_operand *operand; |
5249 | |
5250 | for (; *opindex != 0; opindex++) |
5251 | { |
5252 | operand = &powerpc_operands[*opindex]; |
5253 | if ((operand->flags & PPC_OPERAND_NEXT) != 0 |
5254 | || ((operand->flags & PPC_OPERAND_OPTIONAL) != 0 |
5255 | && operand_value_powerpc (operand, insn, dialect) != 0)) |
5256 | return 0; |
5257 | } |
5258 | |
5259 | return 1; |
5260 | } |
5261 | |
5262 | /* Print a PowerPC or POWER instruction. */ |
5263 | |
5264 | static int |
5265 | print_insn_powerpc (bfd_vma memaddr, |
5266 | struct disassemble_info *info, |
5267 | int bigendian, |
5268 | int dialect) |
5269 | { |
5270 | bfd_byte buffer[4]; |
5271 | int status; |
5272 | unsigned long insn; |
5273 | const struct powerpc_opcode *opcode; |
5274 | const struct powerpc_opcode *opcode_end; |
5275 | unsigned long op; |
5276 | |
5277 | if (dialect == 0) |
5278 | dialect = powerpc_dialect (info); |
5279 | |
5280 | status = (*info->read_memory_func) (memaddr, buffer, 4, info); |
5281 | if (status != 0) |
5282 | { |
5283 | (*info->memory_error_func) (status, memaddr, info); |
5284 | return -1; |
5285 | } |
5286 | |
5287 | if (bigendian) |
5288 | insn = bfd_getb32 (buffer); |
5289 | else |
5290 | insn = bfd_getl32 (buffer); |
5291 | |
5292 | /* Get the major opcode of the instruction. */ |
5293 | op = PPC_OP (insn); |
5294 | |
5295 | /* Find the first match in the opcode table. We could speed this up |
5296 | a bit by doing a binary search on the major opcode. */ |
5297 | opcode_end = powerpc_opcodes + powerpc_num_opcodes; |
5298 | again: |
5299 | for (opcode = powerpc_opcodes; opcode < opcode_end; opcode++) |
5300 | { |
5301 | unsigned long table_op; |
5302 | const unsigned char *opindex; |
5303 | const struct powerpc_operand *operand; |
5304 | int invalid; |
5305 | int need_comma; |
5306 | int need_paren; |
5307 | int skip_optional; |
5308 | |
5309 | table_op = PPC_OP (opcode->opcode); |
5310 | if (op < table_op) |
5311 | break; |
5312 | if (op > table_op) |
5313 | continue; |
5314 | |
5315 | if ((insn & opcode->mask) != opcode->opcode |
5316 | || (opcode->flags & dialect) == 0) |
5317 | continue; |
5318 | |
5319 | /* Make two passes over the operands. First see if any of them |
5320 | have extraction functions, and, if they do, make sure the |
5321 | instruction is valid. */ |
5322 | invalid = 0; |
5323 | for (opindex = opcode->operands; *opindex != 0; opindex++) |
5324 | { |
5325 | operand = powerpc_operands + *opindex; |
5326 | if (operand->extract) |
5327 | (*operand->extract) (insn, dialect, &invalid); |
5328 | } |
5329 | if (invalid) |
5330 | continue; |
5331 | |
5332 | /* The instruction is valid. */ |
5333 | if (opcode->operands[0] != 0) |
5334 | (*info->fprintf_func) (info->stream, "%-7s " , opcode->name); |
5335 | else |
5336 | (*info->fprintf_func) (info->stream, "%s" , opcode->name); |
5337 | |
5338 | /* Now extract and print the operands. */ |
5339 | need_comma = 0; |
5340 | need_paren = 0; |
5341 | skip_optional = -1; |
5342 | for (opindex = opcode->operands; *opindex != 0; opindex++) |
5343 | { |
5344 | long value; |
5345 | |
5346 | operand = powerpc_operands + *opindex; |
5347 | |
5348 | /* Operands that are marked FAKE are simply ignored. We |
5349 | already made sure that the extract function considered |
5350 | the instruction to be valid. */ |
5351 | if ((operand->flags & PPC_OPERAND_FAKE) != 0) |
5352 | continue; |
5353 | |
5354 | /* If all of the optional operands have the value zero, |
5355 | then don't print any of them. */ |
5356 | if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0) |
5357 | { |
5358 | if (skip_optional < 0) |
5359 | skip_optional = skip_optional_operands (opindex, insn, |
5360 | dialect); |
5361 | if (skip_optional) |
5362 | continue; |
5363 | } |
5364 | |
5365 | value = operand_value_powerpc (operand, insn, dialect); |
5366 | |
5367 | if (need_comma) |
5368 | { |
5369 | (*info->fprintf_func) (info->stream, "," ); |
5370 | need_comma = 0; |
5371 | } |
5372 | |
5373 | /* Print the operand as directed by the flags. */ |
5374 | if ((operand->flags & PPC_OPERAND_GPR) != 0 |
5375 | || ((operand->flags & PPC_OPERAND_GPR_0) != 0 && value != 0)) |
5376 | (*info->fprintf_func) (info->stream, "r%ld" , value); |
5377 | else if ((operand->flags & PPC_OPERAND_FPR) != 0) |
5378 | (*info->fprintf_func) (info->stream, "f%ld" , value); |
5379 | else if ((operand->flags & PPC_OPERAND_VR) != 0) |
5380 | (*info->fprintf_func) (info->stream, "v%ld" , value); |
5381 | else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0) |
5382 | (*info->print_address_func) (memaddr + value, info); |
5383 | else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0) |
5384 | (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info); |
5385 | else if ((operand->flags & PPC_OPERAND_CR) == 0 |
5386 | || (dialect & PPC_OPCODE_PPC) == 0) |
5387 | (*info->fprintf_func) (info->stream, "%ld" , value); |
5388 | else |
5389 | { |
5390 | if (operand->bitm == 7) |
5391 | (*info->fprintf_func) (info->stream, "cr%ld" , value); |
5392 | else |
5393 | { |
5394 | static const char *cbnames[4] = { "lt" , "gt" , "eq" , "so" }; |
5395 | int cr; |
5396 | int cc; |
5397 | |
5398 | cr = value >> 2; |
5399 | if (cr != 0) |
5400 | (*info->fprintf_func) (info->stream, "4*cr%d+" , cr); |
5401 | cc = value & 3; |
5402 | (*info->fprintf_func) (info->stream, "%s" , cbnames[cc]); |
5403 | } |
5404 | } |
5405 | |
5406 | if (need_paren) |
5407 | { |
5408 | (*info->fprintf_func) (info->stream, ")" ); |
5409 | need_paren = 0; |
5410 | } |
5411 | |
5412 | if ((operand->flags & PPC_OPERAND_PARENS) == 0) |
5413 | need_comma = 1; |
5414 | else |
5415 | { |
5416 | (*info->fprintf_func) (info->stream, "(" ); |
5417 | need_paren = 1; |
5418 | } |
5419 | } |
5420 | |
5421 | /* We have found and printed an instruction; return. */ |
5422 | return 4; |
5423 | } |
5424 | |
5425 | if ((dialect & PPC_OPCODE_ANY) != 0) |
5426 | { |
5427 | dialect = ~PPC_OPCODE_ANY; |
5428 | goto again; |
5429 | } |
5430 | |
5431 | /* We could not find a match. */ |
5432 | (*info->fprintf_func) (info->stream, ".long 0x%lx" , insn); |
5433 | |
5434 | return 4; |
5435 | } |
5436 | |