1 | /* |
2 | * These files from binutils are concatenated: |
3 | * include/opcode/sparc.h, opcodes/sparc-opc.c, opcodes/sparc-dis.c |
4 | */ |
5 | |
6 | /* include/opcode/sparc.h */ |
7 | |
8 | /* Definitions for opcode table for the sparc. |
9 | Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2002, |
10 | 2003, 2005 Free Software Foundation, Inc. |
11 | |
12 | This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and |
13 | the GNU Binutils. |
14 | |
15 | GAS/GDB is free software; you can redistribute it and/or modify |
16 | it under the terms of the GNU General Public License as published by |
17 | the Free Software Foundation; either version 2, or (at your option) |
18 | any later version. |
19 | |
20 | GAS/GDB is distributed in the hope that it will be useful, |
21 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
22 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
23 | GNU General Public License for more details. |
24 | |
25 | You should have received a copy of the GNU General Public License |
26 | along with GAS or GDB; see the file COPYING. If not, |
27 | see <http://www.gnu.org/licenses/>. */ |
28 | |
29 | #include "qemu/osdep.h" |
30 | #include "disas/dis-asm.h" |
31 | |
32 | /* The SPARC opcode table (and other related data) is defined in |
33 | the opcodes library in sparc-opc.c. If you change anything here, make |
34 | sure you fix up that file, and vice versa. */ |
35 | |
36 | /* FIXME-someday: perhaps the ,a's and such should be embedded in the |
37 | instruction's name rather than the args. This would make gas faster, pinsn |
38 | slower, but would mess up some macros a bit. xoxorich. */ |
39 | |
40 | /* List of instruction sets variations. |
41 | These values are such that each element is either a superset of a |
42 | preceding each one or they conflict in which case SPARC_OPCODE_CONFLICT_P |
43 | returns non-zero. |
44 | The values are indices into `sparc_opcode_archs' defined in sparc-opc.c. |
45 | Don't change this without updating sparc-opc.c. */ |
46 | |
47 | enum sparc_opcode_arch_val |
48 | { |
49 | SPARC_OPCODE_ARCH_V6 = 0, |
50 | SPARC_OPCODE_ARCH_V7, |
51 | SPARC_OPCODE_ARCH_V8, |
52 | SPARC_OPCODE_ARCH_SPARCLET, |
53 | SPARC_OPCODE_ARCH_SPARCLITE, |
54 | /* V9 variants must appear last. */ |
55 | SPARC_OPCODE_ARCH_V9, |
56 | SPARC_OPCODE_ARCH_V9A, /* V9 with ultrasparc additions. */ |
57 | SPARC_OPCODE_ARCH_V9B, /* V9 with ultrasparc and cheetah additions. */ |
58 | SPARC_OPCODE_ARCH_BAD /* Error return from sparc_opcode_lookup_arch. */ |
59 | }; |
60 | |
61 | /* The highest architecture in the table. */ |
62 | #define SPARC_OPCODE_ARCH_MAX (SPARC_OPCODE_ARCH_BAD - 1) |
63 | |
64 | /* Given an enum sparc_opcode_arch_val, return the bitmask to use in |
65 | insn encoding/decoding. */ |
66 | #define SPARC_OPCODE_ARCH_MASK(arch) (1 << (arch)) |
67 | |
68 | /* Given a valid sparc_opcode_arch_val, return non-zero if it's v9. */ |
69 | #define SPARC_OPCODE_ARCH_V9_P(arch) ((arch) >= SPARC_OPCODE_ARCH_V9) |
70 | |
71 | /* Table of cpu variants. */ |
72 | |
73 | typedef struct sparc_opcode_arch |
74 | { |
75 | const char *name; |
76 | /* Mask of sparc_opcode_arch_val's supported. |
77 | EG: For v7 this would be |
78 | (SPARC_OPCODE_ARCH_MASK (..._V6) | SPARC_OPCODE_ARCH_MASK (..._V7)). |
79 | These are short's because sparc_opcode.architecture is. */ |
80 | short supported; |
81 | } sparc_opcode_arch; |
82 | |
83 | /* Structure of an opcode table entry. */ |
84 | |
85 | typedef struct sparc_opcode |
86 | { |
87 | const char *name; |
88 | unsigned long match; /* Bits that must be set. */ |
89 | unsigned long lose; /* Bits that must not be set. */ |
90 | const char *args; |
91 | /* This was called "delayed" in versions before the flags. */ |
92 | char flags; |
93 | short architecture; /* Bitmask of sparc_opcode_arch_val's. */ |
94 | } sparc_opcode; |
95 | |
96 | #define F_DELAYED 1 /* Delayed branch. */ |
97 | #define F_ALIAS 2 /* Alias for a "real" instruction. */ |
98 | #define F_UNBR 4 /* Unconditional branch. */ |
99 | #define F_CONDBR 8 /* Conditional branch. */ |
100 | #define F_JSR 16 /* Subroutine call. */ |
101 | #define F_FLOAT 32 /* Floating point instruction (not a branch). */ |
102 | #define F_FBR 64 /* Floating point branch. */ |
103 | /* FIXME: Add F_ANACHRONISTIC flag for v9. */ |
104 | |
105 | /* All sparc opcodes are 32 bits, except for the `set' instruction (really a |
106 | macro), which is 64 bits. It is handled as a special case. |
107 | |
108 | The match component is a mask saying which bits must match a particular |
109 | opcode in order for an instruction to be an instance of that opcode. |
110 | |
111 | The args component is a string containing one character for each operand of the |
112 | instruction. |
113 | |
114 | Kinds of operands: |
115 | # Number used by optimizer. It is ignored. |
116 | 1 rs1 register. |
117 | 2 rs2 register. |
118 | d rd register. |
119 | e frs1 floating point register. |
120 | v frs1 floating point register (double/even). |
121 | V frs1 floating point register (quad/multiple of 4). |
122 | f frs2 floating point register. |
123 | B frs2 floating point register (double/even). |
124 | R frs2 floating point register (quad/multiple of 4). |
125 | g frsd floating point register. |
126 | H frsd floating point register (double/even). |
127 | J frsd floating point register (quad/multiple of 4). |
128 | b crs1 coprocessor register |
129 | c crs2 coprocessor register |
130 | D crsd coprocessor register |
131 | m alternate space register (asr) in rd |
132 | M alternate space register (asr) in rs1 |
133 | h 22 high bits. |
134 | X 5 bit unsigned immediate |
135 | Y 6 bit unsigned immediate |
136 | 3 SIAM mode (3 bits). (v9b) |
137 | K MEMBAR mask (7 bits). (v9) |
138 | j 10 bit Immediate. (v9) |
139 | I 11 bit Immediate. (v9) |
140 | i 13 bit Immediate. |
141 | n 22 bit immediate. |
142 | k 2+14 bit PC relative immediate. (v9) |
143 | G 19 bit PC relative immediate. (v9) |
144 | l 22 bit PC relative immediate. |
145 | L 30 bit PC relative immediate. |
146 | a Annul. The annul bit is set. |
147 | A Alternate address space. Stored as 8 bits. |
148 | C Coprocessor state register. |
149 | F floating point state register. |
150 | p Processor state register. |
151 | N Branch predict clear ",pn" (v9) |
152 | T Branch predict set ",pt" (v9) |
153 | z %icc. (v9) |
154 | Z %xcc. (v9) |
155 | q Floating point queue. |
156 | r Single register that is both rs1 and rd. |
157 | O Single register that is both rs2 and rd. |
158 | Q Coprocessor queue. |
159 | S Special case. |
160 | t Trap base register. |
161 | w Window invalid mask register. |
162 | y Y register. |
163 | u sparclet coprocessor registers in rd position |
164 | U sparclet coprocessor registers in rs1 position |
165 | E %ccr. (v9) |
166 | s %fprs. (v9) |
167 | P %pc. (v9) |
168 | W %tick. (v9) |
169 | o %asi. (v9) |
170 | 6 %fcc0. (v9) |
171 | 7 %fcc1. (v9) |
172 | 8 %fcc2. (v9) |
173 | 9 %fcc3. (v9) |
174 | ! Privileged Register in rd (v9) |
175 | ? Privileged Register in rs1 (v9) |
176 | * Prefetch function constant. (v9) |
177 | x OPF field (v9 impdep). |
178 | 0 32/64 bit immediate for set or setx (v9) insns |
179 | _ Ancillary state register in rd (v9a) |
180 | / Ancillary state register in rs1 (v9a) |
181 | |
182 | The following chars are unused: (note: ,[] are used as punctuation) |
183 | [45]. */ |
184 | |
185 | #define OP2(x) (((x) & 0x7) << 22) /* Op2 field of format2 insns. */ |
186 | #define OP3(x) (((x) & 0x3f) << 19) /* Op3 field of format3 insns. */ |
187 | #define OP(x) ((unsigned) ((x) & 0x3) << 30) /* Op field of all insns. */ |
188 | #define OPF(x) (((x) & 0x1ff) << 5) /* Opf field of float insns. */ |
189 | #define OPF_LOW5(x) OPF ((x) & 0x1f) /* V9. */ |
190 | #define F3F(x, y, z) (OP (x) | OP3 (y) | OPF (z)) /* Format3 float insns. */ |
191 | #define F3I(x) (((x) & 0x1) << 13) /* Immediate field of format 3 insns. */ |
192 | #define F2(x, y) (OP (x) | OP2(y)) /* Format 2 insns. */ |
193 | #define F3(x, y, z) (OP (x) | OP3(y) | F3I(z)) /* Format3 insns. */ |
194 | #define F1(x) (OP (x)) |
195 | #define DISP30(x) ((x) & 0x3fffffff) |
196 | #define ASI(x) (((x) & 0xff) << 5) /* Asi field of format3 insns. */ |
197 | #define RS2(x) ((x) & 0x1f) /* Rs2 field. */ |
198 | #define SIMM13(x) ((x) & 0x1fff) /* Simm13 field. */ |
199 | #define RD(x) (((x) & 0x1f) << 25) /* Destination register field. */ |
200 | #define RS1(x) (((x) & 0x1f) << 14) /* Rs1 field. */ |
201 | #define ASI_RS2(x) (SIMM13 (x)) |
202 | #define MEMBAR(x) ((x) & 0x7f) |
203 | #define SLCPOP(x) (((x) & 0x7f) << 6) /* Sparclet cpop. */ |
204 | |
205 | #define ANNUL (1 << 29) |
206 | #define BPRED (1 << 19) /* V9. */ |
207 | #define IMMED F3I (1) |
208 | #define RD_G0 RD (~0) |
209 | #define RS1_G0 RS1 (~0) |
210 | #define RS2_G0 RS2 (~0) |
211 | |
212 | static const struct sparc_opcode sparc_opcodes[]; |
213 | |
214 | static const char *sparc_decode_asi_v8 (int); |
215 | static const char *sparc_decode_asi_v9 (int); |
216 | static const char *sparc_decode_membar (int); |
217 | static const char *sparc_decode_prefetch (int); |
218 | static const char *sparc_decode_sparclet_cpreg (int); |
219 | |
220 | /* Local Variables: |
221 | fill-column: 131 |
222 | comment-column: 0 |
223 | End: */ |
224 | |
225 | /* opcodes/sparc-opc.c */ |
226 | |
227 | /* Table of opcodes for the sparc. |
228 | Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
229 | 2000, 2002, 2004, 2005 |
230 | Free Software Foundation, Inc. |
231 | |
232 | This file is part of the BFD library. |
233 | |
234 | BFD is free software; you can redistribute it and/or modify it under |
235 | the terms of the GNU General Public License as published by the Free |
236 | Software Foundation; either version 2, or (at your option) any later |
237 | version. |
238 | |
239 | BFD is distributed in the hope that it will be useful, but WITHOUT ANY |
240 | WARRANTY; without even the implied warranty of MERCHANTABILITY or |
241 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
242 | for more details. |
243 | |
244 | You should have received a copy of the GNU General Public License |
245 | along with this software; see the file COPYING. If not, |
246 | see <http://www.gnu.org/licenses/>. */ |
247 | |
248 | /* FIXME-someday: perhaps the ,a's and such should be embedded in the |
249 | instruction's name rather than the args. This would make gas faster, pinsn |
250 | slower, but would mess up some macros a bit. xoxorich. */ |
251 | |
252 | /* Some defines to make life easy. */ |
253 | #define MASK_V6 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V6) |
254 | #define MASK_V7 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V7) |
255 | #define MASK_V8 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8) |
256 | #define MASK_SPARCLET SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET) |
257 | #define MASK_SPARCLITE SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE) |
258 | #define MASK_V9 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9) |
259 | #define MASK_V9A SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A) |
260 | #define MASK_V9B SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B) |
261 | |
262 | /* Bit masks of architectures supporting the insn. */ |
263 | |
264 | #define v6 (MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET \ |
265 | | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B) |
266 | /* v6 insns not supported on the sparclet. */ |
267 | #define v6notlet (MASK_V6 | MASK_V7 | MASK_V8 \ |
268 | | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B) |
269 | #define v7 (MASK_V7 | MASK_V8 | MASK_SPARCLET \ |
270 | | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B) |
271 | /* Although not all insns are implemented in hardware, sparclite is defined |
272 | to be a superset of v8. Unimplemented insns trap and are then theoretically |
273 | implemented in software. |
274 | It's not clear that the same is true for sparclet, although the docs |
275 | suggest it is. Rather than complicating things, the sparclet assembler |
276 | recognizes all v8 insns. */ |
277 | #define v8 (MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE \ |
278 | | MASK_V9 | MASK_V9A | MASK_V9B) |
279 | #define sparclet (MASK_SPARCLET) |
280 | #define sparclite (MASK_SPARCLITE) |
281 | #define v9 (MASK_V9 | MASK_V9A | MASK_V9B) |
282 | #define v9a (MASK_V9A | MASK_V9B) |
283 | #define v9b (MASK_V9B) |
284 | /* v6 insns not supported by v9. */ |
285 | #define v6notv9 (MASK_V6 | MASK_V7 | MASK_V8 \ |
286 | | MASK_SPARCLET | MASK_SPARCLITE) |
287 | /* v9a instructions which would appear to be aliases to v9's impdep's |
288 | otherwise. */ |
289 | #define v9notv9a (MASK_V9) |
290 | |
291 | /* Branch condition field. */ |
292 | #define COND(x) (((x) & 0xf) << 25) |
293 | |
294 | /* v9: Move (MOVcc and FMOVcc) condition field. */ |
295 | #define MCOND(x,i_or_f) ((((i_or_f) & 1) << 18) | (((x) >> 11) & (0xf << 14))) /* v9 */ |
296 | |
297 | /* v9: Move register (MOVRcc and FMOVRcc) condition field. */ |
298 | #define RCOND(x) (((x) & 0x7) << 10) /* v9 */ |
299 | |
300 | #define CONDA (COND (0x8)) |
301 | #define CONDCC (COND (0xd)) |
302 | #define CONDCS (COND (0x5)) |
303 | #define CONDE (COND (0x1)) |
304 | #define CONDG (COND (0xa)) |
305 | #define CONDGE (COND (0xb)) |
306 | #define CONDGU (COND (0xc)) |
307 | #define CONDL (COND (0x3)) |
308 | #define CONDLE (COND (0x2)) |
309 | #define CONDLEU (COND (0x4)) |
310 | #define CONDN (COND (0x0)) |
311 | #define CONDNE (COND (0x9)) |
312 | #define CONDNEG (COND (0x6)) |
313 | #define CONDPOS (COND (0xe)) |
314 | #define CONDVC (COND (0xf)) |
315 | #define CONDVS (COND (0x7)) |
316 | |
317 | #define CONDNZ CONDNE |
318 | #define CONDZ CONDE |
319 | #define CONDGEU CONDCC |
320 | #define CONDLU CONDCS |
321 | |
322 | #define FCONDA (COND (0x8)) |
323 | #define FCONDE (COND (0x9)) |
324 | #define FCONDG (COND (0x6)) |
325 | #define FCONDGE (COND (0xb)) |
326 | #define FCONDL (COND (0x4)) |
327 | #define FCONDLE (COND (0xd)) |
328 | #define FCONDLG (COND (0x2)) |
329 | #define FCONDN (COND (0x0)) |
330 | #define FCONDNE (COND (0x1)) |
331 | #define FCONDO (COND (0xf)) |
332 | #define FCONDU (COND (0x7)) |
333 | #define FCONDUE (COND (0xa)) |
334 | #define FCONDUG (COND (0x5)) |
335 | #define FCONDUGE (COND (0xc)) |
336 | #define FCONDUL (COND (0x3)) |
337 | #define FCONDULE (COND (0xe)) |
338 | |
339 | #define FCONDNZ FCONDNE |
340 | #define FCONDZ FCONDE |
341 | |
342 | #define ICC (0) /* v9 */ |
343 | #define XCC (1 << 12) /* v9 */ |
344 | #define FCC(x) (((x) & 0x3) << 11) /* v9 */ |
345 | #define FBFCC(x) (((x) & 0x3) << 20) /* v9 */ |
346 | |
347 | /* The order of the opcodes in the table is significant: |
348 | |
349 | * The assembler requires that all instances of the same mnemonic must |
350 | be consecutive. If they aren't, the assembler will bomb at runtime. |
351 | |
352 | * The disassembler should not care about the order of the opcodes. */ |
353 | |
354 | /* Entries for commutative arithmetic operations. */ |
355 | /* ??? More entries can make use of this. */ |
356 | #define COMMUTEOP(opcode, op3, arch_mask) \ |
357 | { opcode, F3(2, op3, 0), F3(~2, ~op3, ~0)|ASI(~0), "1,2,d", 0, arch_mask }, \ |
358 | { opcode, F3(2, op3, 1), F3(~2, ~op3, ~1), "1,i,d", 0, arch_mask }, \ |
359 | { opcode, F3(2, op3, 1), F3(~2, ~op3, ~1), "i,1,d", 0, arch_mask } |
360 | |
361 | static const struct sparc_opcode sparc_opcodes[] = { |
362 | |
363 | { "ld" , F3(3, 0x00, 0), F3(~3, ~0x00, ~0), "[1+2],d" , 0, v6 }, |
364 | { "ld" , F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0, "[1],d" , 0, v6 }, /* ld [rs1+%g0],d */ |
365 | { "ld" , F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[1+i],d" , 0, v6 }, |
366 | { "ld" , F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[i+1],d" , 0, v6 }, |
367 | { "ld" , F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0, "[i],d" , 0, v6 }, |
368 | { "ld" , F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0), "[1],d" , 0, v6 }, /* ld [rs1+0],d */ |
369 | { "ld" , F3(3, 0x20, 0), F3(~3, ~0x20, ~0), "[1+2],g" , 0, v6 }, |
370 | { "ld" , F3(3, 0x20, 0), F3(~3, ~0x20, ~0)|RS2_G0, "[1],g" , 0, v6 }, /* ld [rs1+%g0],d */ |
371 | { "ld" , F3(3, 0x20, 1), F3(~3, ~0x20, ~1), "[1+i],g" , 0, v6 }, |
372 | { "ld" , F3(3, 0x20, 1), F3(~3, ~0x20, ~1), "[i+1],g" , 0, v6 }, |
373 | { "ld" , F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|RS1_G0, "[i],g" , 0, v6 }, |
374 | { "ld" , F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|SIMM13(~0), "[1],g" , 0, v6 }, /* ld [rs1+0],d */ |
375 | |
376 | { "ld" , F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RD(~0), "[1+2],F" , 0, v6 }, |
377 | { "ld" , F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RS2_G0|RD(~0),"[1],F" , 0, v6 }, /* ld [rs1+%g0],d */ |
378 | { "ld" , F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0), "[1+i],F" , 0, v6 }, |
379 | { "ld" , F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0), "[i+1],F" , 0, v6 }, |
380 | { "ld" , F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RS1_G0|RD(~0),"[i],F" , 0, v6 }, |
381 | { "ld" , F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~0),"[1],F" , 0, v6 }, /* ld [rs1+0],d */ |
382 | |
383 | { "ld" , F3(3, 0x30, 0), F3(~3, ~0x30, ~0), "[1+2],D" , 0, v6notv9 }, |
384 | { "ld" , F3(3, 0x30, 0), F3(~3, ~0x30, ~0)|RS2_G0, "[1],D" , 0, v6notv9 }, /* ld [rs1+%g0],d */ |
385 | { "ld" , F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[1+i],D" , 0, v6notv9 }, |
386 | { "ld" , F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[i+1],D" , 0, v6notv9 }, |
387 | { "ld" , F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0, "[i],D" , 0, v6notv9 }, |
388 | { "ld" , F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0), "[1],D" , 0, v6notv9 }, /* ld [rs1+0],d */ |
389 | { "ld" , F3(3, 0x31, 0), F3(~3, ~0x31, ~0), "[1+2],C" , 0, v6notv9 }, |
390 | { "ld" , F3(3, 0x31, 0), F3(~3, ~0x31, ~0)|RS2_G0, "[1],C" , 0, v6notv9 }, /* ld [rs1+%g0],d */ |
391 | { "ld" , F3(3, 0x31, 1), F3(~3, ~0x31, ~1), "[1+i],C" , 0, v6notv9 }, |
392 | { "ld" , F3(3, 0x31, 1), F3(~3, ~0x31, ~1), "[i+1],C" , 0, v6notv9 }, |
393 | { "ld" , F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|RS1_G0, "[i],C" , 0, v6notv9 }, |
394 | { "ld" , F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|SIMM13(~0), "[1],C" , 0, v6notv9 }, /* ld [rs1+0],d */ |
395 | |
396 | /* The v9 LDUW is the same as the old 'ld' opcode, it is not the same as the |
397 | 'ld' pseudo-op in v9. */ |
398 | { "lduw" , F3(3, 0x00, 0), F3(~3, ~0x00, ~0), "[1+2],d" , F_ALIAS, v9 }, |
399 | { "lduw" , F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0, "[1],d" , F_ALIAS, v9 }, /* ld [rs1+%g0],d */ |
400 | { "lduw" , F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[1+i],d" , F_ALIAS, v9 }, |
401 | { "lduw" , F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[i+1],d" , F_ALIAS, v9 }, |
402 | { "lduw" , F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0, "[i],d" , F_ALIAS, v9 }, |
403 | { "lduw" , F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0), "[1],d" , F_ALIAS, v9 }, /* ld [rs1+0],d */ |
404 | |
405 | { "ldd" , F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI(~0), "[1+2],d" , 0, v6 }, |
406 | { "ldd" , F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI_RS2(~0), "[1],d" , 0, v6 }, /* ldd [rs1+%g0],d */ |
407 | { "ldd" , F3(3, 0x03, 1), F3(~3, ~0x03, ~1), "[1+i],d" , 0, v6 }, |
408 | { "ldd" , F3(3, 0x03, 1), F3(~3, ~0x03, ~1), "[i+1],d" , 0, v6 }, |
409 | { "ldd" , F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|RS1_G0, "[i],d" , 0, v6 }, |
410 | { "ldd" , F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|SIMM13(~0), "[1],d" , 0, v6 }, /* ldd [rs1+0],d */ |
411 | { "ldd" , F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI(~0), "[1+2],H" , 0, v6 }, |
412 | { "ldd" , F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI_RS2(~0), "[1],H" , 0, v6 }, /* ldd [rs1+%g0],d */ |
413 | { "ldd" , F3(3, 0x23, 1), F3(~3, ~0x23, ~1), "[1+i],H" , 0, v6 }, |
414 | { "ldd" , F3(3, 0x23, 1), F3(~3, ~0x23, ~1), "[i+1],H" , 0, v6 }, |
415 | { "ldd" , F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|RS1_G0, "[i],H" , 0, v6 }, |
416 | { "ldd" , F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|SIMM13(~0), "[1],H" , 0, v6 }, /* ldd [rs1+0],d */ |
417 | |
418 | { "ldd" , F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI(~0), "[1+2],D" , 0, v6notv9 }, |
419 | { "ldd" , F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI_RS2(~0), "[1],D" , 0, v6notv9 }, /* ldd [rs1+%g0],d */ |
420 | { "ldd" , F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[1+i],D" , 0, v6notv9 }, |
421 | { "ldd" , F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[i+1],D" , 0, v6notv9 }, |
422 | { "ldd" , F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|RS1_G0, "[i],D" , 0, v6notv9 }, |
423 | { "ldd" , F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|SIMM13(~0), "[1],D" , 0, v6notv9 }, /* ldd [rs1+0],d */ |
424 | |
425 | { "ldq" , F3(3, 0x22, 0), F3(~3, ~0x22, ~0)|ASI(~0), "[1+2],J" , 0, v9 }, |
426 | { "ldq" , F3(3, 0x22, 0), F3(~3, ~0x22, ~0)|ASI_RS2(~0), "[1],J" , 0, v9 }, /* ldd [rs1+%g0],d */ |
427 | { "ldq" , F3(3, 0x22, 1), F3(~3, ~0x22, ~1), "[1+i],J" , 0, v9 }, |
428 | { "ldq" , F3(3, 0x22, 1), F3(~3, ~0x22, ~1), "[i+1],J" , 0, v9 }, |
429 | { "ldq" , F3(3, 0x22, 1), F3(~3, ~0x22, ~1)|RS1_G0, "[i],J" , 0, v9 }, |
430 | { "ldq" , F3(3, 0x22, 1), F3(~3, ~0x22, ~1)|SIMM13(~0), "[1],J" , 0, v9 }, /* ldd [rs1+0],d */ |
431 | |
432 | { "ldsb" , F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI(~0), "[1+2],d" , 0, v6 }, |
433 | { "ldsb" , F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI_RS2(~0), "[1],d" , 0, v6 }, /* ldsb [rs1+%g0],d */ |
434 | { "ldsb" , F3(3, 0x09, 1), F3(~3, ~0x09, ~1), "[1+i],d" , 0, v6 }, |
435 | { "ldsb" , F3(3, 0x09, 1), F3(~3, ~0x09, ~1), "[i+1],d" , 0, v6 }, |
436 | { "ldsb" , F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|RS1_G0, "[i],d" , 0, v6 }, |
437 | { "ldsb" , F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|SIMM13(~0), "[1],d" , 0, v6 }, /* ldsb [rs1+0],d */ |
438 | |
439 | { "ldsh" , F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI_RS2(~0), "[1],d" , 0, v6 }, /* ldsh [rs1+%g0],d */ |
440 | { "ldsh" , F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI(~0), "[1+2],d" , 0, v6 }, |
441 | { "ldsh" , F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1), "[1+i],d" , 0, v6 }, |
442 | { "ldsh" , F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1), "[i+1],d" , 0, v6 }, |
443 | { "ldsh" , F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|RS1_G0, "[i],d" , 0, v6 }, |
444 | { "ldsh" , F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|SIMM13(~0), "[1],d" , 0, v6 }, /* ldsh [rs1+0],d */ |
445 | |
446 | { "ldstub" , F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI(~0), "[1+2],d" , 0, v6 }, |
447 | { "ldstub" , F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI_RS2(~0), "[1],d" , 0, v6 }, /* ldstub [rs1+%g0],d */ |
448 | { "ldstub" , F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1), "[1+i],d" , 0, v6 }, |
449 | { "ldstub" , F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1), "[i+1],d" , 0, v6 }, |
450 | { "ldstub" , F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1)|RS1_G0, "[i],d" , 0, v6 }, |
451 | { "ldstub" , F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1)|SIMM13(~0), "[1],d" , 0, v6 }, /* ldstub [rs1+0],d */ |
452 | |
453 | { "ldsw" , F3(3, 0x08, 0), F3(~3, ~0x08, ~0)|ASI(~0), "[1+2],d" , 0, v9 }, |
454 | { "ldsw" , F3(3, 0x08, 0), F3(~3, ~0x08, ~0)|ASI_RS2(~0), "[1],d" , 0, v9 }, /* ldsw [rs1+%g0],d */ |
455 | { "ldsw" , F3(3, 0x08, 1), F3(~3, ~0x08, ~1), "[1+i],d" , 0, v9 }, |
456 | { "ldsw" , F3(3, 0x08, 1), F3(~3, ~0x08, ~1), "[i+1],d" , 0, v9 }, |
457 | { "ldsw" , F3(3, 0x08, 1), F3(~3, ~0x08, ~1)|RS1_G0, "[i],d" , 0, v9 }, |
458 | { "ldsw" , F3(3, 0x08, 1), F3(~3, ~0x08, ~1)|SIMM13(~0), "[1],d" , 0, v9 }, /* ldsw [rs1+0],d */ |
459 | |
460 | { "ldub" , F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI(~0), "[1+2],d" , 0, v6 }, |
461 | { "ldub" , F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI_RS2(~0), "[1],d" , 0, v6 }, /* ldub [rs1+%g0],d */ |
462 | { "ldub" , F3(3, 0x01, 1), F3(~3, ~0x01, ~1), "[1+i],d" , 0, v6 }, |
463 | { "ldub" , F3(3, 0x01, 1), F3(~3, ~0x01, ~1), "[i+1],d" , 0, v6 }, |
464 | { "ldub" , F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|RS1_G0, "[i],d" , 0, v6 }, |
465 | { "ldub" , F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|SIMM13(~0), "[1],d" , 0, v6 }, /* ldub [rs1+0],d */ |
466 | |
467 | { "lduh" , F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI(~0), "[1+2],d" , 0, v6 }, |
468 | { "lduh" , F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI_RS2(~0), "[1],d" , 0, v6 }, /* lduh [rs1+%g0],d */ |
469 | { "lduh" , F3(3, 0x02, 1), F3(~3, ~0x02, ~1), "[1+i],d" , 0, v6 }, |
470 | { "lduh" , F3(3, 0x02, 1), F3(~3, ~0x02, ~1), "[i+1],d" , 0, v6 }, |
471 | { "lduh" , F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|RS1_G0, "[i],d" , 0, v6 }, |
472 | { "lduh" , F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|SIMM13(~0), "[1],d" , 0, v6 }, /* lduh [rs1+0],d */ |
473 | |
474 | { "ldx" , F3(3, 0x0b, 0), F3(~3, ~0x0b, ~0)|ASI(~0), "[1+2],d" , 0, v9 }, |
475 | { "ldx" , F3(3, 0x0b, 0), F3(~3, ~0x0b, ~0)|ASI_RS2(~0), "[1],d" , 0, v9 }, /* ldx [rs1+%g0],d */ |
476 | { "ldx" , F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1), "[1+i],d" , 0, v9 }, |
477 | { "ldx" , F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1), "[i+1],d" , 0, v9 }, |
478 | { "ldx" , F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1)|RS1_G0, "[i],d" , 0, v9 }, |
479 | { "ldx" , F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1)|SIMM13(~0), "[1],d" , 0, v9 }, /* ldx [rs1+0],d */ |
480 | |
481 | { "ldx" , F3(3, 0x21, 0)|RD(1), F3(~3, ~0x21, ~0)|RD(~1), "[1+2],F" , 0, v9 }, |
482 | { "ldx" , F3(3, 0x21, 0)|RD(1), F3(~3, ~0x21, ~0)|RS2_G0|RD(~1), "[1],F" , 0, v9 }, /* ld [rs1+%g0],d */ |
483 | { "ldx" , F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RD(~1), "[1+i],F" , 0, v9 }, |
484 | { "ldx" , F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RD(~1), "[i+1],F" , 0, v9 }, |
485 | { "ldx" , F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RS1_G0|RD(~1), "[i],F" , 0, v9 }, |
486 | { "ldx" , F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~1),"[1],F" , 0, v9 }, /* ld [rs1+0],d */ |
487 | |
488 | { "lda" , F3(3, 0x10, 0), F3(~3, ~0x10, ~0), "[1+2]A,d" , 0, v6 }, |
489 | { "lda" , F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0, "[1]A,d" , 0, v6 }, /* lda [rs1+%g0],d */ |
490 | { "lda" , F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[1+i]o,d" , 0, v9 }, |
491 | { "lda" , F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[i+1]o,d" , 0, v9 }, |
492 | { "lda" , F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|RS1_G0, "[i]o,d" , 0, v9 }, |
493 | { "lda" , F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|SIMM13(~0), "[1]o,d" , 0, v9 }, /* ld [rs1+0],d */ |
494 | { "lda" , F3(3, 0x30, 0), F3(~3, ~0x30, ~0), "[1+2]A,g" , 0, v9 }, |
495 | { "lda" , F3(3, 0x30, 0), F3(~3, ~0x30, ~0)|RS2_G0, "[1]A,g" , 0, v9 }, /* lda [rs1+%g0],d */ |
496 | { "lda" , F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[1+i]o,g" , 0, v9 }, |
497 | { "lda" , F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[i+1]o,g" , 0, v9 }, |
498 | { "lda" , F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0, "[i]o,g" , 0, v9 }, |
499 | { "lda" , F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0), "[1]o,g" , 0, v9 }, /* ld [rs1+0],d */ |
500 | |
501 | { "ldda" , F3(3, 0x13, 0), F3(~3, ~0x13, ~0), "[1+2]A,d" , 0, v6 }, |
502 | { "ldda" , F3(3, 0x13, 0), F3(~3, ~0x13, ~0)|RS2_G0, "[1]A,d" , 0, v6 }, /* ldda [rs1+%g0],d */ |
503 | { "ldda" , F3(3, 0x13, 1), F3(~3, ~0x13, ~1), "[1+i]o,d" , 0, v9 }, |
504 | { "ldda" , F3(3, 0x13, 1), F3(~3, ~0x13, ~1), "[i+1]o,d" , 0, v9 }, |
505 | { "ldda" , F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|RS1_G0, "[i]o,d" , 0, v9 }, |
506 | { "ldda" , F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|SIMM13(~0), "[1]o,d" , 0, v9 }, /* ld [rs1+0],d */ |
507 | |
508 | { "ldda" , F3(3, 0x33, 0), F3(~3, ~0x33, ~0), "[1+2]A,H" , 0, v9 }, |
509 | { "ldda" , F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|RS2_G0, "[1]A,H" , 0, v9 }, /* ldda [rs1+%g0],d */ |
510 | { "ldda" , F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[1+i]o,H" , 0, v9 }, |
511 | { "ldda" , F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[i+1]o,H" , 0, v9 }, |
512 | { "ldda" , F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|RS1_G0, "[i]o,H" , 0, v9 }, |
513 | { "ldda" , F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|SIMM13(~0), "[1]o,H" , 0, v9 }, /* ld [rs1+0],d */ |
514 | |
515 | { "ldqa" , F3(3, 0x32, 0), F3(~3, ~0x32, ~0), "[1+2]A,J" , 0, v9 }, |
516 | { "ldqa" , F3(3, 0x32, 0), F3(~3, ~0x32, ~0)|RS2_G0, "[1]A,J" , 0, v9 }, /* ldd [rs1+%g0],d */ |
517 | { "ldqa" , F3(3, 0x32, 1), F3(~3, ~0x32, ~1), "[1+i]o,J" , 0, v9 }, |
518 | { "ldqa" , F3(3, 0x32, 1), F3(~3, ~0x32, ~1), "[i+1]o,J" , 0, v9 }, |
519 | { "ldqa" , F3(3, 0x32, 1), F3(~3, ~0x32, ~1)|RS1_G0, "[i]o,J" , 0, v9 }, |
520 | { "ldqa" , F3(3, 0x32, 1), F3(~3, ~0x32, ~1)|SIMM13(~0), "[1]o,J" , 0, v9 }, /* ldd [rs1+0],d */ |
521 | |
522 | { "ldsba" , F3(3, 0x19, 0), F3(~3, ~0x19, ~0), "[1+2]A,d" , 0, v6 }, |
523 | { "ldsba" , F3(3, 0x19, 0), F3(~3, ~0x19, ~0)|RS2_G0, "[1]A,d" , 0, v6 }, /* ldsba [rs1+%g0],d */ |
524 | { "ldsba" , F3(3, 0x19, 1), F3(~3, ~0x19, ~1), "[1+i]o,d" , 0, v9 }, |
525 | { "ldsba" , F3(3, 0x19, 1), F3(~3, ~0x19, ~1), "[i+1]o,d" , 0, v9 }, |
526 | { "ldsba" , F3(3, 0x19, 1), F3(~3, ~0x19, ~1)|RS1_G0, "[i]o,d" , 0, v9 }, |
527 | { "ldsba" , F3(3, 0x19, 1), F3(~3, ~0x19, ~1)|SIMM13(~0), "[1]o,d" , 0, v9 }, /* ld [rs1+0],d */ |
528 | |
529 | { "ldsha" , F3(3, 0x1a, 0), F3(~3, ~0x1a, ~0), "[1+2]A,d" , 0, v6 }, |
530 | { "ldsha" , F3(3, 0x1a, 0), F3(~3, ~0x1a, ~0)|RS2_G0, "[1]A,d" , 0, v6 }, /* ldsha [rs1+%g0],d */ |
531 | { "ldsha" , F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1), "[1+i]o,d" , 0, v9 }, |
532 | { "ldsha" , F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1), "[i+1]o,d" , 0, v9 }, |
533 | { "ldsha" , F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1)|RS1_G0, "[i]o,d" , 0, v9 }, |
534 | { "ldsha" , F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1)|SIMM13(~0), "[1]o,d" , 0, v9 }, /* ld [rs1+0],d */ |
535 | |
536 | { "ldstuba" , F3(3, 0x1d, 0), F3(~3, ~0x1d, ~0), "[1+2]A,d" , 0, v6 }, |
537 | { "ldstuba" , F3(3, 0x1d, 0), F3(~3, ~0x1d, ~0)|RS2_G0, "[1]A,d" , 0, v6 }, /* ldstuba [rs1+%g0],d */ |
538 | { "ldstuba" , F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1), "[1+i]o,d" , 0, v9 }, |
539 | { "ldstuba" , F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1), "[i+1]o,d" , 0, v9 }, |
540 | { "ldstuba" , F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1)|RS1_G0, "[i]o,d" , 0, v9 }, |
541 | { "ldstuba" , F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1)|SIMM13(~0), "[1]o,d" , 0, v9 }, /* ld [rs1+0],d */ |
542 | |
543 | { "ldswa" , F3(3, 0x18, 0), F3(~3, ~0x18, ~0), "[1+2]A,d" , 0, v9 }, |
544 | { "ldswa" , F3(3, 0x18, 0), F3(~3, ~0x18, ~0)|RS2_G0, "[1]A,d" , 0, v9 }, /* lda [rs1+%g0],d */ |
545 | { "ldswa" , F3(3, 0x18, 1), F3(~3, ~0x18, ~1), "[1+i]o,d" , 0, v9 }, |
546 | { "ldswa" , F3(3, 0x18, 1), F3(~3, ~0x18, ~1), "[i+1]o,d" , 0, v9 }, |
547 | { "ldswa" , F3(3, 0x18, 1), F3(~3, ~0x18, ~1)|RS1_G0, "[i]o,d" , 0, v9 }, |
548 | { "ldswa" , F3(3, 0x18, 1), F3(~3, ~0x18, ~1)|SIMM13(~0), "[1]o,d" , 0, v9 }, /* ld [rs1+0],d */ |
549 | |
550 | { "lduba" , F3(3, 0x11, 0), F3(~3, ~0x11, ~0), "[1+2]A,d" , 0, v6 }, |
551 | { "lduba" , F3(3, 0x11, 0), F3(~3, ~0x11, ~0)|RS2_G0, "[1]A,d" , 0, v6 }, /* lduba [rs1+%g0],d */ |
552 | { "lduba" , F3(3, 0x11, 1), F3(~3, ~0x11, ~1), "[1+i]o,d" , 0, v9 }, |
553 | { "lduba" , F3(3, 0x11, 1), F3(~3, ~0x11, ~1), "[i+1]o,d" , 0, v9 }, |
554 | { "lduba" , F3(3, 0x11, 1), F3(~3, ~0x11, ~1)|RS1_G0, "[i]o,d" , 0, v9 }, |
555 | { "lduba" , F3(3, 0x11, 1), F3(~3, ~0x11, ~1)|SIMM13(~0), "[1]o,d" , 0, v9 }, /* ld [rs1+0],d */ |
556 | |
557 | { "lduha" , F3(3, 0x12, 0), F3(~3, ~0x12, ~0), "[1+2]A,d" , 0, v6 }, |
558 | { "lduha" , F3(3, 0x12, 0), F3(~3, ~0x12, ~0)|RS2_G0, "[1]A,d" , 0, v6 }, /* lduha [rs1+%g0],d */ |
559 | { "lduha" , F3(3, 0x12, 1), F3(~3, ~0x12, ~1), "[1+i]o,d" , 0, v9 }, |
560 | { "lduha" , F3(3, 0x12, 1), F3(~3, ~0x12, ~1), "[i+1]o,d" , 0, v9 }, |
561 | { "lduha" , F3(3, 0x12, 1), F3(~3, ~0x12, ~1)|RS1_G0, "[i]o,d" , 0, v9 }, |
562 | { "lduha" , F3(3, 0x12, 1), F3(~3, ~0x12, ~1)|SIMM13(~0), "[1]o,d" , 0, v9 }, /* ld [rs1+0],d */ |
563 | |
564 | { "lduwa" , F3(3, 0x10, 0), F3(~3, ~0x10, ~0), "[1+2]A,d" , F_ALIAS, v9 }, /* lduwa === lda */ |
565 | { "lduwa" , F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0, "[1]A,d" , F_ALIAS, v9 }, /* lda [rs1+%g0],d */ |
566 | { "lduwa" , F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[1+i]o,d" , F_ALIAS, v9 }, |
567 | { "lduwa" , F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[i+1]o,d" , F_ALIAS, v9 }, |
568 | { "lduwa" , F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|RS1_G0, "[i]o,d" , F_ALIAS, v9 }, |
569 | { "lduwa" , F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|SIMM13(~0), "[1]o,d" , F_ALIAS, v9 }, /* ld [rs1+0],d */ |
570 | |
571 | { "ldxa" , F3(3, 0x1b, 0), F3(~3, ~0x1b, ~0), "[1+2]A,d" , 0, v9 }, |
572 | { "ldxa" , F3(3, 0x1b, 0), F3(~3, ~0x1b, ~0)|RS2_G0, "[1]A,d" , 0, v9 }, /* lda [rs1+%g0],d */ |
573 | { "ldxa" , F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1), "[1+i]o,d" , 0, v9 }, |
574 | { "ldxa" , F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1), "[i+1]o,d" , 0, v9 }, |
575 | { "ldxa" , F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1)|RS1_G0, "[i]o,d" , 0, v9 }, |
576 | { "ldxa" , F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1)|SIMM13(~0), "[1]o,d" , 0, v9 }, /* ld [rs1+0],d */ |
577 | |
578 | { "st" , F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]" , 0, v6 }, |
579 | { "st" , F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]" , 0, v6 }, /* st d,[rs1+%g0] */ |
580 | { "st" , F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]" , 0, v6 }, |
581 | { "st" , F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]" , 0, v6 }, |
582 | { "st" , F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]" , 0, v6 }, |
583 | { "st" , F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]" , 0, v6 }, /* st d,[rs1+0] */ |
584 | { "st" , F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI(~0), "g,[1+2]" , 0, v6 }, |
585 | { "st" , F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI_RS2(~0), "g,[1]" , 0, v6 }, /* st d[rs1+%g0] */ |
586 | { "st" , F3(3, 0x24, 1), F3(~3, ~0x24, ~1), "g,[1+i]" , 0, v6 }, |
587 | { "st" , F3(3, 0x24, 1), F3(~3, ~0x24, ~1), "g,[i+1]" , 0, v6 }, |
588 | { "st" , F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|RS1_G0, "g,[i]" , 0, v6 }, |
589 | { "st" , F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|SIMM13(~0), "g,[1]" , 0, v6 }, /* st d,[rs1+0] */ |
590 | |
591 | { "st" , F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI(~0), "D,[1+2]" , 0, v6notv9 }, |
592 | { "st" , F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI_RS2(~0), "D,[1]" , 0, v6notv9 }, /* st d,[rs1+%g0] */ |
593 | { "st" , F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "D,[1+i]" , 0, v6notv9 }, |
594 | { "st" , F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "D,[i+1]" , 0, v6notv9 }, |
595 | { "st" , F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|RS1_G0, "D,[i]" , 0, v6notv9 }, |
596 | { "st" , F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|SIMM13(~0), "D,[1]" , 0, v6notv9 }, /* st d,[rs1+0] */ |
597 | { "st" , F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI(~0), "C,[1+2]" , 0, v6notv9 }, |
598 | { "st" , F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI_RS2(~0), "C,[1]" , 0, v6notv9 }, /* st d,[rs1+%g0] */ |
599 | { "st" , F3(3, 0x35, 1), F3(~3, ~0x35, ~1), "C,[1+i]" , 0, v6notv9 }, |
600 | { "st" , F3(3, 0x35, 1), F3(~3, ~0x35, ~1), "C,[i+1]" , 0, v6notv9 }, |
601 | { "st" , F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|RS1_G0, "C,[i]" , 0, v6notv9 }, |
602 | { "st" , F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|SIMM13(~0), "C,[1]" , 0, v6notv9 }, /* st d,[rs1+0] */ |
603 | |
604 | { "st" , F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0|ASI(~0), "F,[1+2]" , 0, v6 }, |
605 | { "st" , F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0|ASI_RS2(~0), "F,[1]" , 0, v6 }, /* st d,[rs1+%g0] */ |
606 | { "st" , F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0, "F,[1+i]" , 0, v6 }, |
607 | { "st" , F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0, "F,[i+1]" , 0, v6 }, |
608 | { "st" , F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0|RS1_G0, "F,[i]" , 0, v6 }, |
609 | { "st" , F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0|SIMM13(~0), "F,[1]" , 0, v6 }, /* st d,[rs1+0] */ |
610 | |
611 | { "stw" , F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]" , F_ALIAS, v9 }, |
612 | { "stw" , F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]" , F_ALIAS, v9 }, /* st d,[rs1+%g0] */ |
613 | { "stw" , F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]" , F_ALIAS, v9 }, |
614 | { "stw" , F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]" , F_ALIAS, v9 }, |
615 | { "stw" , F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]" , F_ALIAS, v9 }, |
616 | { "stw" , F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]" , F_ALIAS, v9 }, /* st d,[rs1+0] */ |
617 | { "stsw" , F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]" , F_ALIAS, v9 }, |
618 | { "stsw" , F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]" , F_ALIAS, v9 }, /* st d,[rs1+%g0] */ |
619 | { "stsw" , F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]" , F_ALIAS, v9 }, |
620 | { "stsw" , F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]" , F_ALIAS, v9 }, |
621 | { "stsw" , F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]" , F_ALIAS, v9 }, |
622 | { "stsw" , F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]" , F_ALIAS, v9 }, /* st d,[rs1+0] */ |
623 | { "stuw" , F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]" , F_ALIAS, v9 }, |
624 | { "stuw" , F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]" , F_ALIAS, v9 }, /* st d,[rs1+%g0] */ |
625 | { "stuw" , F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]" , F_ALIAS, v9 }, |
626 | { "stuw" , F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]" , F_ALIAS, v9 }, |
627 | { "stuw" , F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]" , F_ALIAS, v9 }, |
628 | { "stuw" , F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]" , F_ALIAS, v9 }, /* st d,[rs1+0] */ |
629 | |
630 | { "spill" , F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]" , F_ALIAS, v6 }, |
631 | { "spill" , F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]" , F_ALIAS, v6 }, /* st d,[rs1+%g0] */ |
632 | { "spill" , F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]" , F_ALIAS, v6 }, |
633 | { "spill" , F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]" , F_ALIAS, v6 }, |
634 | { "spill" , F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]" , F_ALIAS, v6 }, |
635 | { "spill" , F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]" , F_ALIAS, v6 }, /* st d,[rs1+0] */ |
636 | |
637 | { "sta" , F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A" , 0, v6 }, |
638 | { "sta" , F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A" , 0, v6 }, /* sta d,[rs1+%g0] */ |
639 | { "sta" , F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o" , 0, v9 }, |
640 | { "sta" , F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o" , 0, v9 }, |
641 | { "sta" , F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o" , 0, v9 }, |
642 | { "sta" , F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o" , 0, v9 }, /* st d,[rs1+0] */ |
643 | |
644 | { "sta" , F3(3, 0x34, 0), F3(~3, ~0x34, ~0), "g,[1+2]A" , 0, v9 }, |
645 | { "sta" , F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|RS2(~0), "g,[1]A" , 0, v9 }, /* sta d,[rs1+%g0] */ |
646 | { "sta" , F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "g,[1+i]o" , 0, v9 }, |
647 | { "sta" , F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "g,[i+1]o" , 0, v9 }, |
648 | { "sta" , F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|RS1_G0, "g,[i]o" , 0, v9 }, |
649 | { "sta" , F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|SIMM13(~0), "g,[1]o" , 0, v9 }, /* st d,[rs1+0] */ |
650 | |
651 | { "stwa" , F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A" , F_ALIAS, v9 }, |
652 | { "stwa" , F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A" , F_ALIAS, v9 }, /* sta d,[rs1+%g0] */ |
653 | { "stwa" , F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o" , F_ALIAS, v9 }, |
654 | { "stwa" , F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o" , F_ALIAS, v9 }, |
655 | { "stwa" , F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o" , F_ALIAS, v9 }, |
656 | { "stwa" , F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o" , F_ALIAS, v9 }, /* st d,[rs1+0] */ |
657 | { "stswa" , F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A" , F_ALIAS, v9 }, |
658 | { "stswa" , F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A" , F_ALIAS, v9 }, /* sta d,[rs1+%g0] */ |
659 | { "stswa" , F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o" , F_ALIAS, v9 }, |
660 | { "stswa" , F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o" , F_ALIAS, v9 }, |
661 | { "stswa" , F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o" , F_ALIAS, v9 }, |
662 | { "stswa" , F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o" , F_ALIAS, v9 }, /* st d,[rs1+0] */ |
663 | { "stuwa" , F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A" , F_ALIAS, v9 }, |
664 | { "stuwa" , F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A" , F_ALIAS, v9 }, /* sta d,[rs1+%g0] */ |
665 | { "stuwa" , F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o" , F_ALIAS, v9 }, |
666 | { "stuwa" , F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o" , F_ALIAS, v9 }, |
667 | { "stuwa" , F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o" , F_ALIAS, v9 }, |
668 | { "stuwa" , F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o" , F_ALIAS, v9 }, /* st d,[rs1+0] */ |
669 | |
670 | { "stb" , F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]" , 0, v6 }, |
671 | { "stb" , F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]" , 0, v6 }, /* stb d,[rs1+%g0] */ |
672 | { "stb" , F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]" , 0, v6 }, |
673 | { "stb" , F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]" , 0, v6 }, |
674 | { "stb" , F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0, "d,[i]" , 0, v6 }, |
675 | { "stb" , F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]" , 0, v6 }, /* stb d,[rs1+0] */ |
676 | |
677 | { "stsb" , F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]" , F_ALIAS, v6 }, |
678 | { "stsb" , F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]" , F_ALIAS, v6 }, /* stb d,[rs1+%g0] */ |
679 | { "stsb" , F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]" , F_ALIAS, v6 }, |
680 | { "stsb" , F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]" , F_ALIAS, v6 }, |
681 | { "stsb" , F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0, "d,[i]" , F_ALIAS, v6 }, |
682 | { "stsb" , F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]" , F_ALIAS, v6 }, /* stb d,[rs1+0] */ |
683 | { "stub" , F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]" , F_ALIAS, v6 }, |
684 | { "stub" , F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]" , F_ALIAS, v6 }, /* stb d,[rs1+%g0] */ |
685 | { "stub" , F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]" , F_ALIAS, v6 }, |
686 | { "stub" , F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]" , F_ALIAS, v6 }, |
687 | { "stub" , F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0, "d,[i]" , F_ALIAS, v6 }, |
688 | { "stub" , F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]" , F_ALIAS, v6 }, /* stb d,[rs1+0] */ |
689 | |
690 | { "stba" , F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A" , 0, v6 }, |
691 | { "stba" , F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A" , 0, v6 }, /* stba d,[rs1+%g0] */ |
692 | { "stba" , F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[1+i]o" , 0, v9 }, |
693 | { "stba" , F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[i+1]o" , 0, v9 }, |
694 | { "stba" , F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0, "d,[i]o" , 0, v9 }, |
695 | { "stba" , F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o" , 0, v9 }, /* stb d,[rs1+0] */ |
696 | |
697 | { "stsba" , F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A" , F_ALIAS, v6 }, |
698 | { "stsba" , F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A" , F_ALIAS, v6 }, /* stba d,[rs1+%g0] */ |
699 | { "stsba" , F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[1+i]o" , F_ALIAS, v9 }, |
700 | { "stsba" , F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[i+1]o" , F_ALIAS, v9 }, |
701 | { "stsba" , F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0, "d,[i]o" , F_ALIAS, v9 }, |
702 | { "stsba" , F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o" , F_ALIAS, v9 }, /* stb d,[rs1+0] */ |
703 | { "stuba" , F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A" , F_ALIAS, v6 }, |
704 | { "stuba" , F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A" , F_ALIAS, v6 }, /* stba d,[rs1+%g0] */ |
705 | { "stuba" , F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[1+i]o" , F_ALIAS, v9 }, |
706 | { "stuba" , F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[i+1]o" , F_ALIAS, v9 }, |
707 | { "stuba" , F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0, "d,[i]o" , F_ALIAS, v9 }, |
708 | { "stuba" , F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o" , F_ALIAS, v9 }, /* stb d,[rs1+0] */ |
709 | |
710 | { "std" , F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0), "d,[1+2]" , 0, v6 }, |
711 | { "std" , F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0), "d,[1]" , 0, v6 }, /* std d,[rs1+%g0] */ |
712 | { "std" , F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[1+i]" , 0, v6 }, |
713 | { "std" , F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[i+1]" , 0, v6 }, |
714 | { "std" , F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0, "d,[i]" , 0, v6 }, |
715 | { "std" , F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0), "d,[1]" , 0, v6 }, /* std d,[rs1+0] */ |
716 | |
717 | { "std" , F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI(~0), "q,[1+2]" , 0, v6notv9 }, |
718 | { "std" , F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI_RS2(~0), "q,[1]" , 0, v6notv9 }, /* std d,[rs1+%g0] */ |
719 | { "std" , F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "q,[1+i]" , 0, v6notv9 }, |
720 | { "std" , F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "q,[i+1]" , 0, v6notv9 }, |
721 | { "std" , F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|RS1_G0, "q,[i]" , 0, v6notv9 }, |
722 | { "std" , F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|SIMM13(~0), "q,[1]" , 0, v6notv9 }, /* std d,[rs1+0] */ |
723 | { "std" , F3(3, 0x27, 0), F3(~3, ~0x27, ~0)|ASI(~0), "H,[1+2]" , 0, v6 }, |
724 | { "std" , F3(3, 0x27, 0), F3(~3, ~0x27, ~0)|ASI_RS2(~0), "H,[1]" , 0, v6 }, /* std d,[rs1+%g0] */ |
725 | { "std" , F3(3, 0x27, 1), F3(~3, ~0x27, ~1), "H,[1+i]" , 0, v6 }, |
726 | { "std" , F3(3, 0x27, 1), F3(~3, ~0x27, ~1), "H,[i+1]" , 0, v6 }, |
727 | { "std" , F3(3, 0x27, 1), F3(~3, ~0x27, ~1)|RS1_G0, "H,[i]" , 0, v6 }, |
728 | { "std" , F3(3, 0x27, 1), F3(~3, ~0x27, ~1)|SIMM13(~0), "H,[1]" , 0, v6 }, /* std d,[rs1+0] */ |
729 | |
730 | { "std" , F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI(~0), "Q,[1+2]" , 0, v6notv9 }, |
731 | { "std" , F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI_RS2(~0), "Q,[1]" , 0, v6notv9 }, /* std d,[rs1+%g0] */ |
732 | { "std" , F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "Q,[1+i]" , 0, v6notv9 }, |
733 | { "std" , F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "Q,[i+1]" , 0, v6notv9 }, |
734 | { "std" , F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|RS1_G0, "Q,[i]" , 0, v6notv9 }, |
735 | { "std" , F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|SIMM13(~0), "Q,[1]" , 0, v6notv9 }, /* std d,[rs1+0] */ |
736 | { "std" , F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI(~0), "D,[1+2]" , 0, v6notv9 }, |
737 | { "std" , F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI_RS2(~0), "D,[1]" , 0, v6notv9 }, /* std d,[rs1+%g0] */ |
738 | { "std" , F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "D,[1+i]" , 0, v6notv9 }, |
739 | { "std" , F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "D,[i+1]" , 0, v6notv9 }, |
740 | { "std" , F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|RS1_G0, "D,[i]" , 0, v6notv9 }, |
741 | { "std" , F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|SIMM13(~0), "D,[1]" , 0, v6notv9 }, /* std d,[rs1+0] */ |
742 | |
743 | { "spilld" , F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0), "d,[1+2]" , F_ALIAS, v6 }, |
744 | { "spilld" , F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0), "d,[1]" , F_ALIAS, v6 }, /* std d,[rs1+%g0] */ |
745 | { "spilld" , F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[1+i]" , F_ALIAS, v6 }, |
746 | { "spilld" , F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[i+1]" , F_ALIAS, v6 }, |
747 | { "spilld" , F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0, "d,[i]" , F_ALIAS, v6 }, |
748 | { "spilld" , F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0), "d,[1]" , F_ALIAS, v6 }, /* std d,[rs1+0] */ |
749 | |
750 | { "stda" , F3(3, 0x17, 0), F3(~3, ~0x17, ~0), "d,[1+2]A" , 0, v6 }, |
751 | { "stda" , F3(3, 0x17, 0), F3(~3, ~0x17, ~0)|RS2(~0), "d,[1]A" , 0, v6 }, /* stda d,[rs1+%g0] */ |
752 | { "stda" , F3(3, 0x17, 1), F3(~3, ~0x17, ~1), "d,[1+i]o" , 0, v9 }, |
753 | { "stda" , F3(3, 0x17, 1), F3(~3, ~0x17, ~1), "d,[i+1]o" , 0, v9 }, |
754 | { "stda" , F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|RS1_G0, "d,[i]o" , 0, v9 }, |
755 | { "stda" , F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|SIMM13(~0), "d,[1]o" , 0, v9 }, /* std d,[rs1+0] */ |
756 | { "stda" , F3(3, 0x37, 0), F3(~3, ~0x37, ~0), "H,[1+2]A" , 0, v9 }, |
757 | { "stda" , F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|RS2(~0), "H,[1]A" , 0, v9 }, /* stda d,[rs1+%g0] */ |
758 | { "stda" , F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "H,[1+i]o" , 0, v9 }, |
759 | { "stda" , F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "H,[i+1]o" , 0, v9 }, |
760 | { "stda" , F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|RS1_G0, "H,[i]o" , 0, v9 }, |
761 | { "stda" , F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|SIMM13(~0), "H,[1]o" , 0, v9 }, /* std d,[rs1+0] */ |
762 | |
763 | { "sth" , F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]" , 0, v6 }, |
764 | { "sth" , F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]" , 0, v6 }, /* sth d,[rs1+%g0] */ |
765 | { "sth" , F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]" , 0, v6 }, |
766 | { "sth" , F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]" , 0, v6 }, |
767 | { "sth" , F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0, "d,[i]" , 0, v6 }, |
768 | { "sth" , F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]" , 0, v6 }, /* sth d,[rs1+0] */ |
769 | |
770 | { "stsh" , F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]" , F_ALIAS, v6 }, |
771 | { "stsh" , F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]" , F_ALIAS, v6 }, /* sth d,[rs1+%g0] */ |
772 | { "stsh" , F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]" , F_ALIAS, v6 }, |
773 | { "stsh" , F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]" , F_ALIAS, v6 }, |
774 | { "stsh" , F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0, "d,[i]" , F_ALIAS, v6 }, |
775 | { "stsh" , F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]" , F_ALIAS, v6 }, /* sth d,[rs1+0] */ |
776 | { "stuh" , F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]" , F_ALIAS, v6 }, |
777 | { "stuh" , F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]" , F_ALIAS, v6 }, /* sth d,[rs1+%g0] */ |
778 | { "stuh" , F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]" , F_ALIAS, v6 }, |
779 | { "stuh" , F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]" , F_ALIAS, v6 }, |
780 | { "stuh" , F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0, "d,[i]" , F_ALIAS, v6 }, |
781 | { "stuh" , F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]" , F_ALIAS, v6 }, /* sth d,[rs1+0] */ |
782 | |
783 | { "stha" , F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A" , 0, v6 }, |
784 | { "stha" , F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A" , 0, v6 }, /* stha ,[rs1+%g0] */ |
785 | { "stha" , F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[1+i]o" , 0, v9 }, |
786 | { "stha" , F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[i+1]o" , 0, v9 }, |
787 | { "stha" , F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0, "d,[i]o" , 0, v9 }, |
788 | { "stha" , F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o" , 0, v9 }, /* sth d,[rs1+0] */ |
789 | |
790 | { "stsha" , F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A" , F_ALIAS, v6 }, |
791 | { "stsha" , F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A" , F_ALIAS, v6 }, /* stha ,[rs1+%g0] */ |
792 | { "stsha" , F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[1+i]o" , F_ALIAS, v9 }, |
793 | { "stsha" , F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[i+1]o" , F_ALIAS, v9 }, |
794 | { "stsha" , F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0, "d,[i]o" , F_ALIAS, v9 }, |
795 | { "stsha" , F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o" , F_ALIAS, v9 }, /* sth d,[rs1+0] */ |
796 | { "stuha" , F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A" , F_ALIAS, v6 }, |
797 | { "stuha" , F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A" , F_ALIAS, v6 }, /* stha ,[rs1+%g0] */ |
798 | { "stuha" , F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[1+i]o" , F_ALIAS, v9 }, |
799 | { "stuha" , F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[i+1]o" , F_ALIAS, v9 }, |
800 | { "stuha" , F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0, "d,[i]o" , F_ALIAS, v9 }, |
801 | { "stuha" , F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o" , F_ALIAS, v9 }, /* sth d,[rs1+0] */ |
802 | |
803 | { "stx" , F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|ASI(~0), "d,[1+2]" , 0, v9 }, |
804 | { "stx" , F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|ASI_RS2(~0), "d,[1]" , 0, v9 }, /* stx d,[rs1+%g0] */ |
805 | { "stx" , F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1), "d,[1+i]" , 0, v9 }, |
806 | { "stx" , F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1), "d,[i+1]" , 0, v9 }, |
807 | { "stx" , F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RS1_G0, "d,[i]" , 0, v9 }, |
808 | { "stx" , F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|SIMM13(~0), "d,[1]" , 0, v9 }, /* stx d,[rs1+0] */ |
809 | |
810 | { "stx" , F3(3, 0x25, 0)|RD(1), F3(~3, ~0x25, ~0)|ASI(~0)|RD(~1), "F,[1+2]" , 0, v9 }, |
811 | { "stx" , F3(3, 0x25, 0)|RD(1), F3(~3, ~0x25, ~0)|ASI_RS2(~0)|RD(~1),"F,[1]" , 0, v9 }, /* stx d,[rs1+%g0] */ |
812 | { "stx" , F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RD(~1), "F,[1+i]" , 0, v9 }, |
813 | { "stx" , F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RD(~1), "F,[i+1]" , 0, v9 }, |
814 | { "stx" , F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RS1_G0|RD(~1), "F,[i]" , 0, v9 }, |
815 | { "stx" , F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|SIMM13(~0)|RD(~1),"F,[1]" , 0, v9 }, /* stx d,[rs1+0] */ |
816 | |
817 | { "stxa" , F3(3, 0x1e, 0), F3(~3, ~0x1e, ~0), "d,[1+2]A" , 0, v9 }, |
818 | { "stxa" , F3(3, 0x1e, 0), F3(~3, ~0x1e, ~0)|RS2(~0), "d,[1]A" , 0, v9 }, /* stxa d,[rs1+%g0] */ |
819 | { "stxa" , F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1), "d,[1+i]o" , 0, v9 }, |
820 | { "stxa" , F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1), "d,[i+1]o" , 0, v9 }, |
821 | { "stxa" , F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1)|RS1_G0, "d,[i]o" , 0, v9 }, |
822 | { "stxa" , F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1)|SIMM13(~0), "d,[1]o" , 0, v9 }, /* stx d,[rs1+0] */ |
823 | |
824 | { "stq" , F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI(~0), "J,[1+2]" , 0, v9 }, |
825 | { "stq" , F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI_RS2(~0), "J,[1]" , 0, v9 }, /* stq [rs1+%g0] */ |
826 | { "stq" , F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "J,[1+i]" , 0, v9 }, |
827 | { "stq" , F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "J,[i+1]" , 0, v9 }, |
828 | { "stq" , F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|RS1_G0, "J,[i]" , 0, v9 }, |
829 | { "stq" , F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|SIMM13(~0), "J,[1]" , 0, v9 }, /* stq [rs1+0] */ |
830 | |
831 | { "stqa" , F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI(~0), "J,[1+2]A" , 0, v9 }, |
832 | { "stqa" , F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI_RS2(~0), "J,[1]A" , 0, v9 }, /* stqa [rs1+%g0] */ |
833 | { "stqa" , F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "J,[1+i]o" , 0, v9 }, |
834 | { "stqa" , F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "J,[i+1]o" , 0, v9 }, |
835 | { "stqa" , F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|RS1_G0, "J,[i]o" , 0, v9 }, |
836 | { "stqa" , F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|SIMM13(~0), "J,[1]o" , 0, v9 }, /* stqa [rs1+0] */ |
837 | |
838 | { "swap" , F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI(~0), "[1+2],d" , 0, v7 }, |
839 | { "swap" , F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI_RS2(~0), "[1],d" , 0, v7 }, /* swap [rs1+%g0],d */ |
840 | { "swap" , F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1), "[1+i],d" , 0, v7 }, |
841 | { "swap" , F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1), "[i+1],d" , 0, v7 }, |
842 | { "swap" , F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|RS1_G0, "[i],d" , 0, v7 }, |
843 | { "swap" , F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|SIMM13(~0), "[1],d" , 0, v7 }, /* swap [rs1+0],d */ |
844 | |
845 | { "swapa" , F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0), "[1+2]A,d" , 0, v7 }, |
846 | { "swapa" , F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0)|RS2(~0), "[1]A,d" , 0, v7 }, /* swapa [rs1+%g0],d */ |
847 | { "swapa" , F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1), "[1+i]o,d" , 0, v9 }, |
848 | { "swapa" , F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1), "[i+1]o,d" , 0, v9 }, |
849 | { "swapa" , F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1)|RS1_G0, "[i]o,d" , 0, v9 }, |
850 | { "swapa" , F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1)|SIMM13(~0), "[1]o,d" , 0, v9 }, /* swap [rs1+0],d */ |
851 | |
852 | { "restore" , F3(2, 0x3d, 0), F3(~2, ~0x3d, ~0)|ASI(~0), "1,2,d" , 0, v6 }, |
853 | { "restore" , F3(2, 0x3d, 0), F3(~2, ~0x3d, ~0)|RD_G0|RS1_G0|ASI_RS2(~0), "" , 0, v6 }, /* restore %g0,%g0,%g0 */ |
854 | { "restore" , F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1), "1,i,d" , 0, v6 }, |
855 | { "restore" , F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1)|RD_G0|RS1_G0|SIMM13(~0), "" , 0, v6 }, /* restore %g0,0,%g0 */ |
856 | |
857 | { "rett" , F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI(~0), "1+2" , F_UNBR|F_DELAYED, v6 }, /* rett rs1+rs2 */ |
858 | { "rett" , F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI_RS2(~0), "1" , F_UNBR|F_DELAYED, v6 }, /* rett rs1,%g0 */ |
859 | { "rett" , F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0, "1+i" , F_UNBR|F_DELAYED, v6 }, /* rett rs1+X */ |
860 | { "rett" , F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0, "i+1" , F_UNBR|F_DELAYED, v6 }, /* rett X+rs1 */ |
861 | { "rett" , F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0, "i" , F_UNBR|F_DELAYED, v6 }, /* rett X+rs1 */ |
862 | { "rett" , F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0, "i" , F_UNBR|F_DELAYED, v6 }, /* rett X */ |
863 | { "rett" , F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|SIMM13(~0), "1" , F_UNBR|F_DELAYED, v6 }, /* rett rs1+0 */ |
864 | |
865 | { "save" , F3(2, 0x3c, 0), F3(~2, ~0x3c, ~0)|ASI(~0), "1,2,d" , 0, v6 }, |
866 | { "save" , F3(2, 0x3c, 1), F3(~2, ~0x3c, ~1), "1,i,d" , 0, v6 }, |
867 | { "save" , 0x81e00000, ~0x81e00000, "" , F_ALIAS, v6 }, |
868 | |
869 | { "ret" , F3(2, 0x38, 1)|RS1(0x1f)|SIMM13(8), F3(~2, ~0x38, ~1)|SIMM13(~8), "" , F_UNBR|F_DELAYED, v6 }, /* jmpl %i7+8,%g0 */ |
870 | { "retl" , F3(2, 0x38, 1)|RS1(0x0f)|SIMM13(8), F3(~2, ~0x38, ~1)|RS1(~0x0f)|SIMM13(~8), "" , F_UNBR|F_DELAYED, v6 }, /* jmpl %o7+8,%g0 */ |
871 | |
872 | { "jmpl" , F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|ASI(~0), "1+2,d" , F_JSR|F_DELAYED, v6 }, |
873 | { "jmpl" , F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|ASI_RS2(~0), "1,d" , F_JSR|F_DELAYED, v6 }, /* jmpl rs1+%g0,d */ |
874 | { "jmpl" , F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|SIMM13(~0), "1,d" , F_JSR|F_DELAYED, v6 }, /* jmpl rs1+0,d */ |
875 | { "jmpl" , F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RS1_G0, "i,d" , F_JSR|F_DELAYED, v6 }, /* jmpl %g0+i,d */ |
876 | { "jmpl" , F3(2, 0x38, 1), F3(~2, ~0x38, ~1), "1+i,d" , F_JSR|F_DELAYED, v6 }, |
877 | { "jmpl" , F3(2, 0x38, 1), F3(~2, ~0x38, ~1), "i+1,d" , F_JSR|F_DELAYED, v6 }, |
878 | |
879 | { "done" , F3(2, 0x3e, 0)|RD(0), F3(~2, ~0x3e, ~0)|RD(~0)|RS1_G0|SIMM13(~0), "" , 0, v9 }, |
880 | { "retry" , F3(2, 0x3e, 0)|RD(1), F3(~2, ~0x3e, ~0)|RD(~1)|RS1_G0|SIMM13(~0), "" , 0, v9 }, |
881 | { "saved" , F3(2, 0x31, 0)|RD(0), F3(~2, ~0x31, ~0)|RD(~0)|RS1_G0|SIMM13(~0), "" , 0, v9 }, |
882 | { "restored" , F3(2, 0x31, 0)|RD(1), F3(~2, ~0x31, ~0)|RD(~1)|RS1_G0|SIMM13(~0), "" , 0, v9 }, |
883 | { "allclean" , F3(2, 0x31, 0)|RD(2), F3(~2, ~0x31, ~0)|RD(~2)|RS1_G0|SIMM13(~0), "" , 0, v9 }, |
884 | { "otherw" , F3(2, 0x31, 0)|RD(3), F3(~2, ~0x31, ~0)|RD(~3)|RS1_G0|SIMM13(~0), "" , 0, v9 }, |
885 | { "normalw" , F3(2, 0x31, 0)|RD(4), F3(~2, ~0x31, ~0)|RD(~4)|RS1_G0|SIMM13(~0), "" , 0, v9 }, |
886 | { "invalw" , F3(2, 0x31, 0)|RD(5), F3(~2, ~0x31, ~0)|RD(~5)|RS1_G0|SIMM13(~0), "" , 0, v9 }, |
887 | { "sir" , F3(2, 0x30, 1)|RD(0xf), F3(~2, ~0x30, ~1)|RD(~0xf)|RS1_G0, "i" , 0, v9 }, |
888 | |
889 | { "flush" , F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0), "1+2" , 0, v8 }, |
890 | { "flush" , F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0), "1" , 0, v8 }, /* flush rs1+%g0 */ |
891 | { "flush" , F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0), "1" , 0, v8 }, /* flush rs1+0 */ |
892 | { "flush" , F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0, "i" , 0, v8 }, /* flush %g0+i */ |
893 | { "flush" , F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "1+i" , 0, v8 }, |
894 | { "flush" , F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "i+1" , 0, v8 }, |
895 | |
896 | /* IFLUSH was renamed to FLUSH in v8. */ |
897 | { "iflush" , F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0), "1+2" , F_ALIAS, v6 }, |
898 | { "iflush" , F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0), "1" , F_ALIAS, v6 }, /* flush rs1+%g0 */ |
899 | { "iflush" , F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0), "1" , F_ALIAS, v6 }, /* flush rs1+0 */ |
900 | { "iflush" , F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0, "i" , F_ALIAS, v6 }, |
901 | { "iflush" , F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "1+i" , F_ALIAS, v6 }, |
902 | { "iflush" , F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "i+1" , F_ALIAS, v6 }, |
903 | |
904 | { "return" , F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|ASI(~0), "1+2" , 0, v9 }, |
905 | { "return" , F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|ASI_RS2(~0), "1" , 0, v9 }, /* return rs1+%g0 */ |
906 | { "return" , F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|SIMM13(~0), "1" , 0, v9 }, /* return rs1+0 */ |
907 | { "return" , F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RS1_G0, "i" , 0, v9 }, /* return %g0+i */ |
908 | { "return" , F3(2, 0x39, 1), F3(~2, ~0x39, ~1), "1+i" , 0, v9 }, |
909 | { "return" , F3(2, 0x39, 1), F3(~2, ~0x39, ~1), "i+1" , 0, v9 }, |
910 | |
911 | { "flushw" , F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RD_G0|RS1_G0|ASI_RS2(~0), "" , 0, v9 }, |
912 | |
913 | { "membar" , F3(2, 0x28, 1)|RS1(0xf), F3(~2, ~0x28, ~1)|RD_G0|RS1(~0xf)|SIMM13(~127), "K" , 0, v9 }, |
914 | { "stbar" , F3(2, 0x28, 0)|RS1(0xf), F3(~2, ~0x28, ~0)|RD_G0|RS1(~0xf)|SIMM13(~0), "" , 0, v8 }, |
915 | |
916 | { "prefetch" , F3(3, 0x2d, 0), F3(~3, ~0x2d, ~0), "[1+2],*" , 0, v9 }, |
917 | { "prefetch" , F3(3, 0x2d, 0), F3(~3, ~0x2d, ~0)|RS2_G0, "[1],*" , 0, v9 }, /* prefetch [rs1+%g0],prefetch_fcn */ |
918 | { "prefetch" , F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1), "[1+i],*" , 0, v9 }, |
919 | { "prefetch" , F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1), "[i+1],*" , 0, v9 }, |
920 | { "prefetch" , F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1)|RS1_G0, "[i],*" , 0, v9 }, |
921 | { "prefetch" , F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1)|SIMM13(~0), "[1],*" , 0, v9 }, /* prefetch [rs1+0],prefetch_fcn */ |
922 | { "prefetcha" , F3(3, 0x3d, 0), F3(~3, ~0x3d, ~0), "[1+2]A,*" , 0, v9 }, |
923 | { "prefetcha" , F3(3, 0x3d, 0), F3(~3, ~0x3d, ~0)|RS2_G0, "[1]A,*" , 0, v9 }, /* prefetcha [rs1+%g0],prefetch_fcn */ |
924 | { "prefetcha" , F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1), "[1+i]o,*" , 0, v9 }, |
925 | { "prefetcha" , F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1), "[i+1]o,*" , 0, v9 }, |
926 | { "prefetcha" , F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1)|RS1_G0, "[i]o,*" , 0, v9 }, |
927 | { "prefetcha" , F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1)|SIMM13(~0), "[1]o,*" , 0, v9 }, /* prefetcha [rs1+0],d */ |
928 | |
929 | { "sll" , F3(2, 0x25, 0), F3(~2, ~0x25, ~0)|(1<<12)|(0x7f<<5), "1,2,d" , 0, v6 }, |
930 | { "sll" , F3(2, 0x25, 1), F3(~2, ~0x25, ~1)|(1<<12)|(0x7f<<5), "1,X,d" , 0, v6 }, |
931 | { "sra" , F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|(0x7f<<5), "1,2,d" , 0, v6 }, |
932 | { "sra" , F3(2, 0x27, 1), F3(~2, ~0x27, ~1)|(1<<12)|(0x7f<<5), "1,X,d" , 0, v6 }, |
933 | { "srl" , F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|(0x7f<<5), "1,2,d" , 0, v6 }, |
934 | { "srl" , F3(2, 0x26, 1), F3(~2, ~0x26, ~1)|(1<<12)|(0x7f<<5), "1,X,d" , 0, v6 }, |
935 | |
936 | { "sllx" , F3(2, 0x25, 0)|(1<<12), F3(~2, ~0x25, ~0)|(0x7f<<5), "1,2,d" , 0, v9 }, |
937 | { "sllx" , F3(2, 0x25, 1)|(1<<12), F3(~2, ~0x25, ~1)|(0x3f<<6), "1,Y,d" , 0, v9 }, |
938 | { "srax" , F3(2, 0x27, 0)|(1<<12), F3(~2, ~0x27, ~0)|(0x7f<<5), "1,2,d" , 0, v9 }, |
939 | { "srax" , F3(2, 0x27, 1)|(1<<12), F3(~2, ~0x27, ~1)|(0x3f<<6), "1,Y,d" , 0, v9 }, |
940 | { "srlx" , F3(2, 0x26, 0)|(1<<12), F3(~2, ~0x26, ~0)|(0x7f<<5), "1,2,d" , 0, v9 }, |
941 | { "srlx" , F3(2, 0x26, 1)|(1<<12), F3(~2, ~0x26, ~1)|(0x3f<<6), "1,Y,d" , 0, v9 }, |
942 | |
943 | { "mulscc" , F3(2, 0x24, 0), F3(~2, ~0x24, ~0)|ASI(~0), "1,2,d" , 0, v6 }, |
944 | { "mulscc" , F3(2, 0x24, 1), F3(~2, ~0x24, ~1), "1,i,d" , 0, v6 }, |
945 | |
946 | { "divscc" , F3(2, 0x1d, 0), F3(~2, ~0x1d, ~0)|ASI(~0), "1,2,d" , 0, sparclite }, |
947 | { "divscc" , F3(2, 0x1d, 1), F3(~2, ~0x1d, ~1), "1,i,d" , 0, sparclite }, |
948 | |
949 | { "scan" , F3(2, 0x2c, 0), F3(~2, ~0x2c, ~0)|ASI(~0), "1,2,d" , 0, sparclet|sparclite }, |
950 | { "scan" , F3(2, 0x2c, 1), F3(~2, ~0x2c, ~1), "1,i,d" , 0, sparclet|sparclite }, |
951 | |
952 | { "popc" , F3(2, 0x2e, 0), F3(~2, ~0x2e, ~0)|RS1_G0|ASI(~0),"2,d" , 0, v9 }, |
953 | { "popc" , F3(2, 0x2e, 1), F3(~2, ~0x2e, ~1)|RS1_G0, "i,d" , 0, v9 }, |
954 | |
955 | { "clr" , F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RD_G0|RS1_G0|ASI_RS2(~0), "d" , F_ALIAS, v6 }, /* or %g0,%g0,d */ |
956 | { "clr" , F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0|SIMM13(~0), "d" , F_ALIAS, v6 }, /* or %g0,0,d */ |
957 | { "clr" , F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0|ASI(~0), "[1+2]" , F_ALIAS, v6 }, |
958 | { "clr" , F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0|ASI_RS2(~0), "[1]" , F_ALIAS, v6 }, /* st %g0,[rs1+%g0] */ |
959 | { "clr" , F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0, "[1+i]" , F_ALIAS, v6 }, |
960 | { "clr" , F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0, "[i+1]" , F_ALIAS, v6 }, |
961 | { "clr" , F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0|RS1_G0, "[i]" , F_ALIAS, v6 }, |
962 | { "clr" , F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0|SIMM13(~0), "[1]" , F_ALIAS, v6 }, /* st %g0,[rs1+0] */ |
963 | |
964 | { "clrb" , F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0|ASI(~0), "[1+2]" , F_ALIAS, v6 }, |
965 | { "clrb" , F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0|ASI_RS2(~0), "[1]" , F_ALIAS, v6 }, /* stb %g0,[rs1+%g0] */ |
966 | { "clrb" , F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0, "[1+i]" , F_ALIAS, v6 }, |
967 | { "clrb" , F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0, "[i+1]" , F_ALIAS, v6 }, |
968 | { "clrb" , F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0|RS1_G0, "[i]" , F_ALIAS, v6 }, |
969 | { "clrb" , F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0|SIMM13(~0), "[1]" , F_ALIAS, v6 }, /* stb %g0,[rs1+0] */ |
970 | |
971 | { "clrh" , F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0|ASI(~0), "[1+2]" , F_ALIAS, v6 }, |
972 | { "clrh" , F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0|ASI_RS2(~0), "[1]" , F_ALIAS, v6 }, /* sth %g0,[rs1+%g0] */ |
973 | { "clrh" , F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0, "[1+i]" , F_ALIAS, v6 }, |
974 | { "clrh" , F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0, "[i+1]" , F_ALIAS, v6 }, |
975 | { "clrh" , F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0|RS1_G0, "[i]" , F_ALIAS, v6 }, |
976 | { "clrh" , F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0|SIMM13(~0), "[1]" , F_ALIAS, v6 }, /* sth %g0,[rs1+0] */ |
977 | |
978 | { "clrx" , F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|RD_G0|ASI(~0), "[1+2]" , F_ALIAS, v9 }, |
979 | { "clrx" , F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|RD_G0|ASI_RS2(~0), "[1]" , F_ALIAS, v9 }, /* stx %g0,[rs1+%g0] */ |
980 | { "clrx" , F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0, "[1+i]" , F_ALIAS, v9 }, |
981 | { "clrx" , F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0, "[i+1]" , F_ALIAS, v9 }, |
982 | { "clrx" , F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0|RS1_G0, "[i]" , F_ALIAS, v9 }, |
983 | { "clrx" , F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0|SIMM13(~0), "[1]" , F_ALIAS, v9 }, /* stx %g0,[rs1+0] */ |
984 | |
985 | { "orcc" , F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|ASI(~0), "1,2,d" , 0, v6 }, |
986 | { "orcc" , F3(2, 0x12, 1), F3(~2, ~0x12, ~1), "1,i,d" , 0, v6 }, |
987 | { "orcc" , F3(2, 0x12, 1), F3(~2, ~0x12, ~1), "i,1,d" , 0, v6 }, |
988 | |
989 | /* This is not a commutative instruction. */ |
990 | { "orncc" , F3(2, 0x16, 0), F3(~2, ~0x16, ~0)|ASI(~0), "1,2,d" , 0, v6 }, |
991 | { "orncc" , F3(2, 0x16, 1), F3(~2, ~0x16, ~1), "1,i,d" , 0, v6 }, |
992 | |
993 | /* This is not a commutative instruction. */ |
994 | { "orn" , F3(2, 0x06, 0), F3(~2, ~0x06, ~0)|ASI(~0), "1,2,d" , 0, v6 }, |
995 | { "orn" , F3(2, 0x06, 1), F3(~2, ~0x06, ~1), "1,i,d" , 0, v6 }, |
996 | |
997 | { "tst" , F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0|ASI_RS2(~0), "1" , 0, v6 }, /* orcc rs1, %g0, %g0 */ |
998 | { "tst" , F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0|RS1_G0|ASI(~0), "2" , 0, v6 }, /* orcc %g0, rs2, %g0 */ |
999 | { "tst" , F3(2, 0x12, 1), F3(~2, ~0x12, ~1)|RD_G0|SIMM13(~0), "1" , 0, v6 }, /* orcc rs1, 0, %g0 */ |
1000 | |
1001 | { "wr" , F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI(~0), "1,2,m" , 0, v8 }, /* wr r,r,%asrX */ |
1002 | { "wr" , F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "1,i,m" , 0, v8 }, /* wr r,i,%asrX */ |
1003 | { "wr" , F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI_RS2(~0), "1,m" , F_ALIAS, v8 }, /* wr rs1,%g0,%asrX */ |
1004 | { "wr" , F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI(~0), "1,2,y" , 0, v6 }, /* wr r,r,%y */ |
1005 | { "wr" , F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0, "1,i,y" , 0, v6 }, /* wr r,i,%y */ |
1006 | { "wr" , F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI_RS2(~0), "1,y" , F_ALIAS, v6 }, /* wr rs1,%g0,%y */ |
1007 | { "wr" , F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI(~0), "1,2,p" , 0, v6notv9 }, /* wr r,r,%psr */ |
1008 | { "wr" , F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0, "1,i,p" , 0, v6notv9 }, /* wr r,i,%psr */ |
1009 | { "wr" , F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI_RS2(~0), "1,p" , F_ALIAS, v6notv9 }, /* wr rs1,%g0,%psr */ |
1010 | { "wr" , F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI(~0), "1,2,w" , 0, v6notv9 }, /* wr r,r,%wim */ |
1011 | { "wr" , F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0, "1,i,w" , 0, v6notv9 }, /* wr r,i,%wim */ |
1012 | { "wr" , F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI_RS2(~0), "1,w" , F_ALIAS, v6notv9 }, /* wr rs1,%g0,%wim */ |
1013 | { "wr" , F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI(~0), "1,2,t" , 0, v6notv9 }, /* wr r,r,%tbr */ |
1014 | { "wr" , F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0, "1,i,t" , 0, v6notv9 }, /* wr r,i,%tbr */ |
1015 | { "wr" , F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI_RS2(~0), "1,t" , F_ALIAS, v6notv9 }, /* wr rs1,%g0,%tbr */ |
1016 | |
1017 | { "wr" , F3(2, 0x30, 0)|RD(2), F3(~2, ~0x30, ~0)|RD(~2)|ASI(~0), "1,2,E" , 0, v9 }, /* wr r,r,%ccr */ |
1018 | { "wr" , F3(2, 0x30, 1)|RD(2), F3(~2, ~0x30, ~1)|RD(~2), "1,i,E" , 0, v9 }, /* wr r,i,%ccr */ |
1019 | { "wr" , F3(2, 0x30, 0)|RD(3), F3(~2, ~0x30, ~0)|RD(~3)|ASI(~0), "1,2,o" , 0, v9 }, /* wr r,r,%asi */ |
1020 | { "wr" , F3(2, 0x30, 1)|RD(3), F3(~2, ~0x30, ~1)|RD(~3), "1,i,o" , 0, v9 }, /* wr r,i,%asi */ |
1021 | { "wr" , F3(2, 0x30, 0)|RD(6), F3(~2, ~0x30, ~0)|RD(~6)|ASI(~0), "1,2,s" , 0, v9 }, /* wr r,r,%fprs */ |
1022 | { "wr" , F3(2, 0x30, 1)|RD(6), F3(~2, ~0x30, ~1)|RD(~6), "1,i,s" , 0, v9 }, /* wr r,i,%fprs */ |
1023 | |
1024 | { "wr" , F3(2, 0x30, 0)|RD(16), F3(~2, ~0x30, ~0)|RD(~16)|ASI(~0), "1,2,_" , 0, v9a }, /* wr r,r,%pcr */ |
1025 | { "wr" , F3(2, 0x30, 1)|RD(16), F3(~2, ~0x30, ~1)|RD(~16), "1,i,_" , 0, v9a }, /* wr r,i,%pcr */ |
1026 | { "wr" , F3(2, 0x30, 0)|RD(17), F3(~2, ~0x30, ~0)|RD(~17)|ASI(~0), "1,2,_" , 0, v9a }, /* wr r,r,%pic */ |
1027 | { "wr" , F3(2, 0x30, 1)|RD(17), F3(~2, ~0x30, ~1)|RD(~17), "1,i,_" , 0, v9a }, /* wr r,i,%pic */ |
1028 | { "wr" , F3(2, 0x30, 0)|RD(18), F3(~2, ~0x30, ~0)|RD(~18)|ASI(~0), "1,2,_" , 0, v9a }, /* wr r,r,%dcr */ |
1029 | { "wr" , F3(2, 0x30, 1)|RD(18), F3(~2, ~0x30, ~1)|RD(~18), "1,i,_" , 0, v9a }, /* wr r,i,%dcr */ |
1030 | { "wr" , F3(2, 0x30, 0)|RD(19), F3(~2, ~0x30, ~0)|RD(~19)|ASI(~0), "1,2,_" , 0, v9a }, /* wr r,r,%gsr */ |
1031 | { "wr" , F3(2, 0x30, 1)|RD(19), F3(~2, ~0x30, ~1)|RD(~19), "1,i,_" , 0, v9a }, /* wr r,i,%gsr */ |
1032 | { "wr" , F3(2, 0x30, 0)|RD(20), F3(~2, ~0x30, ~0)|RD(~20)|ASI(~0), "1,2,_" , 0, v9a }, /* wr r,r,%set_softint */ |
1033 | { "wr" , F3(2, 0x30, 1)|RD(20), F3(~2, ~0x30, ~1)|RD(~20), "1,i,_" , 0, v9a }, /* wr r,i,%set_softint */ |
1034 | { "wr" , F3(2, 0x30, 0)|RD(21), F3(~2, ~0x30, ~0)|RD(~21)|ASI(~0), "1,2,_" , 0, v9a }, /* wr r,r,%clear_softint */ |
1035 | { "wr" , F3(2, 0x30, 1)|RD(21), F3(~2, ~0x30, ~1)|RD(~21), "1,i,_" , 0, v9a }, /* wr r,i,%clear_softint */ |
1036 | { "wr" , F3(2, 0x30, 0)|RD(22), F3(~2, ~0x30, ~0)|RD(~22)|ASI(~0), "1,2,_" , 0, v9a }, /* wr r,r,%softint */ |
1037 | { "wr" , F3(2, 0x30, 1)|RD(22), F3(~2, ~0x30, ~1)|RD(~22), "1,i,_" , 0, v9a }, /* wr r,i,%softint */ |
1038 | { "wr" , F3(2, 0x30, 0)|RD(23), F3(~2, ~0x30, ~0)|RD(~23)|ASI(~0), "1,2,_" , 0, v9a }, /* wr r,r,%tick_cmpr */ |
1039 | { "wr" , F3(2, 0x30, 1)|RD(23), F3(~2, ~0x30, ~1)|RD(~23), "1,i,_" , 0, v9a }, /* wr r,i,%tick_cmpr */ |
1040 | { "wr" , F3(2, 0x30, 0)|RD(24), F3(~2, ~0x30, ~0)|RD(~24)|ASI(~0), "1,2,_" , 0, v9b }, /* wr r,r,%sys_tick */ |
1041 | { "wr" , F3(2, 0x30, 1)|RD(24), F3(~2, ~0x30, ~1)|RD(~24), "1,i,_" , 0, v9b }, /* wr r,i,%sys_tick */ |
1042 | { "wr" , F3(2, 0x30, 0)|RD(25), F3(~2, ~0x30, ~0)|RD(~25)|ASI(~0), "1,2,_" , 0, v9b }, /* wr r,r,%sys_tick_cmpr */ |
1043 | { "wr" , F3(2, 0x30, 1)|RD(25), F3(~2, ~0x30, ~1)|RD(~25), "1,i,_" , 0, v9b }, /* wr r,i,%sys_tick_cmpr */ |
1044 | |
1045 | { "rd" , F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|SIMM13(~0), "M,d" , 0, v8 }, /* rd %asrX,r */ |
1046 | { "rd" , F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0), "y,d" , 0, v6 }, /* rd %y,r */ |
1047 | { "rd" , F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|RS1_G0|SIMM13(~0), "p,d" , 0, v6notv9 }, /* rd %psr,r */ |
1048 | { "rd" , F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|RS1_G0|SIMM13(~0), "w,d" , 0, v6notv9 }, /* rd %wim,r */ |
1049 | { "rd" , F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RS1_G0|SIMM13(~0), "t,d" , 0, v6notv9 }, /* rd %tbr,r */ |
1050 | |
1051 | { "rd" , F3(2, 0x28, 0)|RS1(2), F3(~2, ~0x28, ~0)|RS1(~2)|SIMM13(~0), "E,d" , 0, v9 }, /* rd %ccr,r */ |
1052 | { "rd" , F3(2, 0x28, 0)|RS1(3), F3(~2, ~0x28, ~0)|RS1(~3)|SIMM13(~0), "o,d" , 0, v9 }, /* rd %asi,r */ |
1053 | { "rd" , F3(2, 0x28, 0)|RS1(4), F3(~2, ~0x28, ~0)|RS1(~4)|SIMM13(~0), "W,d" , 0, v9 }, /* rd %tick,r */ |
1054 | { "rd" , F3(2, 0x28, 0)|RS1(5), F3(~2, ~0x28, ~0)|RS1(~5)|SIMM13(~0), "P,d" , 0, v9 }, /* rd %pc,r */ |
1055 | { "rd" , F3(2, 0x28, 0)|RS1(6), F3(~2, ~0x28, ~0)|RS1(~6)|SIMM13(~0), "s,d" , 0, v9 }, /* rd %fprs,r */ |
1056 | |
1057 | { "rd" , F3(2, 0x28, 0)|RS1(16), F3(~2, ~0x28, ~0)|RS1(~16)|SIMM13(~0), "/,d" , 0, v9a }, /* rd %pcr,r */ |
1058 | { "rd" , F3(2, 0x28, 0)|RS1(17), F3(~2, ~0x28, ~0)|RS1(~17)|SIMM13(~0), "/,d" , 0, v9a }, /* rd %pic,r */ |
1059 | { "rd" , F3(2, 0x28, 0)|RS1(18), F3(~2, ~0x28, ~0)|RS1(~18)|SIMM13(~0), "/,d" , 0, v9a }, /* rd %dcr,r */ |
1060 | { "rd" , F3(2, 0x28, 0)|RS1(19), F3(~2, ~0x28, ~0)|RS1(~19)|SIMM13(~0), "/,d" , 0, v9a }, /* rd %gsr,r */ |
1061 | { "rd" , F3(2, 0x28, 0)|RS1(22), F3(~2, ~0x28, ~0)|RS1(~22)|SIMM13(~0), "/,d" , 0, v9a }, /* rd %softint,r */ |
1062 | { "rd" , F3(2, 0x28, 0)|RS1(23), F3(~2, ~0x28, ~0)|RS1(~23)|SIMM13(~0), "/,d" , 0, v9a }, /* rd %tick_cmpr,r */ |
1063 | { "rd" , F3(2, 0x28, 0)|RS1(24), F3(~2, ~0x28, ~0)|RS1(~24)|SIMM13(~0), "/,d" , 0, v9b }, /* rd %sys_tick,r */ |
1064 | { "rd" , F3(2, 0x28, 0)|RS1(25), F3(~2, ~0x28, ~0)|RS1(~25)|SIMM13(~0), "/,d" , 0, v9b }, /* rd %sys_tick_cmpr,r */ |
1065 | |
1066 | { "rdpr" , F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|SIMM13(~0), "?,d" , 0, v9 }, /* rdpr %priv,r */ |
1067 | { "wrpr" , F3(2, 0x32, 0), F3(~2, ~0x32, ~0), "1,2,!" , 0, v9 }, /* wrpr r1,r2,%priv */ |
1068 | { "wrpr" , F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|SIMM13(~0), "1,!" , 0, v9 }, /* wrpr r1,%priv */ |
1069 | { "wrpr" , F3(2, 0x32, 1), F3(~2, ~0x32, ~1), "1,i,!" , 0, v9 }, /* wrpr r1,i,%priv */ |
1070 | { "wrpr" , F3(2, 0x32, 1), F3(~2, ~0x32, ~1), "i,1,!" , F_ALIAS, v9 }, /* wrpr i,r1,%priv */ |
1071 | { "wrpr" , F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RS1(~0), "i,!" , 0, v9 }, /* wrpr i,%priv */ |
1072 | |
1073 | { "rdhpr" , F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|SIMM13(~0), "$,d" , 0, v9 }, /* rdhpr %hpriv,r */ |
1074 | { "wrhpr" , F3(2, 0x33, 0), F3(~2, ~0x33, ~0), "1,2,%" , 0, v9 }, /* wrhpr r1,r2,%hpriv */ |
1075 | { "wrhpr" , F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|SIMM13(~0), "1,%" , 0, v9 }, /* wrhpr r1,%hpriv */ |
1076 | { "wrhpr" , F3(2, 0x33, 1), F3(~2, ~0x33, ~1), "1,i,%" , 0, v9 }, /* wrhpr r1,i,%hpriv */ |
1077 | { "wrhpr" , F3(2, 0x33, 1), F3(~2, ~0x33, ~1), "i,1,%" , F_ALIAS, v9 }, /* wrhpr i,r1,%hpriv */ |
1078 | { "wrhpr" , F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RS1(~0), "i,%" , 0, v9 }, /* wrhpr i,%hpriv */ |
1079 | |
1080 | /* ??? This group seems wrong. A three operand move? */ |
1081 | { "mov" , F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI(~0), "1,2,m" , F_ALIAS, v8 }, /* wr r,r,%asrX */ |
1082 | { "mov" , F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "1,i,m" , F_ALIAS, v8 }, /* wr r,i,%asrX */ |
1083 | { "mov" , F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI(~0), "1,2,y" , F_ALIAS, v6 }, /* wr r,r,%y */ |
1084 | { "mov" , F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0, "1,i,y" , F_ALIAS, v6 }, /* wr r,i,%y */ |
1085 | { "mov" , F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI(~0), "1,2,p" , F_ALIAS, v6notv9 }, /* wr r,r,%psr */ |
1086 | { "mov" , F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0, "1,i,p" , F_ALIAS, v6notv9 }, /* wr r,i,%psr */ |
1087 | { "mov" , F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI(~0), "1,2,w" , F_ALIAS, v6notv9 }, /* wr r,r,%wim */ |
1088 | { "mov" , F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0, "1,i,w" , F_ALIAS, v6notv9 }, /* wr r,i,%wim */ |
1089 | { "mov" , F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI(~0), "1,2,t" , F_ALIAS, v6notv9 }, /* wr r,r,%tbr */ |
1090 | { "mov" , F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0, "1,i,t" , F_ALIAS, v6notv9 }, /* wr r,i,%tbr */ |
1091 | |
1092 | { "mov" , F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|SIMM13(~0), "M,d" , F_ALIAS, v8 }, /* rd %asr1,r */ |
1093 | { "mov" , F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0), "y,d" , F_ALIAS, v6 }, /* rd %y,r */ |
1094 | { "mov" , F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|RS1_G0|SIMM13(~0), "p,d" , F_ALIAS, v6notv9 }, /* rd %psr,r */ |
1095 | { "mov" , F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|RS1_G0|SIMM13(~0), "w,d" , F_ALIAS, v6notv9 }, /* rd %wim,r */ |
1096 | { "mov" , F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RS1_G0|SIMM13(~0), "t,d" , F_ALIAS, v6notv9 }, /* rd %tbr,r */ |
1097 | |
1098 | { "mov" , F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI_RS2(~0), "1,m" , F_ALIAS, v8 }, /* wr rs1,%g0,%asrX */ |
1099 | { "mov" , F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "i,m" , F_ALIAS, v8 }, /* wr %g0,i,%asrX */ |
1100 | { "mov" , F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|SIMM13(~0), "1,m" , F_ALIAS, v8 }, /* wr rs1,0,%asrX */ |
1101 | { "mov" , F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI_RS2(~0), "1,y" , F_ALIAS, v6 }, /* wr rs1,%g0,%y */ |
1102 | { "mov" , F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0, "i,y" , F_ALIAS, v6 }, /* wr %g0,i,%y */ |
1103 | { "mov" , F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0|SIMM13(~0), "1,y" , F_ALIAS, v6 }, /* wr rs1,0,%y */ |
1104 | { "mov" , F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI_RS2(~0), "1,p" , F_ALIAS, v6notv9 }, /* wr rs1,%g0,%psr */ |
1105 | { "mov" , F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0, "i,p" , F_ALIAS, v6notv9 }, /* wr %g0,i,%psr */ |
1106 | { "mov" , F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0|SIMM13(~0), "1,p" , F_ALIAS, v6notv9 }, /* wr rs1,0,%psr */ |
1107 | { "mov" , F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI_RS2(~0), "1,w" , F_ALIAS, v6notv9 }, /* wr rs1,%g0,%wim */ |
1108 | { "mov" , F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0, "i,w" , F_ALIAS, v6notv9 }, /* wr %g0,i,%wim */ |
1109 | { "mov" , F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0|SIMM13(~0), "1,w" , F_ALIAS, v6notv9 }, /* wr rs1,0,%wim */ |
1110 | { "mov" , F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI_RS2(~0), "1,t" , F_ALIAS, v6notv9 }, /* wr rs1,%g0,%tbr */ |
1111 | { "mov" , F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0, "i,t" , F_ALIAS, v6notv9 }, /* wr %g0,i,%tbr */ |
1112 | { "mov" , F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0|SIMM13(~0), "1,t" , F_ALIAS, v6notv9 }, /* wr rs1,0,%tbr */ |
1113 | |
1114 | { "mov" , F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RS1_G0|ASI(~0), "2,d" , 0, v6 }, /* or %g0,rs2,d */ |
1115 | { "mov" , F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0, "i,d" , 0, v6 }, /* or %g0,i,d */ |
1116 | { "mov" , F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI_RS2(~0), "1,d" , 0, v6 }, /* or rs1,%g0,d */ |
1117 | { "mov" , F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|SIMM13(~0), "1,d" , 0, v6 }, /* or rs1,0,d */ |
1118 | |
1119 | { "or" , F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI(~0), "1,2,d" , 0, v6 }, |
1120 | { "or" , F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "1,i,d" , 0, v6 }, |
1121 | { "or" , F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "i,1,d" , 0, v6 }, |
1122 | |
1123 | { "bset" , F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI(~0), "2,r" , F_ALIAS, v6 }, /* or rd,rs2,rd */ |
1124 | { "bset" , F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "i,r" , F_ALIAS, v6 }, /* or rd,i,rd */ |
1125 | |
1126 | /* This is not a commutative instruction. */ |
1127 | { "andn" , F3(2, 0x05, 0), F3(~2, ~0x05, ~0)|ASI(~0), "1,2,d" , 0, v6 }, |
1128 | { "andn" , F3(2, 0x05, 1), F3(~2, ~0x05, ~1), "1,i,d" , 0, v6 }, |
1129 | |
1130 | /* This is not a commutative instruction. */ |
1131 | { "andncc" , F3(2, 0x15, 0), F3(~2, ~0x15, ~0)|ASI(~0), "1,2,d" , 0, v6 }, |
1132 | { "andncc" , F3(2, 0x15, 1), F3(~2, ~0x15, ~1), "1,i,d" , 0, v6 }, |
1133 | |
1134 | { "bclr" , F3(2, 0x05, 0), F3(~2, ~0x05, ~0)|ASI(~0), "2,r" , F_ALIAS, v6 }, /* andn rd,rs2,rd */ |
1135 | { "bclr" , F3(2, 0x05, 1), F3(~2, ~0x05, ~1), "i,r" , F_ALIAS, v6 }, /* andn rd,i,rd */ |
1136 | |
1137 | { "cmp" , F3(2, 0x14, 0), F3(~2, ~0x14, ~0)|RD_G0|ASI(~0), "1,2" , 0, v6 }, /* subcc rs1,rs2,%g0 */ |
1138 | { "cmp" , F3(2, 0x14, 1), F3(~2, ~0x14, ~1)|RD_G0, "1,i" , 0, v6 }, /* subcc rs1,i,%g0 */ |
1139 | |
1140 | { "sub" , F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|ASI(~0), "1,2,d" , 0, v6 }, |
1141 | { "sub" , F3(2, 0x04, 1), F3(~2, ~0x04, ~1), "1,i,d" , 0, v6 }, |
1142 | |
1143 | { "subcc" , F3(2, 0x14, 0), F3(~2, ~0x14, ~0)|ASI(~0), "1,2,d" , 0, v6 }, |
1144 | { "subcc" , F3(2, 0x14, 1), F3(~2, ~0x14, ~1), "1,i,d" , 0, v6 }, |
1145 | |
1146 | { "subc" , F3(2, 0x0c, 0), F3(~2, ~0x0c, ~0)|ASI(~0), "1,2,d" , 0, v6 }, |
1147 | { "subc" , F3(2, 0x0c, 1), F3(~2, ~0x0c, ~1), "1,i,d" , 0, v6 }, |
1148 | |
1149 | { "subccc" , F3(2, 0x1c, 0), F3(~2, ~0x1c, ~0)|ASI(~0), "1,2,d" , 0, v6 }, |
1150 | { "subccc" , F3(2, 0x1c, 1), F3(~2, ~0x1c, ~1), "1,i,d" , 0, v6 }, |
1151 | |
1152 | { "and" , F3(2, 0x01, 0), F3(~2, ~0x01, ~0)|ASI(~0), "1,2,d" , 0, v6 }, |
1153 | { "and" , F3(2, 0x01, 1), F3(~2, ~0x01, ~1), "1,i,d" , 0, v6 }, |
1154 | { "and" , F3(2, 0x01, 1), F3(~2, ~0x01, ~1), "i,1,d" , 0, v6 }, |
1155 | |
1156 | { "andcc" , F3(2, 0x11, 0), F3(~2, ~0x11, ~0)|ASI(~0), "1,2,d" , 0, v6 }, |
1157 | { "andcc" , F3(2, 0x11, 1), F3(~2, ~0x11, ~1), "1,i,d" , 0, v6 }, |
1158 | { "andcc" , F3(2, 0x11, 1), F3(~2, ~0x11, ~1), "i,1,d" , 0, v6 }, |
1159 | |
1160 | { "dec" , F3(2, 0x04, 1)|SIMM13(0x1), F3(~2, ~0x04, ~1)|SIMM13(~0x0001), "r" , F_ALIAS, v6 }, /* sub rd,1,rd */ |
1161 | { "dec" , F3(2, 0x04, 1), F3(~2, ~0x04, ~1), "i,r" , F_ALIAS, v8 }, /* sub rd,imm,rd */ |
1162 | { "deccc" , F3(2, 0x14, 1)|SIMM13(0x1), F3(~2, ~0x14, ~1)|SIMM13(~0x0001), "r" , F_ALIAS, v6 }, /* subcc rd,1,rd */ |
1163 | { "deccc" , F3(2, 0x14, 1), F3(~2, ~0x14, ~1), "i,r" , F_ALIAS, v8 }, /* subcc rd,imm,rd */ |
1164 | { "inc" , F3(2, 0x00, 1)|SIMM13(0x1), F3(~2, ~0x00, ~1)|SIMM13(~0x0001), "r" , F_ALIAS, v6 }, /* add rd,1,rd */ |
1165 | { "inc" , F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "i,r" , F_ALIAS, v8 }, /* add rd,imm,rd */ |
1166 | { "inccc" , F3(2, 0x10, 1)|SIMM13(0x1), F3(~2, ~0x10, ~1)|SIMM13(~0x0001), "r" , F_ALIAS, v6 }, /* addcc rd,1,rd */ |
1167 | { "inccc" , F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "i,r" , F_ALIAS, v8 }, /* addcc rd,imm,rd */ |
1168 | |
1169 | { "btst" , F3(2, 0x11, 0), F3(~2, ~0x11, ~0)|RD_G0|ASI(~0), "1,2" , F_ALIAS, v6 }, /* andcc rs1,rs2,%g0 */ |
1170 | { "btst" , F3(2, 0x11, 1), F3(~2, ~0x11, ~1)|RD_G0, "i,1" , F_ALIAS, v6 }, /* andcc rs1,i,%g0 */ |
1171 | |
1172 | { "neg" , F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|RS1_G0|ASI(~0), "2,d" , F_ALIAS, v6 }, /* sub %g0,rs2,rd */ |
1173 | { "neg" , F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|RS1_G0|ASI(~0), "O" , F_ALIAS, v6 }, /* sub %g0,rd,rd */ |
1174 | |
1175 | { "add" , F3(2, 0x00, 0), F3(~2, ~0x00, ~0)|ASI(~0), "1,2,d" , 0, v6 }, |
1176 | { "add" , F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "1,i,d" , 0, v6 }, |
1177 | { "add" , F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "i,1,d" , 0, v6 }, |
1178 | { "addcc" , F3(2, 0x10, 0), F3(~2, ~0x10, ~0)|ASI(~0), "1,2,d" , 0, v6 }, |
1179 | { "addcc" , F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "1,i,d" , 0, v6 }, |
1180 | { "addcc" , F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "i,1,d" , 0, v6 }, |
1181 | |
1182 | { "addc" , F3(2, 0x08, 0), F3(~2, ~0x08, ~0)|ASI(~0), "1,2,d" , 0, v6 }, |
1183 | { "addc" , F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "1,i,d" , 0, v6 }, |
1184 | { "addc" , F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "i,1,d" , 0, v6 }, |
1185 | |
1186 | { "addccc" , F3(2, 0x18, 0), F3(~2, ~0x18, ~0)|ASI(~0), "1,2,d" , 0, v6 }, |
1187 | { "addccc" , F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "1,i,d" , 0, v6 }, |
1188 | { "addccc" , F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "i,1,d" , 0, v6 }, |
1189 | |
1190 | { "smul" , F3(2, 0x0b, 0), F3(~2, ~0x0b, ~0)|ASI(~0), "1,2,d" , 0, v8 }, |
1191 | { "smul" , F3(2, 0x0b, 1), F3(~2, ~0x0b, ~1), "1,i,d" , 0, v8 }, |
1192 | { "smul" , F3(2, 0x0b, 1), F3(~2, ~0x0b, ~1), "i,1,d" , 0, v8 }, |
1193 | { "smulcc" , F3(2, 0x1b, 0), F3(~2, ~0x1b, ~0)|ASI(~0), "1,2,d" , 0, v8 }, |
1194 | { "smulcc" , F3(2, 0x1b, 1), F3(~2, ~0x1b, ~1), "1,i,d" , 0, v8 }, |
1195 | { "smulcc" , F3(2, 0x1b, 1), F3(~2, ~0x1b, ~1), "i,1,d" , 0, v8 }, |
1196 | { "umul" , F3(2, 0x0a, 0), F3(~2, ~0x0a, ~0)|ASI(~0), "1,2,d" , 0, v8 }, |
1197 | { "umul" , F3(2, 0x0a, 1), F3(~2, ~0x0a, ~1), "1,i,d" , 0, v8 }, |
1198 | { "umul" , F3(2, 0x0a, 1), F3(~2, ~0x0a, ~1), "i,1,d" , 0, v8 }, |
1199 | { "umulcc" , F3(2, 0x1a, 0), F3(~2, ~0x1a, ~0)|ASI(~0), "1,2,d" , 0, v8 }, |
1200 | { "umulcc" , F3(2, 0x1a, 1), F3(~2, ~0x1a, ~1), "1,i,d" , 0, v8 }, |
1201 | { "umulcc" , F3(2, 0x1a, 1), F3(~2, ~0x1a, ~1), "i,1,d" , 0, v8 }, |
1202 | { "sdiv" , F3(2, 0x0f, 0), F3(~2, ~0x0f, ~0)|ASI(~0), "1,2,d" , 0, v8 }, |
1203 | { "sdiv" , F3(2, 0x0f, 1), F3(~2, ~0x0f, ~1), "1,i,d" , 0, v8 }, |
1204 | { "sdiv" , F3(2, 0x0f, 1), F3(~2, ~0x0f, ~1), "i,1,d" , 0, v8 }, |
1205 | { "sdivcc" , F3(2, 0x1f, 0), F3(~2, ~0x1f, ~0)|ASI(~0), "1,2,d" , 0, v8 }, |
1206 | { "sdivcc" , F3(2, 0x1f, 1), F3(~2, ~0x1f, ~1), "1,i,d" , 0, v8 }, |
1207 | { "sdivcc" , F3(2, 0x1f, 1), F3(~2, ~0x1f, ~1), "i,1,d" , 0, v8 }, |
1208 | { "udiv" , F3(2, 0x0e, 0), F3(~2, ~0x0e, ~0)|ASI(~0), "1,2,d" , 0, v8 }, |
1209 | { "udiv" , F3(2, 0x0e, 1), F3(~2, ~0x0e, ~1), "1,i,d" , 0, v8 }, |
1210 | { "udiv" , F3(2, 0x0e, 1), F3(~2, ~0x0e, ~1), "i,1,d" , 0, v8 }, |
1211 | { "udivcc" , F3(2, 0x1e, 0), F3(~2, ~0x1e, ~0)|ASI(~0), "1,2,d" , 0, v8 }, |
1212 | { "udivcc" , F3(2, 0x1e, 1), F3(~2, ~0x1e, ~1), "1,i,d" , 0, v8 }, |
1213 | { "udivcc" , F3(2, 0x1e, 1), F3(~2, ~0x1e, ~1), "i,1,d" , 0, v8 }, |
1214 | |
1215 | { "mulx" , F3(2, 0x09, 0), F3(~2, ~0x09, ~0)|ASI(~0), "1,2,d" , 0, v9 }, |
1216 | { "mulx" , F3(2, 0x09, 1), F3(~2, ~0x09, ~1), "1,i,d" , 0, v9 }, |
1217 | { "sdivx" , F3(2, 0x2d, 0), F3(~2, ~0x2d, ~0)|ASI(~0), "1,2,d" , 0, v9 }, |
1218 | { "sdivx" , F3(2, 0x2d, 1), F3(~2, ~0x2d, ~1), "1,i,d" , 0, v9 }, |
1219 | { "udivx" , F3(2, 0x0d, 0), F3(~2, ~0x0d, ~0)|ASI(~0), "1,2,d" , 0, v9 }, |
1220 | { "udivx" , F3(2, 0x0d, 1), F3(~2, ~0x0d, ~1), "1,i,d" , 0, v9 }, |
1221 | |
1222 | { "call" , F1(0x1), F1(~0x1), "L" , F_JSR|F_DELAYED, v6 }, |
1223 | { "call" , F1(0x1), F1(~0x1), "L,#" , F_JSR|F_DELAYED, v6 }, |
1224 | |
1225 | { "call" , F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI(~0), "1+2" , F_JSR|F_DELAYED, v6 }, /* jmpl rs1+rs2,%o7 */ |
1226 | { "call" , F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI(~0), "1+2,#" , F_JSR|F_DELAYED, v6 }, |
1227 | { "call" , F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI_RS2(~0), "1" , F_JSR|F_DELAYED, v6 }, /* jmpl rs1+%g0,%o7 */ |
1228 | { "call" , F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI_RS2(~0), "1,#" , F_JSR|F_DELAYED, v6 }, |
1229 | { "call" , F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "1+i" , F_JSR|F_DELAYED, v6 }, /* jmpl rs1+i,%o7 */ |
1230 | { "call" , F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "1+i,#" , F_JSR|F_DELAYED, v6 }, |
1231 | { "call" , F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "i+1" , F_JSR|F_DELAYED, v6 }, /* jmpl i+rs1,%o7 */ |
1232 | { "call" , F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "i+1,#" , F_JSR|F_DELAYED, v6 }, |
1233 | { "call" , F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|RS1_G0, "i" , F_JSR|F_DELAYED, v6 }, /* jmpl %g0+i,%o7 */ |
1234 | { "call" , F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|RS1_G0, "i,#" , F_JSR|F_DELAYED, v6 }, |
1235 | { "call" , F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|SIMM13(~0), "1" , F_JSR|F_DELAYED, v6 }, /* jmpl rs1+0,%o7 */ |
1236 | { "call" , F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|SIMM13(~0), "1,#" , F_JSR|F_DELAYED, v6 }, |
1237 | |
1238 | |
1239 | /* Conditional instructions. |
1240 | |
1241 | Because this part of the table was such a mess earlier, I have |
1242 | macrofied it so that all the branches and traps are generated from |
1243 | a single-line description of each condition value. John Gilmore. */ |
1244 | |
1245 | /* Define branches -- one annulled, one without, etc. */ |
1246 | #define br(opcode, mask, lose, flags) \ |
1247 | { opcode, (mask)|ANNUL, (lose), ",a l", (flags), v6 }, \ |
1248 | { opcode, (mask) , (lose)|ANNUL, "l", (flags), v6 } |
1249 | |
1250 | #define brx(opcode, mask, lose, flags) /* v9 */ \ |
1251 | { opcode, (mask)|(2<<20)|BPRED, ANNUL|(lose), "Z,G", (flags), v9 }, \ |
1252 | { opcode, (mask)|(2<<20)|BPRED, ANNUL|(lose), ",T Z,G", (flags), v9 }, \ |
1253 | { opcode, (mask)|(2<<20)|BPRED|ANNUL, (lose), ",a Z,G", (flags), v9 }, \ |
1254 | { opcode, (mask)|(2<<20)|BPRED|ANNUL, (lose), ",a,T Z,G", (flags), v9 }, \ |
1255 | { opcode, (mask)|(2<<20), ANNUL|BPRED|(lose), ",N Z,G", (flags), v9 }, \ |
1256 | { opcode, (mask)|(2<<20)|ANNUL, BPRED|(lose), ",a,N Z,G", (flags), v9 }, \ |
1257 | { opcode, (mask)|BPRED, ANNUL|(lose)|(2<<20), "z,G", (flags), v9 }, \ |
1258 | { opcode, (mask)|BPRED, ANNUL|(lose)|(2<<20), ",T z,G", (flags), v9 }, \ |
1259 | { opcode, (mask)|BPRED|ANNUL, (lose)|(2<<20), ",a z,G", (flags), v9 }, \ |
1260 | { opcode, (mask)|BPRED|ANNUL, (lose)|(2<<20), ",a,T z,G", (flags), v9 }, \ |
1261 | { opcode, (mask), ANNUL|BPRED|(lose)|(2<<20), ",N z,G", (flags), v9 }, \ |
1262 | { opcode, (mask)|ANNUL, BPRED|(lose)|(2<<20), ",a,N z,G", (flags), v9 } |
1263 | |
1264 | /* Define four traps: reg+reg, reg + immediate, immediate alone, reg alone. */ |
1265 | #define tr(opcode, mask, lose, flags) \ |
1266 | { opcode, (mask)|(2<<11)|IMMED, (lose)|RS1_G0, "Z,i", (flags), v9 }, /* %g0 + imm */ \ |
1267 | { opcode, (mask)|(2<<11)|IMMED, (lose), "Z,1+i", (flags), v9 }, /* rs1 + imm */ \ |
1268 | { opcode, (mask)|(2<<11), IMMED|(lose), "Z,1+2", (flags), v9 }, /* rs1 + rs2 */ \ |
1269 | { opcode, (mask)|(2<<11), IMMED|(lose)|RS2_G0, "Z,1", (flags), v9 }, /* rs1 + %g0 */ \ |
1270 | { opcode, (mask)|IMMED, (lose)|RS1_G0, "z,i", (flags)|F_ALIAS, v9 }, /* %g0 + imm */ \ |
1271 | { opcode, (mask)|IMMED, (lose), "z,1+i", (flags)|F_ALIAS, v9 }, /* rs1 + imm */ \ |
1272 | { opcode, (mask), IMMED|(lose), "z,1+2", (flags)|F_ALIAS, v9 }, /* rs1 + rs2 */ \ |
1273 | { opcode, (mask), IMMED|(lose)|RS2_G0, "z,1", (flags)|F_ALIAS, v9 }, /* rs1 + %g0 */ \ |
1274 | { opcode, (mask)|IMMED, (lose)|RS1_G0, "i", (flags), v6 }, /* %g0 + imm */ \ |
1275 | { opcode, (mask)|IMMED, (lose), "1+i", (flags), v6 }, /* rs1 + imm */ \ |
1276 | { opcode, (mask), IMMED|(lose), "1+2", (flags), v6 }, /* rs1 + rs2 */ \ |
1277 | { opcode, (mask), IMMED|(lose)|RS2_G0, "1", (flags), v6 } /* rs1 + %g0 */ |
1278 | |
1279 | /* v9: We must put `brx' before `br', to ensure that we never match something |
1280 | v9: against an expression unless it is an expression. Otherwise, we end |
1281 | v9: up with undefined symbol tables entries, because they get added, but |
1282 | v9: are not deleted if the pattern fails to match. */ |
1283 | |
1284 | /* Define both branches and traps based on condition mask */ |
1285 | #define cond(bop, top, mask, flags) \ |
1286 | brx(bop, F2(0, 1)|(mask), F2(~0, ~1)|((~mask)&COND(~0)), F_DELAYED|(flags)), /* v9 */ \ |
1287 | br(bop, F2(0, 2)|(mask), F2(~0, ~2)|((~mask)&COND(~0)), F_DELAYED|(flags)), \ |
1288 | tr(top, F3(2, 0x3a, 0)|(mask), F3(~2, ~0x3a, 0)|((~mask)&COND(~0)), ((flags) & ~(F_UNBR|F_CONDBR))) |
1289 | |
1290 | /* Define all the conditions, all the branches, all the traps. */ |
1291 | |
1292 | /* Standard branch, trap mnemonics */ |
1293 | cond ("b" , "ta" , CONDA, F_UNBR), |
1294 | /* Alternative form (just for assembly, not for disassembly) */ |
1295 | cond ("ba" , "t" , CONDA, F_UNBR|F_ALIAS), |
1296 | |
1297 | cond ("bcc" , "tcc" , CONDCC, F_CONDBR), |
1298 | cond ("bcs" , "tcs" , CONDCS, F_CONDBR), |
1299 | cond ("be" , "te" , CONDE, F_CONDBR), |
1300 | cond ("beq" , "teq" , CONDE, F_CONDBR|F_ALIAS), |
1301 | cond ("bg" , "tg" , CONDG, F_CONDBR), |
1302 | cond ("bgt" , "tgt" , CONDG, F_CONDBR|F_ALIAS), |
1303 | cond ("bge" , "tge" , CONDGE, F_CONDBR), |
1304 | cond ("bgeu" , "tgeu" , CONDGEU, F_CONDBR|F_ALIAS), /* for cc */ |
1305 | cond ("bgu" , "tgu" , CONDGU, F_CONDBR), |
1306 | cond ("bl" , "tl" , CONDL, F_CONDBR), |
1307 | cond ("blt" , "tlt" , CONDL, F_CONDBR|F_ALIAS), |
1308 | cond ("ble" , "tle" , CONDLE, F_CONDBR), |
1309 | cond ("bleu" , "tleu" , CONDLEU, F_CONDBR), |
1310 | cond ("blu" , "tlu" , CONDLU, F_CONDBR|F_ALIAS), /* for cs */ |
1311 | cond ("bn" , "tn" , CONDN, F_CONDBR), |
1312 | cond ("bne" , "tne" , CONDNE, F_CONDBR), |
1313 | cond ("bneg" , "tneg" , CONDNEG, F_CONDBR), |
1314 | cond ("bnz" , "tnz" , CONDNZ, F_CONDBR|F_ALIAS), /* for ne */ |
1315 | cond ("bpos" , "tpos" , CONDPOS, F_CONDBR), |
1316 | cond ("bvc" , "tvc" , CONDVC, F_CONDBR), |
1317 | cond ("bvs" , "tvs" , CONDVS, F_CONDBR), |
1318 | cond ("bz" , "tz" , CONDZ, F_CONDBR|F_ALIAS), /* for e */ |
1319 | |
1320 | #undef cond |
1321 | #undef br |
1322 | #undef brr /* v9 */ |
1323 | #undef tr |
1324 | |
1325 | #define brr(opcode, mask, lose, flags) /* v9 */ \ |
1326 | { opcode, (mask)|BPRED, ANNUL|(lose), "1,k", F_DELAYED|(flags), v9 }, \ |
1327 | { opcode, (mask)|BPRED, ANNUL|(lose), ",T 1,k", F_DELAYED|(flags), v9 }, \ |
1328 | { opcode, (mask)|BPRED|ANNUL, (lose), ",a 1,k", F_DELAYED|(flags), v9 }, \ |
1329 | { opcode, (mask)|BPRED|ANNUL, (lose), ",a,T 1,k", F_DELAYED|(flags), v9 }, \ |
1330 | { opcode, (mask), ANNUL|BPRED|(lose), ",N 1,k", F_DELAYED|(flags), v9 }, \ |
1331 | { opcode, (mask)|ANNUL, BPRED|(lose), ",a,N 1,k", F_DELAYED|(flags), v9 } |
1332 | |
1333 | #define condr(bop, mask, flags) /* v9 */ \ |
1334 | brr(bop, F2(0, 3)|COND(mask), F2(~0, ~3)|COND(~(mask)), (flags)) /* v9 */ |
1335 | |
1336 | /* v9 */ condr("brnz" , 0x5, F_CONDBR), |
1337 | /* v9 */ condr("brz" , 0x1, F_CONDBR), |
1338 | /* v9 */ condr("brgez" , 0x7, F_CONDBR), |
1339 | /* v9 */ condr("brlz" , 0x3, F_CONDBR), |
1340 | /* v9 */ condr("brlez" , 0x2, F_CONDBR), |
1341 | /* v9 */ condr("brgz" , 0x6, F_CONDBR), |
1342 | |
1343 | #undef condr /* v9 */ |
1344 | #undef brr /* v9 */ |
1345 | |
1346 | #define movr(opcode, mask, flags) /* v9 */ \ |
1347 | { opcode, F3(2, 0x2f, 0)|RCOND(mask), F3(~2, ~0x2f, ~0)|RCOND(~(mask)), "1,2,d", (flags), v9 }, \ |
1348 | { opcode, F3(2, 0x2f, 1)|RCOND(mask), F3(~2, ~0x2f, ~1)|RCOND(~(mask)), "1,j,d", (flags), v9 } |
1349 | |
1350 | #define fmrrs(opcode, mask, lose, flags) /* v9 */ \ |
1351 | { opcode, (mask), (lose), "1,f,g", (flags) | F_FLOAT, v9 } |
1352 | #define fmrrd(opcode, mask, lose, flags) /* v9 */ \ |
1353 | { opcode, (mask), (lose), "1,B,H", (flags) | F_FLOAT, v9 } |
1354 | #define fmrrq(opcode, mask, lose, flags) /* v9 */ \ |
1355 | { opcode, (mask), (lose), "1,R,J", (flags) | F_FLOAT, v9 } |
1356 | |
1357 | #define fmovrs(mop, mask, flags) /* v9 */ \ |
1358 | fmrrs(mop, F3(2, 0x35, 0)|OPF_LOW5(5)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~5)|RCOND(~(mask)), (flags)) /* v9 */ |
1359 | #define fmovrd(mop, mask, flags) /* v9 */ \ |
1360 | fmrrd(mop, F3(2, 0x35, 0)|OPF_LOW5(6)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~6)|RCOND(~(mask)), (flags)) /* v9 */ |
1361 | #define fmovrq(mop, mask, flags) /* v9 */ \ |
1362 | fmrrq(mop, F3(2, 0x35, 0)|OPF_LOW5(7)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~7)|RCOND(~(mask)), (flags)) /* v9 */ |
1363 | |
1364 | /* v9 */ movr("movrne" , 0x5, 0), |
1365 | /* v9 */ movr("movre" , 0x1, 0), |
1366 | /* v9 */ movr("movrgez" , 0x7, 0), |
1367 | /* v9 */ movr("movrlz" , 0x3, 0), |
1368 | /* v9 */ movr("movrlez" , 0x2, 0), |
1369 | /* v9 */ movr("movrgz" , 0x6, 0), |
1370 | /* v9 */ movr("movrnz" , 0x5, F_ALIAS), |
1371 | /* v9 */ movr("movrz" , 0x1, F_ALIAS), |
1372 | |
1373 | /* v9 */ fmovrs("fmovrsne" , 0x5, 0), |
1374 | /* v9 */ fmovrs("fmovrse" , 0x1, 0), |
1375 | /* v9 */ fmovrs("fmovrsgez" , 0x7, 0), |
1376 | /* v9 */ fmovrs("fmovrslz" , 0x3, 0), |
1377 | /* v9 */ fmovrs("fmovrslez" , 0x2, 0), |
1378 | /* v9 */ fmovrs("fmovrsgz" , 0x6, 0), |
1379 | /* v9 */ fmovrs("fmovrsnz" , 0x5, F_ALIAS), |
1380 | /* v9 */ fmovrs("fmovrsz" , 0x1, F_ALIAS), |
1381 | |
1382 | /* v9 */ fmovrd("fmovrdne" , 0x5, 0), |
1383 | /* v9 */ fmovrd("fmovrde" , 0x1, 0), |
1384 | /* v9 */ fmovrd("fmovrdgez" , 0x7, 0), |
1385 | /* v9 */ fmovrd("fmovrdlz" , 0x3, 0), |
1386 | /* v9 */ fmovrd("fmovrdlez" , 0x2, 0), |
1387 | /* v9 */ fmovrd("fmovrdgz" , 0x6, 0), |
1388 | /* v9 */ fmovrd("fmovrdnz" , 0x5, F_ALIAS), |
1389 | /* v9 */ fmovrd("fmovrdz" , 0x1, F_ALIAS), |
1390 | |
1391 | /* v9 */ fmovrq("fmovrqne" , 0x5, 0), |
1392 | /* v9 */ fmovrq("fmovrqe" , 0x1, 0), |
1393 | /* v9 */ fmovrq("fmovrqgez" , 0x7, 0), |
1394 | /* v9 */ fmovrq("fmovrqlz" , 0x3, 0), |
1395 | /* v9 */ fmovrq("fmovrqlez" , 0x2, 0), |
1396 | /* v9 */ fmovrq("fmovrqgz" , 0x6, 0), |
1397 | /* v9 */ fmovrq("fmovrqnz" , 0x5, F_ALIAS), |
1398 | /* v9 */ fmovrq("fmovrqz" , 0x1, F_ALIAS), |
1399 | |
1400 | #undef movr /* v9 */ |
1401 | #undef fmovr /* v9 */ |
1402 | #undef fmrr /* v9 */ |
1403 | |
1404 | #define movicc(opcode, cond, flags) /* v9 */ \ |
1405 | { opcode, F3(2, 0x2c, 0)|MCOND(cond,1)|ICC, F3(~2, ~0x2c, ~0)|MCOND(~cond,~1)|XCC|(1<<11), "z,2,d", flags, v9 }, \ |
1406 | { opcode, F3(2, 0x2c, 1)|MCOND(cond,1)|ICC, F3(~2, ~0x2c, ~1)|MCOND(~cond,~1)|XCC|(1<<11), "z,I,d", flags, v9 }, \ |
1407 | { opcode, F3(2, 0x2c, 0)|MCOND(cond,1)|XCC, F3(~2, ~0x2c, ~0)|MCOND(~cond,~1)|(1<<11), "Z,2,d", flags, v9 }, \ |
1408 | { opcode, F3(2, 0x2c, 1)|MCOND(cond,1)|XCC, F3(~2, ~0x2c, ~1)|MCOND(~cond,~1)|(1<<11), "Z,I,d", flags, v9 } |
1409 | |
1410 | #define movfcc(opcode, fcond, flags) /* v9 */ \ |
1411 | { opcode, F3(2, 0x2c, 0)|FCC(0)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~0)|F3(~2, ~0x2c, ~0), "6,2,d", flags, v9 }, \ |
1412 | { opcode, F3(2, 0x2c, 1)|FCC(0)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~0)|F3(~2, ~0x2c, ~1), "6,I,d", flags, v9 }, \ |
1413 | { opcode, F3(2, 0x2c, 0)|FCC(1)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~1)|F3(~2, ~0x2c, ~0), "7,2,d", flags, v9 }, \ |
1414 | { opcode, F3(2, 0x2c, 1)|FCC(1)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~1)|F3(~2, ~0x2c, ~1), "7,I,d", flags, v9 }, \ |
1415 | { opcode, F3(2, 0x2c, 0)|FCC(2)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~2)|F3(~2, ~0x2c, ~0), "8,2,d", flags, v9 }, \ |
1416 | { opcode, F3(2, 0x2c, 1)|FCC(2)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~2)|F3(~2, ~0x2c, ~1), "8,I,d", flags, v9 }, \ |
1417 | { opcode, F3(2, 0x2c, 0)|FCC(3)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~3)|F3(~2, ~0x2c, ~0), "9,2,d", flags, v9 }, \ |
1418 | { opcode, F3(2, 0x2c, 1)|FCC(3)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~3)|F3(~2, ~0x2c, ~1), "9,I,d", flags, v9 } |
1419 | |
1420 | #define movcc(opcode, cond, fcond, flags) /* v9 */ \ |
1421 | movfcc (opcode, fcond, flags), /* v9 */ \ |
1422 | movicc (opcode, cond, flags) /* v9 */ |
1423 | |
1424 | /* v9 */ movcc ("mova" , CONDA, FCONDA, 0), |
1425 | /* v9 */ movicc ("movcc" , CONDCC, 0), |
1426 | /* v9 */ movicc ("movgeu" , CONDGEU, F_ALIAS), |
1427 | /* v9 */ movicc ("movcs" , CONDCS, 0), |
1428 | /* v9 */ movicc ("movlu" , CONDLU, F_ALIAS), |
1429 | /* v9 */ movcc ("move" , CONDE, FCONDE, 0), |
1430 | /* v9 */ movcc ("movg" , CONDG, FCONDG, 0), |
1431 | /* v9 */ movcc ("movge" , CONDGE, FCONDGE, 0), |
1432 | /* v9 */ movicc ("movgu" , CONDGU, 0), |
1433 | /* v9 */ movcc ("movl" , CONDL, FCONDL, 0), |
1434 | /* v9 */ movcc ("movle" , CONDLE, FCONDLE, 0), |
1435 | /* v9 */ movicc ("movleu" , CONDLEU, 0), |
1436 | /* v9 */ movfcc ("movlg" , FCONDLG, 0), |
1437 | /* v9 */ movcc ("movn" , CONDN, FCONDN, 0), |
1438 | /* v9 */ movcc ("movne" , CONDNE, FCONDNE, 0), |
1439 | /* v9 */ movicc ("movneg" , CONDNEG, 0), |
1440 | /* v9 */ movcc ("movnz" , CONDNZ, FCONDNZ, F_ALIAS), |
1441 | /* v9 */ movfcc ("movo" , FCONDO, 0), |
1442 | /* v9 */ movicc ("movpos" , CONDPOS, 0), |
1443 | /* v9 */ movfcc ("movu" , FCONDU, 0), |
1444 | /* v9 */ movfcc ("movue" , FCONDUE, 0), |
1445 | /* v9 */ movfcc ("movug" , FCONDUG, 0), |
1446 | /* v9 */ movfcc ("movuge" , FCONDUGE, 0), |
1447 | /* v9 */ movfcc ("movul" , FCONDUL, 0), |
1448 | /* v9 */ movfcc ("movule" , FCONDULE, 0), |
1449 | /* v9 */ movicc ("movvc" , CONDVC, 0), |
1450 | /* v9 */ movicc ("movvs" , CONDVS, 0), |
1451 | /* v9 */ movcc ("movz" , CONDZ, FCONDZ, F_ALIAS), |
1452 | |
1453 | #undef movicc /* v9 */ |
1454 | #undef movfcc /* v9 */ |
1455 | #undef movcc /* v9 */ |
1456 | |
1457 | #define FM_SF 1 /* v9 - values for fpsize */ |
1458 | #define FM_DF 2 /* v9 */ |
1459 | #define FM_QF 3 /* v9 */ |
1460 | |
1461 | #define fmoviccx(opcode, fpsize, args, cond, flags) /* v9 */ \ |
1462 | { opcode, F3F(2, 0x35, 0x100+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x100+fpsize))|MCOND(~cond,~0), "z," args, flags, v9 }, \ |
1463 | { opcode, F3F(2, 0x35, 0x180+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x180+fpsize))|MCOND(~cond,~0), "Z," args, flags, v9 } |
1464 | |
1465 | #define fmovfccx(opcode, fpsize, args, fcond, flags) /* v9 */ \ |
1466 | { opcode, F3F(2, 0x35, 0x000+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x000+fpsize))|MCOND(~fcond,~0), "6," args, flags, v9 }, \ |
1467 | { opcode, F3F(2, 0x35, 0x040+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x040+fpsize))|MCOND(~fcond,~0), "7," args, flags, v9 }, \ |
1468 | { opcode, F3F(2, 0x35, 0x080+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x080+fpsize))|MCOND(~fcond,~0), "8," args, flags, v9 }, \ |
1469 | { opcode, F3F(2, 0x35, 0x0c0+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x0c0+fpsize))|MCOND(~fcond,~0), "9," args, flags, v9 } |
1470 | |
1471 | /* FIXME: use fmovicc/fmovfcc? */ /* v9 */ |
1472 | #define fmovccx(opcode, fpsize, args, cond, fcond, flags) /* v9 */ \ |
1473 | { opcode, F3F(2, 0x35, 0x100+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x100+fpsize))|MCOND(~cond,~0), "z," args, flags | F_FLOAT, v9 }, \ |
1474 | { opcode, F3F(2, 0x35, 0x000+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x000+fpsize))|MCOND(~fcond,~0), "6," args, flags | F_FLOAT, v9 }, \ |
1475 | { opcode, F3F(2, 0x35, 0x180+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x180+fpsize))|MCOND(~cond,~0), "Z," args, flags | F_FLOAT, v9 }, \ |
1476 | { opcode, F3F(2, 0x35, 0x040+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x040+fpsize))|MCOND(~fcond,~0), "7," args, flags | F_FLOAT, v9 }, \ |
1477 | { opcode, F3F(2, 0x35, 0x080+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x080+fpsize))|MCOND(~fcond,~0), "8," args, flags | F_FLOAT, v9 }, \ |
1478 | { opcode, F3F(2, 0x35, 0x0c0+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x0c0+fpsize))|MCOND(~fcond,~0), "9," args, flags | F_FLOAT, v9 } |
1479 | |
1480 | #define fmovicc(suffix, cond, flags) /* v9 */ \ |
1481 | fmoviccx("fmovd" suffix, FM_DF, "B,H", cond, flags), \ |
1482 | fmoviccx("fmovq" suffix, FM_QF, "R,J", cond, flags), \ |
1483 | fmoviccx("fmovs" suffix, FM_SF, "f,g", cond, flags) |
1484 | |
1485 | #define fmovfcc(suffix, fcond, flags) /* v9 */ \ |
1486 | fmovfccx("fmovd" suffix, FM_DF, "B,H", fcond, flags), \ |
1487 | fmovfccx("fmovq" suffix, FM_QF, "R,J", fcond, flags), \ |
1488 | fmovfccx("fmovs" suffix, FM_SF, "f,g", fcond, flags) |
1489 | |
1490 | #define fmovcc(suffix, cond, fcond, flags) /* v9 */ \ |
1491 | fmovccx("fmovd" suffix, FM_DF, "B,H", cond, fcond, flags), \ |
1492 | fmovccx("fmovq" suffix, FM_QF, "R,J", cond, fcond, flags), \ |
1493 | fmovccx("fmovs" suffix, FM_SF, "f,g", cond, fcond, flags) |
1494 | |
1495 | /* v9 */ fmovcc ("a" , CONDA, FCONDA, 0), |
1496 | /* v9 */ fmovicc ("cc" , CONDCC, 0), |
1497 | /* v9 */ fmovicc ("cs" , CONDCS, 0), |
1498 | /* v9 */ fmovcc ("e" , CONDE, FCONDE, 0), |
1499 | /* v9 */ fmovcc ("g" , CONDG, FCONDG, 0), |
1500 | /* v9 */ fmovcc ("ge" , CONDGE, FCONDGE, 0), |
1501 | /* v9 */ fmovicc ("geu" , CONDGEU, F_ALIAS), |
1502 | /* v9 */ fmovicc ("gu" , CONDGU, 0), |
1503 | /* v9 */ fmovcc ("l" , CONDL, FCONDL, 0), |
1504 | /* v9 */ fmovcc ("le" , CONDLE, FCONDLE, 0), |
1505 | /* v9 */ fmovicc ("leu" , CONDLEU, 0), |
1506 | /* v9 */ fmovfcc ("lg" , FCONDLG, 0), |
1507 | /* v9 */ fmovicc ("lu" , CONDLU, F_ALIAS), |
1508 | /* v9 */ fmovcc ("n" , CONDN, FCONDN, 0), |
1509 | /* v9 */ fmovcc ("ne" , CONDNE, FCONDNE, 0), |
1510 | /* v9 */ fmovicc ("neg" , CONDNEG, 0), |
1511 | /* v9 */ fmovcc ("nz" , CONDNZ, FCONDNZ, F_ALIAS), |
1512 | /* v9 */ fmovfcc ("o" , FCONDO, 0), |
1513 | /* v9 */ fmovicc ("pos" , CONDPOS, 0), |
1514 | /* v9 */ fmovfcc ("u" , FCONDU, 0), |
1515 | /* v9 */ fmovfcc ("ue" , FCONDUE, 0), |
1516 | /* v9 */ fmovfcc ("ug" , FCONDUG, 0), |
1517 | /* v9 */ fmovfcc ("uge" , FCONDUGE, 0), |
1518 | /* v9 */ fmovfcc ("ul" , FCONDUL, 0), |
1519 | /* v9 */ fmovfcc ("ule" , FCONDULE, 0), |
1520 | /* v9 */ fmovicc ("vc" , CONDVC, 0), |
1521 | /* v9 */ fmovicc ("vs" , CONDVS, 0), |
1522 | /* v9 */ fmovcc ("z" , CONDZ, FCONDZ, F_ALIAS), |
1523 | |
1524 | #undef fmoviccx /* v9 */ |
1525 | #undef fmovfccx /* v9 */ |
1526 | #undef fmovccx /* v9 */ |
1527 | #undef fmovicc /* v9 */ |
1528 | #undef fmovfcc /* v9 */ |
1529 | #undef fmovcc /* v9 */ |
1530 | #undef FM_DF /* v9 */ |
1531 | #undef FM_QF /* v9 */ |
1532 | #undef FM_SF /* v9 */ |
1533 | |
1534 | /* Coprocessor branches. */ |
1535 | #define CBR(opcode, mask, lose, flags, arch) \ |
1536 | { opcode, (mask), ANNUL | (lose), "l", flags | F_DELAYED, arch }, \ |
1537 | { opcode, (mask) | ANNUL, (lose), ",a l", flags | F_DELAYED, arch } |
1538 | |
1539 | /* Floating point branches. */ |
1540 | #define FBR(opcode, mask, lose, flags) \ |
1541 | { opcode, (mask), ANNUL | (lose), "l", flags | F_DELAYED | F_FBR, v6 }, \ |
1542 | { opcode, (mask) | ANNUL, (lose), ",a l", flags | F_DELAYED | F_FBR, v6 } |
1543 | |
1544 | /* V9 extended floating point branches. */ |
1545 | #define FBRX(opcode, mask, lose, flags) /* v9 */ \ |
1546 | { opcode, FBFCC(0)|(mask)|BPRED, ANNUL|FBFCC(~0)|(lose), "6,G", flags|F_DELAYED|F_FBR, v9 }, \ |
1547 | { opcode, FBFCC(0)|(mask)|BPRED, ANNUL|FBFCC(~0)|(lose), ",T 6,G", flags|F_DELAYED|F_FBR, v9 }, \ |
1548 | { opcode, FBFCC(0)|(mask)|BPRED|ANNUL, FBFCC(~0)|(lose), ",a 6,G", flags|F_DELAYED|F_FBR, v9 }, \ |
1549 | { opcode, FBFCC(0)|(mask)|BPRED|ANNUL, FBFCC(~0)|(lose), ",a,T 6,G", flags|F_DELAYED|F_FBR, v9 }, \ |
1550 | { opcode, FBFCC(0)|(mask), ANNUL|BPRED|FBFCC(~0)|(lose), ",N 6,G", flags|F_DELAYED|F_FBR, v9 }, \ |
1551 | { opcode, FBFCC(0)|(mask)|ANNUL, BPRED|FBFCC(~0)|(lose), ",a,N 6,G", flags|F_DELAYED|F_FBR, v9 }, \ |
1552 | { opcode, FBFCC(1)|(mask)|BPRED, ANNUL|FBFCC(~1)|(lose), "7,G", flags|F_DELAYED|F_FBR, v9 }, \ |
1553 | { opcode, FBFCC(1)|(mask)|BPRED, ANNUL|FBFCC(~1)|(lose), ",T 7,G", flags|F_DELAYED|F_FBR, v9 }, \ |
1554 | { opcode, FBFCC(1)|(mask)|BPRED|ANNUL, FBFCC(~1)|(lose), ",a 7,G", flags|F_DELAYED|F_FBR, v9 }, \ |
1555 | { opcode, FBFCC(1)|(mask)|BPRED|ANNUL, FBFCC(~1)|(lose), ",a,T 7,G", flags|F_DELAYED|F_FBR, v9 }, \ |
1556 | { opcode, FBFCC(1)|(mask), ANNUL|BPRED|FBFCC(~1)|(lose), ",N 7,G", flags|F_DELAYED|F_FBR, v9 }, \ |
1557 | { opcode, FBFCC(1)|(mask)|ANNUL, BPRED|FBFCC(~1)|(lose), ",a,N 7,G", flags|F_DELAYED|F_FBR, v9 }, \ |
1558 | { opcode, FBFCC(2)|(mask)|BPRED, ANNUL|FBFCC(~2)|(lose), "8,G", flags|F_DELAYED|F_FBR, v9 }, \ |
1559 | { opcode, FBFCC(2)|(mask)|BPRED, ANNUL|FBFCC(~2)|(lose), ",T 8,G", flags|F_DELAYED|F_FBR, v9 }, \ |
1560 | { opcode, FBFCC(2)|(mask)|BPRED|ANNUL, FBFCC(~2)|(lose), ",a 8,G", flags|F_DELAYED|F_FBR, v9 }, \ |
1561 | { opcode, FBFCC(2)|(mask)|BPRED|ANNUL, FBFCC(~2)|(lose), ",a,T 8,G", flags|F_DELAYED|F_FBR, v9 }, \ |
1562 | { opcode, FBFCC(2)|(mask), ANNUL|BPRED|FBFCC(~2)|(lose), ",N 8,G", flags|F_DELAYED|F_FBR, v9 }, \ |
1563 | { opcode, FBFCC(2)|(mask)|ANNUL, BPRED|FBFCC(~2)|(lose), ",a,N 8,G", flags|F_DELAYED|F_FBR, v9 }, \ |
1564 | { opcode, FBFCC(3)|(mask)|BPRED, ANNUL|FBFCC(~3)|(lose), "9,G", flags|F_DELAYED|F_FBR, v9 }, \ |
1565 | { opcode, FBFCC(3)|(mask)|BPRED, ANNUL|FBFCC(~3)|(lose), ",T 9,G", flags|F_DELAYED|F_FBR, v9 }, \ |
1566 | { opcode, FBFCC(3)|(mask)|BPRED|ANNUL, FBFCC(~3)|(lose), ",a 9,G", flags|F_DELAYED|F_FBR, v9 }, \ |
1567 | { opcode, FBFCC(3)|(mask)|BPRED|ANNUL, FBFCC(~3)|(lose), ",a,T 9,G", flags|F_DELAYED|F_FBR, v9 }, \ |
1568 | { opcode, FBFCC(3)|(mask), ANNUL|BPRED|FBFCC(~3)|(lose), ",N 9,G", flags|F_DELAYED|F_FBR, v9 }, \ |
1569 | { opcode, FBFCC(3)|(mask)|ANNUL, BPRED|FBFCC(~3)|(lose), ",a,N 9,G", flags|F_DELAYED|F_FBR, v9 } |
1570 | |
1571 | /* v9: We must put `FBRX' before `FBR', to ensure that we never match |
1572 | v9: something against an expression unless it is an expression. Otherwise, |
1573 | v9: we end up with undefined symbol tables entries, because they get added, |
1574 | v9: but are not deleted if the pattern fails to match. */ |
1575 | |
1576 | #define CONDFC(fop, cop, mask, flags) \ |
1577 | FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \ |
1578 | FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags), \ |
1579 | CBR(cop, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)), flags, v6notlet) |
1580 | |
1581 | #define CONDFCL(fop, cop, mask, flags) \ |
1582 | FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \ |
1583 | FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags), \ |
1584 | CBR(cop, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)), flags, v6) |
1585 | |
1586 | #define CONDF(fop, mask, flags) \ |
1587 | FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \ |
1588 | FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags) |
1589 | |
1590 | CONDFC ("fb" , "cb" , 0x8, F_UNBR), |
1591 | CONDFCL ("fba" , "cba" , 0x8, F_UNBR|F_ALIAS), |
1592 | CONDFC ("fbe" , "cb0" , 0x9, F_CONDBR), |
1593 | CONDF ("fbz" , 0x9, F_CONDBR|F_ALIAS), |
1594 | CONDFC ("fbg" , "cb2" , 0x6, F_CONDBR), |
1595 | CONDFC ("fbge" , "cb02" , 0xb, F_CONDBR), |
1596 | CONDFC ("fbl" , "cb1" , 0x4, F_CONDBR), |
1597 | CONDFC ("fble" , "cb01" , 0xd, F_CONDBR), |
1598 | CONDFC ("fblg" , "cb12" , 0x2, F_CONDBR), |
1599 | CONDFCL ("fbn" , "cbn" , 0x0, F_UNBR), |
1600 | CONDFC ("fbne" , "cb123" , 0x1, F_CONDBR), |
1601 | CONDF ("fbnz" , 0x1, F_CONDBR|F_ALIAS), |
1602 | CONDFC ("fbo" , "cb012" , 0xf, F_CONDBR), |
1603 | CONDFC ("fbu" , "cb3" , 0x7, F_CONDBR), |
1604 | CONDFC ("fbue" , "cb03" , 0xa, F_CONDBR), |
1605 | CONDFC ("fbug" , "cb23" , 0x5, F_CONDBR), |
1606 | CONDFC ("fbuge" , "cb023" , 0xc, F_CONDBR), |
1607 | CONDFC ("fbul" , "cb13" , 0x3, F_CONDBR), |
1608 | CONDFC ("fbule" , "cb013" , 0xe, F_CONDBR), |
1609 | |
1610 | #undef CONDFC |
1611 | #undef CONDFCL |
1612 | #undef CONDF |
1613 | #undef CBR |
1614 | #undef FBR |
1615 | #undef FBRX /* v9 */ |
1616 | |
1617 | { "jmp" , F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0|ASI(~0), "1+2" , F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+rs2,%g0 */ |
1618 | { "jmp" , F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0|ASI_RS2(~0), "1" , F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+%g0,%g0 */ |
1619 | { "jmp" , F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0, "1+i" , F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+i,%g0 */ |
1620 | { "jmp" , F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0, "i+1" , F_UNBR|F_DELAYED, v6 }, /* jmpl i+rs1,%g0 */ |
1621 | { "jmp" , F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0|RS1_G0, "i" , F_UNBR|F_DELAYED, v6 }, /* jmpl %g0+i,%g0 */ |
1622 | { "jmp" , F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0|SIMM13(~0), "1" , F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+0,%g0 */ |
1623 | |
1624 | { "nop" , F2(0, 4), 0xfeffffff, "" , 0, v6 }, /* sethi 0, %g0 */ |
1625 | |
1626 | { "set" , F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d" , F_ALIAS, v6 }, |
1627 | { "setuw" , F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d" , F_ALIAS, v9 }, |
1628 | { "setsw" , F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d" , F_ALIAS, v9 }, |
1629 | { "setx" , F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,1,d" , F_ALIAS, v9 }, |
1630 | |
1631 | { "sethi" , F2(0x0, 0x4), F2(~0x0, ~0x4), "h,d" , 0, v6 }, |
1632 | |
1633 | { "taddcc" , F3(2, 0x20, 0), F3(~2, ~0x20, ~0)|ASI(~0), "1,2,d" , 0, v6 }, |
1634 | { "taddcc" , F3(2, 0x20, 1), F3(~2, ~0x20, ~1), "1,i,d" , 0, v6 }, |
1635 | { "taddcc" , F3(2, 0x20, 1), F3(~2, ~0x20, ~1), "i,1,d" , 0, v6 }, |
1636 | { "taddcctv" , F3(2, 0x22, 0), F3(~2, ~0x22, ~0)|ASI(~0), "1,2,d" , 0, v6 }, |
1637 | { "taddcctv" , F3(2, 0x22, 1), F3(~2, ~0x22, ~1), "1,i,d" , 0, v6 }, |
1638 | { "taddcctv" , F3(2, 0x22, 1), F3(~2, ~0x22, ~1), "i,1,d" , 0, v6 }, |
1639 | |
1640 | { "tsubcc" , F3(2, 0x21, 0), F3(~2, ~0x21, ~0)|ASI(~0), "1,2,d" , 0, v6 }, |
1641 | { "tsubcc" , F3(2, 0x21, 1), F3(~2, ~0x21, ~1), "1,i,d" , 0, v6 }, |
1642 | { "tsubcctv" , F3(2, 0x23, 0), F3(~2, ~0x23, ~0)|ASI(~0), "1,2,d" , 0, v6 }, |
1643 | { "tsubcctv" , F3(2, 0x23, 1), F3(~2, ~0x23, ~1), "1,i,d" , 0, v6 }, |
1644 | |
1645 | { "unimp" , F2(0x0, 0x0), 0xffc00000, "n" , 0, v6notv9 }, |
1646 | { "illtrap" , F2(0, 0), F2(~0, ~0)|RD_G0, "n" , 0, v9 }, |
1647 | |
1648 | /* This *is* a commutative instruction. */ |
1649 | { "xnor" , F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "1,2,d" , 0, v6 }, |
1650 | { "xnor" , F3(2, 0x07, 1), F3(~2, ~0x07, ~1), "1,i,d" , 0, v6 }, |
1651 | { "xnor" , F3(2, 0x07, 1), F3(~2, ~0x07, ~1), "i,1,d" , 0, v6 }, |
1652 | /* This *is* a commutative instruction. */ |
1653 | { "xnorcc" , F3(2, 0x17, 0), F3(~2, ~0x17, ~0)|ASI(~0), "1,2,d" , 0, v6 }, |
1654 | { "xnorcc" , F3(2, 0x17, 1), F3(~2, ~0x17, ~1), "1,i,d" , 0, v6 }, |
1655 | { "xnorcc" , F3(2, 0x17, 1), F3(~2, ~0x17, ~1), "i,1,d" , 0, v6 }, |
1656 | { "xor" , F3(2, 0x03, 0), F3(~2, ~0x03, ~0)|ASI(~0), "1,2,d" , 0, v6 }, |
1657 | { "xor" , F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "1,i,d" , 0, v6 }, |
1658 | { "xor" , F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "i,1,d" , 0, v6 }, |
1659 | { "xorcc" , F3(2, 0x13, 0), F3(~2, ~0x13, ~0)|ASI(~0), "1,2,d" , 0, v6 }, |
1660 | { "xorcc" , F3(2, 0x13, 1), F3(~2, ~0x13, ~1), "1,i,d" , 0, v6 }, |
1661 | { "xorcc" , F3(2, 0x13, 1), F3(~2, ~0x13, ~1), "i,1,d" , 0, v6 }, |
1662 | |
1663 | { "not" , F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "1,d" , F_ALIAS, v6 }, /* xnor rs1,%0,rd */ |
1664 | { "not" , F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "r" , F_ALIAS, v6 }, /* xnor rd,%0,rd */ |
1665 | |
1666 | { "btog" , F3(2, 0x03, 0), F3(~2, ~0x03, ~0)|ASI(~0), "2,r" , F_ALIAS, v6 }, /* xor rd,rs2,rd */ |
1667 | { "btog" , F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "i,r" , F_ALIAS, v6 }, /* xor rd,i,rd */ |
1668 | |
1669 | /* FPop1 and FPop2 are not instructions. Don't accept them. */ |
1670 | |
1671 | { "fdtoi" , F3F(2, 0x34, 0x0d2), F3F(~2, ~0x34, ~0x0d2)|RS1_G0, "B,g" , F_FLOAT, v6 }, |
1672 | { "fstoi" , F3F(2, 0x34, 0x0d1), F3F(~2, ~0x34, ~0x0d1)|RS1_G0, "f,g" , F_FLOAT, v6 }, |
1673 | { "fqtoi" , F3F(2, 0x34, 0x0d3), F3F(~2, ~0x34, ~0x0d3)|RS1_G0, "R,g" , F_FLOAT, v8 }, |
1674 | |
1675 | { "fdtox" , F3F(2, 0x34, 0x082), F3F(~2, ~0x34, ~0x082)|RS1_G0, "B,H" , F_FLOAT, v9 }, |
1676 | { "fstox" , F3F(2, 0x34, 0x081), F3F(~2, ~0x34, ~0x081)|RS1_G0, "f,H" , F_FLOAT, v9 }, |
1677 | { "fqtox" , F3F(2, 0x34, 0x083), F3F(~2, ~0x34, ~0x083)|RS1_G0, "R,H" , F_FLOAT, v9 }, |
1678 | |
1679 | { "fitod" , F3F(2, 0x34, 0x0c8), F3F(~2, ~0x34, ~0x0c8)|RS1_G0, "f,H" , F_FLOAT, v6 }, |
1680 | { "fitos" , F3F(2, 0x34, 0x0c4), F3F(~2, ~0x34, ~0x0c4)|RS1_G0, "f,g" , F_FLOAT, v6 }, |
1681 | { "fitoq" , F3F(2, 0x34, 0x0cc), F3F(~2, ~0x34, ~0x0cc)|RS1_G0, "f,J" , F_FLOAT, v8 }, |
1682 | |
1683 | { "fxtod" , F3F(2, 0x34, 0x088), F3F(~2, ~0x34, ~0x088)|RS1_G0, "B,H" , F_FLOAT, v9 }, |
1684 | { "fxtos" , F3F(2, 0x34, 0x084), F3F(~2, ~0x34, ~0x084)|RS1_G0, "B,g" , F_FLOAT, v9 }, |
1685 | { "fxtoq" , F3F(2, 0x34, 0x08c), F3F(~2, ~0x34, ~0x08c)|RS1_G0, "B,J" , F_FLOAT, v9 }, |
1686 | |
1687 | { "fdtoq" , F3F(2, 0x34, 0x0ce), F3F(~2, ~0x34, ~0x0ce)|RS1_G0, "B,J" , F_FLOAT, v8 }, |
1688 | { "fdtos" , F3F(2, 0x34, 0x0c6), F3F(~2, ~0x34, ~0x0c6)|RS1_G0, "B,g" , F_FLOAT, v6 }, |
1689 | { "fqtod" , F3F(2, 0x34, 0x0cb), F3F(~2, ~0x34, ~0x0cb)|RS1_G0, "R,H" , F_FLOAT, v8 }, |
1690 | { "fqtos" , F3F(2, 0x34, 0x0c7), F3F(~2, ~0x34, ~0x0c7)|RS1_G0, "R,g" , F_FLOAT, v8 }, |
1691 | { "fstod" , F3F(2, 0x34, 0x0c9), F3F(~2, ~0x34, ~0x0c9)|RS1_G0, "f,H" , F_FLOAT, v6 }, |
1692 | { "fstoq" , F3F(2, 0x34, 0x0cd), F3F(~2, ~0x34, ~0x0cd)|RS1_G0, "f,J" , F_FLOAT, v8 }, |
1693 | |
1694 | { "fdivd" , F3F(2, 0x34, 0x04e), F3F(~2, ~0x34, ~0x04e), "v,B,H" , F_FLOAT, v6 }, |
1695 | { "fdivq" , F3F(2, 0x34, 0x04f), F3F(~2, ~0x34, ~0x04f), "V,R,J" , F_FLOAT, v8 }, |
1696 | { "fdivx" , F3F(2, 0x34, 0x04f), F3F(~2, ~0x34, ~0x04f), "V,R,J" , F_FLOAT|F_ALIAS, v8 }, |
1697 | { "fdivs" , F3F(2, 0x34, 0x04d), F3F(~2, ~0x34, ~0x04d), "e,f,g" , F_FLOAT, v6 }, |
1698 | { "fmuld" , F3F(2, 0x34, 0x04a), F3F(~2, ~0x34, ~0x04a), "v,B,H" , F_FLOAT, v6 }, |
1699 | { "fmulq" , F3F(2, 0x34, 0x04b), F3F(~2, ~0x34, ~0x04b), "V,R,J" , F_FLOAT, v8 }, |
1700 | { "fmulx" , F3F(2, 0x34, 0x04b), F3F(~2, ~0x34, ~0x04b), "V,R,J" , F_FLOAT|F_ALIAS, v8 }, |
1701 | { "fmuls" , F3F(2, 0x34, 0x049), F3F(~2, ~0x34, ~0x049), "e,f,g" , F_FLOAT, v6 }, |
1702 | |
1703 | { "fdmulq" , F3F(2, 0x34, 0x06e), F3F(~2, ~0x34, ~0x06e), "v,B,J" , F_FLOAT, v8 }, |
1704 | { "fdmulx" , F3F(2, 0x34, 0x06e), F3F(~2, ~0x34, ~0x06e), "v,B,J" , F_FLOAT|F_ALIAS, v8 }, |
1705 | { "fsmuld" , F3F(2, 0x34, 0x069), F3F(~2, ~0x34, ~0x069), "e,f,H" , F_FLOAT, v8 }, |
1706 | |
1707 | { "fsqrtd" , F3F(2, 0x34, 0x02a), F3F(~2, ~0x34, ~0x02a)|RS1_G0, "B,H" , F_FLOAT, v7 }, |
1708 | { "fsqrtq" , F3F(2, 0x34, 0x02b), F3F(~2, ~0x34, ~0x02b)|RS1_G0, "R,J" , F_FLOAT, v8 }, |
1709 | { "fsqrtx" , F3F(2, 0x34, 0x02b), F3F(~2, ~0x34, ~0x02b)|RS1_G0, "R,J" , F_FLOAT|F_ALIAS, v8 }, |
1710 | { "fsqrts" , F3F(2, 0x34, 0x029), F3F(~2, ~0x34, ~0x029)|RS1_G0, "f,g" , F_FLOAT, v7 }, |
1711 | |
1712 | { "fabsd" , F3F(2, 0x34, 0x00a), F3F(~2, ~0x34, ~0x00a)|RS1_G0, "B,H" , F_FLOAT, v9 }, |
1713 | { "fabsq" , F3F(2, 0x34, 0x00b), F3F(~2, ~0x34, ~0x00b)|RS1_G0, "R,J" , F_FLOAT, v9 }, |
1714 | { "fabsx" , F3F(2, 0x34, 0x00b), F3F(~2, ~0x34, ~0x00b)|RS1_G0, "R,J" , F_FLOAT|F_ALIAS, v9 }, |
1715 | { "fabss" , F3F(2, 0x34, 0x009), F3F(~2, ~0x34, ~0x009)|RS1_G0, "f,g" , F_FLOAT, v6 }, |
1716 | { "fmovd" , F3F(2, 0x34, 0x002), F3F(~2, ~0x34, ~0x002)|RS1_G0, "B,H" , F_FLOAT, v9 }, |
1717 | { "fmovq" , F3F(2, 0x34, 0x003), F3F(~2, ~0x34, ~0x003)|RS1_G0, "R,J" , F_FLOAT, v9 }, |
1718 | { "fmovx" , F3F(2, 0x34, 0x003), F3F(~2, ~0x34, ~0x003)|RS1_G0, "R,J" , F_FLOAT|F_ALIAS, v9 }, |
1719 | { "fmovs" , F3F(2, 0x34, 0x001), F3F(~2, ~0x34, ~0x001)|RS1_G0, "f,g" , F_FLOAT, v6 }, |
1720 | { "fnegd" , F3F(2, 0x34, 0x006), F3F(~2, ~0x34, ~0x006)|RS1_G0, "B,H" , F_FLOAT, v9 }, |
1721 | { "fnegq" , F3F(2, 0x34, 0x007), F3F(~2, ~0x34, ~0x007)|RS1_G0, "R,J" , F_FLOAT, v9 }, |
1722 | { "fnegx" , F3F(2, 0x34, 0x007), F3F(~2, ~0x34, ~0x007)|RS1_G0, "R,J" , F_FLOAT|F_ALIAS, v9 }, |
1723 | { "fnegs" , F3F(2, 0x34, 0x005), F3F(~2, ~0x34, ~0x005)|RS1_G0, "f,g" , F_FLOAT, v6 }, |
1724 | |
1725 | { "faddd" , F3F(2, 0x34, 0x042), F3F(~2, ~0x34, ~0x042), "v,B,H" , F_FLOAT, v6 }, |
1726 | { "faddq" , F3F(2, 0x34, 0x043), F3F(~2, ~0x34, ~0x043), "V,R,J" , F_FLOAT, v8 }, |
1727 | { "faddx" , F3F(2, 0x34, 0x043), F3F(~2, ~0x34, ~0x043), "V,R,J" , F_FLOAT|F_ALIAS, v8 }, |
1728 | { "fadds" , F3F(2, 0x34, 0x041), F3F(~2, ~0x34, ~0x041), "e,f,g" , F_FLOAT, v6 }, |
1729 | { "fsubd" , F3F(2, 0x34, 0x046), F3F(~2, ~0x34, ~0x046), "v,B,H" , F_FLOAT, v6 }, |
1730 | { "fsubq" , F3F(2, 0x34, 0x047), F3F(~2, ~0x34, ~0x047), "V,R,J" , F_FLOAT, v8 }, |
1731 | { "fsubx" , F3F(2, 0x34, 0x047), F3F(~2, ~0x34, ~0x047), "V,R,J" , F_FLOAT|F_ALIAS, v8 }, |
1732 | { "fsubs" , F3F(2, 0x34, 0x045), F3F(~2, ~0x34, ~0x045), "e,f,g" , F_FLOAT, v6 }, |
1733 | |
1734 | #define CMPFCC(x) (((x)&0x3)<<25) |
1735 | |
1736 | { "fcmpd" , F3F(2, 0x35, 0x052), F3F(~2, ~0x35, ~0x052)|RD_G0, "v,B" , F_FLOAT, v6 }, |
1737 | { "fcmpd" , CMPFCC(0)|F3F(2, 0x35, 0x052), CMPFCC(~0)|F3F(~2, ~0x35, ~0x052), "6,v,B" , F_FLOAT, v9 }, |
1738 | { "fcmpd" , CMPFCC(1)|F3F(2, 0x35, 0x052), CMPFCC(~1)|F3F(~2, ~0x35, ~0x052), "7,v,B" , F_FLOAT, v9 }, |
1739 | { "fcmpd" , CMPFCC(2)|F3F(2, 0x35, 0x052), CMPFCC(~2)|F3F(~2, ~0x35, ~0x052), "8,v,B" , F_FLOAT, v9 }, |
1740 | { "fcmpd" , CMPFCC(3)|F3F(2, 0x35, 0x052), CMPFCC(~3)|F3F(~2, ~0x35, ~0x052), "9,v,B" , F_FLOAT, v9 }, |
1741 | { "fcmped" , F3F(2, 0x35, 0x056), F3F(~2, ~0x35, ~0x056)|RD_G0, "v,B" , F_FLOAT, v6 }, |
1742 | { "fcmped" , CMPFCC(0)|F3F(2, 0x35, 0x056), CMPFCC(~0)|F3F(~2, ~0x35, ~0x056), "6,v,B" , F_FLOAT, v9 }, |
1743 | { "fcmped" , CMPFCC(1)|F3F(2, 0x35, 0x056), CMPFCC(~1)|F3F(~2, ~0x35, ~0x056), "7,v,B" , F_FLOAT, v9 }, |
1744 | { "fcmped" , CMPFCC(2)|F3F(2, 0x35, 0x056), CMPFCC(~2)|F3F(~2, ~0x35, ~0x056), "8,v,B" , F_FLOAT, v9 }, |
1745 | { "fcmped" , CMPFCC(3)|F3F(2, 0x35, 0x056), CMPFCC(~3)|F3F(~2, ~0x35, ~0x056), "9,v,B" , F_FLOAT, v9 }, |
1746 | { "fcmpq" , F3F(2, 0x35, 0x053), F3F(~2, ~0x35, ~0x053)|RD_G0, "V,R" , F_FLOAT, v8 }, |
1747 | { "fcmpq" , CMPFCC(0)|F3F(2, 0x35, 0x053), CMPFCC(~0)|F3F(~2, ~0x35, ~0x053), "6,V,R" , F_FLOAT, v9 }, |
1748 | { "fcmpq" , CMPFCC(1)|F3F(2, 0x35, 0x053), CMPFCC(~1)|F3F(~2, ~0x35, ~0x053), "7,V,R" , F_FLOAT, v9 }, |
1749 | { "fcmpq" , CMPFCC(2)|F3F(2, 0x35, 0x053), CMPFCC(~2)|F3F(~2, ~0x35, ~0x053), "8,V,R" , F_FLOAT, v9 }, |
1750 | { "fcmpq" , CMPFCC(3)|F3F(2, 0x35, 0x053), CMPFCC(~3)|F3F(~2, ~0x35, ~0x053), "9,V,R" , F_FLOAT, v9 }, |
1751 | { "fcmpeq" , F3F(2, 0x35, 0x057), F3F(~2, ~0x35, ~0x057)|RD_G0, "V,R" , F_FLOAT, v8 }, |
1752 | { "fcmpeq" , CMPFCC(0)|F3F(2, 0x35, 0x057), CMPFCC(~0)|F3F(~2, ~0x35, ~0x057), "6,V,R" , F_FLOAT, v9 }, |
1753 | { "fcmpeq" , CMPFCC(1)|F3F(2, 0x35, 0x057), CMPFCC(~1)|F3F(~2, ~0x35, ~0x057), "7,V,R" , F_FLOAT, v9 }, |
1754 | { "fcmpeq" , CMPFCC(2)|F3F(2, 0x35, 0x057), CMPFCC(~2)|F3F(~2, ~0x35, ~0x057), "8,V,R" , F_FLOAT, v9 }, |
1755 | { "fcmpeq" , CMPFCC(3)|F3F(2, 0x35, 0x057), CMPFCC(~3)|F3F(~2, ~0x35, ~0x057), "9,V,R" , F_FLOAT, v9 }, |
1756 | { "fcmpx" , F3F(2, 0x35, 0x053), F3F(~2, ~0x35, ~0x053)|RD_G0, "V,R" , F_FLOAT|F_ALIAS, v8 }, |
1757 | { "fcmpx" , CMPFCC(0)|F3F(2, 0x35, 0x053), CMPFCC(~0)|F3F(~2, ~0x35, ~0x053), "6,V,R" , F_FLOAT|F_ALIAS, v9 }, |
1758 | { "fcmpx" , CMPFCC(1)|F3F(2, 0x35, 0x053), CMPFCC(~1)|F3F(~2, ~0x35, ~0x053), "7,V,R" , F_FLOAT|F_ALIAS, v9 }, |
1759 | { "fcmpx" , CMPFCC(2)|F3F(2, 0x35, 0x053), CMPFCC(~2)|F3F(~2, ~0x35, ~0x053), "8,V,R" , F_FLOAT|F_ALIAS, v9 }, |
1760 | { "fcmpx" , CMPFCC(3)|F3F(2, 0x35, 0x053), CMPFCC(~3)|F3F(~2, ~0x35, ~0x053), "9,V,R" , F_FLOAT|F_ALIAS, v9 }, |
1761 | { "fcmpex" , F3F(2, 0x35, 0x057), F3F(~2, ~0x35, ~0x057)|RD_G0, "V,R" , F_FLOAT|F_ALIAS, v8 }, |
1762 | { "fcmpex" , CMPFCC(0)|F3F(2, 0x35, 0x057), CMPFCC(~0)|F3F(~2, ~0x35, ~0x057), "6,V,R" , F_FLOAT|F_ALIAS, v9 }, |
1763 | { "fcmpex" , CMPFCC(1)|F3F(2, 0x35, 0x057), CMPFCC(~1)|F3F(~2, ~0x35, ~0x057), "7,V,R" , F_FLOAT|F_ALIAS, v9 }, |
1764 | { "fcmpex" , CMPFCC(2)|F3F(2, 0x35, 0x057), CMPFCC(~2)|F3F(~2, ~0x35, ~0x057), "8,V,R" , F_FLOAT|F_ALIAS, v9 }, |
1765 | { "fcmpex" , CMPFCC(3)|F3F(2, 0x35, 0x057), CMPFCC(~3)|F3F(~2, ~0x35, ~0x057), "9,V,R" , F_FLOAT|F_ALIAS, v9 }, |
1766 | { "fcmps" , F3F(2, 0x35, 0x051), F3F(~2, ~0x35, ~0x051)|RD_G0, "e,f" , F_FLOAT, v6 }, |
1767 | { "fcmps" , CMPFCC(0)|F3F(2, 0x35, 0x051), CMPFCC(~0)|F3F(~2, ~0x35, ~0x051), "6,e,f" , F_FLOAT, v9 }, |
1768 | { "fcmps" , CMPFCC(1)|F3F(2, 0x35, 0x051), CMPFCC(~1)|F3F(~2, ~0x35, ~0x051), "7,e,f" , F_FLOAT, v9 }, |
1769 | { "fcmps" , CMPFCC(2)|F3F(2, 0x35, 0x051), CMPFCC(~2)|F3F(~2, ~0x35, ~0x051), "8,e,f" , F_FLOAT, v9 }, |
1770 | { "fcmps" , CMPFCC(3)|F3F(2, 0x35, 0x051), CMPFCC(~3)|F3F(~2, ~0x35, ~0x051), "9,e,f" , F_FLOAT, v9 }, |
1771 | { "fcmpes" , F3F(2, 0x35, 0x055), F3F(~2, ~0x35, ~0x055)|RD_G0, "e,f" , F_FLOAT, v6 }, |
1772 | { "fcmpes" , CMPFCC(0)|F3F(2, 0x35, 0x055), CMPFCC(~0)|F3F(~2, ~0x35, ~0x055), "6,e,f" , F_FLOAT, v9 }, |
1773 | { "fcmpes" , CMPFCC(1)|F3F(2, 0x35, 0x055), CMPFCC(~1)|F3F(~2, ~0x35, ~0x055), "7,e,f" , F_FLOAT, v9 }, |
1774 | { "fcmpes" , CMPFCC(2)|F3F(2, 0x35, 0x055), CMPFCC(~2)|F3F(~2, ~0x35, ~0x055), "8,e,f" , F_FLOAT, v9 }, |
1775 | { "fcmpes" , CMPFCC(3)|F3F(2, 0x35, 0x055), CMPFCC(~3)|F3F(~2, ~0x35, ~0x055), "9,e,f" , F_FLOAT, v9 }, |
1776 | |
1777 | /* These Extended FPop (FIFO) instructions are new in the Fujitsu |
1778 | MB86934, replacing the CPop instructions from v6 and later |
1779 | processors. */ |
1780 | |
1781 | #define EFPOP1_2(name, op, args) { name, F3F(2, 0x36, op), F3F(~2, ~0x36, ~op)|RS1_G0, args, 0, sparclite } |
1782 | #define EFPOP1_3(name, op, args) { name, F3F(2, 0x36, op), F3F(~2, ~0x36, ~op), args, 0, sparclite } |
1783 | #define EFPOP2_2(name, op, args) { name, F3F(2, 0x37, op), F3F(~2, ~0x37, ~op)|RD_G0, args, 0, sparclite } |
1784 | |
1785 | EFPOP1_2 ("efitod" , 0x0c8, "f,H" ), |
1786 | EFPOP1_2 ("efitos" , 0x0c4, "f,g" ), |
1787 | EFPOP1_2 ("efdtoi" , 0x0d2, "B,g" ), |
1788 | EFPOP1_2 ("efstoi" , 0x0d1, "f,g" ), |
1789 | EFPOP1_2 ("efstod" , 0x0c9, "f,H" ), |
1790 | EFPOP1_2 ("efdtos" , 0x0c6, "B,g" ), |
1791 | EFPOP1_2 ("efmovs" , 0x001, "f,g" ), |
1792 | EFPOP1_2 ("efnegs" , 0x005, "f,g" ), |
1793 | EFPOP1_2 ("efabss" , 0x009, "f,g" ), |
1794 | EFPOP1_2 ("efsqrtd" , 0x02a, "B,H" ), |
1795 | EFPOP1_2 ("efsqrts" , 0x029, "f,g" ), |
1796 | EFPOP1_3 ("efaddd" , 0x042, "v,B,H" ), |
1797 | EFPOP1_3 ("efadds" , 0x041, "e,f,g" ), |
1798 | EFPOP1_3 ("efsubd" , 0x046, "v,B,H" ), |
1799 | EFPOP1_3 ("efsubs" , 0x045, "e,f,g" ), |
1800 | EFPOP1_3 ("efdivd" , 0x04e, "v,B,H" ), |
1801 | EFPOP1_3 ("efdivs" , 0x04d, "e,f,g" ), |
1802 | EFPOP1_3 ("efmuld" , 0x04a, "v,B,H" ), |
1803 | EFPOP1_3 ("efmuls" , 0x049, "e,f,g" ), |
1804 | EFPOP1_3 ("efsmuld" , 0x069, "e,f,H" ), |
1805 | EFPOP2_2 ("efcmpd" , 0x052, "v,B" ), |
1806 | EFPOP2_2 ("efcmped" , 0x056, "v,B" ), |
1807 | EFPOP2_2 ("efcmps" , 0x051, "e,f" ), |
1808 | EFPOP2_2 ("efcmpes" , 0x055, "e,f" ), |
1809 | |
1810 | #undef EFPOP1_2 |
1811 | #undef EFPOP1_3 |
1812 | #undef EFPOP2_2 |
1813 | |
1814 | /* These are marked F_ALIAS, so that they won't conflict with sparclite insns |
1815 | present. Otherwise, the F_ALIAS flag is ignored. */ |
1816 | { "cpop1" , F3(2, 0x36, 0), F3(~2, ~0x36, ~1), "[1+2],d" , F_ALIAS, v6notv9 }, |
1817 | { "cpop2" , F3(2, 0x37, 0), F3(~2, ~0x37, ~1), "[1+2],d" , F_ALIAS, v6notv9 }, |
1818 | |
1819 | /* sparclet specific insns */ |
1820 | |
1821 | COMMUTEOP ("umac" , 0x3e, sparclet), |
1822 | COMMUTEOP ("smac" , 0x3f, sparclet), |
1823 | COMMUTEOP ("umacd" , 0x2e, sparclet), |
1824 | COMMUTEOP ("smacd" , 0x2f, sparclet), |
1825 | COMMUTEOP ("umuld" , 0x09, sparclet), |
1826 | COMMUTEOP ("smuld" , 0x0d, sparclet), |
1827 | |
1828 | { "shuffle" , F3(2, 0x2d, 0), F3(~2, ~0x2d, ~0)|ASI(~0), "1,2,d" , 0, sparclet }, |
1829 | { "shuffle" , F3(2, 0x2d, 1), F3(~2, ~0x2d, ~1), "1,i,d" , 0, sparclet }, |
1830 | |
1831 | /* The manual isn't completely accurate on these insns. The `rs2' field is |
1832 | treated as being 6 bits to account for 6 bit immediates to cpush. It is |
1833 | assumed that it is intended that bit 5 is 0 when rs2 contains a reg. */ |
1834 | #define BIT5 (1<<5) |
1835 | { "crdcxt" , F3(2, 0x36, 0)|SLCPOP(4), F3(~2, ~0x36, ~0)|SLCPOP(~4)|BIT5|RS2(~0), "U,d" , 0, sparclet }, |
1836 | { "cwrcxt" , F3(2, 0x36, 0)|SLCPOP(3), F3(~2, ~0x36, ~0)|SLCPOP(~3)|BIT5|RS2(~0), "1,u" , 0, sparclet }, |
1837 | { "cpush" , F3(2, 0x36, 0)|SLCPOP(0), F3(~2, ~0x36, ~0)|SLCPOP(~0)|BIT5|RD(~0), "1,2" , 0, sparclet }, |
1838 | { "cpush" , F3(2, 0x36, 1)|SLCPOP(0), F3(~2, ~0x36, ~1)|SLCPOP(~0)|RD(~0), "1,Y" , 0, sparclet }, |
1839 | { "cpusha" , F3(2, 0x36, 0)|SLCPOP(1), F3(~2, ~0x36, ~0)|SLCPOP(~1)|BIT5|RD(~0), "1,2" , 0, sparclet }, |
1840 | { "cpusha" , F3(2, 0x36, 1)|SLCPOP(1), F3(~2, ~0x36, ~1)|SLCPOP(~1)|RD(~0), "1,Y" , 0, sparclet }, |
1841 | { "cpull" , F3(2, 0x36, 0)|SLCPOP(2), F3(~2, ~0x36, ~0)|SLCPOP(~2)|BIT5|RS1(~0)|RS2(~0), "d" , 0, sparclet }, |
1842 | #undef BIT5 |
1843 | |
1844 | /* sparclet coprocessor branch insns */ |
1845 | #define SLCBCC2(opcode, mask, lose) \ |
1846 | { opcode, (mask), ANNUL|(lose), "l", F_DELAYED|F_CONDBR, sparclet }, \ |
1847 | { opcode, (mask)|ANNUL, (lose), ",a l", F_DELAYED|F_CONDBR, sparclet } |
1848 | #define SLCBCC(opcode, mask) \ |
1849 | SLCBCC2(opcode, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask))) |
1850 | |
1851 | /* cbn,cba can't be defined here because they're defined elsewhere and GAS |
1852 | requires all mnemonics of the same name to be consecutive. */ |
1853 | /*SLCBCC("cbn", 0), - already defined */ |
1854 | SLCBCC("cbe" , 1), |
1855 | SLCBCC("cbf" , 2), |
1856 | SLCBCC("cbef" , 3), |
1857 | SLCBCC("cbr" , 4), |
1858 | SLCBCC("cber" , 5), |
1859 | SLCBCC("cbfr" , 6), |
1860 | SLCBCC("cbefr" , 7), |
1861 | /*SLCBCC("cba", 8), - already defined */ |
1862 | SLCBCC("cbne" , 9), |
1863 | SLCBCC("cbnf" , 10), |
1864 | SLCBCC("cbnef" , 11), |
1865 | SLCBCC("cbnr" , 12), |
1866 | SLCBCC("cbner" , 13), |
1867 | SLCBCC("cbnfr" , 14), |
1868 | SLCBCC("cbnefr" , 15), |
1869 | |
1870 | #undef SLCBCC2 |
1871 | #undef SLCBCC |
1872 | |
1873 | { "casa" , F3(3, 0x3c, 0), F3(~3, ~0x3c, ~0), "[1]A,2,d" , 0, v9 }, |
1874 | { "casa" , F3(3, 0x3c, 1), F3(~3, ~0x3c, ~1), "[1]o,2,d" , 0, v9 }, |
1875 | { "casxa" , F3(3, 0x3e, 0), F3(~3, ~0x3e, ~0), "[1]A,2,d" , 0, v9 }, |
1876 | { "casxa" , F3(3, 0x3e, 1), F3(~3, ~0x3e, ~1), "[1]o,2,d" , 0, v9 }, |
1877 | |
1878 | /* v9 synthetic insns */ |
1879 | { "iprefetch" , F2(0, 1)|(2<<20)|BPRED, F2(~0, ~1)|(1<<20)|ANNUL|COND(~0), "G" , 0, v9 }, /* bn,a,pt %xcc,label */ |
1880 | { "signx" , F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0)|RS2_G0, "1,d" , F_ALIAS, v9 }, /* sra rs1,%g0,rd */ |
1881 | { "signx" , F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0)|RS2_G0, "r" , F_ALIAS, v9 }, /* sra rd,%g0,rd */ |
1882 | { "clruw" , F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0, "1,d" , F_ALIAS, v9 }, /* srl rs1,%g0,rd */ |
1883 | { "clruw" , F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0, "r" , F_ALIAS, v9 }, /* srl rd,%g0,rd */ |
1884 | { "cas" , F3(3, 0x3c, 0)|ASI(0x80), F3(~3, ~0x3c, ~0)|ASI(~0x80), "[1],2,d" , F_ALIAS, v9 }, /* casa [rs1]ASI_P,rs2,rd */ |
1885 | { "casl" , F3(3, 0x3c, 0)|ASI(0x88), F3(~3, ~0x3c, ~0)|ASI(~0x88), "[1],2,d" , F_ALIAS, v9 }, /* casa [rs1]ASI_P_L,rs2,rd */ |
1886 | { "casx" , F3(3, 0x3e, 0)|ASI(0x80), F3(~3, ~0x3e, ~0)|ASI(~0x80), "[1],2,d" , F_ALIAS, v9 }, /* casxa [rs1]ASI_P,rs2,rd */ |
1887 | { "casxl" , F3(3, 0x3e, 0)|ASI(0x88), F3(~3, ~0x3e, ~0)|ASI(~0x88), "[1],2,d" , F_ALIAS, v9 }, /* casxa [rs1]ASI_P_L,rs2,rd */ |
1888 | |
1889 | /* Ultrasparc extensions */ |
1890 | { "shutdown" , F3F(2, 0x36, 0x080), F3F(~2, ~0x36, ~0x080)|RD_G0|RS1_G0|RS2_G0, "" , 0, v9a }, |
1891 | |
1892 | /* FIXME: Do we want to mark these as F_FLOAT, or something similar? */ |
1893 | { "fpadd16" , F3F(2, 0x36, 0x050), F3F(~2, ~0x36, ~0x050), "v,B,H" , 0, v9a }, |
1894 | { "fpadd16s" , F3F(2, 0x36, 0x051), F3F(~2, ~0x36, ~0x051), "e,f,g" , 0, v9a }, |
1895 | { "fpadd32" , F3F(2, 0x36, 0x052), F3F(~2, ~0x36, ~0x052), "v,B,H" , 0, v9a }, |
1896 | { "fpadd32s" , F3F(2, 0x36, 0x053), F3F(~2, ~0x36, ~0x053), "e,f,g" , 0, v9a }, |
1897 | { "fpsub16" , F3F(2, 0x36, 0x054), F3F(~2, ~0x36, ~0x054), "v,B,H" , 0, v9a }, |
1898 | { "fpsub16s" , F3F(2, 0x36, 0x055), F3F(~2, ~0x36, ~0x055), "e,f,g" , 0, v9a }, |
1899 | { "fpsub32" , F3F(2, 0x36, 0x056), F3F(~2, ~0x36, ~0x056), "v,B,H" , 0, v9a }, |
1900 | { "fpsub32s" , F3F(2, 0x36, 0x057), F3F(~2, ~0x36, ~0x057), "e,f,g" , 0, v9a }, |
1901 | |
1902 | { "fpack32" , F3F(2, 0x36, 0x03a), F3F(~2, ~0x36, ~0x03a), "v,B,H" , 0, v9a }, |
1903 | { "fpack16" , F3F(2, 0x36, 0x03b), F3F(~2, ~0x36, ~0x03b)|RS1_G0, "B,g" , 0, v9a }, |
1904 | { "fpackfix" , F3F(2, 0x36, 0x03d), F3F(~2, ~0x36, ~0x03d)|RS1_G0, "B,g" , 0, v9a }, |
1905 | { "fexpand" , F3F(2, 0x36, 0x04d), F3F(~2, ~0x36, ~0x04d)|RS1_G0, "f,H" , 0, v9a }, |
1906 | { "fpmerge" , F3F(2, 0x36, 0x04b), F3F(~2, ~0x36, ~0x04b), "e,f,H" , 0, v9a }, |
1907 | |
1908 | /* Note that the mixing of 32/64 bit regs is intentional. */ |
1909 | { "fmul8x16" , F3F(2, 0x36, 0x031), F3F(~2, ~0x36, ~0x031), "e,B,H" , 0, v9a }, |
1910 | { "fmul8x16au" , F3F(2, 0x36, 0x033), F3F(~2, ~0x36, ~0x033), "e,f,H" , 0, v9a }, |
1911 | { "fmul8x16al" , F3F(2, 0x36, 0x035), F3F(~2, ~0x36, ~0x035), "e,f,H" , 0, v9a }, |
1912 | { "fmul8sux16" , F3F(2, 0x36, 0x036), F3F(~2, ~0x36, ~0x036), "v,B,H" , 0, v9a }, |
1913 | { "fmul8ulx16" , F3F(2, 0x36, 0x037), F3F(~2, ~0x36, ~0x037), "v,B,H" , 0, v9a }, |
1914 | { "fmuld8sux16" , F3F(2, 0x36, 0x038), F3F(~2, ~0x36, ~0x038), "e,f,H" , 0, v9a }, |
1915 | { "fmuld8ulx16" , F3F(2, 0x36, 0x039), F3F(~2, ~0x36, ~0x039), "e,f,H" , 0, v9a }, |
1916 | |
1917 | { "alignaddr" , F3F(2, 0x36, 0x018), F3F(~2, ~0x36, ~0x018), "1,2,d" , 0, v9a }, |
1918 | { "alignaddrl" , F3F(2, 0x36, 0x01a), F3F(~2, ~0x36, ~0x01a), "1,2,d" , 0, v9a }, |
1919 | { "faligndata" , F3F(2, 0x36, 0x048), F3F(~2, ~0x36, ~0x048), "v,B,H" , 0, v9a }, |
1920 | |
1921 | { "fzero" , F3F(2, 0x36, 0x060), F3F(~2, ~0x36, ~0x060), "H" , 0, v9a }, |
1922 | { "fzeros" , F3F(2, 0x36, 0x061), F3F(~2, ~0x36, ~0x061), "g" , 0, v9a }, |
1923 | { "fone" , F3F(2, 0x36, 0x07e), F3F(~2, ~0x36, ~0x07e), "H" , 0, v9a }, |
1924 | { "fones" , F3F(2, 0x36, 0x07f), F3F(~2, ~0x36, ~0x07f), "g" , 0, v9a }, |
1925 | { "fsrc1" , F3F(2, 0x36, 0x074), F3F(~2, ~0x36, ~0x074), "v,H" , 0, v9a }, |
1926 | { "fsrc1s" , F3F(2, 0x36, 0x075), F3F(~2, ~0x36, ~0x075), "e,g" , 0, v9a }, |
1927 | { "fsrc2" , F3F(2, 0x36, 0x078), F3F(~2, ~0x36, ~0x078), "B,H" , 0, v9a }, |
1928 | { "fsrc2s" , F3F(2, 0x36, 0x079), F3F(~2, ~0x36, ~0x079), "f,g" , 0, v9a }, |
1929 | { "fnot1" , F3F(2, 0x36, 0x06a), F3F(~2, ~0x36, ~0x06a), "v,H" , 0, v9a }, |
1930 | { "fnot1s" , F3F(2, 0x36, 0x06b), F3F(~2, ~0x36, ~0x06b), "e,g" , 0, v9a }, |
1931 | { "fnot2" , F3F(2, 0x36, 0x066), F3F(~2, ~0x36, ~0x066), "B,H" , 0, v9a }, |
1932 | { "fnot2s" , F3F(2, 0x36, 0x067), F3F(~2, ~0x36, ~0x067), "f,g" , 0, v9a }, |
1933 | { "for" , F3F(2, 0x36, 0x07c), F3F(~2, ~0x36, ~0x07c), "v,B,H" , 0, v9a }, |
1934 | { "fors" , F3F(2, 0x36, 0x07d), F3F(~2, ~0x36, ~0x07d), "e,f,g" , 0, v9a }, |
1935 | { "fnor" , F3F(2, 0x36, 0x062), F3F(~2, ~0x36, ~0x062), "v,B,H" , 0, v9a }, |
1936 | { "fnors" , F3F(2, 0x36, 0x063), F3F(~2, ~0x36, ~0x063), "e,f,g" , 0, v9a }, |
1937 | { "fand" , F3F(2, 0x36, 0x070), F3F(~2, ~0x36, ~0x070), "v,B,H" , 0, v9a }, |
1938 | { "fands" , F3F(2, 0x36, 0x071), F3F(~2, ~0x36, ~0x071), "e,f,g" , 0, v9a }, |
1939 | { "fnand" , F3F(2, 0x36, 0x06e), F3F(~2, ~0x36, ~0x06e), "v,B,H" , 0, v9a }, |
1940 | { "fnands" , F3F(2, 0x36, 0x06f), F3F(~2, ~0x36, ~0x06f), "e,f,g" , 0, v9a }, |
1941 | { "fxor" , F3F(2, 0x36, 0x06c), F3F(~2, ~0x36, ~0x06c), "v,B,H" , 0, v9a }, |
1942 | { "fxors" , F3F(2, 0x36, 0x06d), F3F(~2, ~0x36, ~0x06d), "e,f,g" , 0, v9a }, |
1943 | { "fxnor" , F3F(2, 0x36, 0x072), F3F(~2, ~0x36, ~0x072), "v,B,H" , 0, v9a }, |
1944 | { "fxnors" , F3F(2, 0x36, 0x073), F3F(~2, ~0x36, ~0x073), "e,f,g" , 0, v9a }, |
1945 | { "fornot1" , F3F(2, 0x36, 0x07a), F3F(~2, ~0x36, ~0x07a), "v,B,H" , 0, v9a }, |
1946 | { "fornot1s" , F3F(2, 0x36, 0x07b), F3F(~2, ~0x36, ~0x07b), "e,f,g" , 0, v9a }, |
1947 | { "fornot2" , F3F(2, 0x36, 0x076), F3F(~2, ~0x36, ~0x076), "v,B,H" , 0, v9a }, |
1948 | { "fornot2s" , F3F(2, 0x36, 0x077), F3F(~2, ~0x36, ~0x077), "e,f,g" , 0, v9a }, |
1949 | { "fandnot1" , F3F(2, 0x36, 0x068), F3F(~2, ~0x36, ~0x068), "v,B,H" , 0, v9a }, |
1950 | { "fandnot1s" , F3F(2, 0x36, 0x069), F3F(~2, ~0x36, ~0x069), "e,f,g" , 0, v9a }, |
1951 | { "fandnot2" , F3F(2, 0x36, 0x064), F3F(~2, ~0x36, ~0x064), "v,B,H" , 0, v9a }, |
1952 | { "fandnot2s" , F3F(2, 0x36, 0x065), F3F(~2, ~0x36, ~0x065), "e,f,g" , 0, v9a }, |
1953 | |
1954 | { "fcmpgt16" , F3F(2, 0x36, 0x028), F3F(~2, ~0x36, ~0x028), "v,B,d" , 0, v9a }, |
1955 | { "fcmpgt32" , F3F(2, 0x36, 0x02c), F3F(~2, ~0x36, ~0x02c), "v,B,d" , 0, v9a }, |
1956 | { "fcmple16" , F3F(2, 0x36, 0x020), F3F(~2, ~0x36, ~0x020), "v,B,d" , 0, v9a }, |
1957 | { "fcmple32" , F3F(2, 0x36, 0x024), F3F(~2, ~0x36, ~0x024), "v,B,d" , 0, v9a }, |
1958 | { "fcmpne16" , F3F(2, 0x36, 0x022), F3F(~2, ~0x36, ~0x022), "v,B,d" , 0, v9a }, |
1959 | { "fcmpne32" , F3F(2, 0x36, 0x026), F3F(~2, ~0x36, ~0x026), "v,B,d" , 0, v9a }, |
1960 | { "fcmpeq16" , F3F(2, 0x36, 0x02a), F3F(~2, ~0x36, ~0x02a), "v,B,d" , 0, v9a }, |
1961 | { "fcmpeq32" , F3F(2, 0x36, 0x02e), F3F(~2, ~0x36, ~0x02e), "v,B,d" , 0, v9a }, |
1962 | |
1963 | { "edge8" , F3F(2, 0x36, 0x000), F3F(~2, ~0x36, ~0x000), "1,2,d" , 0, v9a }, |
1964 | { "edge8l" , F3F(2, 0x36, 0x002), F3F(~2, ~0x36, ~0x002), "1,2,d" , 0, v9a }, |
1965 | { "edge16" , F3F(2, 0x36, 0x004), F3F(~2, ~0x36, ~0x004), "1,2,d" , 0, v9a }, |
1966 | { "edge16l" , F3F(2, 0x36, 0x006), F3F(~2, ~0x36, ~0x006), "1,2,d" , 0, v9a }, |
1967 | { "edge32" , F3F(2, 0x36, 0x008), F3F(~2, ~0x36, ~0x008), "1,2,d" , 0, v9a }, |
1968 | { "edge32l" , F3F(2, 0x36, 0x00a), F3F(~2, ~0x36, ~0x00a), "1,2,d" , 0, v9a }, |
1969 | |
1970 | { "pdist" , F3F(2, 0x36, 0x03e), F3F(~2, ~0x36, ~0x03e), "v,B,H" , 0, v9a }, |
1971 | |
1972 | { "array8" , F3F(2, 0x36, 0x010), F3F(~2, ~0x36, ~0x010), "1,2,d" , 0, v9a }, |
1973 | { "array16" , F3F(2, 0x36, 0x012), F3F(~2, ~0x36, ~0x012), "1,2,d" , 0, v9a }, |
1974 | { "array32" , F3F(2, 0x36, 0x014), F3F(~2, ~0x36, ~0x014), "1,2,d" , 0, v9a }, |
1975 | |
1976 | /* Cheetah instructions */ |
1977 | { "edge8n" , F3F(2, 0x36, 0x001), F3F(~2, ~0x36, ~0x001), "1,2,d" , 0, v9b }, |
1978 | { "edge8ln" , F3F(2, 0x36, 0x003), F3F(~2, ~0x36, ~0x003), "1,2,d" , 0, v9b }, |
1979 | { "edge16n" , F3F(2, 0x36, 0x005), F3F(~2, ~0x36, ~0x005), "1,2,d" , 0, v9b }, |
1980 | { "edge16ln" , F3F(2, 0x36, 0x007), F3F(~2, ~0x36, ~0x007), "1,2,d" , 0, v9b }, |
1981 | { "edge32n" , F3F(2, 0x36, 0x009), F3F(~2, ~0x36, ~0x009), "1,2,d" , 0, v9b }, |
1982 | { "edge32ln" , F3F(2, 0x36, 0x00b), F3F(~2, ~0x36, ~0x00b), "1,2,d" , 0, v9b }, |
1983 | |
1984 | { "bmask" , F3F(2, 0x36, 0x019), F3F(~2, ~0x36, ~0x019), "1,2,d" , 0, v9b }, |
1985 | { "bshuffle" , F3F(2, 0x36, 0x04c), F3F(~2, ~0x36, ~0x04c), "v,B,H" , 0, v9b }, |
1986 | |
1987 | { "siam" , F3F(2, 0x36, 0x081), F3F(~2, ~0x36, ~0x081)|RD_G0|RS1_G0|RS2(~7), "3" , 0, v9b }, |
1988 | |
1989 | /* More v9 specific insns, these need to come last so they do not clash |
1990 | with v9a instructions such as "edge8" which looks like impdep1. */ |
1991 | |
1992 | #define IMPDEP(name, code) \ |
1993 | { name, F3(2, code, 0), F3(~2, ~code, ~0)|ASI(~0), "1,2,d", 0, v9notv9a }, \ |
1994 | { name, F3(2, code, 1), F3(~2, ~code, ~1), "1,i,d", 0, v9notv9a }, \ |
1995 | { name, F3(2, code, 0), F3(~2, ~code, ~0), "x,1,2,d", 0, v9notv9a }, \ |
1996 | { name, F3(2, code, 0), F3(~2, ~code, ~0), "x,e,f,g", 0, v9notv9a } |
1997 | |
1998 | IMPDEP ("impdep1" , 0x36), |
1999 | IMPDEP ("impdep2" , 0x37), |
2000 | |
2001 | #undef IMPDEP |
2002 | |
2003 | { "addxc" , F3F(2, 0x36, 0x011), F3F(~2, ~0x36, ~0x011), "1,2,d" , 0, v9b }, |
2004 | { "addxccc" , F3F(2, 0x36, 0x013), F3F(~2, ~0x36, ~0x013), "1,2,d" , 0, v9b }, |
2005 | { "umulxhi" , F3F(2, 0x36, 0x016), F3F(~2, ~0x36, ~0x016), "1,2,d" , 0, v9b }, |
2006 | |
2007 | }; |
2008 | |
2009 | static const int sparc_num_opcodes = ((sizeof sparc_opcodes)/(sizeof sparc_opcodes[0])); |
2010 | |
2011 | /* Utilities for argument parsing. */ |
2012 | |
2013 | typedef struct |
2014 | { |
2015 | int value; |
2016 | const char *name; |
2017 | } arg; |
2018 | |
2019 | /* Look up VALUE in TABLE. */ |
2020 | |
2021 | static const char * |
2022 | lookup_value (const arg *table, int value) |
2023 | { |
2024 | const arg *p; |
2025 | |
2026 | for (p = table; p->name; ++p) |
2027 | if (value == p->value) |
2028 | return p->name; |
2029 | |
2030 | return NULL; |
2031 | } |
2032 | |
2033 | /* Handle ASI's. */ |
2034 | |
2035 | static const arg asi_table_v8[] = |
2036 | { |
2037 | { 0x00, "#ASI_M_RES00" }, |
2038 | { 0x01, "#ASI_M_UNA01" }, |
2039 | { 0x02, "#ASI_M_MXCC" }, |
2040 | { 0x03, "#ASI_M_FLUSH_PROBE" }, |
2041 | { 0x04, "#ASI_M_MMUREGS" }, |
2042 | { 0x05, "#ASI_M_TLBDIAG" }, |
2043 | { 0x06, "#ASI_M_DIAGS" }, |
2044 | { 0x07, "#ASI_M_IODIAG" }, |
2045 | { 0x08, "#ASI_M_USERTXT" }, |
2046 | { 0x09, "#ASI_M_KERNELTXT" }, |
2047 | { 0x0A, "#ASI_M_USERDATA" }, |
2048 | { 0x0B, "#ASI_M_KERNELDATA" }, |
2049 | { 0x0C, "#ASI_M_TXTC_TAG" }, |
2050 | { 0x0D, "#ASI_M_TXTC_DATA" }, |
2051 | { 0x0E, "#ASI_M_DATAC_TAG" }, |
2052 | { 0x0F, "#ASI_M_DATAC_DATA" }, |
2053 | { 0x10, "#ASI_M_FLUSH_PAGE" }, |
2054 | { 0x11, "#ASI_M_FLUSH_SEG" }, |
2055 | { 0x12, "#ASI_M_FLUSH_REGION" }, |
2056 | { 0x13, "#ASI_M_FLUSH_CTX" }, |
2057 | { 0x14, "#ASI_M_FLUSH_USER" }, |
2058 | { 0x17, "#ASI_M_BCOPY" }, |
2059 | { 0x18, "#ASI_M_IFLUSH_PAGE" }, |
2060 | { 0x19, "#ASI_M_IFLUSH_SEG" }, |
2061 | { 0x1A, "#ASI_M_IFLUSH_REGION" }, |
2062 | { 0x1B, "#ASI_M_IFLUSH_CTX" }, |
2063 | { 0x1C, "#ASI_M_IFLUSH_USER" }, |
2064 | { 0x1F, "#ASI_M_BFILL" }, |
2065 | { 0x20, "#ASI_M_BYPASS" }, |
2066 | { 0x29, "#ASI_M_FBMEM" }, |
2067 | { 0x2A, "#ASI_M_VMEUS" }, |
2068 | { 0x2B, "#ASI_M_VMEPS" }, |
2069 | { 0x2C, "#ASI_M_VMEUT" }, |
2070 | { 0x2D, "#ASI_M_VMEPT" }, |
2071 | { 0x2E, "#ASI_M_SBUS" }, |
2072 | { 0x2F, "#ASI_M_CTL" }, |
2073 | { 0x31, "#ASI_M_FLUSH_IWHOLE" }, |
2074 | { 0x36, "#ASI_M_IC_FLCLEAR" }, |
2075 | { 0x37, "#ASI_M_DC_FLCLEAR" }, |
2076 | { 0x39, "#ASI_M_DCDR" }, |
2077 | { 0x40, "#ASI_M_VIKING_TMP1" }, |
2078 | { 0x41, "#ASI_M_VIKING_TMP2" }, |
2079 | { 0x4c, "#ASI_M_ACTION" }, |
2080 | { 0, NULL } |
2081 | }; |
2082 | |
2083 | static const arg asi_table_v9[] = |
2084 | { |
2085 | /* These are in the v9 architecture manual. */ |
2086 | /* The shorter versions appear first, they're here because Sun's as has them. |
2087 | Sun's as uses #ASI_P_L instead of #ASI_PL (which appears in the |
2088 | UltraSPARC architecture manual). */ |
2089 | { 0x04, "#ASI_N" }, |
2090 | { 0x0c, "#ASI_N_L" }, |
2091 | { 0x10, "#ASI_AIUP" }, |
2092 | { 0x11, "#ASI_AIUS" }, |
2093 | { 0x18, "#ASI_AIUP_L" }, |
2094 | { 0x19, "#ASI_AIUS_L" }, |
2095 | { 0x80, "#ASI_P" }, |
2096 | { 0x81, "#ASI_S" }, |
2097 | { 0x82, "#ASI_PNF" }, |
2098 | { 0x83, "#ASI_SNF" }, |
2099 | { 0x88, "#ASI_P_L" }, |
2100 | { 0x89, "#ASI_S_L" }, |
2101 | { 0x8a, "#ASI_PNF_L" }, |
2102 | { 0x8b, "#ASI_SNF_L" }, |
2103 | { 0x04, "#ASI_NUCLEUS" }, |
2104 | { 0x0c, "#ASI_NUCLEUS_LITTLE" }, |
2105 | { 0x10, "#ASI_AS_IF_USER_PRIMARY" }, |
2106 | { 0x11, "#ASI_AS_IF_USER_SECONDARY" }, |
2107 | { 0x18, "#ASI_AS_IF_USER_PRIMARY_LITTLE" }, |
2108 | { 0x19, "#ASI_AS_IF_USER_SECONDARY_LITTLE" }, |
2109 | { 0x80, "#ASI_PRIMARY" }, |
2110 | { 0x81, "#ASI_SECONDARY" }, |
2111 | { 0x82, "#ASI_PRIMARY_NOFAULT" }, |
2112 | { 0x83, "#ASI_SECONDARY_NOFAULT" }, |
2113 | { 0x88, "#ASI_PRIMARY_LITTLE" }, |
2114 | { 0x89, "#ASI_SECONDARY_LITTLE" }, |
2115 | { 0x8a, "#ASI_PRIMARY_NOFAULT_LITTLE" }, |
2116 | { 0x8b, "#ASI_SECONDARY_NOFAULT_LITTLE" }, |
2117 | /* These are UltraSPARC extensions. */ |
2118 | { 0x14, "#ASI_PHYS_USE_EC" }, |
2119 | { 0x15, "#ASI_PHYS_BYPASS_EC_WITH_EBIT" }, |
2120 | { 0x45, "#ASI_LSU_CONTROL_REG" }, |
2121 | { 0x47, "#ASI_DCACHE_TAG" }, |
2122 | { 0x4a, "#ASI_UPA_CONFIG_REG" }, |
2123 | { 0x50, "#ASI_IMMU" }, |
2124 | { 0x51, "#ASI_IMMU_TSB_8KB_PTR_REG" }, |
2125 | { 0x52, "#ASI_IMMU_TSB_64KB_PTR_REG" }, |
2126 | /*{ 0x53, "#reserved?" },*/ |
2127 | { 0x54, "#ASI_ITLB_DATA_IN_REG" }, |
2128 | { 0x55, "#ASI_ITLB_DATA_ACCESS_REG" }, |
2129 | { 0x56, "#ASI_ITLB_TAG_READ_REG" }, |
2130 | { 0x57, "#ASI_IMMU_DEMAP" }, |
2131 | { 0x58, "#ASI_DMMU" }, |
2132 | { 0x59, "#ASI_DMMU_TSB_8KB_PTR_REG" }, |
2133 | { 0x5a, "#ASI_DMMU_TSB_64KB_PTR_REG" }, |
2134 | { 0x5b, "#ASI_DMMU_TSB_DIRECT_PTR_REG" }, |
2135 | { 0x5c, "#ASI_DTLB_DATA_IN_REG" }, |
2136 | { 0x5d, "#ASI_DTLB_DATA_ACCESS_REG" }, |
2137 | { 0x5e, "#ASI_DTLB_TAG_READ_REG" }, |
2138 | { 0x5f, "#ASI_DMMU_DEMAP" }, |
2139 | { 0x67, "#ASI_IC_TAG" }, |
2140 | /* FIXME: There are dozens of them. Not sure we want them all. |
2141 | Most are for kernel building but some are for vis type stuff. */ |
2142 | { 0, NULL } |
2143 | }; |
2144 | |
2145 | /* Return the name for ASI value VALUE or NULL if not found. */ |
2146 | |
2147 | static const char * |
2148 | sparc_decode_asi_v9 (int value) |
2149 | { |
2150 | return lookup_value (asi_table_v9, value); |
2151 | } |
2152 | |
2153 | static const char * |
2154 | sparc_decode_asi_v8 (int value) |
2155 | { |
2156 | return lookup_value (asi_table_v8, value); |
2157 | } |
2158 | |
2159 | /* Handle membar masks. */ |
2160 | |
2161 | static const arg membar_table[] = |
2162 | { |
2163 | { 0x40, "#Sync" }, |
2164 | { 0x20, "#MemIssue" }, |
2165 | { 0x10, "#Lookaside" }, |
2166 | { 0x08, "#StoreStore" }, |
2167 | { 0x04, "#LoadStore" }, |
2168 | { 0x02, "#StoreLoad" }, |
2169 | { 0x01, "#LoadLoad" }, |
2170 | { 0, NULL } |
2171 | }; |
2172 | |
2173 | /* Return the name for membar value VALUE or NULL if not found. */ |
2174 | |
2175 | static const char * |
2176 | sparc_decode_membar (int value) |
2177 | { |
2178 | return lookup_value (membar_table, value); |
2179 | } |
2180 | |
2181 | /* Handle prefetch args. */ |
2182 | |
2183 | static const arg prefetch_table[] = |
2184 | { |
2185 | { 0, "#n_reads" }, |
2186 | { 1, "#one_read" }, |
2187 | { 2, "#n_writes" }, |
2188 | { 3, "#one_write" }, |
2189 | { 4, "#page" }, |
2190 | { 16, "#invalidate" }, |
2191 | { 0, NULL } |
2192 | }; |
2193 | |
2194 | /* Return the name for prefetch value VALUE or NULL if not found. */ |
2195 | |
2196 | static const char * |
2197 | sparc_decode_prefetch (int value) |
2198 | { |
2199 | return lookup_value (prefetch_table, value); |
2200 | } |
2201 | |
2202 | /* Handle sparclet coprocessor registers. */ |
2203 | |
2204 | static const arg sparclet_cpreg_table[] = |
2205 | { |
2206 | { 0, "%ccsr" }, |
2207 | { 1, "%ccfr" }, |
2208 | { 2, "%cccrcr" }, |
2209 | { 3, "%ccpr" }, |
2210 | { 4, "%ccsr2" }, |
2211 | { 5, "%cccrr" }, |
2212 | { 6, "%ccrstr" }, |
2213 | { 0, NULL } |
2214 | }; |
2215 | |
2216 | /* Return the name for sparclet cpreg value VALUE or NULL if not found. */ |
2217 | |
2218 | static const char * |
2219 | sparc_decode_sparclet_cpreg (int value) |
2220 | { |
2221 | return lookup_value (sparclet_cpreg_table, value); |
2222 | } |
2223 | |
2224 | #undef MASK_V9 |
2225 | |
2226 | /* opcodes/sparc-dis.c */ |
2227 | |
2228 | /* Print SPARC instructions. |
2229 | Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
2230 | 2000, 2002, 2003, 2004, 2005 Free Software Foundation, Inc. |
2231 | |
2232 | This program is free software; you can redistribute it and/or modify |
2233 | it under the terms of the GNU General Public License as published by |
2234 | the Free Software Foundation; either version 2 of the License, or |
2235 | (at your option) any later version. |
2236 | |
2237 | This program is distributed in the hope that it will be useful, |
2238 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
2239 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
2240 | GNU General Public License for more details. |
2241 | |
2242 | You should have received a copy of the GNU General Public License |
2243 | along with this program; if not, see <http://www.gnu.org/licenses/>. */ |
2244 | |
2245 | /* Bitmask of v9 architectures. */ |
2246 | #define MASK_V9 ((1 << SPARC_OPCODE_ARCH_V9) \ |
2247 | | (1 << SPARC_OPCODE_ARCH_V9A) \ |
2248 | | (1 << SPARC_OPCODE_ARCH_V9B)) |
2249 | /* 1 if INSN is for v9 only. */ |
2250 | #define V9_ONLY_P(insn) (! ((insn)->architecture & ~MASK_V9)) |
2251 | /* 1 if INSN is for v9. */ |
2252 | #define V9_P(insn) (((insn)->architecture & MASK_V9) != 0) |
2253 | |
2254 | /* The sorted opcode table. */ |
2255 | static const sparc_opcode **sorted_opcodes; |
2256 | |
2257 | /* For faster lookup, after insns are sorted they are hashed. */ |
2258 | /* ??? I think there is room for even more improvement. */ |
2259 | |
2260 | #define HASH_SIZE 256 |
2261 | /* It is important that we only look at insn code bits as that is how the |
2262 | opcode table is hashed. OPCODE_BITS is a table of valid bits for each |
2263 | of the main types (0,1,2,3). */ |
2264 | static const int opcode_bits[4] = { 0x01c00000, 0x0, 0x01f80000, 0x01f80000 }; |
2265 | #define HASH_INSN(INSN) \ |
2266 | ((((INSN) >> 24) & 0xc0) | (((INSN) & opcode_bits[((INSN) >> 30) & 3]) >> 19)) |
2267 | typedef struct sparc_opcode_hash |
2268 | { |
2269 | struct sparc_opcode_hash *next; |
2270 | const sparc_opcode *opcode; |
2271 | } sparc_opcode_hash; |
2272 | |
2273 | static sparc_opcode_hash *opcode_hash_table[HASH_SIZE]; |
2274 | |
2275 | /* Sign-extend a value which is N bits long. */ |
2276 | #define SEX(value, bits) \ |
2277 | ((((int)(value)) << ((8 * sizeof (int)) - bits)) \ |
2278 | >> ((8 * sizeof (int)) - bits) ) |
2279 | |
2280 | static const char * const reg_names[] = |
2281 | { "g0" , "g1" , "g2" , "g3" , "g4" , "g5" , "g6" , "g7" , |
2282 | "o0" , "o1" , "o2" , "o3" , "o4" , "o5" , "sp" , "o7" , |
2283 | "l0" , "l1" , "l2" , "l3" , "l4" , "l5" , "l6" , "l7" , |
2284 | "i0" , "i1" , "i2" , "i3" , "i4" , "i5" , "fp" , "i7" , |
2285 | "f0" , "f1" , "f2" , "f3" , "f4" , "f5" , "f6" , "f7" , |
2286 | "f8" , "f9" , "f10" , "f11" , "f12" , "f13" , "f14" , "f15" , |
2287 | "f16" , "f17" , "f18" , "f19" , "f20" , "f21" , "f22" , "f23" , |
2288 | "f24" , "f25" , "f26" , "f27" , "f28" , "f29" , "f30" , "f31" , |
2289 | "f32" , "f33" , "f34" , "f35" , "f36" , "f37" , "f38" , "f39" , |
2290 | "f40" , "f41" , "f42" , "f43" , "f44" , "f45" , "f46" , "f47" , |
2291 | "f48" , "f49" , "f50" , "f51" , "f52" , "f53" , "f54" , "f55" , |
2292 | "f56" , "f57" , "f58" , "f59" , "f60" , "f61" , "f62" , "f63" , |
2293 | /* psr, wim, tbr, fpsr, cpsr are v8 only. */ |
2294 | "y" , "psr" , "wim" , "tbr" , "pc" , "npc" , "fpsr" , "cpsr" |
2295 | }; |
2296 | |
2297 | #define freg_names (®_names[4 * 8]) |
2298 | |
2299 | /* These are ordered according to there register number in |
2300 | rdpr and wrpr insns. */ |
2301 | static const char * const v9_priv_reg_names[] = |
2302 | { |
2303 | "tpc" , "tnpc" , "tstate" , "tt" , "tick" , "tba" , "pstate" , "tl" , |
2304 | "pil" , "cwp" , "cansave" , "canrestore" , "cleanwin" , "otherwin" , |
2305 | "wstate" , "fq" , "gl" |
2306 | /* "ver" - special cased */ |
2307 | }; |
2308 | |
2309 | /* These are ordered according to there register number in |
2310 | rdhpr and wrhpr insns. */ |
2311 | static const char * const v9_hpriv_reg_names[] = |
2312 | { |
2313 | "hpstate" , "htstate" , "resv2" , "hintp" , "resv4" , "htba" , "hver" , |
2314 | "resv7" , "resv8" , "resv9" , "resv10" , "resv11" , "resv12" , "resv13" , |
2315 | "resv14" , "resv15" , "resv16" , "resv17" , "resv18" , "resv19" , "resv20" , |
2316 | "resv21" , "resv22" , "resv23" , "resv24" , "resv25" , "resv26" , "resv27" , |
2317 | "resv28" , "resv29" , "resv30" , "hstick_cmpr" |
2318 | }; |
2319 | |
2320 | /* These are ordered according to there register number in |
2321 | rd and wr insns (-16). */ |
2322 | static const char * const v9a_asr_reg_names[] = |
2323 | { |
2324 | "pcr" , "pic" , "dcr" , "gsr" , "set_softint" , "clear_softint" , |
2325 | "softint" , "tick_cmpr" , "sys_tick" , "sys_tick_cmpr" |
2326 | }; |
2327 | |
2328 | /* Macros used to extract instruction fields. Not all fields have |
2329 | macros defined here, only those which are actually used. */ |
2330 | |
2331 | #define X_RD(i) (((i) >> 25) & 0x1f) |
2332 | #define X_RS1(i) (((i) >> 14) & 0x1f) |
2333 | #define X_LDST_I(i) (((i) >> 13) & 1) |
2334 | #define X_ASI(i) (((i) >> 5) & 0xff) |
2335 | #define X_RS2(i) (((i) >> 0) & 0x1f) |
2336 | #define X_IMM(i,n) (((i) >> 0) & ((1 << (n)) - 1)) |
2337 | #define X_SIMM(i,n) SEX (X_IMM ((i), (n)), (n)) |
2338 | #define X_DISP22(i) (((i) >> 0) & 0x3fffff) |
2339 | #define X_IMM22(i) X_DISP22 (i) |
2340 | #define X_DISP30(i) (((i) >> 0) & 0x3fffffff) |
2341 | |
2342 | /* These are for v9. */ |
2343 | #define X_DISP16(i) (((((i) >> 20) & 3) << 14) | (((i) >> 0) & 0x3fff)) |
2344 | #define X_DISP19(i) (((i) >> 0) & 0x7ffff) |
2345 | #define X_MEMBAR(i) ((i) & 0x7f) |
2346 | |
2347 | /* Here is the union which was used to extract instruction fields |
2348 | before the shift and mask macros were written. |
2349 | |
2350 | union sparc_insn |
2351 | { |
2352 | unsigned long int code; |
2353 | struct |
2354 | { |
2355 | unsigned int anop:2; |
2356 | #define op ldst.anop |
2357 | unsigned int anrd:5; |
2358 | #define rd ldst.anrd |
2359 | unsigned int op3:6; |
2360 | unsigned int anrs1:5; |
2361 | #define rs1 ldst.anrs1 |
2362 | unsigned int i:1; |
2363 | unsigned int anasi:8; |
2364 | #define asi ldst.anasi |
2365 | unsigned int anrs2:5; |
2366 | #define rs2 ldst.anrs2 |
2367 | #define shcnt rs2 |
2368 | } ldst; |
2369 | struct |
2370 | { |
2371 | unsigned int anop:2, anrd:5, op3:6, anrs1:5, i:1; |
2372 | unsigned int IMM13:13; |
2373 | #define imm13 IMM13.IMM13 |
2374 | } IMM13; |
2375 | struct |
2376 | { |
2377 | unsigned int anop:2; |
2378 | unsigned int a:1; |
2379 | unsigned int cond:4; |
2380 | unsigned int op2:3; |
2381 | unsigned int DISP22:22; |
2382 | #define disp22 branch.DISP22 |
2383 | #define imm22 disp22 |
2384 | } branch; |
2385 | struct |
2386 | { |
2387 | unsigned int anop:2; |
2388 | unsigned int a:1; |
2389 | unsigned int z:1; |
2390 | unsigned int rcond:3; |
2391 | unsigned int op2:3; |
2392 | unsigned int DISP16HI:2; |
2393 | unsigned int p:1; |
2394 | unsigned int _rs1:5; |
2395 | unsigned int DISP16LO:14; |
2396 | } branch16; |
2397 | struct |
2398 | { |
2399 | unsigned int anop:2; |
2400 | unsigned int adisp30:30; |
2401 | #define disp30 call.adisp30 |
2402 | } call; |
2403 | }; */ |
2404 | |
2405 | /* Nonzero if INSN is the opcode for a delayed branch. */ |
2406 | |
2407 | static int |
2408 | is_delayed_branch (unsigned long insn) |
2409 | { |
2410 | sparc_opcode_hash *op; |
2411 | |
2412 | for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next) |
2413 | { |
2414 | const sparc_opcode *opcode = op->opcode; |
2415 | |
2416 | if ((opcode->match & insn) == opcode->match |
2417 | && (opcode->lose & insn) == 0) |
2418 | return opcode->flags & F_DELAYED; |
2419 | } |
2420 | return 0; |
2421 | } |
2422 | |
2423 | /* extern void qsort (); */ |
2424 | |
2425 | /* Records current mask of SPARC_OPCODE_ARCH_FOO values, used to pass value |
2426 | to compare_opcodes. */ |
2427 | static unsigned int current_arch_mask; |
2428 | |
2429 | /* Given BFD mach number, return a mask of SPARC_OPCODE_ARCH_FOO values. */ |
2430 | |
2431 | static int |
2432 | compute_arch_mask (unsigned long mach) |
2433 | { |
2434 | switch (mach) |
2435 | { |
2436 | case 0 : |
2437 | case bfd_mach_sparc : |
2438 | return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8); |
2439 | case bfd_mach_sparc_sparclet : |
2440 | return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET); |
2441 | case bfd_mach_sparc_sparclite : |
2442 | case bfd_mach_sparc_sparclite_le : |
2443 | /* sparclites insns are recognized by default (because that's how |
2444 | they've always been treated, for better or worse). Kludge this by |
2445 | indicating generic v8 is also selected. */ |
2446 | return (SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE) |
2447 | | SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8)); |
2448 | case bfd_mach_sparc_v8plus : |
2449 | case bfd_mach_sparc_v9 : |
2450 | return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9); |
2451 | case bfd_mach_sparc_v8plusa : |
2452 | case bfd_mach_sparc_v9a : |
2453 | return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A); |
2454 | case bfd_mach_sparc_v8plusb : |
2455 | case bfd_mach_sparc_v9b : |
2456 | return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B); |
2457 | } |
2458 | abort (); |
2459 | } |
2460 | |
2461 | /* Compare opcodes A and B. */ |
2462 | |
2463 | static int |
2464 | compare_opcodes (const void * a, const void * b) |
2465 | { |
2466 | sparc_opcode *op0 = * (sparc_opcode **) a; |
2467 | sparc_opcode *op1 = * (sparc_opcode **) b; |
2468 | unsigned long int match0 = op0->match, match1 = op1->match; |
2469 | unsigned long int lose0 = op0->lose, lose1 = op1->lose; |
2470 | register unsigned int i; |
2471 | |
2472 | /* If one (and only one) insn isn't supported by the current architecture, |
2473 | prefer the one that is. If neither are supported, but they're both for |
2474 | the same architecture, continue processing. Otherwise (both unsupported |
2475 | and for different architectures), prefer lower numbered arch's (fudged |
2476 | by comparing the bitmasks). */ |
2477 | if (op0->architecture & current_arch_mask) |
2478 | { |
2479 | if (! (op1->architecture & current_arch_mask)) |
2480 | return -1; |
2481 | } |
2482 | else |
2483 | { |
2484 | if (op1->architecture & current_arch_mask) |
2485 | return 1; |
2486 | else if (op0->architecture != op1->architecture) |
2487 | return op0->architecture - op1->architecture; |
2488 | } |
2489 | |
2490 | /* If a bit is set in both match and lose, there is something |
2491 | wrong with the opcode table. */ |
2492 | if (match0 & lose0) |
2493 | { |
2494 | fprintf |
2495 | (stderr, |
2496 | /* xgettext:c-format */ |
2497 | "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" , |
2498 | op0->name, match0, lose0); |
2499 | op0->lose &= ~op0->match; |
2500 | lose0 = op0->lose; |
2501 | } |
2502 | |
2503 | if (match1 & lose1) |
2504 | { |
2505 | fprintf |
2506 | (stderr, |
2507 | /* xgettext:c-format */ |
2508 | "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" , |
2509 | op1->name, match1, lose1); |
2510 | op1->lose &= ~op1->match; |
2511 | lose1 = op1->lose; |
2512 | } |
2513 | |
2514 | /* Because the bits that are variable in one opcode are constant in |
2515 | another, it is important to order the opcodes in the right order. */ |
2516 | for (i = 0; i < 32; ++i) |
2517 | { |
2518 | unsigned long int x = 1 << i; |
2519 | int x0 = (match0 & x) != 0; |
2520 | int x1 = (match1 & x) != 0; |
2521 | |
2522 | if (x0 != x1) |
2523 | return x1 - x0; |
2524 | } |
2525 | |
2526 | for (i = 0; i < 32; ++i) |
2527 | { |
2528 | unsigned long int x = 1 << i; |
2529 | int x0 = (lose0 & x) != 0; |
2530 | int x1 = (lose1 & x) != 0; |
2531 | |
2532 | if (x0 != x1) |
2533 | return x1 - x0; |
2534 | } |
2535 | |
2536 | /* They are functionally equal. So as long as the opcode table is |
2537 | valid, we can put whichever one first we want, on aesthetic grounds. */ |
2538 | |
2539 | /* Our first aesthetic ground is that aliases defer to real insns. */ |
2540 | { |
2541 | int alias_diff = (op0->flags & F_ALIAS) - (op1->flags & F_ALIAS); |
2542 | |
2543 | if (alias_diff != 0) |
2544 | /* Put the one that isn't an alias first. */ |
2545 | return alias_diff; |
2546 | } |
2547 | |
2548 | /* Except for aliases, two "identical" instructions had |
2549 | better have the same opcode. This is a sanity check on the table. */ |
2550 | i = strcmp (op0->name, op1->name); |
2551 | if (i) |
2552 | { |
2553 | if (op0->flags & F_ALIAS) /* If they're both aliases, be arbitrary. */ |
2554 | return i; |
2555 | else |
2556 | fprintf (stderr, |
2557 | /* xgettext:c-format */ |
2558 | "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n" , |
2559 | op0->name, op1->name); |
2560 | } |
2561 | |
2562 | /* Fewer arguments are preferred. */ |
2563 | { |
2564 | int length_diff = strlen (op0->args) - strlen (op1->args); |
2565 | |
2566 | if (length_diff != 0) |
2567 | /* Put the one with fewer arguments first. */ |
2568 | return length_diff; |
2569 | } |
2570 | |
2571 | /* Put 1+i before i+1. */ |
2572 | { |
2573 | char *p0 = (char *) strchr (op0->args, '+'); |
2574 | char *p1 = (char *) strchr (op1->args, '+'); |
2575 | |
2576 | if (p0 && p1) |
2577 | { |
2578 | /* There is a plus in both operands. Note that a plus |
2579 | sign cannot be the first character in args, |
2580 | so the following [-1]'s are valid. */ |
2581 | if (p0[-1] == 'i' && p1[1] == 'i') |
2582 | /* op0 is i+1 and op1 is 1+i, so op1 goes first. */ |
2583 | return 1; |
2584 | if (p0[1] == 'i' && p1[-1] == 'i') |
2585 | /* op0 is 1+i and op1 is i+1, so op0 goes first. */ |
2586 | return -1; |
2587 | } |
2588 | } |
2589 | |
2590 | /* Put 1,i before i,1. */ |
2591 | { |
2592 | int i0 = strncmp (op0->args, "i,1" , 3) == 0; |
2593 | int i1 = strncmp (op1->args, "i,1" , 3) == 0; |
2594 | |
2595 | if (i0 ^ i1) |
2596 | return i0 - i1; |
2597 | } |
2598 | |
2599 | /* They are, as far as we can tell, identical. |
2600 | Since qsort may have rearranged the table partially, there is |
2601 | no way to tell which one was first in the opcode table as |
2602 | written, so just say there are equal. */ |
2603 | /* ??? This is no longer true now that we sort a vector of pointers, |
2604 | not the table itself. */ |
2605 | return 0; |
2606 | } |
2607 | |
2608 | /* Build a hash table from the opcode table. |
2609 | OPCODE_TABLE is a sorted list of pointers into the opcode table. */ |
2610 | |
2611 | static void |
2612 | build_hash_table (const sparc_opcode **opcode_table, |
2613 | sparc_opcode_hash **hash_table, |
2614 | int num_opcodes) |
2615 | { |
2616 | int i; |
2617 | int hash_count[HASH_SIZE]; |
2618 | static sparc_opcode_hash *hash_buf = NULL; |
2619 | |
2620 | /* Start at the end of the table and work backwards so that each |
2621 | chain is sorted. */ |
2622 | |
2623 | memset (hash_table, 0, HASH_SIZE * sizeof (hash_table[0])); |
2624 | memset (hash_count, 0, HASH_SIZE * sizeof (hash_count[0])); |
2625 | free(hash_buf); |
2626 | hash_buf = malloc (sizeof (* hash_buf) * num_opcodes); |
2627 | for (i = num_opcodes - 1; i >= 0; --i) |
2628 | { |
2629 | int hash = HASH_INSN (opcode_table[i]->match); |
2630 | sparc_opcode_hash *h = &hash_buf[i]; |
2631 | |
2632 | h->next = hash_table[hash]; |
2633 | h->opcode = opcode_table[i]; |
2634 | hash_table[hash] = h; |
2635 | ++hash_count[hash]; |
2636 | } |
2637 | |
2638 | #if 0 /* for debugging */ |
2639 | { |
2640 | int min_count = num_opcodes, max_count = 0; |
2641 | int total; |
2642 | |
2643 | for (i = 0; i < HASH_SIZE; ++i) |
2644 | { |
2645 | if (hash_count[i] < min_count) |
2646 | min_count = hash_count[i]; |
2647 | if (hash_count[i] > max_count) |
2648 | max_count = hash_count[i]; |
2649 | total += hash_count[i]; |
2650 | } |
2651 | |
2652 | printf ("Opcode hash table stats: min %d, max %d, ave %f\n" , |
2653 | min_count, max_count, (double) total / HASH_SIZE); |
2654 | } |
2655 | #endif |
2656 | } |
2657 | |
2658 | /* Print one instruction from MEMADDR on INFO->STREAM. |
2659 | |
2660 | We suffix the instruction with a comment that gives the absolute |
2661 | address involved, as well as its symbolic form, if the instruction |
2662 | is preceded by a findable `sethi' and it either adds an immediate |
2663 | displacement to that register, or it is an `add' or `or' instruction |
2664 | on that register. */ |
2665 | |
2666 | int |
2667 | print_insn_sparc (bfd_vma memaddr, disassemble_info *info) |
2668 | { |
2669 | FILE *stream = info->stream; |
2670 | bfd_byte buffer[4]; |
2671 | unsigned long insn; |
2672 | sparc_opcode_hash *op; |
2673 | /* Nonzero of opcode table has been initialized. */ |
2674 | static int opcodes_initialized = 0; |
2675 | /* bfd mach number of last call. */ |
2676 | static unsigned long current_mach = 0; |
2677 | bfd_vma (*getword) (const unsigned char *); |
2678 | |
2679 | if (!opcodes_initialized |
2680 | || info->mach != current_mach) |
2681 | { |
2682 | int i; |
2683 | |
2684 | current_arch_mask = compute_arch_mask (info->mach); |
2685 | |
2686 | if (!opcodes_initialized) |
2687 | sorted_opcodes = |
2688 | malloc (sparc_num_opcodes * sizeof (sparc_opcode *)); |
2689 | /* Reset the sorted table so we can resort it. */ |
2690 | for (i = 0; i < sparc_num_opcodes; ++i) |
2691 | sorted_opcodes[i] = &sparc_opcodes[i]; |
2692 | qsort ((char *) sorted_opcodes, sparc_num_opcodes, |
2693 | sizeof (sorted_opcodes[0]), compare_opcodes); |
2694 | |
2695 | build_hash_table (sorted_opcodes, opcode_hash_table, sparc_num_opcodes); |
2696 | current_mach = info->mach; |
2697 | opcodes_initialized = 1; |
2698 | } |
2699 | |
2700 | { |
2701 | int status = |
2702 | (*info->read_memory_func) (memaddr, buffer, sizeof (buffer), info); |
2703 | |
2704 | if (status != 0) |
2705 | { |
2706 | (*info->memory_error_func) (status, memaddr, info); |
2707 | return -1; |
2708 | } |
2709 | } |
2710 | |
2711 | /* On SPARClite variants such as DANlite (sparc86x), instructions |
2712 | are always big-endian even when the machine is in little-endian mode. */ |
2713 | if (info->endian == BFD_ENDIAN_BIG || info->mach == bfd_mach_sparc_sparclite) |
2714 | getword = bfd_getb32; |
2715 | else |
2716 | getword = bfd_getl32; |
2717 | |
2718 | insn = getword (buffer); |
2719 | |
2720 | info->insn_info_valid = 1; /* We do return this info. */ |
2721 | info->insn_type = dis_nonbranch; /* Assume non branch insn. */ |
2722 | info->branch_delay_insns = 0; /* Assume no delay. */ |
2723 | info->target = 0; /* Assume no target known. */ |
2724 | |
2725 | for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next) |
2726 | { |
2727 | const sparc_opcode *opcode = op->opcode; |
2728 | |
2729 | /* If the insn isn't supported by the current architecture, skip it. */ |
2730 | if (! (opcode->architecture & current_arch_mask)) |
2731 | continue; |
2732 | |
2733 | if ((opcode->match & insn) == opcode->match |
2734 | && (opcode->lose & insn) == 0) |
2735 | { |
2736 | /* Nonzero means that we have found an instruction which has |
2737 | the effect of adding or or'ing the imm13 field to rs1. */ |
2738 | int imm_added_to_rs1 = 0; |
2739 | int imm_ored_to_rs1 = 0; |
2740 | |
2741 | /* Nonzero means that we have found a plus sign in the args |
2742 | field of the opcode table. */ |
2743 | int found_plus = 0; |
2744 | |
2745 | /* Nonzero means we have an annulled branch. */ |
2746 | /* int is_annulled = 0; */ /* see FIXME below */ |
2747 | |
2748 | /* Do we have an `add' or `or' instruction combining an |
2749 | immediate with rs1? */ |
2750 | if (opcode->match == 0x80102000) /* or */ |
2751 | imm_ored_to_rs1 = 1; |
2752 | if (opcode->match == 0x80002000) /* add */ |
2753 | imm_added_to_rs1 = 1; |
2754 | |
2755 | if (X_RS1 (insn) != X_RD (insn) |
2756 | && strchr (opcode->args, 'r') != NULL) |
2757 | /* Can't do simple format if source and dest are different. */ |
2758 | continue; |
2759 | if (X_RS2 (insn) != X_RD (insn) |
2760 | && strchr (opcode->args, 'O') != NULL) |
2761 | /* Can't do simple format if source and dest are different. */ |
2762 | continue; |
2763 | |
2764 | (*info->fprintf_func) (stream, "%s" , opcode->name); |
2765 | |
2766 | { |
2767 | const char *s; |
2768 | |
2769 | if (opcode->args[0] != ',') |
2770 | (*info->fprintf_func) (stream, " " ); |
2771 | |
2772 | for (s = opcode->args; *s != '\0'; ++s) |
2773 | { |
2774 | while (*s == ',') |
2775 | { |
2776 | (*info->fprintf_func) (stream, "," ); |
2777 | ++s; |
2778 | switch (*s) |
2779 | { |
2780 | case 'a': |
2781 | (*info->fprintf_func) (stream, "a" ); |
2782 | /* is_annulled = 1; */ /* see FIXME below */ |
2783 | ++s; |
2784 | continue; |
2785 | case 'N': |
2786 | (*info->fprintf_func) (stream, "pn" ); |
2787 | ++s; |
2788 | continue; |
2789 | |
2790 | case 'T': |
2791 | (*info->fprintf_func) (stream, "pt" ); |
2792 | ++s; |
2793 | continue; |
2794 | |
2795 | default: |
2796 | break; |
2797 | } |
2798 | } |
2799 | |
2800 | (*info->fprintf_func) (stream, " " ); |
2801 | |
2802 | switch (*s) |
2803 | { |
2804 | case '+': |
2805 | found_plus = 1; |
2806 | /* Fall through. */ |
2807 | |
2808 | default: |
2809 | (*info->fprintf_func) (stream, "%c" , *s); |
2810 | break; |
2811 | |
2812 | case '#': |
2813 | (*info->fprintf_func) (stream, "0" ); |
2814 | break; |
2815 | |
2816 | #define reg(n) (*info->fprintf_func) (stream, "%%%s", reg_names[n]) |
2817 | case '1': |
2818 | case 'r': |
2819 | reg (X_RS1 (insn)); |
2820 | break; |
2821 | |
2822 | case '2': |
2823 | case 'O': |
2824 | reg (X_RS2 (insn)); |
2825 | break; |
2826 | |
2827 | case 'd': |
2828 | reg (X_RD (insn)); |
2829 | break; |
2830 | #undef reg |
2831 | |
2832 | #define freg(n) (*info->fprintf_func) (stream, "%%%s", freg_names[n]) |
2833 | #define fregx(n) (*info->fprintf_func) (stream, "%%%s", freg_names[((n) & ~1) | (((n) & 1) << 5)]) |
2834 | case 'e': |
2835 | freg (X_RS1 (insn)); |
2836 | break; |
2837 | case 'v': /* Double/even. */ |
2838 | case 'V': /* Quad/multiple of 4. */ |
2839 | fregx (X_RS1 (insn)); |
2840 | break; |
2841 | |
2842 | case 'f': |
2843 | freg (X_RS2 (insn)); |
2844 | break; |
2845 | case 'B': /* Double/even. */ |
2846 | case 'R': /* Quad/multiple of 4. */ |
2847 | fregx (X_RS2 (insn)); |
2848 | break; |
2849 | |
2850 | case 'g': |
2851 | freg (X_RD (insn)); |
2852 | break; |
2853 | case 'H': /* Double/even. */ |
2854 | case 'J': /* Quad/multiple of 4. */ |
2855 | fregx (X_RD (insn)); |
2856 | break; |
2857 | #undef freg |
2858 | #undef fregx |
2859 | |
2860 | #define creg(n) (*info->fprintf_func) (stream, "%%c%u", (unsigned int) (n)) |
2861 | case 'b': |
2862 | creg (X_RS1 (insn)); |
2863 | break; |
2864 | |
2865 | case 'c': |
2866 | creg (X_RS2 (insn)); |
2867 | break; |
2868 | |
2869 | case 'D': |
2870 | creg (X_RD (insn)); |
2871 | break; |
2872 | #undef creg |
2873 | |
2874 | case 'h': |
2875 | (*info->fprintf_func) (stream, "%%hi(%#x)" , |
2876 | ((unsigned) 0xFFFFFFFF |
2877 | & ((int) X_IMM22 (insn) << 10))); |
2878 | break; |
2879 | |
2880 | case 'i': /* 13 bit immediate. */ |
2881 | case 'I': /* 11 bit immediate. */ |
2882 | case 'j': /* 10 bit immediate. */ |
2883 | { |
2884 | int imm; |
2885 | |
2886 | if (*s == 'i') |
2887 | imm = X_SIMM (insn, 13); |
2888 | else if (*s == 'I') |
2889 | imm = X_SIMM (insn, 11); |
2890 | else |
2891 | imm = X_SIMM (insn, 10); |
2892 | |
2893 | /* Check to see whether we have a 1+i, and take |
2894 | note of that fact. |
2895 | |
2896 | Note: because of the way we sort the table, |
2897 | we will be matching 1+i rather than i+1, |
2898 | so it is OK to assume that i is after +, |
2899 | not before it. */ |
2900 | if (found_plus) |
2901 | imm_added_to_rs1 = 1; |
2902 | |
2903 | if (imm <= 9) |
2904 | (*info->fprintf_func) (stream, "%d" , imm); |
2905 | else |
2906 | (*info->fprintf_func) (stream, "%#x" , imm); |
2907 | } |
2908 | break; |
2909 | |
2910 | case 'X': /* 5 bit unsigned immediate. */ |
2911 | case 'Y': /* 6 bit unsigned immediate. */ |
2912 | { |
2913 | int imm = X_IMM (insn, *s == 'X' ? 5 : 6); |
2914 | |
2915 | if (imm <= 9) |
2916 | (info->fprintf_func) (stream, "%d" , imm); |
2917 | else |
2918 | (info->fprintf_func) (stream, "%#x" , (unsigned) imm); |
2919 | } |
2920 | break; |
2921 | |
2922 | case '3': |
2923 | (info->fprintf_func) (stream, "%ld" , X_IMM (insn, 3)); |
2924 | break; |
2925 | |
2926 | case 'K': |
2927 | { |
2928 | int mask = X_MEMBAR (insn); |
2929 | int bit = 0x40, printed_one = 0; |
2930 | const char *name; |
2931 | |
2932 | if (mask == 0) |
2933 | (info->fprintf_func) (stream, "0" ); |
2934 | else |
2935 | while (bit) |
2936 | { |
2937 | if (mask & bit) |
2938 | { |
2939 | if (printed_one) |
2940 | (info->fprintf_func) (stream, "|" ); |
2941 | name = sparc_decode_membar (bit); |
2942 | (info->fprintf_func) (stream, "%s" , name); |
2943 | printed_one = 1; |
2944 | } |
2945 | bit >>= 1; |
2946 | } |
2947 | break; |
2948 | } |
2949 | |
2950 | case 'k': |
2951 | info->target = memaddr + SEX (X_DISP16 (insn), 16) * 4; |
2952 | (*info->print_address_func) (info->target, info); |
2953 | break; |
2954 | |
2955 | case 'G': |
2956 | info->target = memaddr + SEX (X_DISP19 (insn), 19) * 4; |
2957 | (*info->print_address_func) (info->target, info); |
2958 | break; |
2959 | |
2960 | case '6': |
2961 | case '7': |
2962 | case '8': |
2963 | case '9': |
2964 | (*info->fprintf_func) (stream, "%%fcc%c" , *s - '6' + '0'); |
2965 | break; |
2966 | |
2967 | case 'z': |
2968 | (*info->fprintf_func) (stream, "%%icc" ); |
2969 | break; |
2970 | |
2971 | case 'Z': |
2972 | (*info->fprintf_func) (stream, "%%xcc" ); |
2973 | break; |
2974 | |
2975 | case 'E': |
2976 | (*info->fprintf_func) (stream, "%%ccr" ); |
2977 | break; |
2978 | |
2979 | case 's': |
2980 | (*info->fprintf_func) (stream, "%%fprs" ); |
2981 | break; |
2982 | |
2983 | case 'o': |
2984 | (*info->fprintf_func) (stream, "%%asi" ); |
2985 | break; |
2986 | |
2987 | case 'W': |
2988 | (*info->fprintf_func) (stream, "%%tick" ); |
2989 | break; |
2990 | |
2991 | case 'P': |
2992 | (*info->fprintf_func) (stream, "%%pc" ); |
2993 | break; |
2994 | |
2995 | case '?': |
2996 | if (X_RS1 (insn) == 31) |
2997 | (*info->fprintf_func) (stream, "%%ver" ); |
2998 | else if ((unsigned) X_RS1 (insn) < 17) |
2999 | (*info->fprintf_func) (stream, "%%%s" , |
3000 | v9_priv_reg_names[X_RS1 (insn)]); |
3001 | else |
3002 | (*info->fprintf_func) (stream, "%%reserved" ); |
3003 | break; |
3004 | |
3005 | case '!': |
3006 | if ((unsigned) X_RD (insn) < 17) |
3007 | (*info->fprintf_func) (stream, "%%%s" , |
3008 | v9_priv_reg_names[X_RD (insn)]); |
3009 | else |
3010 | (*info->fprintf_func) (stream, "%%reserved" ); |
3011 | break; |
3012 | |
3013 | case '$': |
3014 | if ((unsigned) X_RS1 (insn) < 32) |
3015 | (*info->fprintf_func) (stream, "%%%s" , |
3016 | v9_hpriv_reg_names[X_RS1 (insn)]); |
3017 | else |
3018 | (*info->fprintf_func) (stream, "%%reserved" ); |
3019 | break; |
3020 | |
3021 | case '%': |
3022 | if ((unsigned) X_RD (insn) < 32) |
3023 | (*info->fprintf_func) (stream, "%%%s" , |
3024 | v9_hpriv_reg_names[X_RD (insn)]); |
3025 | else |
3026 | (*info->fprintf_func) (stream, "%%reserved" ); |
3027 | break; |
3028 | |
3029 | case '/': |
3030 | if (X_RS1 (insn) < 16 || X_RS1 (insn) > 25) |
3031 | (*info->fprintf_func) (stream, "%%reserved" ); |
3032 | else |
3033 | (*info->fprintf_func) (stream, "%%%s" , |
3034 | v9a_asr_reg_names[X_RS1 (insn)-16]); |
3035 | break; |
3036 | |
3037 | case '_': |
3038 | if (X_RD (insn) < 16 || X_RD (insn) > 25) |
3039 | (*info->fprintf_func) (stream, "%%reserved" ); |
3040 | else |
3041 | (*info->fprintf_func) (stream, "%%%s" , |
3042 | v9a_asr_reg_names[X_RD (insn)-16]); |
3043 | break; |
3044 | |
3045 | case '*': |
3046 | { |
3047 | const char *name = sparc_decode_prefetch (X_RD (insn)); |
3048 | |
3049 | if (name) |
3050 | (*info->fprintf_func) (stream, "%s" , name); |
3051 | else |
3052 | (*info->fprintf_func) (stream, "%ld" , X_RD (insn)); |
3053 | break; |
3054 | } |
3055 | |
3056 | case 'M': |
3057 | (*info->fprintf_func) (stream, "%%asr%ld" , X_RS1 (insn)); |
3058 | break; |
3059 | |
3060 | case 'm': |
3061 | (*info->fprintf_func) (stream, "%%asr%ld" , X_RD (insn)); |
3062 | break; |
3063 | |
3064 | case 'L': |
3065 | info->target = memaddr + SEX (X_DISP30 (insn), 30) * 4; |
3066 | (*info->print_address_func) (info->target, info); |
3067 | break; |
3068 | |
3069 | case 'n': |
3070 | (*info->fprintf_func) |
3071 | (stream, "%#x" , SEX (X_DISP22 (insn), 22)); |
3072 | break; |
3073 | |
3074 | case 'l': |
3075 | info->target = memaddr + SEX (X_DISP22 (insn), 22) * 4; |
3076 | (*info->print_address_func) (info->target, info); |
3077 | break; |
3078 | |
3079 | case 'A': |
3080 | { |
3081 | const char *name; |
3082 | |
3083 | if ((info->mach == bfd_mach_sparc_v8plusa) || |
3084 | ((info->mach >= bfd_mach_sparc_v9) && |
3085 | (info->mach <= bfd_mach_sparc_v9b))) |
3086 | name = sparc_decode_asi_v9 (X_ASI (insn)); |
3087 | else |
3088 | name = sparc_decode_asi_v8 (X_ASI (insn)); |
3089 | |
3090 | if (name) |
3091 | (*info->fprintf_func) (stream, "%s" , name); |
3092 | else |
3093 | (*info->fprintf_func) (stream, "(%ld)" , X_ASI (insn)); |
3094 | break; |
3095 | } |
3096 | |
3097 | case 'C': |
3098 | (*info->fprintf_func) (stream, "%%csr" ); |
3099 | break; |
3100 | |
3101 | case 'F': |
3102 | (*info->fprintf_func) (stream, "%%fsr" ); |
3103 | break; |
3104 | |
3105 | case 'p': |
3106 | (*info->fprintf_func) (stream, "%%psr" ); |
3107 | break; |
3108 | |
3109 | case 'q': |
3110 | (*info->fprintf_func) (stream, "%%fq" ); |
3111 | break; |
3112 | |
3113 | case 'Q': |
3114 | (*info->fprintf_func) (stream, "%%cq" ); |
3115 | break; |
3116 | |
3117 | case 't': |
3118 | (*info->fprintf_func) (stream, "%%tbr" ); |
3119 | break; |
3120 | |
3121 | case 'w': |
3122 | (*info->fprintf_func) (stream, "%%wim" ); |
3123 | break; |
3124 | |
3125 | case 'x': |
3126 | (*info->fprintf_func) (stream, "%ld" , |
3127 | ((X_LDST_I (insn) << 8) |
3128 | + X_ASI (insn))); |
3129 | break; |
3130 | |
3131 | case 'y': |
3132 | (*info->fprintf_func) (stream, "%%y" ); |
3133 | break; |
3134 | |
3135 | case 'u': |
3136 | case 'U': |
3137 | { |
3138 | int val = *s == 'U' ? X_RS1 (insn) : X_RD (insn); |
3139 | const char *name = sparc_decode_sparclet_cpreg (val); |
3140 | |
3141 | if (name) |
3142 | (*info->fprintf_func) (stream, "%s" , name); |
3143 | else |
3144 | (*info->fprintf_func) (stream, "%%cpreg(%d)" , val); |
3145 | break; |
3146 | } |
3147 | } |
3148 | } |
3149 | } |
3150 | |
3151 | /* If we are adding or or'ing something to rs1, then |
3152 | check to see whether the previous instruction was |
3153 | a sethi to the same register as in the sethi. |
3154 | If so, attempt to print the result of the add or |
3155 | or (in this context add and or do the same thing) |
3156 | and its symbolic value. */ |
3157 | if (imm_ored_to_rs1 || imm_added_to_rs1) |
3158 | { |
3159 | unsigned long prev_insn; |
3160 | int errcode; |
3161 | |
3162 | if (memaddr >= 4) |
3163 | errcode = |
3164 | (*info->read_memory_func) |
3165 | (memaddr - 4, buffer, sizeof (buffer), info); |
3166 | else |
3167 | errcode = 1; |
3168 | |
3169 | prev_insn = getword (buffer); |
3170 | |
3171 | if (errcode == 0) |
3172 | { |
3173 | /* If it is a delayed branch, we need to look at the |
3174 | instruction before the delayed branch. This handles |
3175 | sequences such as: |
3176 | |
3177 | sethi %o1, %hi(_foo), %o1 |
3178 | call _printf |
3179 | or %o1, %lo(_foo), %o1 */ |
3180 | |
3181 | if (is_delayed_branch (prev_insn)) |
3182 | { |
3183 | if (memaddr >= 8) |
3184 | errcode = (*info->read_memory_func) |
3185 | (memaddr - 8, buffer, sizeof (buffer), info); |
3186 | else |
3187 | errcode = 1; |
3188 | |
3189 | prev_insn = getword (buffer); |
3190 | } |
3191 | } |
3192 | |
3193 | /* If there was a problem reading memory, then assume |
3194 | the previous instruction was not sethi. */ |
3195 | if (errcode == 0) |
3196 | { |
3197 | /* Is it sethi to the same register? */ |
3198 | if ((prev_insn & 0xc1c00000) == 0x01000000 |
3199 | && X_RD (prev_insn) == X_RS1 (insn)) |
3200 | { |
3201 | (*info->fprintf_func) (stream, "\t! " ); |
3202 | info->target = |
3203 | ((unsigned) 0xFFFFFFFF |
3204 | & ((int) X_IMM22 (prev_insn) << 10)); |
3205 | if (imm_added_to_rs1) |
3206 | info->target += X_SIMM (insn, 13); |
3207 | else |
3208 | info->target |= X_SIMM (insn, 13); |
3209 | (*info->print_address_func) (info->target, info); |
3210 | info->insn_type = dis_dref; |
3211 | info->data_size = 4; /* FIXME!!! */ |
3212 | } |
3213 | } |
3214 | } |
3215 | |
3216 | if (opcode->flags & (F_UNBR|F_CONDBR|F_JSR)) |
3217 | { |
3218 | /* FIXME -- check is_annulled flag. */ |
3219 | if (opcode->flags & F_UNBR) |
3220 | info->insn_type = dis_branch; |
3221 | if (opcode->flags & F_CONDBR) |
3222 | info->insn_type = dis_condbranch; |
3223 | if (opcode->flags & F_JSR) |
3224 | info->insn_type = dis_jsr; |
3225 | if (opcode->flags & F_DELAYED) |
3226 | info->branch_delay_insns = 1; |
3227 | } |
3228 | |
3229 | return sizeof (buffer); |
3230 | } |
3231 | } |
3232 | |
3233 | info->insn_type = dis_noninsn; /* Mark as non-valid instruction. */ |
3234 | (*info->fprintf_func) (stream, ".long %#08lx" , insn); |
3235 | return sizeof (buffer); |
3236 | } |
3237 | |