| 1 | /* |
|---|---|
| 2 | * Arm PrimeCell PL041 Advanced Audio Codec Interface |
| 3 | * |
| 4 | * Copyright (c) 2011 |
| 5 | * Written by Mathieu Sonet - www.elasticsheep.com |
| 6 | * |
| 7 | * This code is licensed under the GPL. |
| 8 | * |
| 9 | * ***************************************************************** |
| 10 | */ |
| 11 | |
| 12 | /* PL041 register file description */ |
| 13 | |
| 14 | REGISTER( rxcr1, 0x00 ) |
| 15 | REGISTER( txcr1, 0x04 ) |
| 16 | REGISTER( sr1, 0x08 ) |
| 17 | REGISTER( isr1, 0x0C ) |
| 18 | REGISTER( ie1, 0x10 ) |
| 19 | REGISTER( rxcr2, 0x14 ) |
| 20 | REGISTER( txcr2, 0x18 ) |
| 21 | REGISTER( sr2, 0x1C ) |
| 22 | REGISTER( isr2, 0x20 ) |
| 23 | REGISTER( ie2, 0x24 ) |
| 24 | REGISTER( rxcr3, 0x28 ) |
| 25 | REGISTER( txcr3, 0x2C ) |
| 26 | REGISTER( sr3, 0x30 ) |
| 27 | REGISTER( isr3, 0x34 ) |
| 28 | REGISTER( ie3, 0x38 ) |
| 29 | REGISTER( rxcr4, 0x3C ) |
| 30 | REGISTER( txcr4, 0x40 ) |
| 31 | REGISTER( sr4, 0x44 ) |
| 32 | REGISTER( isr4, 0x48 ) |
| 33 | REGISTER( ie4, 0x4C ) |
| 34 | REGISTER( sl1rx, 0x50 ) |
| 35 | REGISTER( sl1tx, 0x54 ) |
| 36 | REGISTER( sl2rx, 0x58 ) |
| 37 | REGISTER( sl2tx, 0x5C ) |
| 38 | REGISTER( sl12rx, 0x60 ) |
| 39 | REGISTER( sl12tx, 0x64 ) |
| 40 | REGISTER( slfr, 0x68 ) |
| 41 | REGISTER( slistat, 0x6C ) |
| 42 | REGISTER( slien, 0x70 ) |
| 43 | REGISTER( intclr, 0x74 ) |
| 44 | REGISTER( maincr, 0x78 ) |
| 45 | REGISTER( reset, 0x7C ) |
| 46 | REGISTER( sync, 0x80 ) |
| 47 | REGISTER( allints, 0x84 ) |
| 48 | REGISTER( mainfr, 0x88 ) |
| 49 | REGISTER( unused, 0x8C ) |
| 50 | REGISTER( dr1_0, 0x90 ) |
| 51 | REGISTER( dr1_1, 0x94 ) |
| 52 | REGISTER( dr1_2, 0x98 ) |
| 53 | REGISTER( dr1_3, 0x9C ) |
| 54 | REGISTER( dr1_4, 0xA0 ) |
| 55 | REGISTER( dr1_5, 0xA4 ) |
| 56 | REGISTER( dr1_6, 0xA8 ) |
| 57 | REGISTER( dr1_7, 0xAC ) |
| 58 | REGISTER( dr2_0, 0xB0 ) |
| 59 | REGISTER( dr2_1, 0xB4 ) |
| 60 | REGISTER( dr2_2, 0xB8 ) |
| 61 | REGISTER( dr2_3, 0xBC ) |
| 62 | REGISTER( dr2_4, 0xC0 ) |
| 63 | REGISTER( dr2_5, 0xC4 ) |
| 64 | REGISTER( dr2_6, 0xC8 ) |
| 65 | REGISTER( dr2_7, 0xCC ) |
| 66 | REGISTER( dr3_0, 0xD0 ) |
| 67 | REGISTER( dr3_1, 0xD4 ) |
| 68 | REGISTER( dr3_2, 0xD8 ) |
| 69 | REGISTER( dr3_3, 0xDC ) |
| 70 | REGISTER( dr3_4, 0xE0 ) |
| 71 | REGISTER( dr3_5, 0xE4 ) |
| 72 | REGISTER( dr3_6, 0xE8 ) |
| 73 | REGISTER( dr3_7, 0xEC ) |
| 74 | REGISTER( dr4_0, 0xF0 ) |
| 75 | REGISTER( dr4_1, 0xF4 ) |
| 76 | REGISTER( dr4_2, 0xF8 ) |
| 77 | REGISTER( dr4_3, 0xFC ) |
| 78 | REGISTER( dr4_4, 0x100 ) |
| 79 | REGISTER( dr4_5, 0x104 ) |
| 80 | REGISTER( dr4_6, 0x108 ) |
| 81 | REGISTER( dr4_7, 0x10C ) |
| 82 |
Generated while processing qemu/hw/audio/pl041.c
Generated on 2019-Sep-06 from project qemu revision 4.1.50
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