1 | #include "qemu/osdep.h" |
2 | #include "qemu/units.h" |
3 | #include "hw/sh4/sh.h" |
4 | #include "hw/loader.h" |
5 | #include "sysemu/qtest.h" |
6 | #include "qemu/error-report.h" |
7 | |
8 | #define CE1 0x0100 |
9 | #define CE2 0x0200 |
10 | #define RE 0x0400 |
11 | #define WE 0x0800 |
12 | #define ALE 0x1000 |
13 | #define CLE 0x2000 |
14 | #define RDY1 0x4000 |
15 | #define RDY2 0x8000 |
16 | #define RDY(n) ((n) == 0 ? RDY1 : RDY2) |
17 | |
18 | typedef enum { WAIT, READ1, READ2, READ3 } state_t; |
19 | |
20 | typedef struct { |
21 | uint8_t *flash_contents; |
22 | state_t state; |
23 | uint32_t address; |
24 | uint8_t address_cycle; |
25 | } tc58128_dev; |
26 | |
27 | static tc58128_dev tc58128_devs[2]; |
28 | |
29 | #define FLASH_SIZE (16 * MiB) |
30 | |
31 | static void init_dev(tc58128_dev * dev, const char *filename) |
32 | { |
33 | int ret, blocks; |
34 | |
35 | dev->state = WAIT; |
36 | dev->flash_contents = g_malloc(FLASH_SIZE); |
37 | memset(dev->flash_contents, 0xff, FLASH_SIZE); |
38 | if (filename) { |
39 | /* Load flash image skipping the first block */ |
40 | ret = load_image_size(filename, dev->flash_contents + 528 * 32, |
41 | FLASH_SIZE - 528 * 32); |
42 | if (ret < 0) { |
43 | if (!qtest_enabled()) { |
44 | error_report("Could not load flash image %s" , filename); |
45 | exit(1); |
46 | } |
47 | } else { |
48 | /* Build first block with number of blocks */ |
49 | blocks = DIV_ROUND_UP(ret, 528 * 32); |
50 | dev->flash_contents[0] = blocks & 0xff; |
51 | dev->flash_contents[1] = (blocks >> 8) & 0xff; |
52 | dev->flash_contents[2] = (blocks >> 16) & 0xff; |
53 | dev->flash_contents[3] = (blocks >> 24) & 0xff; |
54 | fprintf(stderr, "loaded %d bytes for %s into flash\n" , ret, |
55 | filename); |
56 | } |
57 | } |
58 | } |
59 | |
60 | static void handle_command(tc58128_dev * dev, uint8_t command) |
61 | { |
62 | switch (command) { |
63 | case 0xff: |
64 | fprintf(stderr, "reset flash device\n" ); |
65 | dev->state = WAIT; |
66 | break; |
67 | case 0x00: |
68 | fprintf(stderr, "read mode 1\n" ); |
69 | dev->state = READ1; |
70 | dev->address_cycle = 0; |
71 | break; |
72 | case 0x01: |
73 | fprintf(stderr, "read mode 2\n" ); |
74 | dev->state = READ2; |
75 | dev->address_cycle = 0; |
76 | break; |
77 | case 0x50: |
78 | fprintf(stderr, "read mode 3\n" ); |
79 | dev->state = READ3; |
80 | dev->address_cycle = 0; |
81 | break; |
82 | default: |
83 | fprintf(stderr, "unknown flash command 0x%02x\n" , command); |
84 | abort(); |
85 | } |
86 | } |
87 | |
88 | static void handle_address(tc58128_dev * dev, uint8_t data) |
89 | { |
90 | switch (dev->state) { |
91 | case READ1: |
92 | case READ2: |
93 | case READ3: |
94 | switch (dev->address_cycle) { |
95 | case 0: |
96 | dev->address = data; |
97 | if (dev->state == READ2) |
98 | dev->address |= 0x100; |
99 | else if (dev->state == READ3) |
100 | dev->address |= 0x200; |
101 | break; |
102 | case 1: |
103 | dev->address += data * 528 * 0x100; |
104 | break; |
105 | case 2: |
106 | dev->address += data * 528; |
107 | fprintf(stderr, "address pointer in flash: 0x%08x\n" , |
108 | dev->address); |
109 | break; |
110 | default: |
111 | /* Invalid data */ |
112 | abort(); |
113 | } |
114 | dev->address_cycle++; |
115 | break; |
116 | default: |
117 | abort(); |
118 | } |
119 | } |
120 | |
121 | static uint8_t handle_read(tc58128_dev * dev) |
122 | { |
123 | #if 0 |
124 | if (dev->address % 0x100000 == 0) |
125 | fprintf(stderr, "reading flash at address 0x%08x\n" , dev->address); |
126 | #endif |
127 | return dev->flash_contents[dev->address++]; |
128 | } |
129 | |
130 | /* We never mark the device as busy, so interrupts cannot be triggered |
131 | XXXXX */ |
132 | |
133 | static int tc58128_cb(uint16_t porta, uint16_t portb, |
134 | uint16_t * periph_pdtra, uint16_t * periph_portadir, |
135 | uint16_t * periph_pdtrb, uint16_t * periph_portbdir) |
136 | { |
137 | int dev; |
138 | |
139 | if ((porta & CE1) == 0) |
140 | dev = 0; |
141 | else if ((porta & CE2) == 0) |
142 | dev = 1; |
143 | else |
144 | return 0; /* No device selected */ |
145 | |
146 | if ((porta & RE) && (porta & WE)) { |
147 | /* Nothing to do, assert ready and return to input state */ |
148 | *periph_portadir &= 0xff00; |
149 | *periph_portadir |= RDY(dev); |
150 | *periph_pdtra |= RDY(dev); |
151 | return 1; |
152 | } |
153 | |
154 | if (porta & CLE) { |
155 | /* Command */ |
156 | assert((porta & WE) == 0); |
157 | handle_command(&tc58128_devs[dev], porta & 0x00ff); |
158 | } else if (porta & ALE) { |
159 | assert((porta & WE) == 0); |
160 | handle_address(&tc58128_devs[dev], porta & 0x00ff); |
161 | } else if ((porta & RE) == 0) { |
162 | *periph_portadir |= 0x00ff; |
163 | *periph_pdtra &= 0xff00; |
164 | *periph_pdtra |= handle_read(&tc58128_devs[dev]); |
165 | } else { |
166 | abort(); |
167 | } |
168 | return 1; |
169 | } |
170 | |
171 | static sh7750_io_device tc58128 = { |
172 | RE | WE, /* Port A triggers */ |
173 | 0, /* Port B triggers */ |
174 | tc58128_cb /* Callback */ |
175 | }; |
176 | |
177 | int tc58128_init(struct SH7750State *s, const char *zone1, const char *zone2) |
178 | { |
179 | init_dev(&tc58128_devs[0], zone1); |
180 | init_dev(&tc58128_devs[1], zone2); |
181 | return sh7750_register_io_device(s, &tc58128); |
182 | } |
183 | |