1 | /* |
2 | * QEMU CPU model |
3 | * |
4 | * Copyright (c) 2012-2014 SUSE LINUX Products GmbH |
5 | * |
6 | * This program is free software; you can redistribute it and/or |
7 | * modify it under the terms of the GNU General Public License |
8 | * as published by the Free Software Foundation; either version 2 |
9 | * of the License, or (at your option) any later version. |
10 | * |
11 | * This program is distributed in the hope that it will be useful, |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
14 | * GNU General Public License for more details. |
15 | * |
16 | * You should have received a copy of the GNU General Public License |
17 | * along with this program; if not, see |
18 | * <http://www.gnu.org/licenses/gpl-2.0.html> |
19 | */ |
20 | |
21 | #include "qemu/osdep.h" |
22 | #include "qapi/error.h" |
23 | #include "hw/core/cpu.h" |
24 | #include "sysemu/hw_accel.h" |
25 | #include "qemu/notify.h" |
26 | #include "qemu/log.h" |
27 | #include "qemu/main-loop.h" |
28 | #include "exec/log.h" |
29 | #include "qemu/error-report.h" |
30 | #include "qemu/qemu-print.h" |
31 | #include "sysemu/tcg.h" |
32 | #include "hw/boards.h" |
33 | #include "hw/qdev-properties.h" |
34 | #include "trace-root.h" |
35 | |
36 | CPUInterruptHandler cpu_interrupt_handler; |
37 | |
38 | CPUState *cpu_by_arch_id(int64_t id) |
39 | { |
40 | CPUState *cpu; |
41 | |
42 | CPU_FOREACH(cpu) { |
43 | CPUClass *cc = CPU_GET_CLASS(cpu); |
44 | |
45 | if (cc->get_arch_id(cpu) == id) { |
46 | return cpu; |
47 | } |
48 | } |
49 | return NULL; |
50 | } |
51 | |
52 | bool cpu_exists(int64_t id) |
53 | { |
54 | return !!cpu_by_arch_id(id); |
55 | } |
56 | |
57 | CPUState *cpu_create(const char *typename) |
58 | { |
59 | Error *err = NULL; |
60 | CPUState *cpu = CPU(object_new(typename)); |
61 | object_property_set_bool(OBJECT(cpu), true, "realized" , &err); |
62 | if (err != NULL) { |
63 | error_report_err(err); |
64 | object_unref(OBJECT(cpu)); |
65 | exit(EXIT_FAILURE); |
66 | } |
67 | return cpu; |
68 | } |
69 | |
70 | bool cpu_paging_enabled(const CPUState *cpu) |
71 | { |
72 | CPUClass *cc = CPU_GET_CLASS(cpu); |
73 | |
74 | return cc->get_paging_enabled(cpu); |
75 | } |
76 | |
77 | static bool cpu_common_get_paging_enabled(const CPUState *cpu) |
78 | { |
79 | return false; |
80 | } |
81 | |
82 | void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list, |
83 | Error **errp) |
84 | { |
85 | CPUClass *cc = CPU_GET_CLASS(cpu); |
86 | |
87 | cc->get_memory_mapping(cpu, list, errp); |
88 | } |
89 | |
90 | static void cpu_common_get_memory_mapping(CPUState *cpu, |
91 | MemoryMappingList *list, |
92 | Error **errp) |
93 | { |
94 | error_setg(errp, "Obtaining memory mappings is unsupported on this CPU." ); |
95 | } |
96 | |
97 | /* Resetting the IRQ comes from across the code base so we take the |
98 | * BQL here if we need to. cpu_interrupt assumes it is held.*/ |
99 | void cpu_reset_interrupt(CPUState *cpu, int mask) |
100 | { |
101 | bool need_lock = !qemu_mutex_iothread_locked(); |
102 | |
103 | if (need_lock) { |
104 | qemu_mutex_lock_iothread(); |
105 | } |
106 | cpu->interrupt_request &= ~mask; |
107 | if (need_lock) { |
108 | qemu_mutex_unlock_iothread(); |
109 | } |
110 | } |
111 | |
112 | void cpu_exit(CPUState *cpu) |
113 | { |
114 | atomic_set(&cpu->exit_request, 1); |
115 | /* Ensure cpu_exec will see the exit request after TCG has exited. */ |
116 | smp_wmb(); |
117 | atomic_set(&cpu->icount_decr_ptr->u16.high, -1); |
118 | } |
119 | |
120 | int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu, |
121 | void *opaque) |
122 | { |
123 | CPUClass *cc = CPU_GET_CLASS(cpu); |
124 | |
125 | return (*cc->write_elf32_qemunote)(f, cpu, opaque); |
126 | } |
127 | |
128 | static int cpu_common_write_elf32_qemunote(WriteCoreDumpFunction f, |
129 | CPUState *cpu, void *opaque) |
130 | { |
131 | return 0; |
132 | } |
133 | |
134 | int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu, |
135 | int cpuid, void *opaque) |
136 | { |
137 | CPUClass *cc = CPU_GET_CLASS(cpu); |
138 | |
139 | return (*cc->write_elf32_note)(f, cpu, cpuid, opaque); |
140 | } |
141 | |
142 | static int cpu_common_write_elf32_note(WriteCoreDumpFunction f, |
143 | CPUState *cpu, int cpuid, |
144 | void *opaque) |
145 | { |
146 | return -1; |
147 | } |
148 | |
149 | int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu, |
150 | void *opaque) |
151 | { |
152 | CPUClass *cc = CPU_GET_CLASS(cpu); |
153 | |
154 | return (*cc->write_elf64_qemunote)(f, cpu, opaque); |
155 | } |
156 | |
157 | static int cpu_common_write_elf64_qemunote(WriteCoreDumpFunction f, |
158 | CPUState *cpu, void *opaque) |
159 | { |
160 | return 0; |
161 | } |
162 | |
163 | int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, |
164 | int cpuid, void *opaque) |
165 | { |
166 | CPUClass *cc = CPU_GET_CLASS(cpu); |
167 | |
168 | return (*cc->write_elf64_note)(f, cpu, cpuid, opaque); |
169 | } |
170 | |
171 | static int cpu_common_write_elf64_note(WriteCoreDumpFunction f, |
172 | CPUState *cpu, int cpuid, |
173 | void *opaque) |
174 | { |
175 | return -1; |
176 | } |
177 | |
178 | |
179 | static int cpu_common_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg) |
180 | { |
181 | return 0; |
182 | } |
183 | |
184 | static int cpu_common_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg) |
185 | { |
186 | return 0; |
187 | } |
188 | |
189 | static bool cpu_common_debug_check_watchpoint(CPUState *cpu, CPUWatchpoint *wp) |
190 | { |
191 | /* If no extra check is required, QEMU watchpoint match can be considered |
192 | * as an architectural match. |
193 | */ |
194 | return true; |
195 | } |
196 | |
197 | static bool cpu_common_virtio_is_big_endian(CPUState *cpu) |
198 | { |
199 | return target_words_bigendian(); |
200 | } |
201 | |
202 | static void cpu_common_noop(CPUState *cpu) |
203 | { |
204 | } |
205 | |
206 | static bool cpu_common_exec_interrupt(CPUState *cpu, int int_req) |
207 | { |
208 | return false; |
209 | } |
210 | |
211 | GuestPanicInformation *cpu_get_crash_info(CPUState *cpu) |
212 | { |
213 | CPUClass *cc = CPU_GET_CLASS(cpu); |
214 | GuestPanicInformation *res = NULL; |
215 | |
216 | if (cc->get_crash_info) { |
217 | res = cc->get_crash_info(cpu); |
218 | } |
219 | return res; |
220 | } |
221 | |
222 | void cpu_dump_state(CPUState *cpu, FILE *f, int flags) |
223 | { |
224 | CPUClass *cc = CPU_GET_CLASS(cpu); |
225 | |
226 | if (cc->dump_state) { |
227 | cpu_synchronize_state(cpu); |
228 | cc->dump_state(cpu, f, flags); |
229 | } |
230 | } |
231 | |
232 | void cpu_dump_statistics(CPUState *cpu, int flags) |
233 | { |
234 | CPUClass *cc = CPU_GET_CLASS(cpu); |
235 | |
236 | if (cc->dump_statistics) { |
237 | cc->dump_statistics(cpu, flags); |
238 | } |
239 | } |
240 | |
241 | void cpu_reset(CPUState *cpu) |
242 | { |
243 | CPUClass *klass = CPU_GET_CLASS(cpu); |
244 | |
245 | if (klass->reset != NULL) { |
246 | (*klass->reset)(cpu); |
247 | } |
248 | |
249 | trace_guest_cpu_reset(cpu); |
250 | } |
251 | |
252 | static void cpu_common_reset(CPUState *cpu) |
253 | { |
254 | CPUClass *cc = CPU_GET_CLASS(cpu); |
255 | |
256 | if (qemu_loglevel_mask(CPU_LOG_RESET)) { |
257 | qemu_log("CPU Reset (CPU %d)\n" , cpu->cpu_index); |
258 | log_cpu_state(cpu, cc->reset_dump_flags); |
259 | } |
260 | |
261 | cpu->interrupt_request = 0; |
262 | cpu->halted = 0; |
263 | cpu->mem_io_pc = 0; |
264 | cpu->mem_io_vaddr = 0; |
265 | cpu->icount_extra = 0; |
266 | atomic_set(&cpu->icount_decr_ptr->u32, 0); |
267 | cpu->can_do_io = 1; |
268 | cpu->exception_index = -1; |
269 | cpu->crash_occurred = false; |
270 | cpu->cflags_next_tb = -1; |
271 | |
272 | if (tcg_enabled()) { |
273 | cpu_tb_jmp_cache_clear(cpu); |
274 | |
275 | tcg_flush_softmmu_tlb(cpu); |
276 | } |
277 | } |
278 | |
279 | static bool cpu_common_has_work(CPUState *cs) |
280 | { |
281 | return false; |
282 | } |
283 | |
284 | ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model) |
285 | { |
286 | CPUClass *cc = CPU_CLASS(object_class_by_name(typename)); |
287 | |
288 | assert(cpu_model && cc->class_by_name); |
289 | return cc->class_by_name(cpu_model); |
290 | } |
291 | |
292 | static void cpu_common_parse_features(const char *typename, char *features, |
293 | Error **errp) |
294 | { |
295 | char *val; |
296 | static bool cpu_globals_initialized; |
297 | /* Single "key=value" string being parsed */ |
298 | char *featurestr = features ? strtok(features, "," ) : NULL; |
299 | |
300 | /* should be called only once, catch invalid users */ |
301 | assert(!cpu_globals_initialized); |
302 | cpu_globals_initialized = true; |
303 | |
304 | while (featurestr) { |
305 | val = strchr(featurestr, '='); |
306 | if (val) { |
307 | GlobalProperty *prop = g_new0(typeof(*prop), 1); |
308 | *val = 0; |
309 | val++; |
310 | prop->driver = typename; |
311 | prop->property = g_strdup(featurestr); |
312 | prop->value = g_strdup(val); |
313 | qdev_prop_register_global(prop); |
314 | } else { |
315 | error_setg(errp, "Expected key=value format, found %s." , |
316 | featurestr); |
317 | return; |
318 | } |
319 | featurestr = strtok(NULL, "," ); |
320 | } |
321 | } |
322 | |
323 | static void cpu_common_realizefn(DeviceState *dev, Error **errp) |
324 | { |
325 | CPUState *cpu = CPU(dev); |
326 | Object *machine = qdev_get_machine(); |
327 | |
328 | /* qdev_get_machine() can return something that's not TYPE_MACHINE |
329 | * if this is one of the user-only emulators; in that case there's |
330 | * no need to check the ignore_memory_transaction_failures board flag. |
331 | */ |
332 | if (object_dynamic_cast(machine, TYPE_MACHINE)) { |
333 | ObjectClass *oc = object_get_class(machine); |
334 | MachineClass *mc = MACHINE_CLASS(oc); |
335 | |
336 | if (mc) { |
337 | cpu->ignore_memory_transaction_failures = |
338 | mc->ignore_memory_transaction_failures; |
339 | } |
340 | } |
341 | |
342 | if (dev->hotplugged) { |
343 | cpu_synchronize_post_init(cpu); |
344 | cpu_resume(cpu); |
345 | } |
346 | |
347 | /* NOTE: latest generic point where the cpu is fully realized */ |
348 | trace_init_vcpu(cpu); |
349 | } |
350 | |
351 | static void cpu_common_unrealizefn(DeviceState *dev, Error **errp) |
352 | { |
353 | CPUState *cpu = CPU(dev); |
354 | /* NOTE: latest generic point before the cpu is fully unrealized */ |
355 | trace_fini_vcpu(cpu); |
356 | cpu_exec_unrealizefn(cpu); |
357 | } |
358 | |
359 | static void cpu_common_initfn(Object *obj) |
360 | { |
361 | CPUState *cpu = CPU(obj); |
362 | CPUClass *cc = CPU_GET_CLASS(obj); |
363 | |
364 | cpu->cpu_index = UNASSIGNED_CPU_INDEX; |
365 | cpu->cluster_index = UNASSIGNED_CLUSTER_INDEX; |
366 | cpu->gdb_num_regs = cpu->gdb_num_g_regs = cc->gdb_num_core_regs; |
367 | /* *-user doesn't have configurable SMP topology */ |
368 | /* the default value is changed by qemu_init_vcpu() for softmmu */ |
369 | cpu->nr_cores = 1; |
370 | cpu->nr_threads = 1; |
371 | |
372 | qemu_mutex_init(&cpu->work_mutex); |
373 | QTAILQ_INIT(&cpu->breakpoints); |
374 | QTAILQ_INIT(&cpu->watchpoints); |
375 | |
376 | cpu_exec_initfn(cpu); |
377 | } |
378 | |
379 | static void cpu_common_finalize(Object *obj) |
380 | { |
381 | CPUState *cpu = CPU(obj); |
382 | |
383 | qemu_mutex_destroy(&cpu->work_mutex); |
384 | } |
385 | |
386 | static int64_t cpu_common_get_arch_id(CPUState *cpu) |
387 | { |
388 | return cpu->cpu_index; |
389 | } |
390 | |
391 | static vaddr cpu_adjust_watchpoint_address(CPUState *cpu, vaddr addr, int len) |
392 | { |
393 | return addr; |
394 | } |
395 | |
396 | static void generic_handle_interrupt(CPUState *cpu, int mask) |
397 | { |
398 | cpu->interrupt_request |= mask; |
399 | |
400 | if (!qemu_cpu_is_self(cpu)) { |
401 | qemu_cpu_kick(cpu); |
402 | } |
403 | } |
404 | |
405 | CPUInterruptHandler cpu_interrupt_handler = generic_handle_interrupt; |
406 | |
407 | static void cpu_class_init(ObjectClass *klass, void *data) |
408 | { |
409 | DeviceClass *dc = DEVICE_CLASS(klass); |
410 | CPUClass *k = CPU_CLASS(klass); |
411 | |
412 | k->parse_features = cpu_common_parse_features; |
413 | k->reset = cpu_common_reset; |
414 | k->get_arch_id = cpu_common_get_arch_id; |
415 | k->has_work = cpu_common_has_work; |
416 | k->get_paging_enabled = cpu_common_get_paging_enabled; |
417 | k->get_memory_mapping = cpu_common_get_memory_mapping; |
418 | k->write_elf32_qemunote = cpu_common_write_elf32_qemunote; |
419 | k->write_elf32_note = cpu_common_write_elf32_note; |
420 | k->write_elf64_qemunote = cpu_common_write_elf64_qemunote; |
421 | k->write_elf64_note = cpu_common_write_elf64_note; |
422 | k->gdb_read_register = cpu_common_gdb_read_register; |
423 | k->gdb_write_register = cpu_common_gdb_write_register; |
424 | k->virtio_is_big_endian = cpu_common_virtio_is_big_endian; |
425 | k->debug_excp_handler = cpu_common_noop; |
426 | k->debug_check_watchpoint = cpu_common_debug_check_watchpoint; |
427 | k->cpu_exec_enter = cpu_common_noop; |
428 | k->cpu_exec_exit = cpu_common_noop; |
429 | k->cpu_exec_interrupt = cpu_common_exec_interrupt; |
430 | k->adjust_watchpoint_address = cpu_adjust_watchpoint_address; |
431 | set_bit(DEVICE_CATEGORY_CPU, dc->categories); |
432 | dc->realize = cpu_common_realizefn; |
433 | dc->unrealize = cpu_common_unrealizefn; |
434 | dc->props = cpu_common_props; |
435 | /* |
436 | * Reason: CPUs still need special care by board code: wiring up |
437 | * IRQs, adding reset handlers, halting non-first CPUs, ... |
438 | */ |
439 | dc->user_creatable = false; |
440 | } |
441 | |
442 | static const TypeInfo cpu_type_info = { |
443 | .name = TYPE_CPU, |
444 | .parent = TYPE_DEVICE, |
445 | .instance_size = sizeof(CPUState), |
446 | .instance_init = cpu_common_initfn, |
447 | .instance_finalize = cpu_common_finalize, |
448 | .abstract = true, |
449 | .class_size = sizeof(CPUClass), |
450 | .class_init = cpu_class_init, |
451 | }; |
452 | |
453 | static void cpu_register_types(void) |
454 | { |
455 | type_register_static(&cpu_type_info); |
456 | } |
457 | |
458 | type_init(cpu_register_types) |
459 | |