1 | #include "qemu/osdep.h" |
2 | #include "ati_int.h" |
3 | |
4 | #ifdef DEBUG_ATI |
5 | struct ati_regdesc { |
6 | const char *name; |
7 | int num; |
8 | }; |
9 | |
10 | static struct ati_regdesc ati_reg_names[] = { |
11 | {"MM_INDEX" , 0x0000}, |
12 | {"MM_DATA" , 0x0004}, |
13 | {"CLOCK_CNTL_INDEX" , 0x0008}, |
14 | {"CLOCK_CNTL_DATA" , 0x000c}, |
15 | {"BIOS_0_SCRATCH" , 0x0010}, |
16 | {"BUS_CNTL" , 0x0030}, |
17 | {"BUS_CNTL1" , 0x0034}, |
18 | {"GEN_INT_CNTL" , 0x0040}, |
19 | {"GEN_INT_STATUS" , 0x0044}, |
20 | {"CRTC_GEN_CNTL" , 0x0050}, |
21 | {"CRTC_EXT_CNTL" , 0x0054}, |
22 | {"DAC_CNTL" , 0x0058}, |
23 | {"GPIO_VGA_DDC" , 0x0060}, |
24 | {"GPIO_DVI_DDC" , 0x0064}, |
25 | {"GPIO_MONID" , 0x0068}, |
26 | {"I2C_CNTL_1" , 0x0094}, |
27 | {"AMCGPIO_MASK_MIR" , 0x009c}, |
28 | {"AMCGPIO_A_MIR" , 0x00a0}, |
29 | {"AMCGPIO_Y_MIR" , 0x00a4}, |
30 | {"AMCGPIO_EN_MIR" , 0x00a8}, |
31 | {"PALETTE_INDEX" , 0x00b0}, |
32 | {"PALETTE_DATA" , 0x00b4}, |
33 | {"CNFG_CNTL" , 0x00e0}, |
34 | {"GEN_RESET_CNTL" , 0x00f0}, |
35 | {"CNFG_MEMSIZE" , 0x00f8}, |
36 | {"CONFIG_APER_0_BASE" , 0x0100}, |
37 | {"CONFIG_APER_1_BASE" , 0x0104}, |
38 | {"CONFIG_APER_SIZE" , 0x0108}, |
39 | {"CONFIG_REG_1_BASE" , 0x010c}, |
40 | {"CONFIG_REG_APER_SIZE" , 0x0110}, |
41 | {"MEM_CNTL" , 0x0140}, |
42 | {"MC_FB_LOCATION" , 0x0148}, |
43 | {"MC_AGP_LOCATION" , 0x014C}, |
44 | {"MC_STATUS" , 0x0150}, |
45 | {"MEM_POWER_MISC" , 0x015c}, |
46 | {"AGP_BASE" , 0x0170}, |
47 | {"AGP_CNTL" , 0x0174}, |
48 | {"AGP_APER_OFFSET" , 0x0178}, |
49 | {"PCI_GART_PAGE" , 0x017c}, |
50 | {"PC_NGUI_MODE" , 0x0180}, |
51 | {"PC_NGUI_CTLSTAT" , 0x0184}, |
52 | {"MPP_TB_CONFIG" , 0x01C0}, |
53 | {"MPP_GP_CONFIG" , 0x01C8}, |
54 | {"VIPH_CONTROL" , 0x01D0}, |
55 | {"CRTC_H_TOTAL_DISP" , 0x0200}, |
56 | {"CRTC_H_SYNC_STRT_WID" , 0x0204}, |
57 | {"CRTC_V_TOTAL_DISP" , 0x0208}, |
58 | {"CRTC_V_SYNC_STRT_WID" , 0x020c}, |
59 | {"CRTC_VLINE_CRNT_VLINE" , 0x0210}, |
60 | {"CRTC_CRNT_FRAME" , 0x0214}, |
61 | {"CRTC_GUI_TRIG_VLINE" , 0x0218}, |
62 | {"CRTC_OFFSET" , 0x0224}, |
63 | {"CRTC_OFFSET_CNTL" , 0x0228}, |
64 | {"CRTC_PITCH" , 0x022c}, |
65 | {"OVR_CLR" , 0x0230}, |
66 | {"OVR_WID_LEFT_RIGHT" , 0x0234}, |
67 | {"OVR_WID_TOP_BOTTOM" , 0x0238}, |
68 | {"CUR_OFFSET" , 0x0260}, |
69 | {"CUR_HORZ_VERT_POSN" , 0x0264}, |
70 | {"CUR_HORZ_VERT_OFF" , 0x0268}, |
71 | {"CUR_CLR0" , 0x026c}, |
72 | {"CUR_CLR1" , 0x0270}, |
73 | {"LVDS_GEN_CNTL" , 0x02d0}, |
74 | {"DDA_CONFIG" , 0x02e0}, |
75 | {"DDA_ON_OFF" , 0x02e4}, |
76 | {"VGA_DDA_CONFIG" , 0x02e8}, |
77 | {"VGA_DDA_ON_OFF" , 0x02ec}, |
78 | {"CRTC2_H_TOTAL_DISP" , 0x0300}, |
79 | {"CRTC2_H_SYNC_STRT_WID" , 0x0304}, |
80 | {"CRTC2_V_TOTAL_DISP" , 0x0308}, |
81 | {"CRTC2_V_SYNC_STRT_WID" , 0x030c}, |
82 | {"CRTC2_VLINE_CRNT_VLINE" , 0x0310}, |
83 | {"CRTC2_CRNT_FRAME" , 0x0314}, |
84 | {"CRTC2_GUI_TRIG_VLINE" , 0x0318}, |
85 | {"CRTC2_OFFSET" , 0x0324}, |
86 | {"CRTC2_OFFSET_CNTL" , 0x0328}, |
87 | {"CRTC2_PITCH" , 0x032c}, |
88 | {"DDA2_CONFIG" , 0x03e0}, |
89 | {"DDA2_ON_OFF" , 0x03e4}, |
90 | {"CRTC2_GEN_CNTL" , 0x03f8}, |
91 | {"CRTC2_STATUS" , 0x03fc}, |
92 | {"OV0_SCALE_CNTL" , 0x0420}, |
93 | {"SUBPIC_CNTL" , 0x0540}, |
94 | {"PM4_BUFFER_OFFSET" , 0x0700}, |
95 | {"PM4_BUFFER_CNTL" , 0x0704}, |
96 | {"PM4_BUFFER_WM_CNTL" , 0x0708}, |
97 | {"PM4_BUFFER_DL_RPTR_ADDR" , 0x070c}, |
98 | {"PM4_BUFFER_DL_RPTR" , 0x0710}, |
99 | {"PM4_BUFFER_DL_WPTR" , 0x0714}, |
100 | {"PM4_VC_FPU_SETUP" , 0x071c}, |
101 | {"PM4_FPU_CNTL" , 0x0720}, |
102 | {"PM4_VC_FORMAT" , 0x0724}, |
103 | {"PM4_VC_CNTL" , 0x0728}, |
104 | {"PM4_VC_I01" , 0x072c}, |
105 | {"PM4_VC_VLOFF" , 0x0730}, |
106 | {"PM4_VC_VLSIZE" , 0x0734}, |
107 | {"PM4_IW_INDOFF" , 0x0738}, |
108 | {"PM4_IW_INDSIZE" , 0x073c}, |
109 | {"PM4_FPU_FPX0" , 0x0740}, |
110 | {"PM4_FPU_FPY0" , 0x0744}, |
111 | {"PM4_FPU_FPX1" , 0x0748}, |
112 | {"PM4_FPU_FPY1" , 0x074c}, |
113 | {"PM4_FPU_FPX2" , 0x0750}, |
114 | {"PM4_FPU_FPY2" , 0x0754}, |
115 | {"PM4_FPU_FPY3" , 0x0758}, |
116 | {"PM4_FPU_FPY4" , 0x075c}, |
117 | {"PM4_FPU_FPY5" , 0x0760}, |
118 | {"PM4_FPU_FPY6" , 0x0764}, |
119 | {"PM4_FPU_FPR" , 0x0768}, |
120 | {"PM4_FPU_FPG" , 0x076c}, |
121 | {"PM4_FPU_FPB" , 0x0770}, |
122 | {"PM4_FPU_FPA" , 0x0774}, |
123 | {"PM4_FPU_INTXY0" , 0x0780}, |
124 | {"PM4_FPU_INTXY1" , 0x0784}, |
125 | {"PM4_FPU_INTXY2" , 0x0788}, |
126 | {"PM4_FPU_INTARGB" , 0x078c}, |
127 | {"PM4_FPU_FPTWICEAREA" , 0x0790}, |
128 | {"PM4_FPU_DMAJOR01" , 0x0794}, |
129 | {"PM4_FPU_DMAJOR12" , 0x0798}, |
130 | {"PM4_FPU_DMAJOR02" , 0x079c}, |
131 | {"PM4_FPU_STAT" , 0x07a0}, |
132 | {"PM4_STAT" , 0x07b8}, |
133 | {"PM4_TEST_CNTL" , 0x07d0}, |
134 | {"PM4_MICROCODE_ADDR" , 0x07d4}, |
135 | {"PM4_MICROCODE_RADDR" , 0x07d8}, |
136 | {"PM4_MICROCODE_DATAH" , 0x07dc}, |
137 | {"PM4_MICROCODE_DATAL" , 0x07e0}, |
138 | {"PM4_CMDFIFO_ADDR" , 0x07e4}, |
139 | {"PM4_CMDFIFO_DATAH" , 0x07e8}, |
140 | {"PM4_CMDFIFO_DATAL" , 0x07ec}, |
141 | {"PM4_BUFFER_ADDR" , 0x07f0}, |
142 | {"PM4_BUFFER_DATAH" , 0x07f4}, |
143 | {"PM4_BUFFER_DATAL" , 0x07f8}, |
144 | {"PM4_MICRO_CNTL" , 0x07fc}, |
145 | {"CAP0_TRIG_CNTL" , 0x0950}, |
146 | {"CAP1_TRIG_CNTL" , 0x09c0}, |
147 | {"RBBM_STATUS" , 0x0e40}, |
148 | {"PM4_FIFO_DATA_EVEN" , 0x1000}, |
149 | {"PM4_FIFO_DATA_ODD" , 0x1004}, |
150 | {"DST_OFFSET" , 0x1404}, |
151 | {"DST_PITCH" , 0x1408}, |
152 | {"DST_WIDTH" , 0x140c}, |
153 | {"DST_HEIGHT" , 0x1410}, |
154 | {"SRC_X" , 0x1414}, |
155 | {"SRC_Y" , 0x1418}, |
156 | {"DST_X" , 0x141c}, |
157 | {"DST_Y" , 0x1420}, |
158 | {"SRC_PITCH_OFFSET" , 0x1428}, |
159 | {"DST_PITCH_OFFSET" , 0x142c}, |
160 | {"SRC_Y_X" , 0x1434}, |
161 | {"DST_Y_X" , 0x1438}, |
162 | {"DST_HEIGHT_WIDTH" , 0x143c}, |
163 | {"DP_GUI_MASTER_CNTL" , 0x146c}, |
164 | {"BRUSH_SCALE" , 0x1470}, |
165 | {"BRUSH_Y_X" , 0x1474}, |
166 | {"DP_BRUSH_BKGD_CLR" , 0x1478}, |
167 | {"DP_BRUSH_FRGD_CLR" , 0x147c}, |
168 | {"DST_WIDTH_X" , 0x1588}, |
169 | {"DST_HEIGHT_WIDTH_8" , 0x158c}, |
170 | {"SRC_X_Y" , 0x1590}, |
171 | {"DST_X_Y" , 0x1594}, |
172 | {"DST_WIDTH_HEIGHT" , 0x1598}, |
173 | {"DST_WIDTH_X_INCY" , 0x159c}, |
174 | {"DST_HEIGHT_Y" , 0x15a0}, |
175 | {"DST_X_SUB" , 0x15a4}, |
176 | {"DST_Y_SUB" , 0x15a8}, |
177 | {"SRC_OFFSET" , 0x15ac}, |
178 | {"SRC_PITCH" , 0x15b0}, |
179 | {"DST_HEIGHT_WIDTH_BW" , 0x15b4}, |
180 | {"CLR_CMP_CNTL" , 0x15c0}, |
181 | {"CLR_CMP_CLR_SRC" , 0x15c4}, |
182 | {"CLR_CMP_CLR_DST" , 0x15c8}, |
183 | {"CLR_CMP_MASK" , 0x15cc}, |
184 | {"DP_SRC_FRGD_CLR" , 0x15d8}, |
185 | {"DP_SRC_BKGD_CLR" , 0x15dc}, |
186 | {"DST_BRES_ERR" , 0x1628}, |
187 | {"DST_BRES_INC" , 0x162c}, |
188 | {"DST_BRES_DEC" , 0x1630}, |
189 | {"DST_BRES_LNTH" , 0x1634}, |
190 | {"DST_BRES_LNTH_SUB" , 0x1638}, |
191 | {"SC_LEFT" , 0x1640}, |
192 | {"SC_RIGHT" , 0x1644}, |
193 | {"SC_TOP" , 0x1648}, |
194 | {"SC_BOTTOM" , 0x164c}, |
195 | {"SRC_SC_RIGHT" , 0x1654}, |
196 | {"SRC_SC_BOTTOM" , 0x165c}, |
197 | {"GUI_DEBUG0" , 0x16a0}, |
198 | {"GUI_DEBUG1" , 0x16a4}, |
199 | {"GUI_TIMEOUT" , 0x16b0}, |
200 | {"GUI_TIMEOUT0" , 0x16b4}, |
201 | {"GUI_TIMEOUT1" , 0x16b8}, |
202 | {"GUI_PROBE" , 0x16bc}, |
203 | {"DP_CNTL" , 0x16c0}, |
204 | {"DP_DATATYPE" , 0x16c4}, |
205 | {"DP_MIX" , 0x16c8}, |
206 | {"DP_WRITE_MASK" , 0x16cc}, |
207 | {"DP_CNTL_XDIR_YDIR_YMAJOR" , 0x16d0}, |
208 | {"DEFAULT_OFFSET" , 0x16e0}, |
209 | {"DEFAULT_PITCH" , 0x16e4}, |
210 | {"DEFAULT_SC_BOTTOM_RIGHT" , 0x16e8}, |
211 | {"SC_TOP_LEFT" , 0x16ec}, |
212 | {"SC_BOTTOM_RIGHT" , 0x16f0}, |
213 | {"SRC_SC_BOTTOM_RIGHT" , 0x16f4}, |
214 | {"DST_TILE" , 0x1700}, |
215 | {"WAIT_UNTIL" , 0x1720}, |
216 | {"CACHE_CNTL" , 0x1724}, |
217 | {"GUI_STAT" , 0x1740}, |
218 | {"PC_GUI_MODE" , 0x1744}, |
219 | {"PC_GUI_CTLSTAT" , 0x1748}, |
220 | {"PC_DEBUG_MODE" , 0x1760}, |
221 | {"BRES_DST_ERR_DEC" , 0x1780}, |
222 | {"TRAIL_BRES_T12_ERR_DEC" , 0x1784}, |
223 | {"TRAIL_BRES_T12_INC" , 0x1788}, |
224 | {"DP_T12_CNTL" , 0x178c}, |
225 | {"DST_BRES_T1_LNTH" , 0x1790}, |
226 | {"DST_BRES_T2_LNTH" , 0x1794}, |
227 | {"SCALE_SRC_HEIGHT_WIDTH" , 0x1994}, |
228 | {"SCALE_OFFSET_0" , 0x1998}, |
229 | {"SCALE_PITCH" , 0x199c}, |
230 | {"SCALE_X_INC" , 0x19a0}, |
231 | {"SCALE_Y_INC" , 0x19a4}, |
232 | {"SCALE_HACC" , 0x19a8}, |
233 | {"SCALE_VACC" , 0x19ac}, |
234 | {"SCALE_DST_X_Y" , 0x19b0}, |
235 | {"SCALE_DST_HEIGHT_WIDTH" , 0x19b4}, |
236 | {"SCALE_3D_CNTL" , 0x1a00}, |
237 | {"SCALE_3D_DATATYPE" , 0x1a20}, |
238 | {"SETUP_CNTL" , 0x1bc4}, |
239 | {"SOLID_COLOR" , 0x1bc8}, |
240 | {"WINDOW_XY_OFFSET" , 0x1bcc}, |
241 | {"DRAW_LINE_POINT" , 0x1bd0}, |
242 | {"SETUP_CNTL_PM4" , 0x1bd4}, |
243 | {"DST_PITCH_OFFSET_C" , 0x1c80}, |
244 | {"DP_GUI_MASTER_CNTL_C" , 0x1c84}, |
245 | {"SC_TOP_LEFT_C" , 0x1c88}, |
246 | {"SC_BOTTOM_RIGHT_C" , 0x1c8c}, |
247 | {"CLR_CMP_MASK_3D" , 0x1A28}, |
248 | {"MISC_3D_STATE_CNTL_REG" , 0x1CA0}, |
249 | {"MC_SRC1_CNTL" , 0x19D8}, |
250 | {"TEX_CNTL" , 0x1800}, |
251 | {"RAGE128_MPP_TB_CONFIG" , 0x01c0}, |
252 | {NULL, -1} |
253 | }; |
254 | |
255 | const char *ati_reg_name(int num) |
256 | { |
257 | int i; |
258 | |
259 | num &= ~3; |
260 | for (i = 0; ati_reg_names[i].name; i++) { |
261 | if (ati_reg_names[i].num == num) { |
262 | return ati_reg_names[i].name; |
263 | } |
264 | } |
265 | return "unknown" ; |
266 | } |
267 | #else |
268 | const char *ati_reg_name(int num) |
269 | { |
270 | return "" ; |
271 | } |
272 | #endif |
273 | |