1 | /* |
2 | * QEMU AHCI Emulation |
3 | * |
4 | * Copyright (c) 2010 qiaochong@loongson.cn |
5 | * Copyright (c) 2010 Roland Elek <elek.roland@gmail.com> |
6 | * Copyright (c) 2010 Sebastian Herbszt <herbszt@gmx.de> |
7 | * Copyright (c) 2010 Alexander Graf <agraf@suse.de> |
8 | * |
9 | * This library is free software; you can redistribute it and/or |
10 | * modify it under the terms of the GNU Lesser General Public |
11 | * License as published by the Free Software Foundation; either |
12 | * version 2 of the License, or (at your option) any later version. |
13 | * |
14 | * This library is distributed in the hope that it will be useful, |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
17 | * Lesser General Public License for more details. |
18 | * |
19 | * You should have received a copy of the GNU Lesser General Public |
20 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
21 | * |
22 | */ |
23 | |
24 | #ifndef HW_IDE_AHCI_INTERNAL_H |
25 | #define HW_IDE_AHCI_INTERNAL_H |
26 | |
27 | #include "hw/ide/ahci.h" |
28 | #include "hw/ide/internal.h" |
29 | #include "hw/sysbus.h" |
30 | |
31 | #define AHCI_MEM_BAR_SIZE 0x1000 |
32 | #define AHCI_MAX_PORTS 32 |
33 | #define AHCI_MAX_SG 168 /* hardware max is 64K */ |
34 | #define AHCI_DMA_BOUNDARY 0xffffffff |
35 | #define AHCI_USE_CLUSTERING 0 |
36 | #define AHCI_MAX_CMDS 32 |
37 | #define AHCI_CMD_SZ 32 |
38 | #define AHCI_CMD_SLOT_SZ (AHCI_MAX_CMDS * AHCI_CMD_SZ) |
39 | #define AHCI_RX_FIS_SZ 256 |
40 | #define AHCI_CMD_TBL_CDB 0x40 |
41 | #define AHCI_CMD_TBL_HDR_SZ 0x80 |
42 | #define AHCI_CMD_TBL_SZ (AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16)) |
43 | #define AHCI_CMD_TBL_AR_SZ (AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS) |
44 | #define AHCI_PORT_PRIV_DMA_SZ (AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ + \ |
45 | AHCI_RX_FIS_SZ) |
46 | |
47 | #define AHCI_IRQ_ON_SG (1U << 31) |
48 | #define AHCI_CMD_ATAPI (1 << 5) |
49 | #define AHCI_CMD_WRITE (1 << 6) |
50 | #define AHCI_CMD_PREFETCH (1 << 7) |
51 | #define AHCI_CMD_RESET (1 << 8) |
52 | #define AHCI_CMD_CLR_BUSY (1 << 10) |
53 | |
54 | #define RX_FIS_D2H_REG 0x40 /* offset of D2H Register FIS data */ |
55 | #define RX_FIS_SDB 0x58 /* offset of SDB FIS data */ |
56 | #define RX_FIS_UNK 0x60 /* offset of Unknown FIS data */ |
57 | |
58 | /* global controller registers */ |
59 | enum AHCIHostReg { |
60 | AHCI_HOST_REG_CAP = 0, /* CAP: host capabilities */ |
61 | AHCI_HOST_REG_CTL = 1, /* GHC: global host control */ |
62 | AHCI_HOST_REG_IRQ_STAT = 2, /* IS: interrupt status */ |
63 | AHCI_HOST_REG_PORTS_IMPL = 3, /* PI: bitmap of implemented ports */ |
64 | AHCI_HOST_REG_VERSION = 4, /* VS: AHCI spec. version compliancy */ |
65 | AHCI_HOST_REG_CCC_CTL = 5, /* CCC_CTL: CCC Control */ |
66 | AHCI_HOST_REG_CCC_PORTS = 6, /* CCC_PORTS: CCC Ports */ |
67 | AHCI_HOST_REG_EM_LOC = 7, /* EM_LOC: Enclosure Mgmt Location */ |
68 | AHCI_HOST_REG_EM_CTL = 8, /* EM_CTL: Enclosure Mgmt Control */ |
69 | AHCI_HOST_REG_CAP2 = 9, /* CAP2: host capabilities, extended */ |
70 | AHCI_HOST_REG_BOHC = 10, /* BOHC: firmare/os handoff ctrl & status */ |
71 | AHCI_HOST_REG__COUNT = 11 |
72 | }; |
73 | |
74 | /* HOST_CTL bits */ |
75 | #define HOST_CTL_RESET (1 << 0) /* reset controller; self-clear */ |
76 | #define HOST_CTL_IRQ_EN (1 << 1) /* global IRQ enable */ |
77 | #define HOST_CTL_AHCI_EN (1U << 31) /* AHCI enabled */ |
78 | |
79 | /* HOST_CAP bits */ |
80 | #define HOST_CAP_SSC (1 << 14) /* Slumber capable */ |
81 | #define HOST_CAP_AHCI (1 << 18) /* AHCI only */ |
82 | #define HOST_CAP_CLO (1 << 24) /* Command List Override support */ |
83 | #define HOST_CAP_SSS (1 << 27) /* Staggered Spin-up */ |
84 | #define HOST_CAP_NCQ (1 << 30) /* Native Command Queueing */ |
85 | #define HOST_CAP_64 (1U << 31) /* PCI DAC (64-bit DMA) support */ |
86 | |
87 | /* registers for each SATA port */ |
88 | enum AHCIPortReg { |
89 | AHCI_PORT_REG_LST_ADDR = 0, /* PxCLB: command list DMA addr */ |
90 | AHCI_PORT_REG_LST_ADDR_HI = 1, /* PxCLBU: command list DMA addr hi */ |
91 | AHCI_PORT_REG_FIS_ADDR = 2, /* PxFB: FIS rx buf addr */ |
92 | AHCI_PORT_REG_FIS_ADDR_HI = 3, /* PxFBU: FIX rx buf addr hi */ |
93 | AHCI_PORT_REG_IRQ_STAT = 4, /* PxIS: interrupt status */ |
94 | AHCI_PORT_REG_IRQ_MASK = 5, /* PxIE: interrupt enable/disable mask */ |
95 | AHCI_PORT_REG_CMD = 6, /* PxCMD: port command */ |
96 | /* RESERVED */ |
97 | AHCI_PORT_REG_TFDATA = 8, /* PxTFD: taskfile data */ |
98 | AHCI_PORT_REG_SIG = 9, /* PxSIG: device TF signature */ |
99 | AHCI_PORT_REG_SCR_STAT = 10, /* PxSSTS: SATA phy register: SStatus */ |
100 | AHCI_PORT_REG_SCR_CTL = 11, /* PxSCTL: SATA phy register: SControl */ |
101 | AHCI_PORT_REG_SCR_ERR = 12, /* PxSERR: SATA phy register: SError */ |
102 | AHCI_PORT_REG_SCR_ACT = 13, /* PxSACT: SATA phy register: SActive */ |
103 | AHCI_PORT_REG_CMD_ISSUE = 14, /* PxCI: command issue */ |
104 | AHCI_PORT_REG_SCR_NOTIF = 15, /* PxSNTF: SATA phy register: SNotification */ |
105 | AHCI_PORT_REG_FIS_CTL = 16, /* PxFBS: Port multiplier switching ctl */ |
106 | AHCI_PORT_REG_DEV_SLEEP = 17, /* PxDEVSLP: device sleep control */ |
107 | /* RESERVED */ |
108 | AHCI_PORT_REG_VENDOR_1 = 28, /* PxVS: Vendor Specific */ |
109 | AHCI_PORT_REG_VENDOR_2 = 29, |
110 | AHCI_PORT_REG_VENDOR_3 = 30, |
111 | AHCI_PORT_REG_VENDOR_4 = 31, |
112 | AHCI_PORT_REG__COUNT = 32 |
113 | }; |
114 | |
115 | /* Port interrupt bit descriptors */ |
116 | enum AHCIPortIRQ { |
117 | AHCI_PORT_IRQ_BIT_DHRS = 0, |
118 | AHCI_PORT_IRQ_BIT_PSS = 1, |
119 | AHCI_PORT_IRQ_BIT_DSS = 2, |
120 | AHCI_PORT_IRQ_BIT_SDBS = 3, |
121 | AHCI_PORT_IRQ_BIT_UFS = 4, |
122 | AHCI_PORT_IRQ_BIT_DPS = 5, |
123 | AHCI_PORT_IRQ_BIT_PCS = 6, |
124 | AHCI_PORT_IRQ_BIT_DMPS = 7, |
125 | /* RESERVED */ |
126 | AHCI_PORT_IRQ_BIT_PRCS = 22, |
127 | AHCI_PORT_IRQ_BIT_IPMS = 23, |
128 | AHCI_PORT_IRQ_BIT_OFS = 24, |
129 | /* RESERVED */ |
130 | AHCI_PORT_IRQ_BIT_INFS = 26, |
131 | AHCI_PORT_IRQ_BIT_IFS = 27, |
132 | AHCI_PORT_IRQ_BIT_HBDS = 28, |
133 | AHCI_PORT_IRQ_BIT_HBFS = 29, |
134 | AHCI_PORT_IRQ_BIT_TFES = 30, |
135 | AHCI_PORT_IRQ_BIT_CPDS = 31, |
136 | AHCI_PORT_IRQ__COUNT = 32 |
137 | }; |
138 | |
139 | |
140 | /* PORT_IRQ_{STAT,MASK} bits */ |
141 | #define PORT_IRQ_COLD_PRES (1U << 31) /* cold presence detect */ |
142 | #define PORT_IRQ_TF_ERR (1 << 30) /* task file error */ |
143 | #define PORT_IRQ_HBUS_ERR (1 << 29) /* host bus fatal error */ |
144 | #define PORT_IRQ_HBUS_DATA_ERR (1 << 28) /* host bus data error */ |
145 | #define PORT_IRQ_IF_ERR (1 << 27) /* interface fatal error */ |
146 | #define PORT_IRQ_IF_NONFATAL (1 << 26) /* interface non-fatal error */ |
147 | /* reserved */ |
148 | #define PORT_IRQ_OVERFLOW (1 << 24) /* xfer exhausted available S/G */ |
149 | #define PORT_IRQ_BAD_PMP (1 << 23) /* incorrect port multiplier */ |
150 | #define PORT_IRQ_PHYRDY (1 << 22) /* PhyRdy changed */ |
151 | /* reserved */ |
152 | #define PORT_IRQ_DEV_ILCK (1 << 7) /* device interlock */ |
153 | #define PORT_IRQ_CONNECT (1 << 6) /* port connect change status */ |
154 | #define PORT_IRQ_SG_DONE (1 << 5) /* descriptor processed */ |
155 | #define PORT_IRQ_UNK_FIS (1 << 4) /* unknown FIS rx'd */ |
156 | #define PORT_IRQ_SDB_FIS (1 << 3) /* Set Device Bits FIS rx'd */ |
157 | #define PORT_IRQ_DMAS_FIS (1 << 2) /* DMA Setup FIS rx'd */ |
158 | #define PORT_IRQ_PIOS_FIS (1 << 1) /* PIO Setup FIS rx'd */ |
159 | #define PORT_IRQ_D2H_REG_FIS (1 << 0) /* D2H Register FIS rx'd */ |
160 | |
161 | #define PORT_IRQ_FREEZE (PORT_IRQ_HBUS_ERR | PORT_IRQ_IF_ERR | \ |
162 | PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY | \ |
163 | PORT_IRQ_UNK_FIS) |
164 | #define PORT_IRQ_ERROR (PORT_IRQ_FREEZE | PORT_IRQ_TF_ERR | \ |
165 | PORT_IRQ_HBUS_DATA_ERR) |
166 | #define DEF_PORT_IRQ (PORT_IRQ_ERROR | PORT_IRQ_SG_DONE | \ |
167 | PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS | \ |
168 | PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS) |
169 | |
170 | /* PORT_CMD bits */ |
171 | #define PORT_CMD_ATAPI (1 << 24) /* Device is ATAPI */ |
172 | #define PORT_CMD_LIST_ON (1 << 15) /* cmd list DMA engine running */ |
173 | #define PORT_CMD_FIS_ON (1 << 14) /* FIS DMA engine running */ |
174 | #define PORT_CMD_FIS_RX (1 << 4) /* Enable FIS receive DMA engine */ |
175 | #define PORT_CMD_CLO (1 << 3) /* Command list override */ |
176 | #define PORT_CMD_POWER_ON (1 << 2) /* Power up device */ |
177 | #define PORT_CMD_SPIN_UP (1 << 1) /* Spin up device */ |
178 | #define PORT_CMD_START (1 << 0) /* Enable port DMA engine */ |
179 | |
180 | #define PORT_CMD_ICC_MASK (0xfU << 28) /* i/f ICC state mask */ |
181 | #define PORT_CMD_ICC_ACTIVE (0x1 << 28) /* Put i/f in active state */ |
182 | #define PORT_CMD_ICC_PARTIAL (0x2 << 28) /* Put i/f in partial state */ |
183 | #define PORT_CMD_ICC_SLUMBER (0x6 << 28) /* Put i/f in slumber state */ |
184 | |
185 | #define PORT_CMD_RO_MASK 0x007dffe0 /* Which CMD bits are read only? */ |
186 | |
187 | /* ap->flags bits */ |
188 | #define AHCI_FLAG_NO_NCQ (1 << 24) |
189 | #define AHCI_FLAG_IGN_IRQ_IF_ERR (1 << 25) /* ignore IRQ_IF_ERR */ |
190 | #define AHCI_FLAG_HONOR_PI (1 << 26) /* honor PORTS_IMPL */ |
191 | #define AHCI_FLAG_IGN_SERR_INTERNAL (1 << 27) /* ignore SERR_INTERNAL */ |
192 | #define AHCI_FLAG_32BIT_ONLY (1 << 28) /* force 32bit */ |
193 | |
194 | #define ATA_SRST (1 << 2) /* software reset */ |
195 | |
196 | #define STATE_RUN 0 |
197 | #define STATE_RESET 1 |
198 | |
199 | #define SATA_SCR_SSTATUS_DET_NODEV 0x0 |
200 | #define SATA_SCR_SSTATUS_DET_DEV_PRESENT_PHY_UP 0x3 |
201 | |
202 | #define SATA_SCR_SSTATUS_SPD_NODEV 0x00 |
203 | #define SATA_SCR_SSTATUS_SPD_GEN1 0x10 |
204 | |
205 | #define SATA_SCR_SSTATUS_IPM_NODEV 0x000 |
206 | #define SATA_SCR_SSTATUS_IPM_ACTIVE 0X100 |
207 | |
208 | #define AHCI_SCR_SCTL_DET 0xf |
209 | |
210 | #define SATA_FIS_TYPE_REGISTER_H2D 0x27 |
211 | #define SATA_FIS_REG_H2D_UPDATE_COMMAND_REGISTER 0x80 |
212 | #define SATA_FIS_TYPE_REGISTER_D2H 0x34 |
213 | #define SATA_FIS_TYPE_PIO_SETUP 0x5f |
214 | #define SATA_FIS_TYPE_SDB 0xA1 |
215 | |
216 | #define AHCI_CMD_HDR_CMD_FIS_LEN 0x1f |
217 | #define AHCI_CMD_HDR_PRDT_LEN 16 |
218 | |
219 | #define SATA_SIGNATURE_CDROM 0xeb140101 |
220 | #define SATA_SIGNATURE_DISK 0x00000101 |
221 | |
222 | #define AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR 0x2c |
223 | |
224 | #define AHCI_PORT_REGS_START_ADDR 0x100 |
225 | #define AHCI_PORT_ADDR_OFFSET_MASK 0x7f |
226 | #define AHCI_PORT_ADDR_OFFSET_LEN 0x80 |
227 | |
228 | #define AHCI_NUM_COMMAND_SLOTS 31 |
229 | #define AHCI_SUPPORTED_SPEED 20 |
230 | #define AHCI_SUPPORTED_SPEED_GEN1 1 |
231 | #define AHCI_VERSION_1_0 0x10000 |
232 | |
233 | #define AHCI_PROGMODE_MAJOR_REV_1 1 |
234 | |
235 | #define AHCI_COMMAND_TABLE_ACMD 0x40 |
236 | |
237 | #define AHCI_PRDT_SIZE_MASK 0x3fffff |
238 | |
239 | #define IDE_FEATURE_DMA 1 |
240 | |
241 | #define READ_FPDMA_QUEUED 0x60 |
242 | #define WRITE_FPDMA_QUEUED 0x61 |
243 | #define NCQ_NON_DATA 0x63 |
244 | #define RECEIVE_FPDMA_QUEUED 0x65 |
245 | #define SEND_FPDMA_QUEUED 0x64 |
246 | |
247 | #define NCQ_FIS_FUA_MASK 0x80 |
248 | #define NCQ_FIS_RARC_MASK 0x01 |
249 | |
250 | #define RES_FIS_DSFIS 0x00 |
251 | #define RES_FIS_PSFIS 0x20 |
252 | #define RES_FIS_RFIS 0x40 |
253 | #define RES_FIS_SDBFIS 0x58 |
254 | #define RES_FIS_UFIS 0x60 |
255 | |
256 | #define SATA_CAP_SIZE 0x8 |
257 | #define SATA_CAP_REV 0x2 |
258 | #define SATA_CAP_BAR 0x4 |
259 | |
260 | typedef struct AHCIPortRegs { |
261 | uint32_t lst_addr; |
262 | uint32_t lst_addr_hi; |
263 | uint32_t fis_addr; |
264 | uint32_t fis_addr_hi; |
265 | uint32_t irq_stat; |
266 | uint32_t irq_mask; |
267 | uint32_t cmd; |
268 | uint32_t unused0; |
269 | uint32_t tfdata; |
270 | uint32_t sig; |
271 | uint32_t scr_stat; |
272 | uint32_t scr_ctl; |
273 | uint32_t scr_err; |
274 | uint32_t scr_act; |
275 | uint32_t cmd_issue; |
276 | uint32_t reserved; |
277 | } AHCIPortRegs; |
278 | |
279 | typedef struct AHCICmdHdr { |
280 | uint16_t opts; |
281 | uint16_t prdtl; |
282 | uint32_t status; |
283 | uint64_t tbl_addr; |
284 | uint32_t reserved[4]; |
285 | } QEMU_PACKED AHCICmdHdr; |
286 | |
287 | typedef struct AHCI_SG { |
288 | uint64_t addr; |
289 | uint32_t reserved; |
290 | uint32_t flags_size; |
291 | } QEMU_PACKED AHCI_SG; |
292 | |
293 | typedef struct NCQTransferState { |
294 | AHCIDevice *drive; |
295 | BlockAIOCB *aiocb; |
296 | AHCICmdHdr *cmdh; |
297 | QEMUSGList sglist; |
298 | BlockAcctCookie acct; |
299 | uint32_t sector_count; |
300 | uint64_t lba; |
301 | uint8_t tag; |
302 | uint8_t cmd; |
303 | uint8_t slot; |
304 | bool used; |
305 | bool halt; |
306 | } NCQTransferState; |
307 | |
308 | struct AHCIDevice { |
309 | IDEDMA dma; |
310 | IDEBus port; |
311 | int port_no; |
312 | uint32_t port_state; |
313 | uint32_t finished; |
314 | AHCIPortRegs port_regs; |
315 | struct AHCIState *hba; |
316 | QEMUBH *check_bh; |
317 | uint8_t *lst; |
318 | uint8_t *res_fis; |
319 | bool done_first_drq; |
320 | int32_t busy_slot; |
321 | bool init_d2h_sent; |
322 | AHCICmdHdr *cur_cmd; |
323 | NCQTransferState ncq_tfs[AHCI_MAX_CMDS]; |
324 | }; |
325 | |
326 | struct AHCIPCIState { |
327 | /*< private >*/ |
328 | PCIDevice parent_obj; |
329 | /*< public >*/ |
330 | |
331 | AHCIState ahci; |
332 | }; |
333 | |
334 | #define ICH_AHCI(obj) \ |
335 | OBJECT_CHECK(AHCIPCIState, (obj), TYPE_ICH9_AHCI) |
336 | |
337 | extern const VMStateDescription vmstate_ahci; |
338 | |
339 | #define VMSTATE_AHCI(_field, _state) { \ |
340 | .name = (stringify(_field)), \ |
341 | .size = sizeof(AHCIState), \ |
342 | .vmsd = &vmstate_ahci, \ |
343 | .flags = VMS_STRUCT, \ |
344 | .offset = vmstate_offset_value(_state, _field, AHCIState), \ |
345 | } |
346 | |
347 | /** |
348 | * NCQFrame is the same as a Register H2D FIS (described in SATA 3.2), |
349 | * but some fields have been re-mapped and re-purposed, as seen in |
350 | * SATA 3.2 section 13.6.4.1 ("READ FPDMA QUEUED") |
351 | * |
352 | * cmd_fis[3], feature 7:0, becomes sector count 7:0. |
353 | * cmd_fis[7], device 7:0, uses bit 7 as the Force Unit Access bit. |
354 | * cmd_fis[11], feature 15:8, becomes sector count 15:8. |
355 | * cmd_fis[12], count 7:0, becomes the NCQ TAG (7:3) and RARC bit (0) |
356 | * cmd_fis[13], count 15:8, becomes the priority value (7:6) |
357 | * bytes 16-19 become an le32 "auxiliary" field. |
358 | */ |
359 | typedef struct NCQFrame { |
360 | uint8_t fis_type; |
361 | uint8_t c; |
362 | uint8_t command; |
363 | uint8_t sector_count_low; /* (feature 7:0) */ |
364 | uint8_t lba0; |
365 | uint8_t lba1; |
366 | uint8_t lba2; |
367 | uint8_t fua; /* (device 7:0) */ |
368 | uint8_t lba3; |
369 | uint8_t lba4; |
370 | uint8_t lba5; |
371 | uint8_t sector_count_high; /* (feature 15:8) */ |
372 | uint8_t tag; /* (count 0:7) */ |
373 | uint8_t prio; /* (count 15:8) */ |
374 | uint8_t icc; |
375 | uint8_t control; |
376 | uint8_t aux0; |
377 | uint8_t aux1; |
378 | uint8_t aux2; |
379 | uint8_t aux3; |
380 | } QEMU_PACKED NCQFrame; |
381 | |
382 | typedef struct SDBFIS { |
383 | uint8_t type; |
384 | uint8_t flags; |
385 | uint8_t status; |
386 | uint8_t error; |
387 | uint32_t payload; |
388 | } QEMU_PACKED SDBFIS; |
389 | |
390 | void ahci_realize(AHCIState *s, DeviceState *qdev, AddressSpace *as, int ports); |
391 | void ahci_init(AHCIState *s, DeviceState *qdev); |
392 | void ahci_uninit(AHCIState *s); |
393 | |
394 | void ahci_reset(AHCIState *s); |
395 | |
396 | #define SYSBUS_AHCI(obj) OBJECT_CHECK(SysbusAHCIState, (obj), TYPE_SYSBUS_AHCI) |
397 | |
398 | #endif /* HW_IDE_AHCI_INTERNAL_H */ |
399 | |