1/*
2 * QEMU 8259 - common bits of emulated and KVM kernel model
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 * Copyright (c) 2011 Jan Kiszka, Siemens AG
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25
26#include "qemu/osdep.h"
27#include "hw/i386/pc.h"
28#include "hw/isa/i8259_internal.h"
29#include "hw/qdev-properties.h"
30#include "migration/vmstate.h"
31#include "monitor/monitor.h"
32
33static int irq_level[16];
34static uint64_t irq_count[16];
35
36void pic_reset_common(PICCommonState *s)
37{
38 s->last_irr = 0;
39 s->irr &= s->elcr;
40 s->imr = 0;
41 s->isr = 0;
42 s->priority_add = 0;
43 s->irq_base = 0;
44 s->read_reg_select = 0;
45 s->poll = 0;
46 s->special_mask = 0;
47 s->init_state = 0;
48 s->auto_eoi = 0;
49 s->rotate_on_auto_eoi = 0;
50 s->special_fully_nested_mode = 0;
51 s->init4 = 0;
52 s->single_mode = 0;
53 /* Note: ELCR is not reset */
54}
55
56static int pic_dispatch_pre_save(void *opaque)
57{
58 PICCommonState *s = opaque;
59 PICCommonClass *info = PIC_COMMON_GET_CLASS(s);
60
61 if (info->pre_save) {
62 info->pre_save(s);
63 }
64
65 return 0;
66}
67
68static int pic_dispatch_post_load(void *opaque, int version_id)
69{
70 PICCommonState *s = opaque;
71 PICCommonClass *info = PIC_COMMON_GET_CLASS(s);
72
73 if (info->post_load) {
74 info->post_load(s);
75 }
76 return 0;
77}
78
79static void pic_common_realize(DeviceState *dev, Error **errp)
80{
81 PICCommonState *s = PIC_COMMON(dev);
82 ISADevice *isa = ISA_DEVICE(dev);
83
84 isa_register_ioport(isa, &s->base_io, s->iobase);
85 if (s->elcr_addr != -1) {
86 isa_register_ioport(isa, &s->elcr_io, s->elcr_addr);
87 }
88
89 qdev_set_legacy_instance_id(dev, s->iobase, 1);
90}
91
92ISADevice *i8259_init_chip(const char *name, ISABus *bus, bool master)
93{
94 DeviceState *dev;
95 ISADevice *isadev;
96
97 isadev = isa_create(bus, name);
98 dev = DEVICE(isadev);
99 qdev_prop_set_uint32(dev, "iobase", master ? 0x20 : 0xa0);
100 qdev_prop_set_uint32(dev, "elcr_addr", master ? 0x4d0 : 0x4d1);
101 qdev_prop_set_uint8(dev, "elcr_mask", master ? 0xf8 : 0xde);
102 qdev_prop_set_bit(dev, "master", master);
103 qdev_init_nofail(dev);
104
105 return isadev;
106}
107
108void pic_stat_update_irq(int irq, int level)
109{
110 if (level != irq_level[irq]) {
111 irq_level[irq] = level;
112 if (level == 1) {
113 irq_count[irq]++;
114 }
115 }
116}
117
118bool pic_get_statistics(InterruptStatsProvider *obj,
119 uint64_t **irq_counts, unsigned int *nb_irqs)
120{
121 PICCommonState *s = PIC_COMMON(obj);
122
123 if (s->master) {
124 *irq_counts = irq_count;
125 *nb_irqs = ARRAY_SIZE(irq_count);
126 } else {
127 *irq_counts = NULL;
128 *nb_irqs = 0;
129 }
130
131 return true;
132}
133
134void pic_print_info(InterruptStatsProvider *obj, Monitor *mon)
135{
136 PICCommonState *s = PIC_COMMON(obj);
137
138 pic_dispatch_pre_save(s);
139 monitor_printf(mon, "pic%d: irr=%02x imr=%02x isr=%02x hprio=%d "
140 "irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n",
141 s->master ? 0 : 1, s->irr, s->imr, s->isr, s->priority_add,
142 s->irq_base, s->read_reg_select, s->elcr,
143 s->special_fully_nested_mode);
144}
145
146static const VMStateDescription vmstate_pic_common = {
147 .name = "i8259",
148 .version_id = 1,
149 .minimum_version_id = 1,
150 .pre_save = pic_dispatch_pre_save,
151 .post_load = pic_dispatch_post_load,
152 .fields = (VMStateField[]) {
153 VMSTATE_UINT8(last_irr, PICCommonState),
154 VMSTATE_UINT8(irr, PICCommonState),
155 VMSTATE_UINT8(imr, PICCommonState),
156 VMSTATE_UINT8(isr, PICCommonState),
157 VMSTATE_UINT8(priority_add, PICCommonState),
158 VMSTATE_UINT8(irq_base, PICCommonState),
159 VMSTATE_UINT8(read_reg_select, PICCommonState),
160 VMSTATE_UINT8(poll, PICCommonState),
161 VMSTATE_UINT8(special_mask, PICCommonState),
162 VMSTATE_UINT8(init_state, PICCommonState),
163 VMSTATE_UINT8(auto_eoi, PICCommonState),
164 VMSTATE_UINT8(rotate_on_auto_eoi, PICCommonState),
165 VMSTATE_UINT8(special_fully_nested_mode, PICCommonState),
166 VMSTATE_UINT8(init4, PICCommonState),
167 VMSTATE_UINT8(single_mode, PICCommonState),
168 VMSTATE_UINT8(elcr, PICCommonState),
169 VMSTATE_END_OF_LIST()
170 }
171};
172
173static Property pic_properties_common[] = {
174 DEFINE_PROP_UINT32("iobase", PICCommonState, iobase, -1),
175 DEFINE_PROP_UINT32("elcr_addr", PICCommonState, elcr_addr, -1),
176 DEFINE_PROP_UINT8("elcr_mask", PICCommonState, elcr_mask, -1),
177 DEFINE_PROP_BIT("master", PICCommonState, master, 0, false),
178 DEFINE_PROP_END_OF_LIST(),
179};
180
181static void pic_common_class_init(ObjectClass *klass, void *data)
182{
183 DeviceClass *dc = DEVICE_CLASS(klass);
184 InterruptStatsProviderClass *ic = INTERRUPT_STATS_PROVIDER_CLASS(klass);
185
186 dc->vmsd = &vmstate_pic_common;
187 dc->props = pic_properties_common;
188 dc->realize = pic_common_realize;
189 /*
190 * Reason: unlike ordinary ISA devices, the PICs need additional
191 * wiring: its IRQ input lines are set up by board code, and the
192 * wiring of the slave to the master is hard-coded in device model
193 * code.
194 */
195 dc->user_creatable = false;
196 ic->get_statistics = pic_get_statistics;
197 ic->print_info = pic_print_info;
198}
199
200static const TypeInfo pic_common_type = {
201 .name = TYPE_PIC_COMMON,
202 .parent = TYPE_ISA_DEVICE,
203 .instance_size = sizeof(PICCommonState),
204 .class_size = sizeof(PICCommonClass),
205 .class_init = pic_common_class_init,
206 .abstract = true,
207 .interfaces = (InterfaceInfo[]) {
208 { TYPE_INTERRUPT_STATS_PROVIDER },
209 { }
210 },
211};
212
213static void pic_common_register_types(void)
214{
215 type_register_static(&pic_common_type);
216}
217
218type_init(pic_common_register_types)
219