1 | #ifndef MPTSAS_H |
---|---|
2 | #define MPTSAS_H |
3 | |
4 | #include "mpi.h" |
5 | |
6 | #define MPTSAS_NUM_PORTS 8 |
7 | #define MPTSAS_MAX_FRAMES 2048 /* Firmware limit at 65535 */ |
8 | |
9 | #define MPTSAS_REQUEST_QUEUE_DEPTH 128 |
10 | #define MPTSAS_REPLY_QUEUE_DEPTH 128 |
11 | |
12 | #define MPTSAS_MAXIMUM_CHAIN_DEPTH 0x22 |
13 | |
14 | typedef struct MPTSASState MPTSASState; |
15 | typedef struct MPTSASRequest MPTSASRequest; |
16 | |
17 | enum { |
18 | DOORBELL_NONE, |
19 | DOORBELL_WRITE, |
20 | DOORBELL_READ |
21 | }; |
22 | |
23 | struct MPTSASState { |
24 | PCIDevice dev; |
25 | MemoryRegion mmio_io; |
26 | MemoryRegion port_io; |
27 | MemoryRegion diag_io; |
28 | QEMUBH *request_bh; |
29 | |
30 | /* properties */ |
31 | OnOffAuto msi; |
32 | uint64_t sas_addr; |
33 | |
34 | bool msi_in_use; |
35 | |
36 | /* Doorbell register */ |
37 | uint32_t state; |
38 | uint8_t who_init; |
39 | uint8_t doorbell_state; |
40 | |
41 | /* Buffer for requests that are sent through the doorbell register. */ |
42 | uint32_t doorbell_msg[256]; |
43 | int doorbell_idx; |
44 | int doorbell_cnt; |
45 | |
46 | uint16_t doorbell_reply[256]; |
47 | int doorbell_reply_idx; |
48 | int doorbell_reply_size; |
49 | |
50 | /* Other registers */ |
51 | uint8_t diagnostic_idx; |
52 | uint32_t diagnostic; |
53 | uint32_t intr_mask; |
54 | uint32_t intr_status; |
55 | |
56 | /* Request queues */ |
57 | uint32_t request_post[MPTSAS_REQUEST_QUEUE_DEPTH + 1]; |
58 | uint16_t request_post_head; |
59 | uint16_t request_post_tail; |
60 | |
61 | uint32_t reply_post[MPTSAS_REPLY_QUEUE_DEPTH + 1]; |
62 | uint16_t reply_post_head; |
63 | uint16_t reply_post_tail; |
64 | |
65 | uint32_t reply_free[MPTSAS_REPLY_QUEUE_DEPTH + 1]; |
66 | uint16_t reply_free_head; |
67 | uint16_t reply_free_tail; |
68 | |
69 | /* IOC Facts */ |
70 | hwaddr host_mfa_high_addr; |
71 | hwaddr sense_buffer_high_addr; |
72 | uint16_t max_devices; |
73 | uint16_t max_buses; |
74 | uint16_t reply_frame_size; |
75 | |
76 | SCSIBus bus; |
77 | QTAILQ_HEAD(, MPTSASRequest) pending; |
78 | }; |
79 | |
80 | void mptsas_fix_scsi_io_endianness(MPIMsgSCSIIORequest *req); |
81 | void mptsas_fix_scsi_io_reply_endianness(MPIMsgSCSIIOReply *reply); |
82 | void mptsas_fix_scsi_task_mgmt_endianness(MPIMsgSCSITaskMgmt *req); |
83 | void mptsas_fix_scsi_task_mgmt_reply_endianness(MPIMsgSCSITaskMgmtReply *reply); |
84 | void mptsas_fix_ioc_init_endianness(MPIMsgIOCInit *req); |
85 | void mptsas_fix_ioc_init_reply_endianness(MPIMsgIOCInitReply *reply); |
86 | void mptsas_fix_ioc_facts_endianness(MPIMsgIOCFacts *req); |
87 | void mptsas_fix_ioc_facts_reply_endianness(MPIMsgIOCFactsReply *reply); |
88 | void mptsas_fix_config_endianness(MPIMsgConfig *req); |
89 | void mptsas_fix_config_reply_endianness(MPIMsgConfigReply *reply); |
90 | void mptsas_fix_port_facts_endianness(MPIMsgPortFacts *req); |
91 | void mptsas_fix_port_facts_reply_endianness(MPIMsgPortFactsReply *reply); |
92 | void mptsas_fix_port_enable_endianness(MPIMsgPortEnable *req); |
93 | void mptsas_fix_port_enable_reply_endianness(MPIMsgPortEnableReply *reply); |
94 | void mptsas_fix_event_notification_endianness(MPIMsgEventNotify *req); |
95 | void mptsas_fix_event_notification_reply_endianness(MPIMsgEventNotifyReply *reply); |
96 | |
97 | void mptsas_reply(MPTSASState *s, MPIDefaultReply *reply); |
98 | |
99 | void mptsas_process_config(MPTSASState *s, MPIMsgConfig *req); |
100 | |
101 | #endif /* MPTSAS_H */ |
102 |