1#ifndef BLOCK_NVME_H
2#define BLOCK_NVME_H
3
4typedef struct NvmeBar {
5 uint64_t cap;
6 uint32_t vs;
7 uint32_t intms;
8 uint32_t intmc;
9 uint32_t cc;
10 uint32_t rsvd1;
11 uint32_t csts;
12 uint32_t nssrc;
13 uint32_t aqa;
14 uint64_t asq;
15 uint64_t acq;
16 uint32_t cmbloc;
17 uint32_t cmbsz;
18} NvmeBar;
19
20enum NvmeCapShift {
21 CAP_MQES_SHIFT = 0,
22 CAP_CQR_SHIFT = 16,
23 CAP_AMS_SHIFT = 17,
24 CAP_TO_SHIFT = 24,
25 CAP_DSTRD_SHIFT = 32,
26 CAP_NSSRS_SHIFT = 33,
27 CAP_CSS_SHIFT = 37,
28 CAP_MPSMIN_SHIFT = 48,
29 CAP_MPSMAX_SHIFT = 52,
30};
31
32enum NvmeCapMask {
33 CAP_MQES_MASK = 0xffff,
34 CAP_CQR_MASK = 0x1,
35 CAP_AMS_MASK = 0x3,
36 CAP_TO_MASK = 0xff,
37 CAP_DSTRD_MASK = 0xf,
38 CAP_NSSRS_MASK = 0x1,
39 CAP_CSS_MASK = 0xff,
40 CAP_MPSMIN_MASK = 0xf,
41 CAP_MPSMAX_MASK = 0xf,
42};
43
44#define NVME_CAP_MQES(cap) (((cap) >> CAP_MQES_SHIFT) & CAP_MQES_MASK)
45#define NVME_CAP_CQR(cap) (((cap) >> CAP_CQR_SHIFT) & CAP_CQR_MASK)
46#define NVME_CAP_AMS(cap) (((cap) >> CAP_AMS_SHIFT) & CAP_AMS_MASK)
47#define NVME_CAP_TO(cap) (((cap) >> CAP_TO_SHIFT) & CAP_TO_MASK)
48#define NVME_CAP_DSTRD(cap) (((cap) >> CAP_DSTRD_SHIFT) & CAP_DSTRD_MASK)
49#define NVME_CAP_NSSRS(cap) (((cap) >> CAP_NSSRS_SHIFT) & CAP_NSSRS_MASK)
50#define NVME_CAP_CSS(cap) (((cap) >> CAP_CSS_SHIFT) & CAP_CSS_MASK)
51#define NVME_CAP_MPSMIN(cap)(((cap) >> CAP_MPSMIN_SHIFT) & CAP_MPSMIN_MASK)
52#define NVME_CAP_MPSMAX(cap)(((cap) >> CAP_MPSMAX_SHIFT) & CAP_MPSMAX_MASK)
53
54#define NVME_CAP_SET_MQES(cap, val) (cap |= (uint64_t)(val & CAP_MQES_MASK) \
55 << CAP_MQES_SHIFT)
56#define NVME_CAP_SET_CQR(cap, val) (cap |= (uint64_t)(val & CAP_CQR_MASK) \
57 << CAP_CQR_SHIFT)
58#define NVME_CAP_SET_AMS(cap, val) (cap |= (uint64_t)(val & CAP_AMS_MASK) \
59 << CAP_AMS_SHIFT)
60#define NVME_CAP_SET_TO(cap, val) (cap |= (uint64_t)(val & CAP_TO_MASK) \
61 << CAP_TO_SHIFT)
62#define NVME_CAP_SET_DSTRD(cap, val) (cap |= (uint64_t)(val & CAP_DSTRD_MASK) \
63 << CAP_DSTRD_SHIFT)
64#define NVME_CAP_SET_NSSRS(cap, val) (cap |= (uint64_t)(val & CAP_NSSRS_MASK) \
65 << CAP_NSSRS_SHIFT)
66#define NVME_CAP_SET_CSS(cap, val) (cap |= (uint64_t)(val & CAP_CSS_MASK) \
67 << CAP_CSS_SHIFT)
68#define NVME_CAP_SET_MPSMIN(cap, val) (cap |= (uint64_t)(val & CAP_MPSMIN_MASK)\
69 << CAP_MPSMIN_SHIFT)
70#define NVME_CAP_SET_MPSMAX(cap, val) (cap |= (uint64_t)(val & CAP_MPSMAX_MASK)\
71 << CAP_MPSMAX_SHIFT)
72
73enum NvmeCcShift {
74 CC_EN_SHIFT = 0,
75 CC_CSS_SHIFT = 4,
76 CC_MPS_SHIFT = 7,
77 CC_AMS_SHIFT = 11,
78 CC_SHN_SHIFT = 14,
79 CC_IOSQES_SHIFT = 16,
80 CC_IOCQES_SHIFT = 20,
81};
82
83enum NvmeCcMask {
84 CC_EN_MASK = 0x1,
85 CC_CSS_MASK = 0x7,
86 CC_MPS_MASK = 0xf,
87 CC_AMS_MASK = 0x7,
88 CC_SHN_MASK = 0x3,
89 CC_IOSQES_MASK = 0xf,
90 CC_IOCQES_MASK = 0xf,
91};
92
93#define NVME_CC_EN(cc) ((cc >> CC_EN_SHIFT) & CC_EN_MASK)
94#define NVME_CC_CSS(cc) ((cc >> CC_CSS_SHIFT) & CC_CSS_MASK)
95#define NVME_CC_MPS(cc) ((cc >> CC_MPS_SHIFT) & CC_MPS_MASK)
96#define NVME_CC_AMS(cc) ((cc >> CC_AMS_SHIFT) & CC_AMS_MASK)
97#define NVME_CC_SHN(cc) ((cc >> CC_SHN_SHIFT) & CC_SHN_MASK)
98#define NVME_CC_IOSQES(cc) ((cc >> CC_IOSQES_SHIFT) & CC_IOSQES_MASK)
99#define NVME_CC_IOCQES(cc) ((cc >> CC_IOCQES_SHIFT) & CC_IOCQES_MASK)
100
101enum NvmeCstsShift {
102 CSTS_RDY_SHIFT = 0,
103 CSTS_CFS_SHIFT = 1,
104 CSTS_SHST_SHIFT = 2,
105 CSTS_NSSRO_SHIFT = 4,
106};
107
108enum NvmeCstsMask {
109 CSTS_RDY_MASK = 0x1,
110 CSTS_CFS_MASK = 0x1,
111 CSTS_SHST_MASK = 0x3,
112 CSTS_NSSRO_MASK = 0x1,
113};
114
115enum NvmeCsts {
116 NVME_CSTS_READY = 1 << CSTS_RDY_SHIFT,
117 NVME_CSTS_FAILED = 1 << CSTS_CFS_SHIFT,
118 NVME_CSTS_SHST_NORMAL = 0 << CSTS_SHST_SHIFT,
119 NVME_CSTS_SHST_PROGRESS = 1 << CSTS_SHST_SHIFT,
120 NVME_CSTS_SHST_COMPLETE = 2 << CSTS_SHST_SHIFT,
121 NVME_CSTS_NSSRO = 1 << CSTS_NSSRO_SHIFT,
122};
123
124#define NVME_CSTS_RDY(csts) ((csts >> CSTS_RDY_SHIFT) & CSTS_RDY_MASK)
125#define NVME_CSTS_CFS(csts) ((csts >> CSTS_CFS_SHIFT) & CSTS_CFS_MASK)
126#define NVME_CSTS_SHST(csts) ((csts >> CSTS_SHST_SHIFT) & CSTS_SHST_MASK)
127#define NVME_CSTS_NSSRO(csts) ((csts >> CSTS_NSSRO_SHIFT) & CSTS_NSSRO_MASK)
128
129enum NvmeAqaShift {
130 AQA_ASQS_SHIFT = 0,
131 AQA_ACQS_SHIFT = 16,
132};
133
134enum NvmeAqaMask {
135 AQA_ASQS_MASK = 0xfff,
136 AQA_ACQS_MASK = 0xfff,
137};
138
139#define NVME_AQA_ASQS(aqa) ((aqa >> AQA_ASQS_SHIFT) & AQA_ASQS_MASK)
140#define NVME_AQA_ACQS(aqa) ((aqa >> AQA_ACQS_SHIFT) & AQA_ACQS_MASK)
141
142enum NvmeCmblocShift {
143 CMBLOC_BIR_SHIFT = 0,
144 CMBLOC_OFST_SHIFT = 12,
145};
146
147enum NvmeCmblocMask {
148 CMBLOC_BIR_MASK = 0x7,
149 CMBLOC_OFST_MASK = 0xfffff,
150};
151
152#define NVME_CMBLOC_BIR(cmbloc) ((cmbloc >> CMBLOC_BIR_SHIFT) & \
153 CMBLOC_BIR_MASK)
154#define NVME_CMBLOC_OFST(cmbloc)((cmbloc >> CMBLOC_OFST_SHIFT) & \
155 CMBLOC_OFST_MASK)
156
157#define NVME_CMBLOC_SET_BIR(cmbloc, val) \
158 (cmbloc |= (uint64_t)(val & CMBLOC_BIR_MASK) << CMBLOC_BIR_SHIFT)
159#define NVME_CMBLOC_SET_OFST(cmbloc, val) \
160 (cmbloc |= (uint64_t)(val & CMBLOC_OFST_MASK) << CMBLOC_OFST_SHIFT)
161
162enum NvmeCmbszShift {
163 CMBSZ_SQS_SHIFT = 0,
164 CMBSZ_CQS_SHIFT = 1,
165 CMBSZ_LISTS_SHIFT = 2,
166 CMBSZ_RDS_SHIFT = 3,
167 CMBSZ_WDS_SHIFT = 4,
168 CMBSZ_SZU_SHIFT = 8,
169 CMBSZ_SZ_SHIFT = 12,
170};
171
172enum NvmeCmbszMask {
173 CMBSZ_SQS_MASK = 0x1,
174 CMBSZ_CQS_MASK = 0x1,
175 CMBSZ_LISTS_MASK = 0x1,
176 CMBSZ_RDS_MASK = 0x1,
177 CMBSZ_WDS_MASK = 0x1,
178 CMBSZ_SZU_MASK = 0xf,
179 CMBSZ_SZ_MASK = 0xfffff,
180};
181
182#define NVME_CMBSZ_SQS(cmbsz) ((cmbsz >> CMBSZ_SQS_SHIFT) & CMBSZ_SQS_MASK)
183#define NVME_CMBSZ_CQS(cmbsz) ((cmbsz >> CMBSZ_CQS_SHIFT) & CMBSZ_CQS_MASK)
184#define NVME_CMBSZ_LISTS(cmbsz)((cmbsz >> CMBSZ_LISTS_SHIFT) & CMBSZ_LISTS_MASK)
185#define NVME_CMBSZ_RDS(cmbsz) ((cmbsz >> CMBSZ_RDS_SHIFT) & CMBSZ_RDS_MASK)
186#define NVME_CMBSZ_WDS(cmbsz) ((cmbsz >> CMBSZ_WDS_SHIFT) & CMBSZ_WDS_MASK)
187#define NVME_CMBSZ_SZU(cmbsz) ((cmbsz >> CMBSZ_SZU_SHIFT) & CMBSZ_SZU_MASK)
188#define NVME_CMBSZ_SZ(cmbsz) ((cmbsz >> CMBSZ_SZ_SHIFT) & CMBSZ_SZ_MASK)
189
190#define NVME_CMBSZ_SET_SQS(cmbsz, val) \
191 (cmbsz |= (uint64_t)(val & CMBSZ_SQS_MASK) << CMBSZ_SQS_SHIFT)
192#define NVME_CMBSZ_SET_CQS(cmbsz, val) \
193 (cmbsz |= (uint64_t)(val & CMBSZ_CQS_MASK) << CMBSZ_CQS_SHIFT)
194#define NVME_CMBSZ_SET_LISTS(cmbsz, val) \
195 (cmbsz |= (uint64_t)(val & CMBSZ_LISTS_MASK) << CMBSZ_LISTS_SHIFT)
196#define NVME_CMBSZ_SET_RDS(cmbsz, val) \
197 (cmbsz |= (uint64_t)(val & CMBSZ_RDS_MASK) << CMBSZ_RDS_SHIFT)
198#define NVME_CMBSZ_SET_WDS(cmbsz, val) \
199 (cmbsz |= (uint64_t)(val & CMBSZ_WDS_MASK) << CMBSZ_WDS_SHIFT)
200#define NVME_CMBSZ_SET_SZU(cmbsz, val) \
201 (cmbsz |= (uint64_t)(val & CMBSZ_SZU_MASK) << CMBSZ_SZU_SHIFT)
202#define NVME_CMBSZ_SET_SZ(cmbsz, val) \
203 (cmbsz |= (uint64_t)(val & CMBSZ_SZ_MASK) << CMBSZ_SZ_SHIFT)
204
205#define NVME_CMBSZ_GETSIZE(cmbsz) \
206 (NVME_CMBSZ_SZ(cmbsz) * (1 << (12 + 4 * NVME_CMBSZ_SZU(cmbsz))))
207
208typedef struct NvmeCmd {
209 uint8_t opcode;
210 uint8_t fuse;
211 uint16_t cid;
212 uint32_t nsid;
213 uint64_t res1;
214 uint64_t mptr;
215 uint64_t prp1;
216 uint64_t prp2;
217 uint32_t cdw10;
218 uint32_t cdw11;
219 uint32_t cdw12;
220 uint32_t cdw13;
221 uint32_t cdw14;
222 uint32_t cdw15;
223} NvmeCmd;
224
225enum NvmeAdminCommands {
226 NVME_ADM_CMD_DELETE_SQ = 0x00,
227 NVME_ADM_CMD_CREATE_SQ = 0x01,
228 NVME_ADM_CMD_GET_LOG_PAGE = 0x02,
229 NVME_ADM_CMD_DELETE_CQ = 0x04,
230 NVME_ADM_CMD_CREATE_CQ = 0x05,
231 NVME_ADM_CMD_IDENTIFY = 0x06,
232 NVME_ADM_CMD_ABORT = 0x08,
233 NVME_ADM_CMD_SET_FEATURES = 0x09,
234 NVME_ADM_CMD_GET_FEATURES = 0x0a,
235 NVME_ADM_CMD_ASYNC_EV_REQ = 0x0c,
236 NVME_ADM_CMD_ACTIVATE_FW = 0x10,
237 NVME_ADM_CMD_DOWNLOAD_FW = 0x11,
238 NVME_ADM_CMD_FORMAT_NVM = 0x80,
239 NVME_ADM_CMD_SECURITY_SEND = 0x81,
240 NVME_ADM_CMD_SECURITY_RECV = 0x82,
241};
242
243enum NvmeIoCommands {
244 NVME_CMD_FLUSH = 0x00,
245 NVME_CMD_WRITE = 0x01,
246 NVME_CMD_READ = 0x02,
247 NVME_CMD_WRITE_UNCOR = 0x04,
248 NVME_CMD_COMPARE = 0x05,
249 NVME_CMD_WRITE_ZEROS = 0x08,
250 NVME_CMD_DSM = 0x09,
251};
252
253typedef struct NvmeDeleteQ {
254 uint8_t opcode;
255 uint8_t flags;
256 uint16_t cid;
257 uint32_t rsvd1[9];
258 uint16_t qid;
259 uint16_t rsvd10;
260 uint32_t rsvd11[5];
261} NvmeDeleteQ;
262
263typedef struct NvmeCreateCq {
264 uint8_t opcode;
265 uint8_t flags;
266 uint16_t cid;
267 uint32_t rsvd1[5];
268 uint64_t prp1;
269 uint64_t rsvd8;
270 uint16_t cqid;
271 uint16_t qsize;
272 uint16_t cq_flags;
273 uint16_t irq_vector;
274 uint32_t rsvd12[4];
275} NvmeCreateCq;
276
277#define NVME_CQ_FLAGS_PC(cq_flags) (cq_flags & 0x1)
278#define NVME_CQ_FLAGS_IEN(cq_flags) ((cq_flags >> 1) & 0x1)
279
280typedef struct NvmeCreateSq {
281 uint8_t opcode;
282 uint8_t flags;
283 uint16_t cid;
284 uint32_t rsvd1[5];
285 uint64_t prp1;
286 uint64_t rsvd8;
287 uint16_t sqid;
288 uint16_t qsize;
289 uint16_t sq_flags;
290 uint16_t cqid;
291 uint32_t rsvd12[4];
292} NvmeCreateSq;
293
294#define NVME_SQ_FLAGS_PC(sq_flags) (sq_flags & 0x1)
295#define NVME_SQ_FLAGS_QPRIO(sq_flags) ((sq_flags >> 1) & 0x3)
296
297enum NvmeQueueFlags {
298 NVME_Q_PC = 1,
299 NVME_Q_PRIO_URGENT = 0,
300 NVME_Q_PRIO_HIGH = 1,
301 NVME_Q_PRIO_NORMAL = 2,
302 NVME_Q_PRIO_LOW = 3,
303};
304
305typedef struct NvmeIdentify {
306 uint8_t opcode;
307 uint8_t flags;
308 uint16_t cid;
309 uint32_t nsid;
310 uint64_t rsvd2[2];
311 uint64_t prp1;
312 uint64_t prp2;
313 uint32_t cns;
314 uint32_t rsvd11[5];
315} NvmeIdentify;
316
317typedef struct NvmeRwCmd {
318 uint8_t opcode;
319 uint8_t flags;
320 uint16_t cid;
321 uint32_t nsid;
322 uint64_t rsvd2;
323 uint64_t mptr;
324 uint64_t prp1;
325 uint64_t prp2;
326 uint64_t slba;
327 uint16_t nlb;
328 uint16_t control;
329 uint32_t dsmgmt;
330 uint32_t reftag;
331 uint16_t apptag;
332 uint16_t appmask;
333} NvmeRwCmd;
334
335enum {
336 NVME_RW_LR = 1 << 15,
337 NVME_RW_FUA = 1 << 14,
338 NVME_RW_DSM_FREQ_UNSPEC = 0,
339 NVME_RW_DSM_FREQ_TYPICAL = 1,
340 NVME_RW_DSM_FREQ_RARE = 2,
341 NVME_RW_DSM_FREQ_READS = 3,
342 NVME_RW_DSM_FREQ_WRITES = 4,
343 NVME_RW_DSM_FREQ_RW = 5,
344 NVME_RW_DSM_FREQ_ONCE = 6,
345 NVME_RW_DSM_FREQ_PREFETCH = 7,
346 NVME_RW_DSM_FREQ_TEMP = 8,
347 NVME_RW_DSM_LATENCY_NONE = 0 << 4,
348 NVME_RW_DSM_LATENCY_IDLE = 1 << 4,
349 NVME_RW_DSM_LATENCY_NORM = 2 << 4,
350 NVME_RW_DSM_LATENCY_LOW = 3 << 4,
351 NVME_RW_DSM_SEQ_REQ = 1 << 6,
352 NVME_RW_DSM_COMPRESSED = 1 << 7,
353 NVME_RW_PRINFO_PRACT = 1 << 13,
354 NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12,
355 NVME_RW_PRINFO_PRCHK_APP = 1 << 11,
356 NVME_RW_PRINFO_PRCHK_REF = 1 << 10,
357};
358
359typedef struct NvmeDsmCmd {
360 uint8_t opcode;
361 uint8_t flags;
362 uint16_t cid;
363 uint32_t nsid;
364 uint64_t rsvd2[2];
365 uint64_t prp1;
366 uint64_t prp2;
367 uint32_t nr;
368 uint32_t attributes;
369 uint32_t rsvd12[4];
370} NvmeDsmCmd;
371
372enum {
373 NVME_DSMGMT_IDR = 1 << 0,
374 NVME_DSMGMT_IDW = 1 << 1,
375 NVME_DSMGMT_AD = 1 << 2,
376};
377
378typedef struct NvmeDsmRange {
379 uint32_t cattr;
380 uint32_t nlb;
381 uint64_t slba;
382} NvmeDsmRange;
383
384enum NvmeAsyncEventRequest {
385 NVME_AER_TYPE_ERROR = 0,
386 NVME_AER_TYPE_SMART = 1,
387 NVME_AER_TYPE_IO_SPECIFIC = 6,
388 NVME_AER_TYPE_VENDOR_SPECIFIC = 7,
389 NVME_AER_INFO_ERR_INVALID_SQ = 0,
390 NVME_AER_INFO_ERR_INVALID_DB = 1,
391 NVME_AER_INFO_ERR_DIAG_FAIL = 2,
392 NVME_AER_INFO_ERR_PERS_INTERNAL_ERR = 3,
393 NVME_AER_INFO_ERR_TRANS_INTERNAL_ERR = 4,
394 NVME_AER_INFO_ERR_FW_IMG_LOAD_ERR = 5,
395 NVME_AER_INFO_SMART_RELIABILITY = 0,
396 NVME_AER_INFO_SMART_TEMP_THRESH = 1,
397 NVME_AER_INFO_SMART_SPARE_THRESH = 2,
398};
399
400typedef struct NvmeAerResult {
401 uint8_t event_type;
402 uint8_t event_info;
403 uint8_t log_page;
404 uint8_t resv;
405} NvmeAerResult;
406
407typedef struct NvmeCqe {
408 uint32_t result;
409 uint32_t rsvd;
410 uint16_t sq_head;
411 uint16_t sq_id;
412 uint16_t cid;
413 uint16_t status;
414} NvmeCqe;
415
416enum NvmeStatusCodes {
417 NVME_SUCCESS = 0x0000,
418 NVME_INVALID_OPCODE = 0x0001,
419 NVME_INVALID_FIELD = 0x0002,
420 NVME_CID_CONFLICT = 0x0003,
421 NVME_DATA_TRAS_ERROR = 0x0004,
422 NVME_POWER_LOSS_ABORT = 0x0005,
423 NVME_INTERNAL_DEV_ERROR = 0x0006,
424 NVME_CMD_ABORT_REQ = 0x0007,
425 NVME_CMD_ABORT_SQ_DEL = 0x0008,
426 NVME_CMD_ABORT_FAILED_FUSE = 0x0009,
427 NVME_CMD_ABORT_MISSING_FUSE = 0x000a,
428 NVME_INVALID_NSID = 0x000b,
429 NVME_CMD_SEQ_ERROR = 0x000c,
430 NVME_LBA_RANGE = 0x0080,
431 NVME_CAP_EXCEEDED = 0x0081,
432 NVME_NS_NOT_READY = 0x0082,
433 NVME_NS_RESV_CONFLICT = 0x0083,
434 NVME_INVALID_CQID = 0x0100,
435 NVME_INVALID_QID = 0x0101,
436 NVME_MAX_QSIZE_EXCEEDED = 0x0102,
437 NVME_ACL_EXCEEDED = 0x0103,
438 NVME_RESERVED = 0x0104,
439 NVME_AER_LIMIT_EXCEEDED = 0x0105,
440 NVME_INVALID_FW_SLOT = 0x0106,
441 NVME_INVALID_FW_IMAGE = 0x0107,
442 NVME_INVALID_IRQ_VECTOR = 0x0108,
443 NVME_INVALID_LOG_ID = 0x0109,
444 NVME_INVALID_FORMAT = 0x010a,
445 NVME_FW_REQ_RESET = 0x010b,
446 NVME_INVALID_QUEUE_DEL = 0x010c,
447 NVME_FID_NOT_SAVEABLE = 0x010d,
448 NVME_FID_NOT_NSID_SPEC = 0x010f,
449 NVME_FW_REQ_SUSYSTEM_RESET = 0x0110,
450 NVME_CONFLICTING_ATTRS = 0x0180,
451 NVME_INVALID_PROT_INFO = 0x0181,
452 NVME_WRITE_TO_RO = 0x0182,
453 NVME_WRITE_FAULT = 0x0280,
454 NVME_UNRECOVERED_READ = 0x0281,
455 NVME_E2E_GUARD_ERROR = 0x0282,
456 NVME_E2E_APP_ERROR = 0x0283,
457 NVME_E2E_REF_ERROR = 0x0284,
458 NVME_CMP_FAILURE = 0x0285,
459 NVME_ACCESS_DENIED = 0x0286,
460 NVME_MORE = 0x2000,
461 NVME_DNR = 0x4000,
462 NVME_NO_COMPLETE = 0xffff,
463};
464
465typedef struct NvmeFwSlotInfoLog {
466 uint8_t afi;
467 uint8_t reserved1[7];
468 uint8_t frs1[8];
469 uint8_t frs2[8];
470 uint8_t frs3[8];
471 uint8_t frs4[8];
472 uint8_t frs5[8];
473 uint8_t frs6[8];
474 uint8_t frs7[8];
475 uint8_t reserved2[448];
476} NvmeFwSlotInfoLog;
477
478typedef struct NvmeErrorLog {
479 uint64_t error_count;
480 uint16_t sqid;
481 uint16_t cid;
482 uint16_t status_field;
483 uint16_t param_error_location;
484 uint64_t lba;
485 uint32_t nsid;
486 uint8_t vs;
487 uint8_t resv[35];
488} NvmeErrorLog;
489
490typedef struct NvmeSmartLog {
491 uint8_t critical_warning;
492 uint8_t temperature[2];
493 uint8_t available_spare;
494 uint8_t available_spare_threshold;
495 uint8_t percentage_used;
496 uint8_t reserved1[26];
497 uint64_t data_units_read[2];
498 uint64_t data_units_written[2];
499 uint64_t host_read_commands[2];
500 uint64_t host_write_commands[2];
501 uint64_t controller_busy_time[2];
502 uint64_t power_cycles[2];
503 uint64_t power_on_hours[2];
504 uint64_t unsafe_shutdowns[2];
505 uint64_t media_errors[2];
506 uint64_t number_of_error_log_entries[2];
507 uint8_t reserved2[320];
508} NvmeSmartLog;
509
510enum NvmeSmartWarn {
511 NVME_SMART_SPARE = 1 << 0,
512 NVME_SMART_TEMPERATURE = 1 << 1,
513 NVME_SMART_RELIABILITY = 1 << 2,
514 NVME_SMART_MEDIA_READ_ONLY = 1 << 3,
515 NVME_SMART_FAILED_VOLATILE_MEDIA = 1 << 4,
516};
517
518enum LogIdentifier {
519 NVME_LOG_ERROR_INFO = 0x01,
520 NVME_LOG_SMART_INFO = 0x02,
521 NVME_LOG_FW_SLOT_INFO = 0x03,
522};
523
524typedef struct NvmePSD {
525 uint16_t mp;
526 uint16_t reserved;
527 uint32_t enlat;
528 uint32_t exlat;
529 uint8_t rrt;
530 uint8_t rrl;
531 uint8_t rwt;
532 uint8_t rwl;
533 uint8_t resv[16];
534} NvmePSD;
535
536typedef struct NvmeIdCtrl {
537 uint16_t vid;
538 uint16_t ssvid;
539 uint8_t sn[20];
540 uint8_t mn[40];
541 uint8_t fr[8];
542 uint8_t rab;
543 uint8_t ieee[3];
544 uint8_t cmic;
545 uint8_t mdts;
546 uint8_t rsvd255[178];
547 uint16_t oacs;
548 uint8_t acl;
549 uint8_t aerl;
550 uint8_t frmw;
551 uint8_t lpa;
552 uint8_t elpe;
553 uint8_t npss;
554 uint8_t rsvd511[248];
555 uint8_t sqes;
556 uint8_t cqes;
557 uint16_t rsvd515;
558 uint32_t nn;
559 uint16_t oncs;
560 uint16_t fuses;
561 uint8_t fna;
562 uint8_t vwc;
563 uint16_t awun;
564 uint16_t awupf;
565 uint8_t rsvd703[174];
566 uint8_t rsvd2047[1344];
567 NvmePSD psd[32];
568 uint8_t vs[1024];
569} NvmeIdCtrl;
570
571enum NvmeIdCtrlOacs {
572 NVME_OACS_SECURITY = 1 << 0,
573 NVME_OACS_FORMAT = 1 << 1,
574 NVME_OACS_FW = 1 << 2,
575};
576
577enum NvmeIdCtrlOncs {
578 NVME_ONCS_COMPARE = 1 << 0,
579 NVME_ONCS_WRITE_UNCORR = 1 << 1,
580 NVME_ONCS_DSM = 1 << 2,
581 NVME_ONCS_WRITE_ZEROS = 1 << 3,
582 NVME_ONCS_FEATURES = 1 << 4,
583 NVME_ONCS_RESRVATIONS = 1 << 5,
584 NVME_ONCS_TIMESTAMP = 1 << 6,
585};
586
587#define NVME_CTRL_SQES_MIN(sqes) ((sqes) & 0xf)
588#define NVME_CTRL_SQES_MAX(sqes) (((sqes) >> 4) & 0xf)
589#define NVME_CTRL_CQES_MIN(cqes) ((cqes) & 0xf)
590#define NVME_CTRL_CQES_MAX(cqes) (((cqes) >> 4) & 0xf)
591
592typedef struct NvmeFeatureVal {
593 uint32_t arbitration;
594 uint32_t power_mgmt;
595 uint32_t temp_thresh;
596 uint32_t err_rec;
597 uint32_t volatile_wc;
598 uint32_t num_queues;
599 uint32_t int_coalescing;
600 uint32_t *int_vector_config;
601 uint32_t write_atomicity;
602 uint32_t async_config;
603 uint32_t sw_prog_marker;
604} NvmeFeatureVal;
605
606#define NVME_ARB_AB(arb) (arb & 0x7)
607#define NVME_ARB_LPW(arb) ((arb >> 8) & 0xff)
608#define NVME_ARB_MPW(arb) ((arb >> 16) & 0xff)
609#define NVME_ARB_HPW(arb) ((arb >> 24) & 0xff)
610
611#define NVME_INTC_THR(intc) (intc & 0xff)
612#define NVME_INTC_TIME(intc) ((intc >> 8) & 0xff)
613
614enum NvmeFeatureIds {
615 NVME_ARBITRATION = 0x1,
616 NVME_POWER_MANAGEMENT = 0x2,
617 NVME_LBA_RANGE_TYPE = 0x3,
618 NVME_TEMPERATURE_THRESHOLD = 0x4,
619 NVME_ERROR_RECOVERY = 0x5,
620 NVME_VOLATILE_WRITE_CACHE = 0x6,
621 NVME_NUMBER_OF_QUEUES = 0x7,
622 NVME_INTERRUPT_COALESCING = 0x8,
623 NVME_INTERRUPT_VECTOR_CONF = 0x9,
624 NVME_WRITE_ATOMICITY = 0xa,
625 NVME_ASYNCHRONOUS_EVENT_CONF = 0xb,
626 NVME_TIMESTAMP = 0xe,
627 NVME_SOFTWARE_PROGRESS_MARKER = 0x80
628};
629
630typedef struct NvmeRangeType {
631 uint8_t type;
632 uint8_t attributes;
633 uint8_t rsvd2[14];
634 uint64_t slba;
635 uint64_t nlb;
636 uint8_t guid[16];
637 uint8_t rsvd48[16];
638} NvmeRangeType;
639
640typedef struct NvmeLBAF {
641 uint16_t ms;
642 uint8_t ds;
643 uint8_t rp;
644} NvmeLBAF;
645
646typedef struct NvmeIdNs {
647 uint64_t nsze;
648 uint64_t ncap;
649 uint64_t nuse;
650 uint8_t nsfeat;
651 uint8_t nlbaf;
652 uint8_t flbas;
653 uint8_t mc;
654 uint8_t dpc;
655 uint8_t dps;
656 uint8_t res30[98];
657 NvmeLBAF lbaf[16];
658 uint8_t res192[192];
659 uint8_t vs[3712];
660} NvmeIdNs;
661
662#define NVME_ID_NS_NSFEAT_THIN(nsfeat) ((nsfeat & 0x1))
663#define NVME_ID_NS_FLBAS_EXTENDED(flbas) ((flbas >> 4) & 0x1)
664#define NVME_ID_NS_FLBAS_INDEX(flbas) ((flbas & 0xf))
665#define NVME_ID_NS_MC_SEPARATE(mc) ((mc >> 1) & 0x1)
666#define NVME_ID_NS_MC_EXTENDED(mc) ((mc & 0x1))
667#define NVME_ID_NS_DPC_LAST_EIGHT(dpc) ((dpc >> 4) & 0x1)
668#define NVME_ID_NS_DPC_FIRST_EIGHT(dpc) ((dpc >> 3) & 0x1)
669#define NVME_ID_NS_DPC_TYPE_3(dpc) ((dpc >> 2) & 0x1)
670#define NVME_ID_NS_DPC_TYPE_2(dpc) ((dpc >> 1) & 0x1)
671#define NVME_ID_NS_DPC_TYPE_1(dpc) ((dpc & 0x1))
672#define NVME_ID_NS_DPC_TYPE_MASK 0x7
673
674enum NvmeIdNsDps {
675 DPS_TYPE_NONE = 0,
676 DPS_TYPE_1 = 1,
677 DPS_TYPE_2 = 2,
678 DPS_TYPE_3 = 3,
679 DPS_TYPE_MASK = 0x7,
680 DPS_FIRST_EIGHT = 8,
681};
682
683static inline void _nvme_check_size(void)
684{
685 QEMU_BUILD_BUG_ON(sizeof(NvmeAerResult) != 4);
686 QEMU_BUILD_BUG_ON(sizeof(NvmeCqe) != 16);
687 QEMU_BUILD_BUG_ON(sizeof(NvmeDsmRange) != 16);
688 QEMU_BUILD_BUG_ON(sizeof(NvmeCmd) != 64);
689 QEMU_BUILD_BUG_ON(sizeof(NvmeDeleteQ) != 64);
690 QEMU_BUILD_BUG_ON(sizeof(NvmeCreateCq) != 64);
691 QEMU_BUILD_BUG_ON(sizeof(NvmeCreateSq) != 64);
692 QEMU_BUILD_BUG_ON(sizeof(NvmeIdentify) != 64);
693 QEMU_BUILD_BUG_ON(sizeof(NvmeRwCmd) != 64);
694 QEMU_BUILD_BUG_ON(sizeof(NvmeDsmCmd) != 64);
695 QEMU_BUILD_BUG_ON(sizeof(NvmeRangeType) != 64);
696 QEMU_BUILD_BUG_ON(sizeof(NvmeErrorLog) != 64);
697 QEMU_BUILD_BUG_ON(sizeof(NvmeFwSlotInfoLog) != 512);
698 QEMU_BUILD_BUG_ON(sizeof(NvmeSmartLog) != 512);
699 QEMU_BUILD_BUG_ON(sizeof(NvmeIdCtrl) != 4096);
700 QEMU_BUILD_BUG_ON(sizeof(NvmeIdNs) != 4096);
701}
702#endif
703