1 | /* |
2 | * Samsung exynos4210 SoC emulation |
3 | * |
4 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. All rights reserved. |
5 | * Maksim Kozlov <m.kozlov@samsung.com> |
6 | * Evgeny Voevodin <e.voevodin@samsung.com> |
7 | * Igor Mitsyanko <i.mitsyanko@samsung.com> |
8 | * |
9 | * |
10 | * This program is free software; you can redistribute it and/or modify it |
11 | * under the terms of the GNU General Public License as published by the |
12 | * Free Software Foundation; either version 2 of the License, or |
13 | * (at your option) any later version. |
14 | * |
15 | * This program is distributed in the hope that it will be useful, but WITHOUT |
16 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
17 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
18 | * for more details. |
19 | * |
20 | * You should have received a copy of the GNU General Public License along |
21 | * with this program; if not, see <http://www.gnu.org/licenses/>. |
22 | */ |
23 | |
24 | #ifndef EXYNOS4210_H |
25 | #define EXYNOS4210_H |
26 | |
27 | #include "hw/sysbus.h" |
28 | #include "target/arm/cpu-qom.h" |
29 | |
30 | #define EXYNOS4210_NCPUS 2 |
31 | |
32 | #define EXYNOS4210_DRAM0_BASE_ADDR 0x40000000 |
33 | #define EXYNOS4210_DRAM1_BASE_ADDR 0xa0000000 |
34 | #define EXYNOS4210_DRAM_MAX_SIZE 0x60000000 /* 1.5 GB */ |
35 | |
36 | #define EXYNOS4210_IROM_BASE_ADDR 0x00000000 |
37 | #define EXYNOS4210_IROM_SIZE 0x00010000 /* 64 KB */ |
38 | #define EXYNOS4210_IROM_MIRROR_BASE_ADDR 0x02000000 |
39 | #define EXYNOS4210_IROM_MIRROR_SIZE 0x00010000 /* 64 KB */ |
40 | |
41 | #define EXYNOS4210_IRAM_BASE_ADDR 0x02020000 |
42 | #define EXYNOS4210_IRAM_SIZE 0x00020000 /* 128 KB */ |
43 | |
44 | /* Secondary CPU startup code is in IROM memory */ |
45 | #define EXYNOS4210_SMP_BOOT_ADDR EXYNOS4210_IROM_BASE_ADDR |
46 | #define EXYNOS4210_SMP_BOOT_SIZE 0x1000 |
47 | #define EXYNOS4210_BASE_BOOT_ADDR EXYNOS4210_DRAM0_BASE_ADDR |
48 | /* Secondary CPU polling address to get loader start from */ |
49 | #define EXYNOS4210_SECOND_CPU_BOOTREG 0x10020814 |
50 | |
51 | #define EXYNOS4210_SMP_PRIVATE_BASE_ADDR 0x10500000 |
52 | #define EXYNOS4210_L2X0_BASE_ADDR 0x10502000 |
53 | |
54 | /* |
55 | * exynos4210 IRQ subsystem stub definitions. |
56 | */ |
57 | #define EXYNOS4210_IRQ_GATE_NINPUTS 2 /* Internal and External GIC */ |
58 | |
59 | #define EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ 64 |
60 | #define EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ 16 |
61 | #define EXYNOS4210_MAX_INT_COMBINER_IN_IRQ \ |
62 | (EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ * 8) |
63 | #define EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ \ |
64 | (EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ * 8) |
65 | |
66 | #define EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit) ((grp)*8 + (bit)) |
67 | #define EXYNOS4210_COMBINER_GET_GRP_NUM(irq) ((irq) / 8) |
68 | #define EXYNOS4210_COMBINER_GET_BIT_NUM(irq) \ |
69 | ((irq) - 8 * EXYNOS4210_COMBINER_GET_GRP_NUM(irq)) |
70 | |
71 | /* IRQs number for external and internal GIC */ |
72 | #define EXYNOS4210_EXT_GIC_NIRQ (160-32) |
73 | #define EXYNOS4210_INT_GIC_NIRQ 64 |
74 | |
75 | #define EXYNOS4210_I2C_NUMBER 9 |
76 | |
77 | typedef struct Exynos4210Irq { |
78 | qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ]; |
79 | qemu_irq ext_combiner_irq[EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ]; |
80 | qemu_irq int_gic_irq[EXYNOS4210_INT_GIC_NIRQ]; |
81 | qemu_irq ext_gic_irq[EXYNOS4210_EXT_GIC_NIRQ]; |
82 | qemu_irq board_irqs[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ]; |
83 | } Exynos4210Irq; |
84 | |
85 | typedef struct Exynos4210State { |
86 | /*< private >*/ |
87 | SysBusDevice parent_obj; |
88 | /*< public >*/ |
89 | ARMCPU *cpu[EXYNOS4210_NCPUS]; |
90 | Exynos4210Irq irqs; |
91 | qemu_irq *irq_table; |
92 | |
93 | MemoryRegion chipid_mem; |
94 | MemoryRegion iram_mem; |
95 | MemoryRegion irom_mem; |
96 | MemoryRegion irom_alias_mem; |
97 | MemoryRegion boot_secondary; |
98 | MemoryRegion bootreg_mem; |
99 | I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER]; |
100 | } Exynos4210State; |
101 | |
102 | #define TYPE_EXYNOS4210_SOC "exynos4210" |
103 | #define EXYNOS4210_SOC(obj) \ |
104 | OBJECT_CHECK(Exynos4210State, obj, TYPE_EXYNOS4210_SOC) |
105 | |
106 | void exynos4210_write_secondary(ARMCPU *cpu, |
107 | const struct arm_boot_info *info); |
108 | |
109 | /* Initialize exynos4210 IRQ subsystem stub */ |
110 | qemu_irq *exynos4210_init_irq(Exynos4210Irq *env); |
111 | |
112 | /* Initialize board IRQs. |
113 | * These IRQs contain splitted Int/External Combiner and External Gic IRQs */ |
114 | void exynos4210_init_board_irqs(Exynos4210Irq *s); |
115 | |
116 | /* Get IRQ number from exynos4210 IRQ subsystem stub. |
117 | * To identify IRQ source use internal combiner group and bit number |
118 | * grp - group number |
119 | * bit - bit number inside group */ |
120 | uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit); |
121 | |
122 | /* |
123 | * Get Combiner input GPIO into irqs structure |
124 | */ |
125 | void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs, DeviceState *dev, |
126 | int ext); |
127 | |
128 | /* |
129 | * exynos4210 UART |
130 | */ |
131 | DeviceState *exynos4210_uart_create(hwaddr addr, |
132 | int fifo_size, |
133 | int channel, |
134 | Chardev *chr, |
135 | qemu_irq irq); |
136 | |
137 | #endif /* EXYNOS4210_H */ |
138 | |