1 | /* |
2 | * ASPEED System Control Unit |
3 | * |
4 | * Andrew Jeffery <andrew@aj.id.au> |
5 | * |
6 | * Copyright 2016 IBM Corp. |
7 | * |
8 | * This code is licensed under the GPL version 2 or later. See |
9 | * the COPYING file in the top-level directory. |
10 | */ |
11 | #ifndef ASPEED_SCU_H |
12 | #define ASPEED_SCU_H |
13 | |
14 | #include "hw/sysbus.h" |
15 | |
16 | #define TYPE_ASPEED_SCU "aspeed.scu" |
17 | #define ASPEED_SCU(obj) OBJECT_CHECK(AspeedSCUState, (obj), TYPE_ASPEED_SCU) |
18 | |
19 | #define ASPEED_SCU_NR_REGS (0x1A8 >> 2) |
20 | |
21 | typedef struct AspeedSCUState { |
22 | /*< private >*/ |
23 | SysBusDevice parent_obj; |
24 | |
25 | /*< public >*/ |
26 | MemoryRegion iomem; |
27 | |
28 | uint32_t regs[ASPEED_SCU_NR_REGS]; |
29 | uint32_t silicon_rev; |
30 | uint32_t hw_strap1; |
31 | uint32_t hw_strap2; |
32 | uint32_t hw_prot_key; |
33 | |
34 | uint32_t clkin; |
35 | uint32_t hpll; |
36 | uint32_t apb_freq; |
37 | } AspeedSCUState; |
38 | |
39 | #define AST2400_A0_SILICON_REV 0x02000303U |
40 | #define AST2400_A1_SILICON_REV 0x02010303U |
41 | #define AST2500_A0_SILICON_REV 0x04000303U |
42 | #define AST2500_A1_SILICON_REV 0x04010303U |
43 | |
44 | #define ASPEED_IS_AST2500(si_rev) ((((si_rev) >> 24) & 0xff) == 0x04) |
45 | |
46 | extern bool is_supported_silicon_rev(uint32_t silicon_rev); |
47 | |
48 | #define ASPEED_SCU_PROT_KEY 0x1688A8A8 |
49 | |
50 | /* |
51 | * Extracted from Aspeed SDK v00.03.21. Fixes and extra definitions |
52 | * were added. |
53 | * |
54 | * Original header file : |
55 | * arch/arm/mach-aspeed/include/mach/regs-scu.h |
56 | * |
57 | * Copyright (C) 2012-2020 ASPEED Technology Inc. |
58 | * |
59 | * This program is free software; you can redistribute it and/or modify |
60 | * it under the terms of the GNU General Public License version 2 as |
61 | * published by the Free Software Foundation. |
62 | * |
63 | * History : |
64 | * 1. 2012/12/29 Ryan Chen Create |
65 | */ |
66 | |
67 | /* SCU08 Clock Selection Register |
68 | * |
69 | * 31 Enable Video Engine clock dynamic slow down |
70 | * 30:28 Video Engine clock slow down setting |
71 | * 27 2D Engine GCLK clock source selection |
72 | * 26 2D Engine GCLK clock throttling enable |
73 | * 25:23 APB PCLK divider selection |
74 | * 22:20 LPC Host LHCLK divider selection |
75 | * 19 LPC Host LHCLK clock generation/output enable control |
76 | * 18:16 MAC AHB bus clock divider selection |
77 | * 15 SD/SDIO clock running enable |
78 | * 14:12 SD/SDIO divider selection |
79 | * 11 Reserved |
80 | * 10:8 Video port output clock delay control bit |
81 | * 7 ARM CPU/AHB clock slow down enable |
82 | * 6:4 ARM CPU/AHB clock slow down setting |
83 | * 3:2 ECLK clock source selection |
84 | * 1 CPU/AHB clock slow down idle timer |
85 | * 0 CPU/AHB clock dynamic slow down enable (defined in bit[6:4]) |
86 | */ |
87 | #define SCU_CLK_GET_PCLK_DIV(x) (((x) >> 23) & 0x7) |
88 | |
89 | /* SCU24 H-PLL Parameter Register (for Aspeed AST2400 SOC) |
90 | * |
91 | * 18 H-PLL parameter selection |
92 | * 0: Select H-PLL by strapping resistors |
93 | * 1: Select H-PLL by the programmed registers (SCU24[17:0]) |
94 | * 17 Enable H-PLL bypass mode |
95 | * 16 Turn off H-PLL |
96 | * 10:5 H-PLL Numerator |
97 | * 4 H-PLL Output Divider |
98 | * 3:0 H-PLL Denumerator |
99 | * |
100 | * (Output frequency) = 24MHz * (2-OD) * [(Numerator+2) / (Denumerator+1)] |
101 | */ |
102 | |
103 | #define SCU_AST2400_H_PLL_PROGRAMMED (0x1 << 18) |
104 | #define SCU_AST2400_H_PLL_BYPASS_EN (0x1 << 17) |
105 | #define SCU_AST2400_H_PLL_OFF (0x1 << 16) |
106 | |
107 | /* SCU24 H-PLL Parameter Register (for Aspeed AST2500 SOC) |
108 | * |
109 | * 21 Enable H-PLL reset |
110 | * 20 Enable H-PLL bypass mode |
111 | * 19 Turn off H-PLL |
112 | * 18:13 H-PLL Post Divider |
113 | * 12:5 H-PLL Numerator (M) |
114 | * 4:0 H-PLL Denumerator (N) |
115 | * |
116 | * (Output frequency) = CLKIN(24MHz) * [(M+1) / (N+1)] / (P+1) |
117 | * |
118 | * The default frequency is 792Mhz when CLKIN = 24MHz |
119 | */ |
120 | |
121 | #define SCU_H_PLL_BYPASS_EN (0x1 << 20) |
122 | #define SCU_H_PLL_OFF (0x1 << 19) |
123 | |
124 | /* SCU70 Hardware Strapping Register definition (for Aspeed AST2400 SOC) |
125 | * |
126 | * 31:29 Software defined strapping registers |
127 | * 28:27 DRAM size setting (for VGA driver use) |
128 | * 26:24 DRAM configuration setting |
129 | * 23 Enable 25 MHz reference clock input |
130 | * 22 Enable GPIOE pass-through mode |
131 | * 21 Enable GPIOD pass-through mode |
132 | * 20 Disable LPC to decode SuperIO 0x2E/0x4E address |
133 | * 19 Disable ACPI function |
134 | * 23,18 Clock source selection |
135 | * 17 Enable BMC 2nd boot watchdog timer |
136 | * 16 SuperIO configuration address selection |
137 | * 15 VGA Class Code selection |
138 | * 14 Enable LPC dedicated reset pin function |
139 | * 13:12 SPI mode selection |
140 | * 11:10 CPU/AHB clock frequency ratio selection |
141 | * 9:8 H-PLL default clock frequency selection |
142 | * 7 Define MAC#2 interface |
143 | * 6 Define MAC#1 interface |
144 | * 5 Enable VGA BIOS ROM |
145 | * 4 Boot flash memory extended option |
146 | * 3:2 VGA memory size selection |
147 | * 1:0 BMC CPU boot code selection |
148 | */ |
149 | #define SCU_AST2400_HW_STRAP_SW_DEFINE(x) ((x) << 29) |
150 | #define SCU_AST2400_HW_STRAP_SW_DEFINE_MASK (0x7 << 29) |
151 | |
152 | #define SCU_AST2400_HW_STRAP_DRAM_SIZE(x) ((x) << 27) |
153 | #define SCU_AST2400_HW_STRAP_DRAM_SIZE_MASK (0x3 << 27) |
154 | #define DRAM_SIZE_64MB 0 |
155 | #define DRAM_SIZE_128MB 1 |
156 | #define DRAM_SIZE_256MB 2 |
157 | #define DRAM_SIZE_512MB 3 |
158 | |
159 | #define SCU_AST2400_HW_STRAP_DRAM_CONFIG(x) ((x) << 24) |
160 | #define SCU_AST2400_HW_STRAP_DRAM_CONFIG_MASK (0x7 << 24) |
161 | |
162 | #define SCU_HW_STRAP_GPIOE_PT_EN (0x1 << 22) |
163 | #define SCU_HW_STRAP_GPIOD_PT_EN (0x1 << 21) |
164 | #define SCU_HW_STRAP_LPC_DEC_SUPER_IO (0x1 << 20) |
165 | #define SCU_AST2400_HW_STRAP_ACPI_DIS (0x1 << 19) |
166 | |
167 | /* bit 23, 18 [1,0] */ |
168 | #define SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(x) (((((x) & 0x3) >> 1) << 23) \ |
169 | | (((x) & 0x1) << 18)) |
170 | #define SCU_AST2400_HW_STRAP_GET_CLK_SOURCE(x) (((((x) >> 23) & 0x1) << 1) \ |
171 | | (((x) >> 18) & 0x1)) |
172 | #define SCU_AST2400_HW_STRAP_CLK_SOURCE_MASK ((0x1 << 23) | (0x1 << 18)) |
173 | #define SCU_HW_STRAP_CLK_25M_IN (0x1 << 23) |
174 | #define AST2400_CLK_24M_IN 0 |
175 | #define AST2400_CLK_48M_IN 1 |
176 | #define AST2400_CLK_25M_IN_24M_USB_CKI 2 |
177 | #define AST2400_CLK_25M_IN_48M_USB_CKI 3 |
178 | |
179 | #define SCU_HW_STRAP_CLK_48M_IN (0x1 << 18) |
180 | #define SCU_HW_STRAP_2ND_BOOT_WDT (0x1 << 17) |
181 | #define SCU_HW_STRAP_SUPER_IO_CONFIG (0x1 << 16) |
182 | #define SCU_HW_STRAP_VGA_CLASS_CODE (0x1 << 15) |
183 | #define SCU_HW_STRAP_LPC_RESET_PIN (0x1 << 14) |
184 | |
185 | #define SCU_HW_STRAP_SPI_MODE(x) ((x) << 12) |
186 | #define SCU_HW_STRAP_SPI_MODE_MASK (0x3 << 12) |
187 | #define SCU_HW_STRAP_SPI_DIS 0 |
188 | #define SCU_HW_STRAP_SPI_MASTER 1 |
189 | #define SCU_HW_STRAP_SPI_M_S_EN 2 |
190 | #define SCU_HW_STRAP_SPI_PASS_THROUGH 3 |
191 | |
192 | #define SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(x) ((x) << 10) |
193 | #define SCU_AST2400_HW_STRAP_GET_CPU_AHB_RATIO(x) (((x) >> 10) & 3) |
194 | #define SCU_AST2400_HW_STRAP_CPU_AHB_RATIO_MASK (0x3 << 10) |
195 | #define AST2400_CPU_AHB_RATIO_1_1 0 |
196 | #define AST2400_CPU_AHB_RATIO_2_1 1 |
197 | #define AST2400_CPU_AHB_RATIO_4_1 2 |
198 | #define AST2400_CPU_AHB_RATIO_3_1 3 |
199 | |
200 | #define SCU_AST2400_HW_STRAP_GET_H_PLL_CLK(x) (((x) >> 8) & 0x3) |
201 | #define SCU_AST2400_HW_STRAP_H_PLL_CLK_MASK (0x3 << 8) |
202 | #define AST2400_CPU_384MHZ 0 |
203 | #define AST2400_CPU_360MHZ 1 |
204 | #define AST2400_CPU_336MHZ 2 |
205 | #define AST2400_CPU_408MHZ 3 |
206 | |
207 | #define SCU_HW_STRAP_MAC1_RGMII (0x1 << 7) |
208 | #define SCU_HW_STRAP_MAC0_RGMII (0x1 << 6) |
209 | #define SCU_HW_STRAP_VGA_BIOS_ROM (0x1 << 5) |
210 | #define SCU_HW_STRAP_SPI_WIDTH (0x1 << 4) |
211 | |
212 | #define SCU_HW_STRAP_VGA_SIZE_GET(x) (((x) >> 2) & 0x3) |
213 | #define SCU_HW_STRAP_VGA_MASK (0x3 << 2) |
214 | #define SCU_HW_STRAP_VGA_SIZE_SET(x) ((x) << 2) |
215 | #define VGA_8M_DRAM 0 |
216 | #define VGA_16M_DRAM 1 |
217 | #define VGA_32M_DRAM 2 |
218 | #define VGA_64M_DRAM 3 |
219 | |
220 | #define SCU_AST2400_HW_STRAP_BOOT_MODE(x) (x) |
221 | #define AST2400_NOR_BOOT 0 |
222 | #define AST2400_NAND_BOOT 1 |
223 | #define AST2400_SPI_BOOT 2 |
224 | #define AST2400_DIS_BOOT 3 |
225 | |
226 | /* |
227 | * SCU70 Hardware strapping register definition (for Aspeed AST2500 |
228 | * SoC and higher) |
229 | * |
230 | * 31 Enable SPI Flash Strap Auto Fetch Mode |
231 | * 30 Enable GPIO Strap Mode |
232 | * 29 Select UART Debug Port |
233 | * 28 Reserved (1) |
234 | * 27 Enable fast reset mode for ARM ICE debugger |
235 | * 26 Enable eSPI flash mode |
236 | * 25 Enable eSPI mode |
237 | * 24 Select DDR4 SDRAM |
238 | * 23 Select 25 MHz reference clock input mode |
239 | * 22 Enable GPIOE pass-through mode |
240 | * 21 Enable GPIOD pass-through mode |
241 | * 20 Disable LPC to decode SuperIO 0x2E/0x4E address |
242 | * 19 Enable ACPI function |
243 | * 18 Select USBCKI input frequency |
244 | * 17 Enable BMC 2nd boot watchdog timer |
245 | * 16 SuperIO configuration address selection |
246 | * 15 VGA Class Code selection |
247 | * 14 Select dedicated LPC reset input |
248 | * 13:12 SPI mode selection |
249 | * 11:9 AXI/AHB clock frequency ratio selection |
250 | * 8 Reserved (0) |
251 | * 7 Define MAC#2 interface |
252 | * 6 Define MAC#1 interface |
253 | * 5 Enable dedicated VGA BIOS ROM |
254 | * 4 Reserved (0) |
255 | * 3:2 VGA memory size selection |
256 | * 1 Reserved (1) |
257 | * 0 Disable CPU boot |
258 | */ |
259 | #define SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE (0x1 << 31) |
260 | #define SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE (0x1 << 30) |
261 | #define SCU_AST2500_HW_STRAP_UART_DEBUG (0x1 << 29) |
262 | #define UART_DEBUG_UART1 0 |
263 | #define UART_DEBUG_UART5 1 |
264 | #define SCU_AST2500_HW_STRAP_RESERVED28 (0x1 << 28) |
265 | |
266 | #define SCU_AST2500_HW_STRAP_FAST_RESET_DBG (0x1 << 27) |
267 | #define SCU_AST2500_HW_STRAP_ESPI_FLASH_ENABLE (0x1 << 26) |
268 | #define SCU_AST2500_HW_STRAP_ESPI_ENABLE (0x1 << 25) |
269 | #define SCU_AST2500_HW_STRAP_DDR4_ENABLE (0x1 << 24) |
270 | |
271 | #define SCU_AST2500_HW_STRAP_ACPI_ENABLE (0x1 << 19) |
272 | #define SCU_AST2500_HW_STRAP_USBCKI_FREQ (0x1 << 18) |
273 | #define USBCKI_FREQ_24MHZ 0 |
274 | #define USBCKI_FREQ_28MHZ 1 |
275 | |
276 | #define SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(x) ((x) << 9) |
277 | #define SCU_AST2500_HW_STRAP_GET_AXI_AHB_RATIO(x) (((x) >> 9) & 7) |
278 | #define SCU_AST2500_HW_STRAP_CPU_AXI_RATIO_MASK (0x7 << 9) |
279 | #define AXI_AHB_RATIO_UNDEFINED 0 |
280 | #define AXI_AHB_RATIO_2_1 1 |
281 | #define AXI_AHB_RATIO_3_1 2 |
282 | #define AXI_AHB_RATIO_4_1 3 |
283 | #define AXI_AHB_RATIO_5_1 4 |
284 | #define AXI_AHB_RATIO_6_1 5 |
285 | #define AXI_AHB_RATIO_7_1 6 |
286 | #define AXI_AHB_RATIO_8_1 7 |
287 | |
288 | #define SCU_AST2500_HW_STRAP_RESERVED1 (0x1 << 1) |
289 | #define SCU_AST2500_HW_STRAP_DIS_BOOT (0x1 << 0) |
290 | |
291 | #define AST2500_HW_STRAP1_DEFAULTS ( \ |
292 | SCU_AST2500_HW_STRAP_RESERVED28 | \ |
293 | SCU_HW_STRAP_2ND_BOOT_WDT | \ |
294 | SCU_HW_STRAP_VGA_CLASS_CODE | \ |
295 | SCU_HW_STRAP_LPC_RESET_PIN | \ |
296 | SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ |
297 | SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ |
298 | SCU_AST2500_HW_STRAP_RESERVED1) |
299 | |
300 | #endif /* ASPEED_SCU_H */ |
301 | |