1 | /* |
2 | * QEMU PowerPC sPAPR IRQ backend definitions |
3 | * |
4 | * Copyright (c) 2018, IBM Corporation. |
5 | * |
6 | * This code is licensed under the GPL version 2 or later. See the |
7 | * COPYING file in the top-level directory. |
8 | */ |
9 | |
10 | #ifndef HW_SPAPR_IRQ_H |
11 | #define HW_SPAPR_IRQ_H |
12 | |
13 | #include "target/ppc/cpu-qom.h" |
14 | |
15 | /* |
16 | * IRQ range offsets per device type |
17 | */ |
18 | #define SPAPR_IRQ_IPI 0x0 |
19 | #define SPAPR_IRQ_EPOW 0x1000 /* XICS_IRQ_BASE offset */ |
20 | #define SPAPR_IRQ_HOTPLUG 0x1001 |
21 | #define SPAPR_IRQ_VIO 0x1100 /* 256 VIO devices */ |
22 | #define SPAPR_IRQ_PCI_LSI 0x1200 /* 32+ PHBs devices */ |
23 | |
24 | #define SPAPR_IRQ_MSI 0x1300 /* Offset of the dynamic range covered |
25 | * by the bitmap allocator */ |
26 | |
27 | typedef struct SpaprMachineState SpaprMachineState; |
28 | |
29 | void spapr_irq_msi_init(SpaprMachineState *spapr, uint32_t nr_msis); |
30 | int spapr_irq_msi_alloc(SpaprMachineState *spapr, uint32_t num, bool align, |
31 | Error **errp); |
32 | void spapr_irq_msi_free(SpaprMachineState *spapr, int irq, uint32_t num); |
33 | |
34 | typedef struct SpaprIrq { |
35 | uint32_t nr_irqs; |
36 | uint32_t nr_msis; |
37 | uint8_t ov5; |
38 | |
39 | void (*init)(SpaprMachineState *spapr, int nr_irqs, Error **errp); |
40 | int (*claim)(SpaprMachineState *spapr, int irq, bool lsi, Error **errp); |
41 | void (*free)(SpaprMachineState *spapr, int irq, int num); |
42 | qemu_irq (*qirq)(SpaprMachineState *spapr, int irq); |
43 | void (*print_info)(SpaprMachineState *spapr, Monitor *mon); |
44 | void (*dt_populate)(SpaprMachineState *spapr, uint32_t nr_servers, |
45 | void *fdt, uint32_t phandle); |
46 | void (*cpu_intc_create)(SpaprMachineState *spapr, PowerPCCPU *cpu, |
47 | Error **errp); |
48 | int (*post_load)(SpaprMachineState *spapr, int version_id); |
49 | void (*reset)(SpaprMachineState *spapr, Error **errp); |
50 | void (*set_irq)(void *opaque, int srcno, int val); |
51 | const char *(*get_nodename)(SpaprMachineState *spapr); |
52 | void (*init_kvm)(SpaprMachineState *spapr, Error **errp); |
53 | } SpaprIrq; |
54 | |
55 | extern SpaprIrq spapr_irq_xics; |
56 | extern SpaprIrq spapr_irq_xics_legacy; |
57 | extern SpaprIrq spapr_irq_xive; |
58 | extern SpaprIrq spapr_irq_dual; |
59 | |
60 | void spapr_irq_init(SpaprMachineState *spapr, Error **errp); |
61 | int spapr_irq_claim(SpaprMachineState *spapr, int irq, bool lsi, Error **errp); |
62 | void spapr_irq_free(SpaprMachineState *spapr, int irq, int num); |
63 | qemu_irq spapr_qirq(SpaprMachineState *spapr, int irq); |
64 | int spapr_irq_post_load(SpaprMachineState *spapr, int version_id); |
65 | void spapr_irq_reset(SpaprMachineState *spapr, Error **errp); |
66 | int spapr_irq_get_phandle(SpaprMachineState *spapr, void *fdt, Error **errp); |
67 | |
68 | /* |
69 | * XICS legacy routines |
70 | */ |
71 | int spapr_irq_find(SpaprMachineState *spapr, int num, bool align, Error **errp); |
72 | #define spapr_irq_findone(spapr, errp) spapr_irq_find(spapr, 1, false, errp) |
73 | |
74 | #endif |
75 | |