1 | /* |
2 | * S/390 channel I/O instructions |
3 | * |
4 | * Copyright 2012 IBM Corp. |
5 | * Author(s): Cornelia Huck <cornelia.huck@de.ibm.com> |
6 | * |
7 | * This work is licensed under the terms of the GNU GPL, version 2 or (at |
8 | * your option) any later version. See the COPYING file in the top-level |
9 | * directory. |
10 | */ |
11 | |
12 | #ifndef S390X_IOINST_H |
13 | #define S390X_IOINST_H |
14 | |
15 | /* |
16 | * Channel I/O related definitions, as defined in the Principles |
17 | * Of Operation (and taken from the Linux implementation). |
18 | */ |
19 | |
20 | /* subchannel status word (command mode only) */ |
21 | typedef struct SCSW { |
22 | uint16_t flags; |
23 | uint16_t ctrl; |
24 | uint32_t cpa; |
25 | uint8_t dstat; |
26 | uint8_t cstat; |
27 | uint16_t count; |
28 | } SCSW; |
29 | QEMU_BUILD_BUG_MSG(sizeof(SCSW) != 12, "size of SCSW is wrong" ); |
30 | |
31 | #define SCSW_FLAGS_MASK_KEY 0xf000 |
32 | #define SCSW_FLAGS_MASK_SCTL 0x0800 |
33 | #define SCSW_FLAGS_MASK_ESWF 0x0400 |
34 | #define SCSW_FLAGS_MASK_CC 0x0300 |
35 | #define SCSW_FLAGS_MASK_FMT 0x0080 |
36 | #define SCSW_FLAGS_MASK_PFCH 0x0040 |
37 | #define SCSW_FLAGS_MASK_ISIC 0x0020 |
38 | #define SCSW_FLAGS_MASK_ALCC 0x0010 |
39 | #define SCSW_FLAGS_MASK_SSI 0x0008 |
40 | #define SCSW_FLAGS_MASK_ZCC 0x0004 |
41 | #define SCSW_FLAGS_MASK_ECTL 0x0002 |
42 | #define SCSW_FLAGS_MASK_PNO 0x0001 |
43 | |
44 | #define SCSW_CTRL_MASK_FCTL 0x7000 |
45 | #define SCSW_CTRL_MASK_ACTL 0x0fe0 |
46 | #define SCSW_CTRL_MASK_STCTL 0x001f |
47 | |
48 | #define SCSW_FCTL_CLEAR_FUNC 0x1000 |
49 | #define SCSW_FCTL_HALT_FUNC 0x2000 |
50 | #define SCSW_FCTL_START_FUNC 0x4000 |
51 | |
52 | #define SCSW_ACTL_SUSP 0x0020 |
53 | #define SCSW_ACTL_DEVICE_ACTIVE 0x0040 |
54 | #define SCSW_ACTL_SUBCH_ACTIVE 0x0080 |
55 | #define SCSW_ACTL_CLEAR_PEND 0x0100 |
56 | #define SCSW_ACTL_HALT_PEND 0x0200 |
57 | #define SCSW_ACTL_START_PEND 0x0400 |
58 | #define SCSW_ACTL_RESUME_PEND 0x0800 |
59 | |
60 | #define SCSW_STCTL_STATUS_PEND 0x0001 |
61 | #define SCSW_STCTL_SECONDARY 0x0002 |
62 | #define SCSW_STCTL_PRIMARY 0x0004 |
63 | #define SCSW_STCTL_INTERMEDIATE 0x0008 |
64 | #define SCSW_STCTL_ALERT 0x0010 |
65 | |
66 | #define SCSW_DSTAT_ATTENTION 0x80 |
67 | #define SCSW_DSTAT_STAT_MOD 0x40 |
68 | #define SCSW_DSTAT_CU_END 0x20 |
69 | #define SCSW_DSTAT_BUSY 0x10 |
70 | #define SCSW_DSTAT_CHANNEL_END 0x08 |
71 | #define SCSW_DSTAT_DEVICE_END 0x04 |
72 | #define SCSW_DSTAT_UNIT_CHECK 0x02 |
73 | #define SCSW_DSTAT_UNIT_EXCEP 0x01 |
74 | |
75 | #define SCSW_CSTAT_PCI 0x80 |
76 | #define SCSW_CSTAT_INCORR_LEN 0x40 |
77 | #define SCSW_CSTAT_PROG_CHECK 0x20 |
78 | #define SCSW_CSTAT_PROT_CHECK 0x10 |
79 | #define SCSW_CSTAT_DATA_CHECK 0x08 |
80 | #define SCSW_CSTAT_CHN_CTRL_CHK 0x04 |
81 | #define SCSW_CSTAT_INTF_CTRL_CHK 0x02 |
82 | #define SCSW_CSTAT_CHAIN_CHECK 0x01 |
83 | |
84 | /* path management control word */ |
85 | typedef struct PMCW { |
86 | uint32_t intparm; |
87 | uint16_t flags; |
88 | uint16_t devno; |
89 | uint8_t lpm; |
90 | uint8_t pnom; |
91 | uint8_t lpum; |
92 | uint8_t pim; |
93 | uint16_t mbi; |
94 | uint8_t pom; |
95 | uint8_t pam; |
96 | uint8_t chpid[8]; |
97 | uint32_t chars; |
98 | } PMCW; |
99 | QEMU_BUILD_BUG_MSG(sizeof(PMCW) != 28, "size of PMCW is wrong" ); |
100 | |
101 | #define PMCW_FLAGS_MASK_QF 0x8000 |
102 | #define PMCW_FLAGS_MASK_W 0x4000 |
103 | #define PMCW_FLAGS_MASK_ISC 0x3800 |
104 | #define PMCW_FLAGS_MASK_ENA 0x0080 |
105 | #define PMCW_FLAGS_MASK_LM 0x0060 |
106 | #define PMCW_FLAGS_MASK_MME 0x0018 |
107 | #define PMCW_FLAGS_MASK_MP 0x0004 |
108 | #define PMCW_FLAGS_MASK_TF 0x0002 |
109 | #define PMCW_FLAGS_MASK_DNV 0x0001 |
110 | #define PMCW_FLAGS_MASK_INVALID 0x0700 |
111 | |
112 | #define PMCW_CHARS_MASK_ST 0x00e00000 |
113 | #define PMCW_CHARS_MASK_MBFC 0x00000004 |
114 | #define PMCW_CHARS_MASK_XMWME 0x00000002 |
115 | #define PMCW_CHARS_MASK_CSENSE 0x00000001 |
116 | #define PMCW_CHARS_MASK_INVALID 0xff1ffff8 |
117 | |
118 | /* subchannel information block */ |
119 | typedef struct SCHIB { |
120 | PMCW pmcw; |
121 | SCSW scsw; |
122 | uint64_t mba; |
123 | uint8_t mda[4]; |
124 | } QEMU_PACKED SCHIB; |
125 | |
126 | /* interruption response block */ |
127 | typedef struct IRB { |
128 | SCSW scsw; |
129 | uint32_t esw[5]; |
130 | uint32_t ecw[8]; |
131 | uint32_t emw[8]; |
132 | } IRB; |
133 | QEMU_BUILD_BUG_MSG(sizeof(IRB) != 96, "size of IRB is wrong" ); |
134 | |
135 | /* operation request block */ |
136 | typedef struct ORB { |
137 | uint32_t intparm; |
138 | uint16_t ctrl0; |
139 | uint8_t lpm; |
140 | uint8_t ctrl1; |
141 | uint32_t cpa; |
142 | } ORB; |
143 | QEMU_BUILD_BUG_MSG(sizeof(ORB) != 12, "size of ORB is wrong" ); |
144 | |
145 | #define ORB_CTRL0_MASK_KEY 0xf000 |
146 | #define ORB_CTRL0_MASK_SPND 0x0800 |
147 | #define ORB_CTRL0_MASK_STR 0x0400 |
148 | #define ORB_CTRL0_MASK_MOD 0x0200 |
149 | #define ORB_CTRL0_MASK_SYNC 0x0100 |
150 | #define ORB_CTRL0_MASK_FMT 0x0080 |
151 | #define ORB_CTRL0_MASK_PFCH 0x0040 |
152 | #define ORB_CTRL0_MASK_ISIC 0x0020 |
153 | #define ORB_CTRL0_MASK_ALCC 0x0010 |
154 | #define ORB_CTRL0_MASK_SSIC 0x0008 |
155 | #define ORB_CTRL0_MASK_C64 0x0002 |
156 | #define ORB_CTRL0_MASK_I2K 0x0001 |
157 | #define ORB_CTRL0_MASK_INVALID 0x0004 |
158 | |
159 | #define ORB_CTRL1_MASK_ILS 0x80 |
160 | #define ORB_CTRL1_MASK_MIDAW 0x40 |
161 | #define ORB_CTRL1_MASK_ORBX 0x01 |
162 | #define ORB_CTRL1_MASK_INVALID 0x3e |
163 | |
164 | /* channel command word (type 0) */ |
165 | typedef struct CCW0 { |
166 | uint8_t cmd_code; |
167 | uint8_t cda0; |
168 | uint16_t cda1; |
169 | uint8_t flags; |
170 | uint8_t reserved; |
171 | uint16_t count; |
172 | } CCW0; |
173 | QEMU_BUILD_BUG_MSG(sizeof(CCW0) != 8, "size of CCW0 is wrong" ); |
174 | |
175 | /* channel command word (type 1) */ |
176 | typedef struct CCW1 { |
177 | uint8_t cmd_code; |
178 | uint8_t flags; |
179 | uint16_t count; |
180 | uint32_t cda; |
181 | } CCW1; |
182 | QEMU_BUILD_BUG_MSG(sizeof(CCW1) != 8, "size of CCW1 is wrong" ); |
183 | |
184 | #define CCW_FLAG_DC 0x80 |
185 | #define CCW_FLAG_CC 0x40 |
186 | #define CCW_FLAG_SLI 0x20 |
187 | #define CCW_FLAG_SKIP 0x10 |
188 | #define CCW_FLAG_PCI 0x08 |
189 | #define CCW_FLAG_IDA 0x04 |
190 | #define CCW_FLAG_SUSPEND 0x02 |
191 | #define CCW_FLAG_MIDA 0x01 |
192 | |
193 | #define CCW_CMD_NOOP 0x03 |
194 | #define CCW_CMD_BASIC_SENSE 0x04 |
195 | #define CCW_CMD_TIC 0x08 |
196 | #define CCW_CMD_SENSE_ID 0xe4 |
197 | |
198 | typedef struct CRW { |
199 | uint16_t flags; |
200 | uint16_t rsid; |
201 | } CRW; |
202 | QEMU_BUILD_BUG_MSG(sizeof(CRW) != 4, "size of CRW is wrong" ); |
203 | |
204 | #define CRW_FLAGS_MASK_S 0x4000 |
205 | #define CRW_FLAGS_MASK_R 0x2000 |
206 | #define CRW_FLAGS_MASK_C 0x1000 |
207 | #define CRW_FLAGS_MASK_RSC 0x0f00 |
208 | #define CRW_FLAGS_MASK_A 0x0080 |
209 | #define CRW_FLAGS_MASK_ERC 0x003f |
210 | |
211 | #define CRW_ERC_EVENT 0x00 /* event information pending */ |
212 | #define CRW_ERC_AVAIL 0x01 /* available */ |
213 | #define CRW_ERC_INIT 0x02 /* initialized */ |
214 | #define CRW_ERC_TERROR 0x03 /* temporary error */ |
215 | #define CRW_ERC_IPI 0x04 /* installed parm initialized */ |
216 | #define CRW_ERC_TERM 0x05 /* terminal */ |
217 | #define CRW_ERC_PERRN 0x06 /* perm. error, facility not init */ |
218 | #define CRW_ERC_PERRI 0x07 /* perm. error, facility init */ |
219 | #define CRW_ERC_PMOD 0x08 /* installed parameters modified */ |
220 | #define CRW_ERC_IPR 0x0A /* installed parameters restored */ |
221 | |
222 | #define CRW_RSC_SUBCH 0x3 |
223 | #define CRW_RSC_CHP 0x4 |
224 | #define CRW_RSC_CSS 0xb |
225 | |
226 | /* I/O interruption code */ |
227 | typedef struct IOIntCode { |
228 | uint32_t subsys_id; |
229 | uint32_t intparm; |
230 | uint32_t interrupt_id; |
231 | } QEMU_PACKED IOIntCode; |
232 | |
233 | /* schid disintegration */ |
234 | #define IOINST_SCHID_ONE(_schid) ((_schid & 0x00010000) >> 16) |
235 | #define IOINST_SCHID_M(_schid) ((_schid & 0x00080000) >> 19) |
236 | #define IOINST_SCHID_CSSID(_schid) ((_schid & 0xff000000) >> 24) |
237 | #define IOINST_SCHID_SSID(_schid) ((_schid & 0x00060000) >> 17) |
238 | #define IOINST_SCHID_NR(_schid) (_schid & 0x0000ffff) |
239 | |
240 | #define IO_INT_WORD_ISC(_int_word) ((_int_word & 0x38000000) >> 27) |
241 | #define ISC_TO_ISC_BITS(_isc) ((0x80 >> _isc) << 24) |
242 | |
243 | #define IO_INT_WORD_AI 0x80000000 |
244 | |
245 | int ioinst_disassemble_sch_ident(uint32_t value, int *m, int *cssid, int *ssid, |
246 | int *schid); |
247 | |
248 | #endif |
249 | |