1#ifndef QEMU_HW_ESP_H
2#define QEMU_HW_ESP_H
3
4#include "hw/scsi/scsi.h"
5#include "hw/sysbus.h"
6
7/* esp.c */
8#define ESP_MAX_DEVS 7
9typedef void (*ESPDMAMemoryReadWriteFunc)(void *opaque, uint8_t *buf, int len);
10
11#define ESP_REGS 16
12#define TI_BUFSZ 16
13#define ESP_CMDBUF_SZ 32
14
15typedef struct ESPState ESPState;
16
17struct ESPState {
18 uint8_t rregs[ESP_REGS];
19 uint8_t wregs[ESP_REGS];
20 qemu_irq irq;
21 uint8_t chip_id;
22 bool tchi_written;
23 int32_t ti_size;
24 uint32_t ti_rptr, ti_wptr;
25 uint32_t status;
26 uint32_t deferred_status;
27 bool deferred_complete;
28 uint32_t dma;
29 uint8_t ti_buf[TI_BUFSZ];
30 SCSIBus bus;
31 SCSIDevice *current_dev;
32 SCSIRequest *current_req;
33 uint8_t cmdbuf[ESP_CMDBUF_SZ];
34 uint32_t cmdlen;
35 uint32_t do_cmd;
36
37 /* The amount of data left in the current DMA transfer. */
38 uint32_t dma_left;
39 /* The size of the current DMA transfer. Zero if no transfer is in
40 progress. */
41 uint32_t dma_counter;
42 int dma_enabled;
43
44 uint32_t async_len;
45 uint8_t *async_buf;
46
47 ESPDMAMemoryReadWriteFunc dma_memory_read;
48 ESPDMAMemoryReadWriteFunc dma_memory_write;
49 void *dma_opaque;
50 void (*dma_cb)(ESPState *s);
51};
52
53#define TYPE_ESP "esp"
54#define ESP_STATE(obj) OBJECT_CHECK(SysBusESPState, (obj), TYPE_ESP)
55
56typedef struct {
57 /*< private >*/
58 SysBusDevice parent_obj;
59 /*< public >*/
60
61 MemoryRegion iomem;
62 uint32_t it_shift;
63 ESPState esp;
64} SysBusESPState;
65
66#define ESP_TCLO 0x0
67#define ESP_TCMID 0x1
68#define ESP_FIFO 0x2
69#define ESP_CMD 0x3
70#define ESP_RSTAT 0x4
71#define ESP_WBUSID 0x4
72#define ESP_RINTR 0x5
73#define ESP_WSEL 0x5
74#define ESP_RSEQ 0x6
75#define ESP_WSYNTP 0x6
76#define ESP_RFLAGS 0x7
77#define ESP_WSYNO 0x7
78#define ESP_CFG1 0x8
79#define ESP_RRES1 0x9
80#define ESP_WCCF 0x9
81#define ESP_RRES2 0xa
82#define ESP_WTEST 0xa
83#define ESP_CFG2 0xb
84#define ESP_CFG3 0xc
85#define ESP_RES3 0xd
86#define ESP_TCHI 0xe
87#define ESP_RES4 0xf
88
89#define CMD_DMA 0x80
90#define CMD_CMD 0x7f
91
92#define CMD_NOP 0x00
93#define CMD_FLUSH 0x01
94#define CMD_RESET 0x02
95#define CMD_BUSRESET 0x03
96#define CMD_TI 0x10
97#define CMD_ICCS 0x11
98#define CMD_MSGACC 0x12
99#define CMD_PAD 0x18
100#define CMD_SATN 0x1a
101#define CMD_RSTATN 0x1b
102#define CMD_SEL 0x41
103#define CMD_SELATN 0x42
104#define CMD_SELATNS 0x43
105#define CMD_ENSEL 0x44
106#define CMD_DISSEL 0x45
107
108#define STAT_DO 0x00
109#define STAT_DI 0x01
110#define STAT_CD 0x02
111#define STAT_ST 0x03
112#define STAT_MO 0x06
113#define STAT_MI 0x07
114#define STAT_PIO_MASK 0x06
115
116#define STAT_TC 0x10
117#define STAT_PE 0x20
118#define STAT_GE 0x40
119#define STAT_INT 0x80
120
121#define BUSID_DID 0x07
122
123#define INTR_FC 0x08
124#define INTR_BS 0x10
125#define INTR_DC 0x20
126#define INTR_RST 0x80
127
128#define SEQ_0 0x0
129#define SEQ_CD 0x4
130
131#define CFG1_RESREPT 0x40
132
133#define TCHI_FAS100A 0x4
134#define TCHI_AM53C974 0x12
135
136void esp_dma_enable(ESPState *s, int irq, int level);
137void esp_request_cancelled(SCSIRequest *req);
138void esp_command_complete(SCSIRequest *req, uint32_t status, size_t resid);
139void esp_transfer_data(SCSIRequest *req, uint32_t len);
140void esp_hard_reset(ESPState *s);
141uint64_t esp_reg_read(ESPState *s, uint32_t saddr);
142void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val);
143extern const VMStateDescription vmstate_esp;
144
145#endif
146