1#ifndef ALLWINNER_A10_PIT_H
2#define ALLWINNER_A10_PIT_H
3
4#include "hw/ptimer.h"
5#include "hw/sysbus.h"
6
7#define TYPE_AW_A10_PIT "allwinner-A10-timer"
8#define AW_A10_PIT(obj) OBJECT_CHECK(AwA10PITState, (obj), TYPE_AW_A10_PIT)
9
10#define AW_A10_PIT_TIMER_NR 6
11#define AW_A10_PIT_TIMER_IRQ 0x1
12#define AW_A10_PIT_WDOG_IRQ 0x100
13
14#define AW_A10_PIT_TIMER_IRQ_EN 0
15#define AW_A10_PIT_TIMER_IRQ_ST 0x4
16
17#define AW_A10_PIT_TIMER_CONTROL 0x0
18#define AW_A10_PIT_TIMER_EN 0x1
19#define AW_A10_PIT_TIMER_RELOAD 0x2
20#define AW_A10_PIT_TIMER_MODE 0x80
21
22#define AW_A10_PIT_TIMER_INTERVAL 0x4
23#define AW_A10_PIT_TIMER_COUNT 0x8
24#define AW_A10_PIT_WDOG_CONTROL 0x90
25#define AW_A10_PIT_WDOG_MODE 0x94
26
27#define AW_A10_PIT_COUNT_CTL 0xa0
28#define AW_A10_PIT_COUNT_RL_EN 0x2
29#define AW_A10_PIT_COUNT_CLR_EN 0x1
30#define AW_A10_PIT_COUNT_LO 0xa4
31#define AW_A10_PIT_COUNT_HI 0xa8
32
33#define AW_A10_PIT_TIMER_BASE 0x10
34#define AW_A10_PIT_TIMER_BASE_END \
35 (AW_A10_PIT_TIMER_BASE * 6 + AW_A10_PIT_TIMER_COUNT)
36
37#define AW_A10_PIT_DEFAULT_CLOCK 0x4
38
39typedef struct AwA10PITState AwA10PITState;
40
41typedef struct AwA10TimerContext {
42 AwA10PITState *container;
43 int index;
44} AwA10TimerContext;
45
46struct AwA10PITState {
47 /*< private >*/
48 SysBusDevice parent_obj;
49 /*< public >*/
50 qemu_irq irq[AW_A10_PIT_TIMER_NR];
51 ptimer_state * timer[AW_A10_PIT_TIMER_NR];
52 AwA10TimerContext timer_context[AW_A10_PIT_TIMER_NR];
53 MemoryRegion iomem;
54 uint32_t clk_freq[4];
55
56 uint32_t irq_enable;
57 uint32_t irq_status;
58 uint32_t control[AW_A10_PIT_TIMER_NR];
59 uint32_t interval[AW_A10_PIT_TIMER_NR];
60 uint32_t count[AW_A10_PIT_TIMER_NR];
61 uint32_t watch_dog_mode;
62 uint32_t watch_dog_control;
63 uint32_t count_lo;
64 uint32_t count_hi;
65 uint32_t count_ctl;
66};
67
68#endif
69