1 | /* |
2 | * Copyright 2011 Intel Corporation |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice (including the next |
12 | * paragraph) shall be included in all copies or substantial portions of the |
13 | * Software. |
14 | * |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
21 | * OTHER DEALINGS IN THE SOFTWARE. |
22 | */ |
23 | |
24 | #ifndef DRM_FOURCC_H |
25 | #define DRM_FOURCC_H |
26 | |
27 | |
28 | #if defined(__cplusplus) |
29 | extern "C" { |
30 | #endif |
31 | |
32 | /** |
33 | * DOC: overview |
34 | * |
35 | * In the DRM subsystem, framebuffer pixel formats are described using the |
36 | * fourcc codes defined in `include/uapi/drm/drm_fourcc.h`. In addition to the |
37 | * fourcc code, a Format Modifier may optionally be provided, in order to |
38 | * further describe the buffer's format - for example tiling or compression. |
39 | * |
40 | * Format Modifiers |
41 | * ---------------- |
42 | * |
43 | * Format modifiers are used in conjunction with a fourcc code, forming a |
44 | * unique fourcc:modifier pair. This format:modifier pair must fully define the |
45 | * format and data layout of the buffer, and should be the only way to describe |
46 | * that particular buffer. |
47 | * |
48 | * Having multiple fourcc:modifier pairs which describe the same layout should |
49 | * be avoided, as such aliases run the risk of different drivers exposing |
50 | * different names for the same data format, forcing userspace to understand |
51 | * that they are aliases. |
52 | * |
53 | * Format modifiers may change any property of the buffer, including the number |
54 | * of planes and/or the required allocation size. Format modifiers are |
55 | * vendor-namespaced, and as such the relationship between a fourcc code and a |
56 | * modifier is specific to the modifer being used. For example, some modifiers |
57 | * may preserve meaning - such as number of planes - from the fourcc code, |
58 | * whereas others may not. |
59 | * |
60 | * Vendors should document their modifier usage in as much detail as |
61 | * possible, to ensure maximum compatibility across devices, drivers and |
62 | * applications. |
63 | * |
64 | * The authoritative list of format modifier codes is found in |
65 | * `include/uapi/drm/drm_fourcc.h` |
66 | */ |
67 | |
68 | #define fourcc_code(a, b, c, d) ((uint32_t)(a) | ((uint32_t)(b) << 8) | \ |
69 | ((uint32_t)(c) << 16) | ((uint32_t)(d) << 24)) |
70 | |
71 | #define DRM_FORMAT_BIG_ENDIAN (1<<31) /* format is big endian instead of little endian */ |
72 | |
73 | /* Reserve 0 for the invalid format specifier */ |
74 | #define DRM_FORMAT_INVALID 0 |
75 | |
76 | /* color index */ |
77 | #define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */ |
78 | |
79 | /* 8 bpp Red */ |
80 | #define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */ |
81 | |
82 | /* 16 bpp Red */ |
83 | #define DRM_FORMAT_R16 fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */ |
84 | |
85 | /* 16 bpp RG */ |
86 | #define DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */ |
87 | #define DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */ |
88 | |
89 | /* 32 bpp RG */ |
90 | #define DRM_FORMAT_RG1616 fourcc_code('R', 'G', '3', '2') /* [31:0] R:G 16:16 little endian */ |
91 | #define DRM_FORMAT_GR1616 fourcc_code('G', 'R', '3', '2') /* [31:0] G:R 16:16 little endian */ |
92 | |
93 | /* 8 bpp RGB */ |
94 | #define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */ |
95 | #define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */ |
96 | |
97 | /* 16 bpp RGB */ |
98 | #define DRM_FORMAT_XRGB4444 fourcc_code('X', 'R', '1', '2') /* [15:0] x:R:G:B 4:4:4:4 little endian */ |
99 | #define DRM_FORMAT_XBGR4444 fourcc_code('X', 'B', '1', '2') /* [15:0] x:B:G:R 4:4:4:4 little endian */ |
100 | #define DRM_FORMAT_RGBX4444 fourcc_code('R', 'X', '1', '2') /* [15:0] R:G:B:x 4:4:4:4 little endian */ |
101 | #define DRM_FORMAT_BGRX4444 fourcc_code('B', 'X', '1', '2') /* [15:0] B:G:R:x 4:4:4:4 little endian */ |
102 | |
103 | #define DRM_FORMAT_ARGB4444 fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian */ |
104 | #define DRM_FORMAT_ABGR4444 fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian */ |
105 | #define DRM_FORMAT_RGBA4444 fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian */ |
106 | #define DRM_FORMAT_BGRA4444 fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian */ |
107 | |
108 | #define DRM_FORMAT_XRGB1555 fourcc_code('X', 'R', '1', '5') /* [15:0] x:R:G:B 1:5:5:5 little endian */ |
109 | #define DRM_FORMAT_XBGR1555 fourcc_code('X', 'B', '1', '5') /* [15:0] x:B:G:R 1:5:5:5 little endian */ |
110 | #define DRM_FORMAT_RGBX5551 fourcc_code('R', 'X', '1', '5') /* [15:0] R:G:B:x 5:5:5:1 little endian */ |
111 | #define DRM_FORMAT_BGRX5551 fourcc_code('B', 'X', '1', '5') /* [15:0] B:G:R:x 5:5:5:1 little endian */ |
112 | |
113 | #define DRM_FORMAT_ARGB1555 fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian */ |
114 | #define DRM_FORMAT_ABGR1555 fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian */ |
115 | #define DRM_FORMAT_RGBA5551 fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian */ |
116 | #define DRM_FORMAT_BGRA5551 fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian */ |
117 | |
118 | #define DRM_FORMAT_RGB565 fourcc_code('R', 'G', '1', '6') /* [15:0] R:G:B 5:6:5 little endian */ |
119 | #define DRM_FORMAT_BGR565 fourcc_code('B', 'G', '1', '6') /* [15:0] B:G:R 5:6:5 little endian */ |
120 | |
121 | /* 24 bpp RGB */ |
122 | #define DRM_FORMAT_RGB888 fourcc_code('R', 'G', '2', '4') /* [23:0] R:G:B little endian */ |
123 | #define DRM_FORMAT_BGR888 fourcc_code('B', 'G', '2', '4') /* [23:0] B:G:R little endian */ |
124 | |
125 | /* 32 bpp RGB */ |
126 | #define DRM_FORMAT_XRGB8888 fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian */ |
127 | #define DRM_FORMAT_XBGR8888 fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian */ |
128 | #define DRM_FORMAT_RGBX8888 fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian */ |
129 | #define DRM_FORMAT_BGRX8888 fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian */ |
130 | |
131 | #define DRM_FORMAT_ARGB8888 fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian */ |
132 | #define DRM_FORMAT_ABGR8888 fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian */ |
133 | #define DRM_FORMAT_RGBA8888 fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian */ |
134 | #define DRM_FORMAT_BGRA8888 fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian */ |
135 | |
136 | #define DRM_FORMAT_XRGB2101010 fourcc_code('X', 'R', '3', '0') /* [31:0] x:R:G:B 2:10:10:10 little endian */ |
137 | #define DRM_FORMAT_XBGR2101010 fourcc_code('X', 'B', '3', '0') /* [31:0] x:B:G:R 2:10:10:10 little endian */ |
138 | #define DRM_FORMAT_RGBX1010102 fourcc_code('R', 'X', '3', '0') /* [31:0] R:G:B:x 10:10:10:2 little endian */ |
139 | #define DRM_FORMAT_BGRX1010102 fourcc_code('B', 'X', '3', '0') /* [31:0] B:G:R:x 10:10:10:2 little endian */ |
140 | |
141 | #define DRM_FORMAT_ARGB2101010 fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little endian */ |
142 | #define DRM_FORMAT_ABGR2101010 fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little endian */ |
143 | #define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */ |
144 | #define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */ |
145 | |
146 | /* |
147 | * Floating point 64bpp RGB |
148 | * IEEE 754-2008 binary16 half-precision float |
149 | * [15:0] sign:exponent:mantissa 1:5:10 |
150 | */ |
151 | #define DRM_FORMAT_XRGB16161616F fourcc_code('X', 'R', '4', 'H') /* [63:0] x:R:G:B 16:16:16:16 little endian */ |
152 | #define DRM_FORMAT_XBGR16161616F fourcc_code('X', 'B', '4', 'H') /* [63:0] x:B:G:R 16:16:16:16 little endian */ |
153 | |
154 | #define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */ |
155 | #define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */ |
156 | |
157 | /* packed YCbCr */ |
158 | #define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */ |
159 | #define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */ |
160 | #define DRM_FORMAT_UYVY fourcc_code('U', 'Y', 'V', 'Y') /* [31:0] Y1:Cr0:Y0:Cb0 8:8:8:8 little endian */ |
161 | #define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */ |
162 | |
163 | #define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */ |
164 | #define DRM_FORMAT_XYUV8888 fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */ |
165 | #define DRM_FORMAT_VUY888 fourcc_code('V', 'U', '2', '4') /* [23:0] Cr:Cb:Y 8:8:8 little endian */ |
166 | #define DRM_FORMAT_VUY101010 fourcc_code('V', 'U', '3', '0') /* Y followed by U then V, 10:10:10. Non-linear modifier only */ |
167 | |
168 | /* |
169 | * packed Y2xx indicate for each component, xx valid data occupy msb |
170 | * 16-xx padding occupy lsb |
171 | */ |
172 | #define DRM_FORMAT_Y210 fourcc_code('Y', '2', '1', '0') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 10:6:10:6:10:6:10:6 little endian per 2 Y pixels */ |
173 | #define DRM_FORMAT_Y212 fourcc_code('Y', '2', '1', '2') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 12:4:12:4:12:4:12:4 little endian per 2 Y pixels */ |
174 | #define DRM_FORMAT_Y216 fourcc_code('Y', '2', '1', '6') /* [63:0] Cr0:Y1:Cb0:Y0 16:16:16:16 little endian per 2 Y pixels */ |
175 | |
176 | /* |
177 | * packed Y4xx indicate for each component, xx valid data occupy msb |
178 | * 16-xx padding occupy lsb except Y410 |
179 | */ |
180 | #define DRM_FORMAT_Y410 fourcc_code('Y', '4', '1', '0') /* [31:0] A:Cr:Y:Cb 2:10:10:10 little endian */ |
181 | #define DRM_FORMAT_Y412 fourcc_code('Y', '4', '1', '2') /* [63:0] A:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */ |
182 | #define DRM_FORMAT_Y416 fourcc_code('Y', '4', '1', '6') /* [63:0] A:Cr:Y:Cb 16:16:16:16 little endian */ |
183 | |
184 | #define DRM_FORMAT_XVYU2101010 fourcc_code('X', 'V', '3', '0') /* [31:0] X:Cr:Y:Cb 2:10:10:10 little endian */ |
185 | #define DRM_FORMAT_XVYU12_16161616 fourcc_code('X', 'V', '3', '6') /* [63:0] X:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */ |
186 | #define DRM_FORMAT_XVYU16161616 fourcc_code('X', 'V', '4', '8') /* [63:0] X:Cr:Y:Cb 16:16:16:16 little endian */ |
187 | |
188 | /* |
189 | * packed YCbCr420 2x2 tiled formats |
190 | * first 64 bits will contain Y,Cb,Cr components for a 2x2 tile |
191 | */ |
192 | /* [63:0] A3:A2:Y3:0:Cr0:0:Y2:0:A1:A0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */ |
193 | #define DRM_FORMAT_Y0L0 fourcc_code('Y', '0', 'L', '0') |
194 | /* [63:0] X3:X2:Y3:0:Cr0:0:Y2:0:X1:X0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */ |
195 | #define DRM_FORMAT_X0L0 fourcc_code('X', '0', 'L', '0') |
196 | |
197 | /* [63:0] A3:A2:Y3:Cr0:Y2:A1:A0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */ |
198 | #define DRM_FORMAT_Y0L2 fourcc_code('Y', '0', 'L', '2') |
199 | /* [63:0] X3:X2:Y3:Cr0:Y2:X1:X0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */ |
200 | #define DRM_FORMAT_X0L2 fourcc_code('X', '0', 'L', '2') |
201 | |
202 | /* |
203 | * 1-plane YUV 4:2:0 |
204 | * In these formats, the component ordering is specified (Y, followed by U |
205 | * then V), but the exact Linear layout is undefined. |
206 | * These formats can only be used with a non-Linear modifier. |
207 | */ |
208 | #define DRM_FORMAT_YUV420_8BIT fourcc_code('Y', 'U', '0', '8') |
209 | #define DRM_FORMAT_YUV420_10BIT fourcc_code('Y', 'U', '1', '0') |
210 | |
211 | /* |
212 | * 2 plane RGB + A |
213 | * index 0 = RGB plane, same format as the corresponding non _A8 format has |
214 | * index 1 = A plane, [7:0] A |
215 | */ |
216 | #define DRM_FORMAT_XRGB8888_A8 fourcc_code('X', 'R', 'A', '8') |
217 | #define DRM_FORMAT_XBGR8888_A8 fourcc_code('X', 'B', 'A', '8') |
218 | #define DRM_FORMAT_RGBX8888_A8 fourcc_code('R', 'X', 'A', '8') |
219 | #define DRM_FORMAT_BGRX8888_A8 fourcc_code('B', 'X', 'A', '8') |
220 | #define DRM_FORMAT_RGB888_A8 fourcc_code('R', '8', 'A', '8') |
221 | #define DRM_FORMAT_BGR888_A8 fourcc_code('B', '8', 'A', '8') |
222 | #define DRM_FORMAT_RGB565_A8 fourcc_code('R', '5', 'A', '8') |
223 | #define DRM_FORMAT_BGR565_A8 fourcc_code('B', '5', 'A', '8') |
224 | |
225 | /* |
226 | * 2 plane YCbCr |
227 | * index 0 = Y plane, [7:0] Y |
228 | * index 1 = Cr:Cb plane, [15:0] Cr:Cb little endian |
229 | * or |
230 | * index 1 = Cb:Cr plane, [15:0] Cb:Cr little endian |
231 | */ |
232 | #define DRM_FORMAT_NV12 fourcc_code('N', 'V', '1', '2') /* 2x2 subsampled Cr:Cb plane */ |
233 | #define DRM_FORMAT_NV21 fourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */ |
234 | #define DRM_FORMAT_NV16 fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */ |
235 | #define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */ |
236 | #define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */ |
237 | #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */ |
238 | |
239 | /* |
240 | * 2 plane YCbCr MSB aligned |
241 | * index 0 = Y plane, [15:0] Y:x [10:6] little endian |
242 | * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian |
243 | */ |
244 | #define DRM_FORMAT_P210 fourcc_code('P', '2', '1', '0') /* 2x1 subsampled Cr:Cb plane, 10 bit per channel */ |
245 | |
246 | /* |
247 | * 2 plane YCbCr MSB aligned |
248 | * index 0 = Y plane, [15:0] Y:x [10:6] little endian |
249 | * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian |
250 | */ |
251 | #define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel */ |
252 | |
253 | /* |
254 | * 2 plane YCbCr MSB aligned |
255 | * index 0 = Y plane, [15:0] Y:x [12:4] little endian |
256 | * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [12:4:12:4] little endian |
257 | */ |
258 | #define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cr:Cb plane 12 bits per channel */ |
259 | |
260 | /* |
261 | * 2 plane YCbCr MSB aligned |
262 | * index 0 = Y plane, [15:0] Y little endian |
263 | * index 1 = Cr:Cb plane, [31:0] Cr:Cb [16:16] little endian |
264 | */ |
265 | #define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */ |
266 | |
267 | /* |
268 | * 3 plane YCbCr |
269 | * index 0: Y plane, [7:0] Y |
270 | * index 1: Cb plane, [7:0] Cb |
271 | * index 2: Cr plane, [7:0] Cr |
272 | * or |
273 | * index 1: Cr plane, [7:0] Cr |
274 | * index 2: Cb plane, [7:0] Cb |
275 | */ |
276 | #define DRM_FORMAT_YUV410 fourcc_code('Y', 'U', 'V', '9') /* 4x4 subsampled Cb (1) and Cr (2) planes */ |
277 | #define DRM_FORMAT_YVU410 fourcc_code('Y', 'V', 'U', '9') /* 4x4 subsampled Cr (1) and Cb (2) planes */ |
278 | #define DRM_FORMAT_YUV411 fourcc_code('Y', 'U', '1', '1') /* 4x1 subsampled Cb (1) and Cr (2) planes */ |
279 | #define DRM_FORMAT_YVU411 fourcc_code('Y', 'V', '1', '1') /* 4x1 subsampled Cr (1) and Cb (2) planes */ |
280 | #define DRM_FORMAT_YUV420 fourcc_code('Y', 'U', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes */ |
281 | #define DRM_FORMAT_YVU420 fourcc_code('Y', 'V', '1', '2') /* 2x2 subsampled Cr (1) and Cb (2) planes */ |
282 | #define DRM_FORMAT_YUV422 fourcc_code('Y', 'U', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes */ |
283 | #define DRM_FORMAT_YVU422 fourcc_code('Y', 'V', '1', '6') /* 2x1 subsampled Cr (1) and Cb (2) planes */ |
284 | #define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */ |
285 | #define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */ |
286 | |
287 | |
288 | /* |
289 | * Format Modifiers: |
290 | * |
291 | * Format modifiers describe, typically, a re-ordering or modification |
292 | * of the data in a plane of an FB. This can be used to express tiled/ |
293 | * swizzled formats, or compression, or a combination of the two. |
294 | * |
295 | * The upper 8 bits of the format modifier are a vendor-id as assigned |
296 | * below. The lower 56 bits are assigned as vendor sees fit. |
297 | */ |
298 | |
299 | /* Vendor Ids: */ |
300 | #define DRM_FORMAT_MOD_NONE 0 |
301 | #define DRM_FORMAT_MOD_VENDOR_NONE 0 |
302 | #define DRM_FORMAT_MOD_VENDOR_INTEL 0x01 |
303 | #define DRM_FORMAT_MOD_VENDOR_AMD 0x02 |
304 | #define DRM_FORMAT_MOD_VENDOR_NVIDIA 0x03 |
305 | #define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04 |
306 | #define DRM_FORMAT_MOD_VENDOR_QCOM 0x05 |
307 | #define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06 |
308 | #define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07 |
309 | #define DRM_FORMAT_MOD_VENDOR_ARM 0x08 |
310 | #define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09 |
311 | |
312 | /* add more to the end as needed */ |
313 | |
314 | #define DRM_FORMAT_RESERVED ((1ULL << 56) - 1) |
315 | |
316 | #define fourcc_mod_code(vendor, val) \ |
317 | ((((uint64_t)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | ((val) & 0x00ffffffffffffffULL)) |
318 | |
319 | /* |
320 | * Format Modifier tokens: |
321 | * |
322 | * When adding a new token please document the layout with a code comment, |
323 | * similar to the fourcc codes above. drm_fourcc.h is considered the |
324 | * authoritative source for all of these. |
325 | */ |
326 | |
327 | /* |
328 | * Invalid Modifier |
329 | * |
330 | * This modifier can be used as a sentinel to terminate the format modifiers |
331 | * list, or to initialize a variable with an invalid modifier. It might also be |
332 | * used to report an error back to userspace for certain APIs. |
333 | */ |
334 | #define DRM_FORMAT_MOD_INVALID fourcc_mod_code(NONE, DRM_FORMAT_RESERVED) |
335 | |
336 | /* |
337 | * Linear Layout |
338 | * |
339 | * Just plain linear layout. Note that this is different from no specifying any |
340 | * modifier (e.g. not setting DRM_MODE_FB_MODIFIERS in the DRM_ADDFB2 ioctl), |
341 | * which tells the driver to also take driver-internal information into account |
342 | * and so might actually result in a tiled framebuffer. |
343 | */ |
344 | #define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0) |
345 | |
346 | /* Intel framebuffer modifiers */ |
347 | |
348 | /* |
349 | * Intel X-tiling layout |
350 | * |
351 | * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb) |
352 | * in row-major layout. Within the tile bytes are laid out row-major, with |
353 | * a platform-dependent stride. On top of that the memory can apply |
354 | * platform-depending swizzling of some higher address bits into bit6. |
355 | * |
356 | * This format is highly platforms specific and not useful for cross-driver |
357 | * sharing. It exists since on a given platform it does uniquely identify the |
358 | * layout in a simple way for i915-specific userspace. |
359 | */ |
360 | #define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1) |
361 | |
362 | /* |
363 | * Intel Y-tiling layout |
364 | * |
365 | * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb) |
366 | * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes) |
367 | * chunks column-major, with a platform-dependent height. On top of that the |
368 | * memory can apply platform-depending swizzling of some higher address bits |
369 | * into bit6. |
370 | * |
371 | * This format is highly platforms specific and not useful for cross-driver |
372 | * sharing. It exists since on a given platform it does uniquely identify the |
373 | * layout in a simple way for i915-specific userspace. |
374 | */ |
375 | #define I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2) |
376 | |
377 | /* |
378 | * Intel Yf-tiling layout |
379 | * |
380 | * This is a tiled layout using 4Kb tiles in row-major layout. |
381 | * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which |
382 | * are arranged in four groups (two wide, two high) with column-major layout. |
383 | * Each group therefore consits out of four 256 byte units, which are also laid |
384 | * out as 2x2 column-major. |
385 | * 256 byte units are made out of four 64 byte blocks of pixels, producing |
386 | * either a square block or a 2:1 unit. |
387 | * 64 byte blocks of pixels contain four pixel rows of 16 bytes, where the width |
388 | * in pixel depends on the pixel depth. |
389 | */ |
390 | #define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3) |
391 | |
392 | /* |
393 | * Intel color control surface (CCS) for render compression |
394 | * |
395 | * The framebuffer format must be one of the 8:8:8:8 RGB formats. |
396 | * The main surface will be plane index 0 and must be Y/Yf-tiled, |
397 | * the CCS will be plane index 1. |
398 | * |
399 | * Each CCS tile matches a 1024x512 pixel area of the main surface. |
400 | * To match certain aspects of the 3D hardware the CCS is |
401 | * considered to be made up of normal 128Bx32 Y tiles, Thus |
402 | * the CCS pitch must be specified in multiples of 128 bytes. |
403 | * |
404 | * In reality the CCS tile appears to be a 64Bx64 Y tile, composed |
405 | * of QWORD (8 bytes) chunks instead of OWORD (16 bytes) chunks. |
406 | * But that fact is not relevant unless the memory is accessed |
407 | * directly. |
408 | */ |
409 | #define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4) |
410 | #define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5) |
411 | |
412 | /* |
413 | * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks |
414 | * |
415 | * Macroblocks are laid in a Z-shape, and each pixel data is following the |
416 | * standard NV12 style. |
417 | * As for NV12, an image is the result of two frame buffers: one for Y, |
418 | * one for the interleaved Cb/Cr components (1/2 the height of the Y buffer). |
419 | * Alignment requirements are (for each buffer): |
420 | * - multiple of 128 pixels for the width |
421 | * - multiple of 32 pixels for the height |
422 | * |
423 | * For more information: see https://linuxtv.org/downloads/v4l-dvb-apis/re32.html |
424 | */ |
425 | #define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1) |
426 | |
427 | /* |
428 | * Tiled, 16 (pixels) x 16 (lines) - sized macroblocks |
429 | * |
430 | * This is a simple tiled layout using tiles of 16x16 pixels in a row-major |
431 | * layout. For YCbCr formats Cb/Cr components are taken in such a way that |
432 | * they correspond to their 16x16 luma block. |
433 | */ |
434 | #define DRM_FORMAT_MOD_SAMSUNG_16_16_TILE fourcc_mod_code(SAMSUNG, 2) |
435 | |
436 | /* |
437 | * Qualcomm Compressed Format |
438 | * |
439 | * Refers to a compressed variant of the base format that is compressed. |
440 | * Implementation may be platform and base-format specific. |
441 | * |
442 | * Each macrotile consists of m x n (mostly 4 x 4) tiles. |
443 | * Pixel data pitch/stride is aligned with macrotile width. |
444 | * Pixel data height is aligned with macrotile height. |
445 | * Entire pixel data buffer is aligned with 4k(bytes). |
446 | */ |
447 | #define DRM_FORMAT_MOD_QCOM_COMPRESSED fourcc_mod_code(QCOM, 1) |
448 | |
449 | /* Vivante framebuffer modifiers */ |
450 | |
451 | /* |
452 | * Vivante 4x4 tiling layout |
453 | * |
454 | * This is a simple tiled layout using tiles of 4x4 pixels in a row-major |
455 | * layout. |
456 | */ |
457 | #define DRM_FORMAT_MOD_VIVANTE_TILED fourcc_mod_code(VIVANTE, 1) |
458 | |
459 | /* |
460 | * Vivante 64x64 super-tiling layout |
461 | * |
462 | * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile |
463 | * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row- |
464 | * major layout. |
465 | * |
466 | * For more information: see |
467 | * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling |
468 | */ |
469 | #define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED fourcc_mod_code(VIVANTE, 2) |
470 | |
471 | /* |
472 | * Vivante 4x4 tiling layout for dual-pipe |
473 | * |
474 | * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a |
475 | * different base address. Offsets from the base addresses are therefore halved |
476 | * compared to the non-split tiled layout. |
477 | */ |
478 | #define DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED fourcc_mod_code(VIVANTE, 3) |
479 | |
480 | /* |
481 | * Vivante 64x64 super-tiling layout for dual-pipe |
482 | * |
483 | * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile |
484 | * starts at a different base address. Offsets from the base addresses are |
485 | * therefore halved compared to the non-split super-tiled layout. |
486 | */ |
487 | #define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4) |
488 | |
489 | /* NVIDIA frame buffer modifiers */ |
490 | |
491 | /* |
492 | * Tegra Tiled Layout, used by Tegra 2, 3 and 4. |
493 | * |
494 | * Pixels are arranged in simple tiles of 16 x 16 bytes. |
495 | */ |
496 | #define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1) |
497 | |
498 | /* |
499 | * 16Bx2 Block Linear layout, used by desktop GPUs, and Tegra K1 and later |
500 | * |
501 | * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked |
502 | * vertically by a power of 2 (1 to 32 GOBs) to form a block. |
503 | * |
504 | * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape. |
505 | * |
506 | * Parameter 'v' is the log2 encoding of the number of GOBs stacked vertically. |
507 | * Valid values are: |
508 | * |
509 | * 0 == ONE_GOB |
510 | * 1 == TWO_GOBS |
511 | * 2 == FOUR_GOBS |
512 | * 3 == EIGHT_GOBS |
513 | * 4 == SIXTEEN_GOBS |
514 | * 5 == THIRTYTWO_GOBS |
515 | * |
516 | * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format |
517 | * in full detail. |
518 | */ |
519 | #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) \ |
520 | fourcc_mod_code(NVIDIA, 0x10 | ((v) & 0xf)) |
521 | |
522 | #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB \ |
523 | fourcc_mod_code(NVIDIA, 0x10) |
524 | #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB \ |
525 | fourcc_mod_code(NVIDIA, 0x11) |
526 | #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB \ |
527 | fourcc_mod_code(NVIDIA, 0x12) |
528 | #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB \ |
529 | fourcc_mod_code(NVIDIA, 0x13) |
530 | #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB \ |
531 | fourcc_mod_code(NVIDIA, 0x14) |
532 | #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB \ |
533 | fourcc_mod_code(NVIDIA, 0x15) |
534 | |
535 | /* |
536 | * Some Broadcom modifiers take parameters, for example the number of |
537 | * vertical lines in the image. Reserve the lower 32 bits for modifier |
538 | * type, and the next 24 bits for parameters. Top 8 bits are the |
539 | * vendor code. |
540 | */ |
541 | #define __fourcc_mod_broadcom_param_shift 8 |
542 | #define __fourcc_mod_broadcom_param_bits 48 |
543 | #define fourcc_mod_broadcom_code(val, params) \ |
544 | fourcc_mod_code(BROADCOM, ((((uint64_t)params) << __fourcc_mod_broadcom_param_shift) | val)) |
545 | #define fourcc_mod_broadcom_param(m) \ |
546 | ((int)(((m) >> __fourcc_mod_broadcom_param_shift) & \ |
547 | ((1ULL << __fourcc_mod_broadcom_param_bits) - 1))) |
548 | #define fourcc_mod_broadcom_mod(m) \ |
549 | ((m) & ~(((1ULL << __fourcc_mod_broadcom_param_bits) - 1) << \ |
550 | __fourcc_mod_broadcom_param_shift)) |
551 | |
552 | /* |
553 | * Broadcom VC4 "T" format |
554 | * |
555 | * This is the primary layout that the V3D GPU can texture from (it |
556 | * can't do linear). The T format has: |
557 | * |
558 | * - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4 |
559 | * pixels at 32 bit depth. |
560 | * |
561 | * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually |
562 | * 16x16 pixels). |
563 | * |
564 | * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On |
565 | * even 4k tile rows, they're arranged as (BL, TL, TR, BR), and on odd rows |
566 | * they're (TR, BR, BL, TL), where bottom left is start of memory. |
567 | * |
568 | * - an image made of 4k tiles in rows either left-to-right (even rows of 4k |
569 | * tiles) or right-to-left (odd rows of 4k tiles). |
570 | */ |
571 | #define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1) |
572 | |
573 | /* |
574 | * Broadcom SAND format |
575 | * |
576 | * This is the native format that the H.264 codec block uses. For VC4 |
577 | * HVS, it is only valid for H.264 (NV12/21) and RGBA modes. |
578 | * |
579 | * The image can be considered to be split into columns, and the |
580 | * columns are placed consecutively into memory. The width of those |
581 | * columns can be either 32, 64, 128, or 256 pixels, but in practice |
582 | * only 128 pixel columns are used. |
583 | * |
584 | * The pitch between the start of each column is set to optimally |
585 | * switch between SDRAM banks. This is passed as the number of lines |
586 | * of column width in the modifier (we can't use the stride value due |
587 | * to various core checks that look at it , so you should set the |
588 | * stride to width*cpp). |
589 | * |
590 | * Note that the column height for this format modifier is the same |
591 | * for all of the planes, assuming that each column contains both Y |
592 | * and UV. Some SAND-using hardware stores UV in a separate tiled |
593 | * image from Y to reduce the column height, which is not supported |
594 | * with these modifiers. |
595 | */ |
596 | |
597 | #define DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(v) \ |
598 | fourcc_mod_broadcom_code(2, v) |
599 | #define DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(v) \ |
600 | fourcc_mod_broadcom_code(3, v) |
601 | #define DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(v) \ |
602 | fourcc_mod_broadcom_code(4, v) |
603 | #define DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(v) \ |
604 | fourcc_mod_broadcom_code(5, v) |
605 | |
606 | #define DRM_FORMAT_MOD_BROADCOM_SAND32 \ |
607 | DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(0) |
608 | #define DRM_FORMAT_MOD_BROADCOM_SAND64 \ |
609 | DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(0) |
610 | #define DRM_FORMAT_MOD_BROADCOM_SAND128 \ |
611 | DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(0) |
612 | #define DRM_FORMAT_MOD_BROADCOM_SAND256 \ |
613 | DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(0) |
614 | |
615 | /* Broadcom UIF format |
616 | * |
617 | * This is the common format for the current Broadcom multimedia |
618 | * blocks, including V3D 3.x and newer, newer video codecs, and |
619 | * displays. |
620 | * |
621 | * The image consists of utiles (64b blocks), UIF blocks (2x2 utiles), |
622 | * and macroblocks (4x4 UIF blocks). Those 4x4 UIF block groups are |
623 | * stored in columns, with padding between the columns to ensure that |
624 | * moving from one column to the next doesn't hit the same SDRAM page |
625 | * bank. |
626 | * |
627 | * To calculate the padding, it is assumed that each hardware block |
628 | * and the software driving it knows the platform's SDRAM page size, |
629 | * number of banks, and XOR address, and that it's identical between |
630 | * all blocks using the format. This tiling modifier will use XOR as |
631 | * necessary to reduce the padding. If a hardware block can't do XOR, |
632 | * the assumption is that a no-XOR tiling modifier will be created. |
633 | */ |
634 | #define DRM_FORMAT_MOD_BROADCOM_UIF fourcc_mod_code(BROADCOM, 6) |
635 | |
636 | /* |
637 | * Arm Framebuffer Compression (AFBC) modifiers |
638 | * |
639 | * AFBC is a proprietary lossless image compression protocol and format. |
640 | * It provides fine-grained random access and minimizes the amount of data |
641 | * transferred between IP blocks. |
642 | * |
643 | * AFBC has several features which may be supported and/or used, which are |
644 | * represented using bits in the modifier. Not all combinations are valid, |
645 | * and different devices or use-cases may support different combinations. |
646 | * |
647 | * Further information on the use of AFBC modifiers can be found in |
648 | * Documentation/gpu/afbc.rst |
649 | */ |
650 | #define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) fourcc_mod_code(ARM, __afbc_mode) |
651 | |
652 | /* |
653 | * AFBC superblock size |
654 | * |
655 | * Indicates the superblock size(s) used for the AFBC buffer. The buffer |
656 | * size (in pixels) must be aligned to a multiple of the superblock size. |
657 | * Four lowest significant bits(LSBs) are reserved for block size. |
658 | * |
659 | * Where one superblock size is specified, it applies to all planes of the |
660 | * buffer (e.g. 16x16, 32x8). When multiple superblock sizes are specified, |
661 | * the first applies to the Luma plane and the second applies to the Chroma |
662 | * plane(s). e.g. (32x8_64x4 means 32x8 Luma, with 64x4 Chroma). |
663 | * Multiple superblock sizes are only valid for multi-plane YCbCr formats. |
664 | */ |
665 | #define AFBC_FORMAT_MOD_BLOCK_SIZE_MASK 0xf |
666 | #define AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 (1ULL) |
667 | #define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 (2ULL) |
668 | #define AFBC_FORMAT_MOD_BLOCK_SIZE_64x4 (3ULL) |
669 | #define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8_64x4 (4ULL) |
670 | |
671 | /* |
672 | * AFBC lossless colorspace transform |
673 | * |
674 | * Indicates that the buffer makes use of the AFBC lossless colorspace |
675 | * transform. |
676 | */ |
677 | #define AFBC_FORMAT_MOD_YTR (1ULL << 4) |
678 | |
679 | /* |
680 | * AFBC block-split |
681 | * |
682 | * Indicates that the payload of each superblock is split. The second |
683 | * half of the payload is positioned at a predefined offset from the start |
684 | * of the superblock payload. |
685 | */ |
686 | #define AFBC_FORMAT_MOD_SPLIT (1ULL << 5) |
687 | |
688 | /* |
689 | * AFBC sparse layout |
690 | * |
691 | * This flag indicates that the payload of each superblock must be stored at a |
692 | * predefined position relative to the other superblocks in the same AFBC |
693 | * buffer. This order is the same order used by the header buffer. In this mode |
694 | * each superblock is given the same amount of space as an uncompressed |
695 | * superblock of the particular format would require, rounding up to the next |
696 | * multiple of 128 bytes in size. |
697 | */ |
698 | #define AFBC_FORMAT_MOD_SPARSE (1ULL << 6) |
699 | |
700 | /* |
701 | * AFBC copy-block restrict |
702 | * |
703 | * Buffers with this flag must obey the copy-block restriction. The restriction |
704 | * is such that there are no copy-blocks referring across the border of 8x8 |
705 | * blocks. For the subsampled data the 8x8 limitation is also subsampled. |
706 | */ |
707 | #define AFBC_FORMAT_MOD_CBR (1ULL << 7) |
708 | |
709 | /* |
710 | * AFBC tiled layout |
711 | * |
712 | * The tiled layout groups superblocks in 8x8 or 4x4 tiles, where all |
713 | * superblocks inside a tile are stored together in memory. 8x8 tiles are used |
714 | * for pixel formats up to and including 32 bpp while 4x4 tiles are used for |
715 | * larger bpp formats. The order between the tiles is scan line. |
716 | * When the tiled layout is used, the buffer size (in pixels) must be aligned |
717 | * to the tile size. |
718 | */ |
719 | #define AFBC_FORMAT_MOD_TILED (1ULL << 8) |
720 | |
721 | /* |
722 | * AFBC solid color blocks |
723 | * |
724 | * Indicates that the buffer makes use of solid-color blocks, whereby bandwidth |
725 | * can be reduced if a whole superblock is a single color. |
726 | */ |
727 | #define AFBC_FORMAT_MOD_SC (1ULL << 9) |
728 | |
729 | /* |
730 | * AFBC double-buffer |
731 | * |
732 | * Indicates that the buffer is allocated in a layout safe for front-buffer |
733 | * rendering. |
734 | */ |
735 | #define AFBC_FORMAT_MOD_DB (1ULL << 10) |
736 | |
737 | /* |
738 | * AFBC buffer content hints |
739 | * |
740 | * Indicates that the buffer includes per-superblock content hints. |
741 | */ |
742 | #define AFBC_FORMAT_MOD_BCH (1ULL << 11) |
743 | |
744 | /* |
745 | * Allwinner tiled modifier |
746 | * |
747 | * This tiling mode is implemented by the VPU found on all Allwinner platforms, |
748 | * codenamed sunxi. It is associated with a YUV format that uses either 2 or 3 |
749 | * planes. |
750 | * |
751 | * With this tiling, the luminance samples are disposed in tiles representing |
752 | * 32x32 pixels and the chrominance samples in tiles representing 32x64 pixels. |
753 | * The pixel order in each tile is linear and the tiles are disposed linearly, |
754 | * both in row-major order. |
755 | */ |
756 | #define DRM_FORMAT_MOD_ALLWINNER_TILED fourcc_mod_code(ALLWINNER, 1) |
757 | |
758 | #if defined(__cplusplus) |
759 | } |
760 | #endif |
761 | |
762 | #endif /* DRM_FOURCC_H */ |
763 | |