1 | /* cris.h -- Header file for CRIS opcode and register tables. |
2 | Copyright (C) 2000, 2001, 2004 Free Software Foundation, Inc. |
3 | Contributed by Axis Communications AB, Lund, Sweden. |
4 | Originally written for GAS 1.38.1 by Mikael Asker. |
5 | Updated, BFDized and GNUified by Hans-Peter Nilsson. |
6 | |
7 | This file is part of GAS, GDB and the GNU binutils. |
8 | |
9 | GAS, GDB, and GNU binutils is free software; you can redistribute it |
10 | and/or modify it under the terms of the GNU General Public License as |
11 | published by the Free Software Foundation; either version 2, or (at your |
12 | option) any later version. |
13 | |
14 | GAS, GDB, and GNU binutils are distributed in the hope that they will be |
15 | useful, but WITHOUT ANY WARRANTY; without even the implied warranty of |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
17 | GNU General Public License for more details. |
18 | |
19 | You should have received a copy of the GNU General Public License |
20 | along with this program; if not, see <http://www.gnu.org/licenses/>. */ |
21 | |
22 | #ifndef TARGET_CRIS_OPCODE_CRIS_H |
23 | #define TARGET_CRIS_OPCODE_CRIS_H |
24 | |
25 | #if !defined(__STDC__) && !defined(const) |
26 | #define const |
27 | #endif |
28 | |
29 | |
30 | /* Registers. */ |
31 | #define MAX_REG (15) |
32 | #define CRIS_REG_SP (14) |
33 | #define CRIS_REG_PC (15) |
34 | |
35 | /* CPU version control of disassembly and assembly of instructions. |
36 | May affect how the instruction is assembled, at least the size of |
37 | immediate operands. */ |
38 | enum cris_insn_version_usage |
39 | { |
40 | /* Any version. */ |
41 | cris_ver_version_all=0, |
42 | |
43 | /* Indeterminate (intended for disassembly only, or obsolete). */ |
44 | cris_ver_warning, |
45 | |
46 | /* Only for v0..3 (Etrax 1..4). */ |
47 | cris_ver_v0_3, |
48 | |
49 | /* Only for v3 or higher (ETRAX 4 and beyond). */ |
50 | cris_ver_v3p, |
51 | |
52 | /* Only for v8 (Etrax 100). */ |
53 | cris_ver_v8, |
54 | |
55 | /* Only for v8 or higher (ETRAX 100, ETRAX 100 LX). */ |
56 | cris_ver_v8p, |
57 | |
58 | /* Only for v0..10. FIXME: Not sure what to do with this. */ |
59 | cris_ver_sim_v0_10, |
60 | |
61 | /* Only for v0..10. */ |
62 | cris_ver_v0_10, |
63 | |
64 | /* Only for v3..10. (ETRAX 4, ETRAX 100 and ETRAX 100 LX). */ |
65 | cris_ver_v3_10, |
66 | |
67 | /* Only for v8..10 (ETRAX 100 and ETRAX 100 LX). */ |
68 | cris_ver_v8_10, |
69 | |
70 | /* Only for v10 (ETRAX 100 LX) and same series. */ |
71 | cris_ver_v10, |
72 | |
73 | /* Only for v10 (ETRAX 100 LX) and same series. */ |
74 | cris_ver_v10p, |
75 | |
76 | /* Only for v32 or higher (codename GUINNESS). |
77 | Of course some or all these of may change to cris_ver_v32p if/when |
78 | there's a new revision. */ |
79 | cris_ver_v32p |
80 | }; |
81 | |
82 | |
83 | /* Special registers. */ |
84 | struct cris_spec_reg |
85 | { |
86 | const char *const name; |
87 | unsigned int number; |
88 | |
89 | /* The size of the register. */ |
90 | unsigned int reg_size; |
91 | |
92 | /* What CPU version the special register of that name is implemented |
93 | in. If cris_ver_warning, emit an unimplemented-warning. */ |
94 | enum cris_insn_version_usage applicable_version; |
95 | |
96 | /* There might be a specific warning for using a special register |
97 | here. */ |
98 | const char *const warning; |
99 | }; |
100 | extern const struct cris_spec_reg cris_spec_regs[]; |
101 | |
102 | |
103 | /* Support registers (kind of special too, but not named as such). */ |
104 | struct cris_support_reg |
105 | { |
106 | const char *const name; |
107 | unsigned int number; |
108 | }; |
109 | extern const struct cris_support_reg cris_support_regs[]; |
110 | |
111 | /* Opcode-dependent constants. */ |
112 | #define AUTOINCR_BIT (0x04) |
113 | |
114 | /* Prefixes. */ |
115 | #define BDAP_QUICK_OPCODE (0x0100) |
116 | #define BDAP_QUICK_Z_BITS (0x0e00) |
117 | |
118 | #define BIAP_OPCODE (0x0540) |
119 | #define BIAP_Z_BITS (0x0a80) |
120 | |
121 | #define DIP_OPCODE (0x0970) |
122 | #define DIP_Z_BITS (0xf280) |
123 | |
124 | #define BDAP_INDIR_LOW (0x40) |
125 | #define BDAP_INDIR_LOW_Z (0x80) |
126 | #define BDAP_INDIR_HIGH (0x09) |
127 | #define BDAP_INDIR_HIGH_Z (0x02) |
128 | |
129 | #define BDAP_INDIR_OPCODE (BDAP_INDIR_HIGH * 0x0100 + BDAP_INDIR_LOW) |
130 | #define BDAP_INDIR_Z_BITS (BDAP_INDIR_HIGH_Z * 0x100 + BDAP_INDIR_LOW_Z) |
131 | #define BDAP_PC_LOW (BDAP_INDIR_LOW + CRIS_REG_PC) |
132 | #define BDAP_INCR_HIGH (BDAP_INDIR_HIGH + AUTOINCR_BIT) |
133 | |
134 | /* No prefix must have this code for its "match" bits in the |
135 | opcode-table. "BCC .+2" will do nicely. */ |
136 | #define NO_CRIS_PREFIX 0 |
137 | |
138 | /* Definitions for condition codes. */ |
139 | #define CC_CC 0x0 |
140 | #define CC_HS 0x0 |
141 | #define CC_CS 0x1 |
142 | #define CC_LO 0x1 |
143 | #define CC_NE 0x2 |
144 | #define CC_EQ 0x3 |
145 | #define CC_VC 0x4 |
146 | #define CC_VS 0x5 |
147 | #define CC_PL 0x6 |
148 | #define CC_MI 0x7 |
149 | #define CC_LS 0x8 |
150 | #define CC_HI 0x9 |
151 | #define CC_GE 0xA |
152 | #define CC_LT 0xB |
153 | #define CC_GT 0xC |
154 | #define CC_LE 0xD |
155 | #define CC_A 0xE |
156 | #define CC_EXT 0xF |
157 | |
158 | /* A table of strings "cc", "cs"... indexed with condition code |
159 | values as above. */ |
160 | extern const char *const cris_cc_strings[]; |
161 | |
162 | /* Bcc quick. */ |
163 | #define BRANCH_QUICK_LOW (0) |
164 | #define BRANCH_QUICK_HIGH (0) |
165 | #define BRANCH_QUICK_OPCODE (BRANCH_QUICK_HIGH * 0x0100 + BRANCH_QUICK_LOW) |
166 | #define BRANCH_QUICK_Z_BITS (0x0F00) |
167 | |
168 | /* BA quick. */ |
169 | #define BA_QUICK_HIGH (BRANCH_QUICK_HIGH + CC_A * 0x10) |
170 | #define BA_QUICK_OPCODE (BA_QUICK_HIGH * 0x100 + BRANCH_QUICK_LOW) |
171 | |
172 | /* Bcc [PC+]. */ |
173 | #define BRANCH_PC_LOW (0xFF) |
174 | #define BRANCH_INCR_HIGH (0x0D) |
175 | #define BA_PC_INCR_OPCODE \ |
176 | ((BRANCH_INCR_HIGH + CC_A * 0x10) * 0x0100 + BRANCH_PC_LOW) |
177 | |
178 | /* Jump. */ |
179 | /* Note that old versions generated special register 8 (in high bits) |
180 | and not-that-old versions recognized it as a jump-instruction. |
181 | That opcode now belongs to JUMPU. */ |
182 | #define JUMP_INDIR_OPCODE (0x0930) |
183 | #define JUMP_INDIR_Z_BITS (0xf2c0) |
184 | #define JUMP_PC_INCR_OPCODE \ |
185 | (JUMP_INDIR_OPCODE + AUTOINCR_BIT * 0x0100 + CRIS_REG_PC) |
186 | |
187 | #define MOVE_M_TO_PREG_OPCODE 0x0a30 |
188 | #define MOVE_M_TO_PREG_ZBITS 0x01c0 |
189 | |
190 | /* BDAP.D N,PC. */ |
191 | #define MOVE_PC_INCR_OPCODE_PREFIX \ |
192 | (((BDAP_INCR_HIGH | (CRIS_REG_PC << 4)) << 8) | BDAP_PC_LOW | (2 << 4)) |
193 | #define MOVE_PC_INCR_OPCODE_SUFFIX \ |
194 | (MOVE_M_TO_PREG_OPCODE | CRIS_REG_PC | (AUTOINCR_BIT << 8)) |
195 | |
196 | #define JUMP_PC_INCR_OPCODE_V32 (0x0DBF) |
197 | |
198 | /* BA DWORD (V32). */ |
199 | #define BA_DWORD_OPCODE (0x0EBF) |
200 | |
201 | /* Nop. */ |
202 | #define NOP_OPCODE (0x050F) |
203 | #define NOP_Z_BITS (0xFFFF ^ NOP_OPCODE) |
204 | |
205 | #define NOP_OPCODE_V32 (0x05B0) |
206 | #define NOP_Z_BITS_V32 (0xFFFF ^ NOP_OPCODE_V32) |
207 | |
208 | /* For the compatibility mode, let's use "MOVE R0,P0". Doesn't affect |
209 | registers or flags. Unfortunately shuts off interrupts for one cycle |
210 | for < v32, but there doesn't seem to be any alternative without that |
211 | effect. */ |
212 | #define NOP_OPCODE_COMMON (0x630) |
213 | #define NOP_OPCODE_ZBITS_COMMON (0xffff & ~NOP_OPCODE_COMMON) |
214 | |
215 | /* LAPC.D */ |
216 | #define LAPC_DWORD_OPCODE (0x0D7F) |
217 | #define LAPC_DWORD_Z_BITS (0x0fff & ~LAPC_DWORD_OPCODE) |
218 | |
219 | /* Structure of an opcode table entry. */ |
220 | enum cris_imm_oprnd_size_type |
221 | { |
222 | /* No size is applicable. */ |
223 | SIZE_NONE, |
224 | |
225 | /* Always 32 bits. */ |
226 | SIZE_FIX_32, |
227 | |
228 | /* Indicated by size of special register. */ |
229 | SIZE_SPEC_REG, |
230 | |
231 | /* Indicated by size field, signed. */ |
232 | SIZE_FIELD_SIGNED, |
233 | |
234 | /* Indicated by size field, unsigned. */ |
235 | SIZE_FIELD_UNSIGNED, |
236 | |
237 | /* Indicated by size field, no sign implied. */ |
238 | SIZE_FIELD |
239 | }; |
240 | |
241 | /* For GDB. FIXME: Is this the best way to handle opcode |
242 | interpretation? */ |
243 | enum cris_op_type |
244 | { |
245 | cris_not_implemented_op = 0, |
246 | cris_abs_op, |
247 | cris_addi_op, |
248 | cris_asr_op, |
249 | cris_asrq_op, |
250 | cris_ax_ei_setf_op, |
251 | cris_bdap_prefix, |
252 | cris_biap_prefix, |
253 | cris_break_op, |
254 | cris_btst_nop_op, |
255 | cris_clearf_di_op, |
256 | cris_dip_prefix, |
257 | cris_dstep_logshift_mstep_neg_not_op, |
258 | cris_eight_bit_offset_branch_op, |
259 | cris_move_mem_to_reg_movem_op, |
260 | cris_move_reg_to_mem_movem_op, |
261 | cris_move_to_preg_op, |
262 | cris_muls_op, |
263 | cris_mulu_op, |
264 | cris_none_reg_mode_add_sub_cmp_and_or_move_op, |
265 | cris_none_reg_mode_clear_test_op, |
266 | cris_none_reg_mode_jump_op, |
267 | cris_none_reg_mode_move_from_preg_op, |
268 | cris_quick_mode_add_sub_op, |
269 | cris_quick_mode_and_cmp_move_or_op, |
270 | cris_quick_mode_bdap_prefix, |
271 | cris_reg_mode_add_sub_cmp_and_or_move_op, |
272 | cris_reg_mode_clear_op, |
273 | cris_reg_mode_jump_op, |
274 | cris_reg_mode_move_from_preg_op, |
275 | cris_reg_mode_test_op, |
276 | cris_scc_op, |
277 | cris_sixteen_bit_offset_branch_op, |
278 | cris_three_operand_add_sub_cmp_and_or_op, |
279 | cris_three_operand_bound_op, |
280 | cris_two_operand_bound_op, |
281 | cris_xor_op |
282 | }; |
283 | |
284 | struct cris_opcode |
285 | { |
286 | /* The name of the insn. */ |
287 | const char *name; |
288 | |
289 | /* Bits that must be 1 for a match. */ |
290 | unsigned int match; |
291 | |
292 | /* Bits that must be 0 for a match. */ |
293 | unsigned int lose; |
294 | |
295 | /* See the table in "opcodes/cris-opc.c". */ |
296 | const char *args; |
297 | |
298 | /* Nonzero if this is a delayed branch instruction. */ |
299 | char delayed; |
300 | |
301 | /* Size of immediate operands. */ |
302 | enum cris_imm_oprnd_size_type imm_oprnd_size; |
303 | |
304 | /* Indicates which version this insn was first implemented in. */ |
305 | enum cris_insn_version_usage applicable_version; |
306 | |
307 | /* What kind of operation this is. */ |
308 | enum cris_op_type op; |
309 | }; |
310 | extern const struct cris_opcode cris_opcodes[]; |
311 | |
312 | |
313 | /* These macros are for the target-specific flags in disassemble_info |
314 | used at disassembly. */ |
315 | |
316 | /* This insn accesses memory. This flag is more trustworthy than |
317 | checking insn_type for "dis_dref" which does not work for |
318 | e.g. "JSR [foo]". */ |
319 | #define CRIS_DIS_FLAG_MEMREF (1 << 0) |
320 | |
321 | /* The "target" field holds a register number. */ |
322 | #define CRIS_DIS_FLAG_MEM_TARGET_IS_REG (1 << 1) |
323 | |
324 | /* The "target2" field holds a register number; add it to "target". */ |
325 | #define CRIS_DIS_FLAG_MEM_TARGET2_IS_REG (1 << 2) |
326 | |
327 | /* Yet another add-on: the register in "target2" must be multiplied |
328 | by 2 before adding to "target". */ |
329 | #define CRIS_DIS_FLAG_MEM_TARGET2_MULT2 (1 << 3) |
330 | |
331 | /* Yet another add-on: the register in "target2" must be multiplied |
332 | by 4 (mutually exclusive with .._MULT2). */ |
333 | #define CRIS_DIS_FLAG_MEM_TARGET2_MULT4 (1 << 4) |
334 | |
335 | /* The register in "target2" is an indirect memory reference (of the |
336 | register there), add to "target". Assumed size is dword (mutually |
337 | exclusive with .._MULT[24]). */ |
338 | #define CRIS_DIS_FLAG_MEM_TARGET2_MEM (1 << 5) |
339 | |
340 | /* Add-on to CRIS_DIS_FLAG_MEM_TARGET2_MEM; the memory access is "byte"; |
341 | sign-extended before adding to "target". */ |
342 | #define CRIS_DIS_FLAG_MEM_TARGET2_MEM_BYTE (1 << 6) |
343 | |
344 | /* Add-on to CRIS_DIS_FLAG_MEM_TARGET2_MEM; the memory access is "word"; |
345 | sign-extended before adding to "target". */ |
346 | #define CRIS_DIS_FLAG_MEM_TARGET2_MEM_WORD (1 << 7) |
347 | |
348 | #endif /* TARGET_CRIS_OPCODE_CRIS_H */ |
349 | |
350 | /* |
351 | * Local variables: |
352 | * eval: (c-set-style "gnu") |
353 | * indent-tabs-mode: t |
354 | * End: |
355 | */ |
356 | |