1/*
2 * x86 gdb server stub
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 * Copyright (c) 2013 SUSE LINUX Products GmbH
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20#include "qemu/osdep.h"
21#include "cpu.h"
22#include "exec/gdbstub.h"
23
24#ifdef TARGET_X86_64
25static const int gpr_map[16] = {
26 R_EAX, R_EBX, R_ECX, R_EDX, R_ESI, R_EDI, R_EBP, R_ESP,
27 8, 9, 10, 11, 12, 13, 14, 15
28};
29#else
30#define gpr_map gpr_map32
31#endif
32static const int gpr_map32[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
33
34/*
35 * Keep these in sync with assignment to
36 * gdb_num_core_regs in target/i386/cpu.c
37 * and with the machine description
38 */
39
40/*
41 * SEG: 6 segments, plus fs_base, gs_base, kernel_gs_base
42 */
43
44/*
45 * general regs -----> 8 or 16
46 */
47#define IDX_NB_IP 1
48#define IDX_NB_FLAGS 1
49#define IDX_NB_SEG (6 + 3)
50#define IDX_NB_CTL 6
51#define IDX_NB_FP 16
52/*
53 * fpu regs ----------> 8 or 16
54 */
55#define IDX_NB_MXCSR 1
56/*
57 * total ----> 8+1+1+9+6+16+8+1=50 or 16+1+1+9+6+16+16+1=66
58 */
59
60#define IDX_IP_REG CPU_NB_REGS
61#define IDX_FLAGS_REG (IDX_IP_REG + IDX_NB_IP)
62#define IDX_SEG_REGS (IDX_FLAGS_REG + IDX_NB_FLAGS)
63#define IDX_CTL_REGS (IDX_SEG_REGS + IDX_NB_SEG)
64#define IDX_FP_REGS (IDX_CTL_REGS + IDX_NB_CTL)
65#define IDX_XMM_REGS (IDX_FP_REGS + IDX_NB_FP)
66#define IDX_MXCSR_REG (IDX_XMM_REGS + CPU_NB_REGS)
67
68#define IDX_CTL_CR0_REG (IDX_CTL_REGS + 0)
69#define IDX_CTL_CR2_REG (IDX_CTL_REGS + 1)
70#define IDX_CTL_CR3_REG (IDX_CTL_REGS + 2)
71#define IDX_CTL_CR4_REG (IDX_CTL_REGS + 3)
72#define IDX_CTL_CR8_REG (IDX_CTL_REGS + 4)
73#define IDX_CTL_EFER_REG (IDX_CTL_REGS + 5)
74
75#ifdef TARGET_X86_64
76#define GDB_FORCE_64 1
77#else
78#define GDB_FORCE_64 0
79#endif
80
81
82int x86_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
83{
84 X86CPU *cpu = X86_CPU(cs);
85 CPUX86State *env = &cpu->env;
86
87 uint64_t tpr;
88
89 /* N.B. GDB can't deal with changes in registers or sizes in the middle
90 of a session. So if we're in 32-bit mode on a 64-bit cpu, still act
91 as if we're on a 64-bit cpu. */
92
93 if (n < CPU_NB_REGS) {
94 if (TARGET_LONG_BITS == 64) {
95 if (env->hflags & HF_CS64_MASK) {
96 return gdb_get_reg64(mem_buf, env->regs[gpr_map[n]]);
97 } else if (n < CPU_NB_REGS32) {
98 return gdb_get_reg64(mem_buf,
99 env->regs[gpr_map[n]] & 0xffffffffUL);
100 } else {
101 memset(mem_buf, 0, sizeof(target_ulong));
102 return sizeof(target_ulong);
103 }
104 } else {
105 return gdb_get_reg32(mem_buf, env->regs[gpr_map32[n]]);
106 }
107 } else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) {
108#ifdef USE_X86LDOUBLE
109 /* FIXME: byteswap float values - after fixing fpregs layout. */
110 memcpy(mem_buf, &env->fpregs[n - IDX_FP_REGS], 10);
111#else
112 memset(mem_buf, 0, 10);
113#endif
114 return 10;
115 } else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) {
116 n -= IDX_XMM_REGS;
117 if (n < CPU_NB_REGS32 || TARGET_LONG_BITS == 64) {
118 stq_p(mem_buf, env->xmm_regs[n].ZMM_Q(0));
119 stq_p(mem_buf + 8, env->xmm_regs[n].ZMM_Q(1));
120 return 16;
121 }
122 } else {
123 switch (n) {
124 case IDX_IP_REG:
125 if (TARGET_LONG_BITS == 64) {
126 if (env->hflags & HF_CS64_MASK) {
127 return gdb_get_reg64(mem_buf, env->eip);
128 } else {
129 return gdb_get_reg64(mem_buf, env->eip & 0xffffffffUL);
130 }
131 } else {
132 return gdb_get_reg32(mem_buf, env->eip);
133 }
134 case IDX_FLAGS_REG:
135 return gdb_get_reg32(mem_buf, env->eflags);
136
137 case IDX_SEG_REGS:
138 return gdb_get_reg32(mem_buf, env->segs[R_CS].selector);
139 case IDX_SEG_REGS + 1:
140 return gdb_get_reg32(mem_buf, env->segs[R_SS].selector);
141 case IDX_SEG_REGS + 2:
142 return gdb_get_reg32(mem_buf, env->segs[R_DS].selector);
143 case IDX_SEG_REGS + 3:
144 return gdb_get_reg32(mem_buf, env->segs[R_ES].selector);
145 case IDX_SEG_REGS + 4:
146 return gdb_get_reg32(mem_buf, env->segs[R_FS].selector);
147 case IDX_SEG_REGS + 5:
148 return gdb_get_reg32(mem_buf, env->segs[R_GS].selector);
149
150 case IDX_SEG_REGS + 6:
151 if ((env->hflags & HF_CS64_MASK) || GDB_FORCE_64) {
152 return gdb_get_reg64(mem_buf, env->segs[R_FS].base);
153 }
154 return gdb_get_reg32(mem_buf, env->segs[R_FS].base);
155
156 case IDX_SEG_REGS + 7:
157 if ((env->hflags & HF_CS64_MASK) || GDB_FORCE_64) {
158 return gdb_get_reg64(mem_buf, env->segs[R_GS].base);
159 }
160 return gdb_get_reg32(mem_buf, env->segs[R_GS].base);
161
162 case IDX_SEG_REGS + 8:
163#ifdef TARGET_X86_64
164 if ((env->hflags & HF_CS64_MASK) || GDB_FORCE_64) {
165 return gdb_get_reg64(mem_buf, env->kernelgsbase);
166 }
167 return gdb_get_reg32(mem_buf, env->kernelgsbase);
168#else
169 return gdb_get_reg32(mem_buf, 0);
170#endif
171
172 case IDX_FP_REGS + 8:
173 return gdb_get_reg32(mem_buf, env->fpuc);
174 case IDX_FP_REGS + 9:
175 return gdb_get_reg32(mem_buf, (env->fpus & ~0x3800) |
176 (env->fpstt & 0x7) << 11);
177 case IDX_FP_REGS + 10:
178 return gdb_get_reg32(mem_buf, 0); /* ftag */
179 case IDX_FP_REGS + 11:
180 return gdb_get_reg32(mem_buf, 0); /* fiseg */
181 case IDX_FP_REGS + 12:
182 return gdb_get_reg32(mem_buf, 0); /* fioff */
183 case IDX_FP_REGS + 13:
184 return gdb_get_reg32(mem_buf, 0); /* foseg */
185 case IDX_FP_REGS + 14:
186 return gdb_get_reg32(mem_buf, 0); /* fooff */
187 case IDX_FP_REGS + 15:
188 return gdb_get_reg32(mem_buf, 0); /* fop */
189
190 case IDX_MXCSR_REG:
191 return gdb_get_reg32(mem_buf, env->mxcsr);
192
193 case IDX_CTL_CR0_REG:
194 if ((env->hflags & HF_CS64_MASK) || GDB_FORCE_64) {
195 return gdb_get_reg64(mem_buf, env->cr[0]);
196 }
197 return gdb_get_reg32(mem_buf, env->cr[0]);
198
199 case IDX_CTL_CR2_REG:
200 if ((env->hflags & HF_CS64_MASK) || GDB_FORCE_64) {
201 return gdb_get_reg64(mem_buf, env->cr[2]);
202 }
203 return gdb_get_reg32(mem_buf, env->cr[2]);
204
205 case IDX_CTL_CR3_REG:
206 if ((env->hflags & HF_CS64_MASK) || GDB_FORCE_64) {
207 return gdb_get_reg64(mem_buf, env->cr[3]);
208 }
209 return gdb_get_reg32(mem_buf, env->cr[3]);
210
211 case IDX_CTL_CR4_REG:
212 if ((env->hflags & HF_CS64_MASK) || GDB_FORCE_64) {
213 return gdb_get_reg64(mem_buf, env->cr[4]);
214 }
215 return gdb_get_reg32(mem_buf, env->cr[4]);
216
217 case IDX_CTL_CR8_REG:
218#ifdef CONFIG_SOFTMMU
219 tpr = cpu_get_apic_tpr(cpu->apic_state);
220#else
221 tpr = 0;
222#endif
223 if ((env->hflags & HF_CS64_MASK) || GDB_FORCE_64) {
224 return gdb_get_reg64(mem_buf, tpr);
225 }
226 return gdb_get_reg32(mem_buf, tpr);
227
228 case IDX_CTL_EFER_REG:
229 if ((env->hflags & HF_CS64_MASK) || GDB_FORCE_64) {
230 return gdb_get_reg64(mem_buf, env->efer);
231 }
232 return gdb_get_reg32(mem_buf, env->efer);
233 }
234 }
235 return 0;
236}
237
238static int x86_cpu_gdb_load_seg(X86CPU *cpu, int sreg, uint8_t *mem_buf)
239{
240 CPUX86State *env = &cpu->env;
241 uint16_t selector = ldl_p(mem_buf);
242
243 if (selector != env->segs[sreg].selector) {
244#if defined(CONFIG_USER_ONLY)
245 cpu_x86_load_seg(env, sreg, selector);
246#else
247 unsigned int limit, flags;
248 target_ulong base;
249
250 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
251 int dpl = (env->eflags & VM_MASK) ? 3 : 0;
252 base = selector << 4;
253 limit = 0xffff;
254 flags = DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
255 DESC_A_MASK | (dpl << DESC_DPL_SHIFT);
256 } else {
257 if (!cpu_x86_get_descr_debug(env, selector, &base, &limit,
258 &flags)) {
259 return 4;
260 }
261 }
262 cpu_x86_load_seg_cache(env, sreg, selector, base, limit, flags);
263#endif
264 }
265 return 4;
266}
267
268int x86_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
269{
270 X86CPU *cpu = X86_CPU(cs);
271 CPUX86State *env = &cpu->env;
272 uint32_t tmp;
273
274 /* N.B. GDB can't deal with changes in registers or sizes in the middle
275 of a session. So if we're in 32-bit mode on a 64-bit cpu, still act
276 as if we're on a 64-bit cpu. */
277
278 if (n < CPU_NB_REGS) {
279 if (TARGET_LONG_BITS == 64) {
280 if (env->hflags & HF_CS64_MASK) {
281 env->regs[gpr_map[n]] = ldtul_p(mem_buf);
282 } else if (n < CPU_NB_REGS32) {
283 env->regs[gpr_map[n]] = ldtul_p(mem_buf) & 0xffffffffUL;
284 }
285 return sizeof(target_ulong);
286 } else if (n < CPU_NB_REGS32) {
287 n = gpr_map32[n];
288 env->regs[n] &= ~0xffffffffUL;
289 env->regs[n] |= (uint32_t)ldl_p(mem_buf);
290 return 4;
291 }
292 } else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) {
293#ifdef USE_X86LDOUBLE
294 /* FIXME: byteswap float values - after fixing fpregs layout. */
295 memcpy(&env->fpregs[n - IDX_FP_REGS], mem_buf, 10);
296#endif
297 return 10;
298 } else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) {
299 n -= IDX_XMM_REGS;
300 if (n < CPU_NB_REGS32 || TARGET_LONG_BITS == 64) {
301 env->xmm_regs[n].ZMM_Q(0) = ldq_p(mem_buf);
302 env->xmm_regs[n].ZMM_Q(1) = ldq_p(mem_buf + 8);
303 return 16;
304 }
305 } else {
306 switch (n) {
307 case IDX_IP_REG:
308 if (TARGET_LONG_BITS == 64) {
309 if (env->hflags & HF_CS64_MASK) {
310 env->eip = ldq_p(mem_buf);
311 } else {
312 env->eip = ldq_p(mem_buf) & 0xffffffffUL;
313 }
314 return 8;
315 } else {
316 env->eip &= ~0xffffffffUL;
317 env->eip |= (uint32_t)ldl_p(mem_buf);
318 return 4;
319 }
320 case IDX_FLAGS_REG:
321 env->eflags = ldl_p(mem_buf);
322 return 4;
323
324 case IDX_SEG_REGS:
325 return x86_cpu_gdb_load_seg(cpu, R_CS, mem_buf);
326 case IDX_SEG_REGS + 1:
327 return x86_cpu_gdb_load_seg(cpu, R_SS, mem_buf);
328 case IDX_SEG_REGS + 2:
329 return x86_cpu_gdb_load_seg(cpu, R_DS, mem_buf);
330 case IDX_SEG_REGS + 3:
331 return x86_cpu_gdb_load_seg(cpu, R_ES, mem_buf);
332 case IDX_SEG_REGS + 4:
333 return x86_cpu_gdb_load_seg(cpu, R_FS, mem_buf);
334 case IDX_SEG_REGS + 5:
335 return x86_cpu_gdb_load_seg(cpu, R_GS, mem_buf);
336
337 case IDX_SEG_REGS + 6:
338 if (env->hflags & HF_CS64_MASK) {
339 env->segs[R_FS].base = ldq_p(mem_buf);
340 return 8;
341 }
342 env->segs[R_FS].base = ldl_p(mem_buf);
343 return 4;
344
345 case IDX_SEG_REGS + 7:
346 if (env->hflags & HF_CS64_MASK) {
347 env->segs[R_GS].base = ldq_p(mem_buf);
348 return 8;
349 }
350 env->segs[R_GS].base = ldl_p(mem_buf);
351 return 4;
352
353#ifdef TARGET_X86_64
354 case IDX_SEG_REGS + 8:
355 if (env->hflags & HF_CS64_MASK) {
356 env->kernelgsbase = ldq_p(mem_buf);
357 return 8;
358 }
359 env->kernelgsbase = ldl_p(mem_buf);
360 return 4;
361#endif
362
363 case IDX_FP_REGS + 8:
364 cpu_set_fpuc(env, ldl_p(mem_buf));
365 return 4;
366 case IDX_FP_REGS + 9:
367 tmp = ldl_p(mem_buf);
368 env->fpstt = (tmp >> 11) & 7;
369 env->fpus = tmp & ~0x3800;
370 return 4;
371 case IDX_FP_REGS + 10: /* ftag */
372 return 4;
373 case IDX_FP_REGS + 11: /* fiseg */
374 return 4;
375 case IDX_FP_REGS + 12: /* fioff */
376 return 4;
377 case IDX_FP_REGS + 13: /* foseg */
378 return 4;
379 case IDX_FP_REGS + 14: /* fooff */
380 return 4;
381 case IDX_FP_REGS + 15: /* fop */
382 return 4;
383
384 case IDX_MXCSR_REG:
385 cpu_set_mxcsr(env, ldl_p(mem_buf));
386 return 4;
387
388 case IDX_CTL_CR0_REG:
389 if (env->hflags & HF_CS64_MASK) {
390 cpu_x86_update_cr0(env, ldq_p(mem_buf));
391 return 8;
392 }
393 cpu_x86_update_cr0(env, ldl_p(mem_buf));
394 return 4;
395
396 case IDX_CTL_CR2_REG:
397 if (env->hflags & HF_CS64_MASK) {
398 env->cr[2] = ldq_p(mem_buf);
399 return 8;
400 }
401 env->cr[2] = ldl_p(mem_buf);
402 return 4;
403
404 case IDX_CTL_CR3_REG:
405 if (env->hflags & HF_CS64_MASK) {
406 cpu_x86_update_cr3(env, ldq_p(mem_buf));
407 return 8;
408 }
409 cpu_x86_update_cr3(env, ldl_p(mem_buf));
410 return 4;
411
412 case IDX_CTL_CR4_REG:
413 if (env->hflags & HF_CS64_MASK) {
414 cpu_x86_update_cr4(env, ldq_p(mem_buf));
415 return 8;
416 }
417 cpu_x86_update_cr4(env, ldl_p(mem_buf));
418 return 4;
419
420 case IDX_CTL_CR8_REG:
421 if (env->hflags & HF_CS64_MASK) {
422#ifdef CONFIG_SOFTMMU
423 cpu_set_apic_tpr(cpu->apic_state, ldq_p(mem_buf));
424#endif
425 return 8;
426 }
427#ifdef CONFIG_SOFTMMU
428 cpu_set_apic_tpr(cpu->apic_state, ldl_p(mem_buf));
429#endif
430 return 4;
431
432 case IDX_CTL_EFER_REG:
433 if (env->hflags & HF_CS64_MASK) {
434 cpu_load_efer(env, ldq_p(mem_buf));
435 return 8;
436 }
437 cpu_load_efer(env, ldl_p(mem_buf));
438 return 4;
439
440 }
441 }
442 /* Unrecognised register. */
443 return 0;
444}
445