1 | /* |
2 | * Definitions for Hyper-V guest/hypervisor interaction - x86-specific part |
3 | * |
4 | * Copyright (c) 2017-2018 Virtuozzo International GmbH. |
5 | * |
6 | * This work is licensed under the terms of the GNU GPL, version 2 or later. |
7 | * See the COPYING file in the top-level directory. |
8 | */ |
9 | |
10 | #ifndef TARGET_I386_HYPERV_PROTO_H |
11 | #define TARGET_I386_HYPERV_PROTO_H |
12 | |
13 | #include "hw/hyperv/hyperv-proto.h" |
14 | |
15 | #define HV_CPUID_VENDOR_AND_MAX_FUNCTIONS 0x40000000 |
16 | #define HV_CPUID_INTERFACE 0x40000001 |
17 | #define HV_CPUID_VERSION 0x40000002 |
18 | #define HV_CPUID_FEATURES 0x40000003 |
19 | #define HV_CPUID_ENLIGHTMENT_INFO 0x40000004 |
20 | #define HV_CPUID_IMPLEMENT_LIMITS 0x40000005 |
21 | #define HV_CPUID_NESTED_FEATURES 0x4000000A |
22 | #define HV_CPUID_MIN 0x40000005 |
23 | #define HV_CPUID_MAX 0x4000ffff |
24 | #define HV_HYPERVISOR_PRESENT_BIT 0x80000000 |
25 | |
26 | /* |
27 | * HV_CPUID_FEATURES.EAX bits |
28 | */ |
29 | #define HV_VP_RUNTIME_AVAILABLE (1u << 0) |
30 | #define HV_TIME_REF_COUNT_AVAILABLE (1u << 1) |
31 | #define HV_SYNIC_AVAILABLE (1u << 2) |
32 | #define HV_SYNTIMERS_AVAILABLE (1u << 3) |
33 | #define HV_APIC_ACCESS_AVAILABLE (1u << 4) |
34 | #define HV_HYPERCALL_AVAILABLE (1u << 5) |
35 | #define HV_VP_INDEX_AVAILABLE (1u << 6) |
36 | #define HV_RESET_AVAILABLE (1u << 7) |
37 | #define HV_REFERENCE_TSC_AVAILABLE (1u << 9) |
38 | #define HV_ACCESS_FREQUENCY_MSRS (1u << 11) |
39 | #define HV_ACCESS_REENLIGHTENMENTS_CONTROL (1u << 13) |
40 | |
41 | /* |
42 | * HV_CPUID_FEATURES.EDX bits |
43 | */ |
44 | #define HV_MWAIT_AVAILABLE (1u << 0) |
45 | #define HV_GUEST_DEBUGGING_AVAILABLE (1u << 1) |
46 | #define HV_PERF_MONITOR_AVAILABLE (1u << 2) |
47 | #define HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE (1u << 3) |
48 | #define HV_HYPERCALL_PARAMS_XMM_AVAILABLE (1u << 4) |
49 | #define HV_GUEST_IDLE_STATE_AVAILABLE (1u << 5) |
50 | #define HV_FREQUENCY_MSRS_AVAILABLE (1u << 8) |
51 | #define HV_GUEST_CRASH_MSR_AVAILABLE (1u << 10) |
52 | #define HV_STIMER_DIRECT_MODE_AVAILABLE (1u << 19) |
53 | |
54 | /* |
55 | * HV_CPUID_ENLIGHTMENT_INFO.EAX bits |
56 | */ |
57 | #define HV_AS_SWITCH_RECOMMENDED (1u << 0) |
58 | #define HV_LOCAL_TLB_FLUSH_RECOMMENDED (1u << 1) |
59 | #define HV_REMOTE_TLB_FLUSH_RECOMMENDED (1u << 2) |
60 | #define HV_APIC_ACCESS_RECOMMENDED (1u << 3) |
61 | #define HV_SYSTEM_RESET_RECOMMENDED (1u << 4) |
62 | #define HV_RELAXED_TIMING_RECOMMENDED (1u << 5) |
63 | #define HV_CLUSTER_IPI_RECOMMENDED (1u << 10) |
64 | #define HV_EX_PROCESSOR_MASKS_RECOMMENDED (1u << 11) |
65 | #define HV_ENLIGHTENED_VMCS_RECOMMENDED (1u << 14) |
66 | |
67 | /* |
68 | * Basic virtualized MSRs |
69 | */ |
70 | #define HV_X64_MSR_GUEST_OS_ID 0x40000000 |
71 | #define HV_X64_MSR_HYPERCALL 0x40000001 |
72 | #define HV_X64_MSR_VP_INDEX 0x40000002 |
73 | #define HV_X64_MSR_RESET 0x40000003 |
74 | #define HV_X64_MSR_VP_RUNTIME 0x40000010 |
75 | #define HV_X64_MSR_TIME_REF_COUNT 0x40000020 |
76 | #define HV_X64_MSR_REFERENCE_TSC 0x40000021 |
77 | #define HV_X64_MSR_TSC_FREQUENCY 0x40000022 |
78 | #define HV_X64_MSR_APIC_FREQUENCY 0x40000023 |
79 | |
80 | /* |
81 | * Virtual APIC MSRs |
82 | */ |
83 | #define HV_X64_MSR_EOI 0x40000070 |
84 | #define HV_X64_MSR_ICR 0x40000071 |
85 | #define HV_X64_MSR_TPR 0x40000072 |
86 | #define HV_X64_MSR_APIC_ASSIST_PAGE 0x40000073 |
87 | |
88 | /* |
89 | * Synthetic interrupt controller MSRs |
90 | */ |
91 | #define HV_X64_MSR_SCONTROL 0x40000080 |
92 | #define HV_X64_MSR_SVERSION 0x40000081 |
93 | #define HV_X64_MSR_SIEFP 0x40000082 |
94 | #define HV_X64_MSR_SIMP 0x40000083 |
95 | #define HV_X64_MSR_EOM 0x40000084 |
96 | #define HV_X64_MSR_SINT0 0x40000090 |
97 | #define HV_X64_MSR_SINT1 0x40000091 |
98 | #define HV_X64_MSR_SINT2 0x40000092 |
99 | #define HV_X64_MSR_SINT3 0x40000093 |
100 | #define HV_X64_MSR_SINT4 0x40000094 |
101 | #define HV_X64_MSR_SINT5 0x40000095 |
102 | #define HV_X64_MSR_SINT6 0x40000096 |
103 | #define HV_X64_MSR_SINT7 0x40000097 |
104 | #define HV_X64_MSR_SINT8 0x40000098 |
105 | #define HV_X64_MSR_SINT9 0x40000099 |
106 | #define HV_X64_MSR_SINT10 0x4000009A |
107 | #define HV_X64_MSR_SINT11 0x4000009B |
108 | #define HV_X64_MSR_SINT12 0x4000009C |
109 | #define HV_X64_MSR_SINT13 0x4000009D |
110 | #define HV_X64_MSR_SINT14 0x4000009E |
111 | #define HV_X64_MSR_SINT15 0x4000009F |
112 | |
113 | /* |
114 | * Synthetic timer MSRs |
115 | */ |
116 | #define HV_X64_MSR_STIMER0_CONFIG 0x400000B0 |
117 | #define HV_X64_MSR_STIMER0_COUNT 0x400000B1 |
118 | #define HV_X64_MSR_STIMER1_CONFIG 0x400000B2 |
119 | #define HV_X64_MSR_STIMER1_COUNT 0x400000B3 |
120 | #define HV_X64_MSR_STIMER2_CONFIG 0x400000B4 |
121 | #define HV_X64_MSR_STIMER2_COUNT 0x400000B5 |
122 | #define HV_X64_MSR_STIMER3_CONFIG 0x400000B6 |
123 | #define HV_X64_MSR_STIMER3_COUNT 0x400000B7 |
124 | |
125 | /* |
126 | * Guest crash notification MSRs |
127 | */ |
128 | #define HV_X64_MSR_CRASH_P0 0x40000100 |
129 | #define HV_X64_MSR_CRASH_P1 0x40000101 |
130 | #define HV_X64_MSR_CRASH_P2 0x40000102 |
131 | #define HV_X64_MSR_CRASH_P3 0x40000103 |
132 | #define HV_X64_MSR_CRASH_P4 0x40000104 |
133 | #define HV_CRASH_PARAMS (HV_X64_MSR_CRASH_P4 - HV_X64_MSR_CRASH_P0 + 1) |
134 | #define HV_X64_MSR_CRASH_CTL 0x40000105 |
135 | #define HV_CRASH_CTL_NOTIFY (1ull << 63) |
136 | |
137 | /* |
138 | * Reenlightenment notification MSRs |
139 | */ |
140 | #define HV_X64_MSR_REENLIGHTENMENT_CONTROL 0x40000106 |
141 | #define HV_X64_MSR_TSC_EMULATION_CONTROL 0x40000107 |
142 | #define HV_X64_MSR_TSC_EMULATION_STATUS 0x40000108 |
143 | |
144 | /* |
145 | * Hypercall MSR bits |
146 | */ |
147 | #define HV_HYPERCALL_ENABLE (1u << 0) |
148 | |
149 | /* |
150 | * Synthetic interrupt controller definitions |
151 | */ |
152 | #define HV_SYNIC_VERSION 1 |
153 | #define HV_SYNIC_ENABLE (1u << 0) |
154 | #define HV_SIMP_ENABLE (1u << 0) |
155 | #define HV_SIEFP_ENABLE (1u << 0) |
156 | #define HV_SINT_MASKED (1u << 16) |
157 | #define HV_SINT_AUTO_EOI (1u << 17) |
158 | #define HV_SINT_VECTOR_MASK 0xff |
159 | |
160 | #define HV_STIMER_COUNT 4 |
161 | |
162 | |
163 | #endif |
164 | |