1 | #ifndef SVM_H |
2 | #define SVM_H |
3 | |
4 | #define TLB_CONTROL_DO_NOTHING 0 |
5 | #define TLB_CONTROL_FLUSH_ALL_ASID 1 |
6 | |
7 | #define V_TPR_MASK 0x0f |
8 | |
9 | #define V_IRQ_SHIFT 8 |
10 | #define V_IRQ_MASK (1 << V_IRQ_SHIFT) |
11 | |
12 | #define V_INTR_PRIO_SHIFT 16 |
13 | #define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT) |
14 | |
15 | #define V_IGN_TPR_SHIFT 20 |
16 | #define V_IGN_TPR_MASK (1 << V_IGN_TPR_SHIFT) |
17 | |
18 | #define V_INTR_MASKING_SHIFT 24 |
19 | #define V_INTR_MASKING_MASK (1 << V_INTR_MASKING_SHIFT) |
20 | |
21 | #define SVM_INTERRUPT_SHADOW_MASK 1 |
22 | |
23 | #define SVM_IOIO_STR_SHIFT 2 |
24 | #define SVM_IOIO_REP_SHIFT 3 |
25 | #define SVM_IOIO_SIZE_SHIFT 4 |
26 | #define SVM_IOIO_ASIZE_SHIFT 7 |
27 | |
28 | #define SVM_IOIO_TYPE_MASK 1 |
29 | #define SVM_IOIO_STR_MASK (1 << SVM_IOIO_STR_SHIFT) |
30 | #define SVM_IOIO_REP_MASK (1 << SVM_IOIO_REP_SHIFT) |
31 | #define SVM_IOIO_SIZE_MASK (7 << SVM_IOIO_SIZE_SHIFT) |
32 | #define SVM_IOIO_ASIZE_MASK (7 << SVM_IOIO_ASIZE_SHIFT) |
33 | |
34 | #define SVM_EVTINJ_VEC_MASK 0xff |
35 | |
36 | #define SVM_EVTINJ_TYPE_SHIFT 8 |
37 | #define SVM_EVTINJ_TYPE_MASK (7 << SVM_EVTINJ_TYPE_SHIFT) |
38 | |
39 | #define SVM_EVTINJ_TYPE_INTR (0 << SVM_EVTINJ_TYPE_SHIFT) |
40 | #define SVM_EVTINJ_TYPE_NMI (2 << SVM_EVTINJ_TYPE_SHIFT) |
41 | #define SVM_EVTINJ_TYPE_EXEPT (3 << SVM_EVTINJ_TYPE_SHIFT) |
42 | #define SVM_EVTINJ_TYPE_SOFT (4 << SVM_EVTINJ_TYPE_SHIFT) |
43 | |
44 | #define SVM_EVTINJ_VALID (1 << 31) |
45 | #define SVM_EVTINJ_VALID_ERR (1 << 11) |
46 | |
47 | #define SVM_EXITINTINFO_VEC_MASK SVM_EVTINJ_VEC_MASK |
48 | |
49 | #define SVM_EXITINTINFO_TYPE_INTR SVM_EVTINJ_TYPE_INTR |
50 | #define SVM_EXITINTINFO_TYPE_NMI SVM_EVTINJ_TYPE_NMI |
51 | #define SVM_EXITINTINFO_TYPE_EXEPT SVM_EVTINJ_TYPE_EXEPT |
52 | #define SVM_EXITINTINFO_TYPE_SOFT SVM_EVTINJ_TYPE_SOFT |
53 | |
54 | #define SVM_EXITINTINFO_VALID SVM_EVTINJ_VALID |
55 | #define SVM_EXITINTINFO_VALID_ERR SVM_EVTINJ_VALID_ERR |
56 | |
57 | #define SVM_EXIT_READ_CR0 0x000 |
58 | #define SVM_EXIT_READ_CR3 0x003 |
59 | #define SVM_EXIT_READ_CR4 0x004 |
60 | #define SVM_EXIT_READ_CR8 0x008 |
61 | #define SVM_EXIT_WRITE_CR0 0x010 |
62 | #define SVM_EXIT_WRITE_CR3 0x013 |
63 | #define SVM_EXIT_WRITE_CR4 0x014 |
64 | #define SVM_EXIT_WRITE_CR8 0x018 |
65 | #define SVM_EXIT_READ_DR0 0x020 |
66 | #define SVM_EXIT_READ_DR1 0x021 |
67 | #define SVM_EXIT_READ_DR2 0x022 |
68 | #define SVM_EXIT_READ_DR3 0x023 |
69 | #define SVM_EXIT_READ_DR4 0x024 |
70 | #define SVM_EXIT_READ_DR5 0x025 |
71 | #define SVM_EXIT_READ_DR6 0x026 |
72 | #define SVM_EXIT_READ_DR7 0x027 |
73 | #define SVM_EXIT_WRITE_DR0 0x030 |
74 | #define SVM_EXIT_WRITE_DR1 0x031 |
75 | #define SVM_EXIT_WRITE_DR2 0x032 |
76 | #define SVM_EXIT_WRITE_DR3 0x033 |
77 | #define SVM_EXIT_WRITE_DR4 0x034 |
78 | #define SVM_EXIT_WRITE_DR5 0x035 |
79 | #define SVM_EXIT_WRITE_DR6 0x036 |
80 | #define SVM_EXIT_WRITE_DR7 0x037 |
81 | #define SVM_EXIT_EXCP_BASE 0x040 |
82 | #define SVM_EXIT_INTR 0x060 |
83 | #define SVM_EXIT_NMI 0x061 |
84 | #define SVM_EXIT_SMI 0x062 |
85 | #define SVM_EXIT_INIT 0x063 |
86 | #define SVM_EXIT_VINTR 0x064 |
87 | #define SVM_EXIT_CR0_SEL_WRITE 0x065 |
88 | #define SVM_EXIT_IDTR_READ 0x066 |
89 | #define SVM_EXIT_GDTR_READ 0x067 |
90 | #define SVM_EXIT_LDTR_READ 0x068 |
91 | #define SVM_EXIT_TR_READ 0x069 |
92 | #define SVM_EXIT_IDTR_WRITE 0x06a |
93 | #define SVM_EXIT_GDTR_WRITE 0x06b |
94 | #define SVM_EXIT_LDTR_WRITE 0x06c |
95 | #define SVM_EXIT_TR_WRITE 0x06d |
96 | #define SVM_EXIT_RDTSC 0x06e |
97 | #define SVM_EXIT_RDPMC 0x06f |
98 | #define SVM_EXIT_PUSHF 0x070 |
99 | #define SVM_EXIT_POPF 0x071 |
100 | #define SVM_EXIT_CPUID 0x072 |
101 | #define SVM_EXIT_RSM 0x073 |
102 | #define SVM_EXIT_IRET 0x074 |
103 | #define SVM_EXIT_SWINT 0x075 |
104 | #define SVM_EXIT_INVD 0x076 |
105 | #define SVM_EXIT_PAUSE 0x077 |
106 | #define SVM_EXIT_HLT 0x078 |
107 | #define SVM_EXIT_INVLPG 0x079 |
108 | #define SVM_EXIT_INVLPGA 0x07a |
109 | #define SVM_EXIT_IOIO 0x07b |
110 | #define SVM_EXIT_MSR 0x07c |
111 | #define SVM_EXIT_TASK_SWITCH 0x07d |
112 | #define SVM_EXIT_FERR_FREEZE 0x07e |
113 | #define SVM_EXIT_SHUTDOWN 0x07f |
114 | #define SVM_EXIT_VMRUN 0x080 |
115 | #define SVM_EXIT_VMMCALL 0x081 |
116 | #define SVM_EXIT_VMLOAD 0x082 |
117 | #define SVM_EXIT_VMSAVE 0x083 |
118 | #define SVM_EXIT_STGI 0x084 |
119 | #define SVM_EXIT_CLGI 0x085 |
120 | #define SVM_EXIT_SKINIT 0x086 |
121 | #define SVM_EXIT_RDTSCP 0x087 |
122 | #define SVM_EXIT_ICEBP 0x088 |
123 | #define SVM_EXIT_WBINVD 0x089 |
124 | /* only included in documentation, maybe wrong */ |
125 | #define SVM_EXIT_MONITOR 0x08a |
126 | #define SVM_EXIT_MWAIT 0x08b |
127 | #define SVM_EXIT_NPF 0x400 |
128 | |
129 | #define SVM_EXIT_ERR -1 |
130 | |
131 | #define SVM_CR0_SELECTIVE_MASK (1 << 3 | 1) /* TS and MP */ |
132 | |
133 | #define SVM_NPT_ENABLED (1 << 0) |
134 | |
135 | #define SVM_NPT_PAE (1 << 0) |
136 | #define SVM_NPT_LMA (1 << 1) |
137 | #define SVM_NPT_NXE (1 << 2) |
138 | |
139 | #define SVM_NPTEXIT_P (1ULL << 0) |
140 | #define SVM_NPTEXIT_RW (1ULL << 1) |
141 | #define SVM_NPTEXIT_US (1ULL << 2) |
142 | #define SVM_NPTEXIT_RSVD (1ULL << 3) |
143 | #define SVM_NPTEXIT_ID (1ULL << 4) |
144 | #define SVM_NPTEXIT_GPA (1ULL << 32) |
145 | #define SVM_NPTEXIT_GPT (1ULL << 33) |
146 | |
147 | struct QEMU_PACKED vmcb_control_area { |
148 | uint16_t intercept_cr_read; |
149 | uint16_t intercept_cr_write; |
150 | uint16_t intercept_dr_read; |
151 | uint16_t intercept_dr_write; |
152 | uint32_t intercept_exceptions; |
153 | uint64_t intercept; |
154 | uint8_t reserved_1[44]; |
155 | uint64_t iopm_base_pa; |
156 | uint64_t msrpm_base_pa; |
157 | uint64_t tsc_offset; |
158 | uint32_t asid; |
159 | uint8_t tlb_ctl; |
160 | uint8_t reserved_2[3]; |
161 | uint32_t int_ctl; |
162 | uint32_t int_vector; |
163 | uint32_t int_state; |
164 | uint8_t reserved_3[4]; |
165 | uint64_t exit_code; |
166 | uint64_t exit_info_1; |
167 | uint64_t exit_info_2; |
168 | uint32_t exit_int_info; |
169 | uint32_t exit_int_info_err; |
170 | uint64_t nested_ctl; |
171 | uint8_t reserved_4[16]; |
172 | uint32_t event_inj; |
173 | uint32_t event_inj_err; |
174 | uint64_t nested_cr3; |
175 | uint64_t lbr_ctl; |
176 | uint8_t reserved_5[832]; |
177 | }; |
178 | |
179 | struct QEMU_PACKED vmcb_seg { |
180 | uint16_t selector; |
181 | uint16_t attrib; |
182 | uint32_t limit; |
183 | uint64_t base; |
184 | }; |
185 | |
186 | struct QEMU_PACKED vmcb_save_area { |
187 | struct vmcb_seg es; |
188 | struct vmcb_seg cs; |
189 | struct vmcb_seg ss; |
190 | struct vmcb_seg ds; |
191 | struct vmcb_seg fs; |
192 | struct vmcb_seg gs; |
193 | struct vmcb_seg gdtr; |
194 | struct vmcb_seg ldtr; |
195 | struct vmcb_seg idtr; |
196 | struct vmcb_seg tr; |
197 | uint8_t reserved_1[43]; |
198 | uint8_t cpl; |
199 | uint8_t reserved_2[4]; |
200 | uint64_t efer; |
201 | uint8_t reserved_3[112]; |
202 | uint64_t cr4; |
203 | uint64_t cr3; |
204 | uint64_t cr0; |
205 | uint64_t dr7; |
206 | uint64_t dr6; |
207 | uint64_t rflags; |
208 | uint64_t rip; |
209 | uint8_t reserved_4[88]; |
210 | uint64_t rsp; |
211 | uint8_t reserved_5[24]; |
212 | uint64_t rax; |
213 | uint64_t star; |
214 | uint64_t lstar; |
215 | uint64_t cstar; |
216 | uint64_t sfmask; |
217 | uint64_t kernel_gs_base; |
218 | uint64_t sysenter_cs; |
219 | uint64_t sysenter_esp; |
220 | uint64_t sysenter_eip; |
221 | uint64_t cr2; |
222 | uint8_t reserved_6[32]; |
223 | uint64_t g_pat; |
224 | uint64_t dbgctl; |
225 | uint64_t br_from; |
226 | uint64_t br_to; |
227 | uint64_t last_excp_from; |
228 | uint64_t last_excp_to; |
229 | }; |
230 | |
231 | struct QEMU_PACKED vmcb { |
232 | struct vmcb_control_area control; |
233 | struct vmcb_save_area save; |
234 | }; |
235 | |
236 | #endif |
237 | |