1 | #ifndef MIPS_CPU_H |
2 | #define MIPS_CPU_H |
3 | |
4 | #include "cpu-qom.h" |
5 | #include "exec/cpu-defs.h" |
6 | #include "fpu/softfloat-types.h" |
7 | #include "mips-defs.h" |
8 | |
9 | #define TCG_GUEST_DEFAULT_MO (0) |
10 | |
11 | typedef struct CPUMIPSTLBContext CPUMIPSTLBContext; |
12 | |
13 | /* MSA Context */ |
14 | #define MSA_WRLEN (128) |
15 | |
16 | typedef union wr_t wr_t; |
17 | union wr_t { |
18 | int8_t b[MSA_WRLEN / 8]; |
19 | int16_t h[MSA_WRLEN / 16]; |
20 | int32_t w[MSA_WRLEN / 32]; |
21 | int64_t d[MSA_WRLEN / 64]; |
22 | }; |
23 | |
24 | typedef union fpr_t fpr_t; |
25 | union fpr_t { |
26 | float64 fd; /* ieee double precision */ |
27 | float32 fs[2];/* ieee single precision */ |
28 | uint64_t d; /* binary double fixed-point */ |
29 | uint32_t w[2]; /* binary single fixed-point */ |
30 | /* FPU/MSA register mapping is not tested on big-endian hosts. */ |
31 | wr_t wr; /* vector data */ |
32 | }; |
33 | /* |
34 | *define FP_ENDIAN_IDX to access the same location |
35 | * in the fpr_t union regardless of the host endianness |
36 | */ |
37 | #if defined(HOST_WORDS_BIGENDIAN) |
38 | # define FP_ENDIAN_IDX 1 |
39 | #else |
40 | # define FP_ENDIAN_IDX 0 |
41 | #endif |
42 | |
43 | typedef struct CPUMIPSFPUContext CPUMIPSFPUContext; |
44 | struct CPUMIPSFPUContext { |
45 | /* Floating point registers */ |
46 | fpr_t fpr[32]; |
47 | float_status fp_status; |
48 | /* fpu implementation/revision register (fir) */ |
49 | uint32_t fcr0; |
50 | #define FCR0_FREP 29 |
51 | #define FCR0_UFRP 28 |
52 | #define FCR0_HAS2008 23 |
53 | #define FCR0_F64 22 |
54 | #define FCR0_L 21 |
55 | #define FCR0_W 20 |
56 | #define FCR0_3D 19 |
57 | #define FCR0_PS 18 |
58 | #define FCR0_D 17 |
59 | #define FCR0_S 16 |
60 | #define FCR0_PRID 8 |
61 | #define FCR0_REV 0 |
62 | /* fcsr */ |
63 | uint32_t fcr31_rw_bitmask; |
64 | uint32_t fcr31; |
65 | #define FCR31_FS 24 |
66 | #define FCR31_ABS2008 19 |
67 | #define FCR31_NAN2008 18 |
68 | #define SET_FP_COND(num, env) do { ((env).fcr31) |= \ |
69 | ((num) ? (1 << ((num) + 24)) : \ |
70 | (1 << 23)); \ |
71 | } while (0) |
72 | #define CLEAR_FP_COND(num, env) do { ((env).fcr31) &= \ |
73 | ~((num) ? (1 << ((num) + 24)) : \ |
74 | (1 << 23)); \ |
75 | } while (0) |
76 | #define GET_FP_COND(env) ((((env).fcr31 >> 24) & 0xfe) | \ |
77 | (((env).fcr31 >> 23) & 0x1)) |
78 | #define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f) |
79 | #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f) |
80 | #define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f) |
81 | #define SET_FP_CAUSE(reg, v) do { (reg) = ((reg) & ~(0x3f << 12)) | \ |
82 | ((v & 0x3f) << 12); \ |
83 | } while (0) |
84 | #define SET_FP_ENABLE(reg, v) do { (reg) = ((reg) & ~(0x1f << 7)) | \ |
85 | ((v & 0x1f) << 7); \ |
86 | } while (0) |
87 | #define SET_FP_FLAGS(reg, v) do { (reg) = ((reg) & ~(0x1f << 2)) | \ |
88 | ((v & 0x1f) << 2); \ |
89 | } while (0) |
90 | #define UPDATE_FP_FLAGS(reg, v) do { (reg) |= ((v & 0x1f) << 2); } while (0) |
91 | #define FP_INEXACT 1 |
92 | #define FP_UNDERFLOW 2 |
93 | #define FP_OVERFLOW 4 |
94 | #define FP_DIV0 8 |
95 | #define FP_INVALID 16 |
96 | #define FP_UNIMPLEMENTED 32 |
97 | }; |
98 | |
99 | #define 2 |
100 | |
101 | typedef struct CPUMIPSMVPContext CPUMIPSMVPContext; |
102 | struct CPUMIPSMVPContext { |
103 | int32_t CP0_MVPControl; |
104 | #define CP0MVPCo_CPA 3 |
105 | #define CP0MVPCo_STLB 2 |
106 | #define CP0MVPCo_VPC 1 |
107 | #define CP0MVPCo_EVP 0 |
108 | int32_t CP0_MVPConf0; |
109 | #define CP0MVPC0_M 31 |
110 | #define CP0MVPC0_TLBS 29 |
111 | #define CP0MVPC0_GS 28 |
112 | #define CP0MVPC0_PCP 27 |
113 | #define CP0MVPC0_PTLBE 16 |
114 | #define CP0MVPC0_TCA 15 |
115 | #define CP0MVPC0_PVPE 10 |
116 | #define CP0MVPC0_PTC 0 |
117 | int32_t CP0_MVPConf1; |
118 | #define CP0MVPC1_CIM 31 |
119 | #define CP0MVPC1_CIF 30 |
120 | #define CP0MVPC1_PCX 20 |
121 | #define CP0MVPC1_PCP2 10 |
122 | #define CP0MVPC1_PCP1 0 |
123 | }; |
124 | |
125 | typedef struct mips_def_t mips_def_t; |
126 | |
127 | #define MIPS_SHADOW_SET_MAX 16 |
128 | #define MIPS_TC_MAX 5 |
129 | #define MIPS_FPU_MAX 1 |
130 | #define MIPS_DSP_ACC 4 |
131 | #define MIPS_KSCRATCH_NUM 6 |
132 | #define MIPS_MAAR_MAX 16 /* Must be an even number. */ |
133 | |
134 | |
135 | /* |
136 | * Summary of CP0 registers |
137 | * ======================== |
138 | * |
139 | * |
140 | * Register 0 Register 1 Register 2 Register 3 |
141 | * ---------- ---------- ---------- ---------- |
142 | * |
143 | * 0 Index Random EntryLo0 EntryLo1 |
144 | * 1 MVPControl VPEControl TCStatus GlobalNumber |
145 | * 2 MVPConf0 VPEConf0 TCBind |
146 | * 3 MVPConf1 VPEConf1 TCRestart |
147 | * 4 VPControl YQMask TCHalt |
148 | * 5 VPESchedule TCContext |
149 | * 6 VPEScheFBack TCSchedule |
150 | * 7 VPEOpt TCScheFBack TCOpt |
151 | * |
152 | * |
153 | * Register 4 Register 5 Register 6 Register 7 |
154 | * ---------- ---------- ---------- ---------- |
155 | * |
156 | * 0 Context PageMask Wired HWREna |
157 | * 1 ContextConfig PageGrain SRSConf0 |
158 | * 2 UserLocal SegCtl0 SRSConf1 |
159 | * 3 XContextConfig SegCtl1 SRSConf2 |
160 | * 4 DebugContextID SegCtl2 SRSConf3 |
161 | * 5 MemoryMapID PWBase SRSConf4 |
162 | * 6 PWField PWCtl |
163 | * 7 PWSize |
164 | * |
165 | * |
166 | * Register 8 Register 9 Register 10 Register 11 |
167 | * ---------- ---------- ----------- ----------- |
168 | * |
169 | * 0 BadVAddr Count EntryHi Compare |
170 | * 1 BadInstr |
171 | * 2 BadInstrP |
172 | * 3 BadInstrX |
173 | * 4 GuestCtl1 GuestCtl0Ext |
174 | * 5 GuestCtl2 |
175 | * 6 SAARI GuestCtl3 |
176 | * 7 SAAR |
177 | * |
178 | * |
179 | * Register 12 Register 13 Register 14 Register 15 |
180 | * ----------- ----------- ----------- ----------- |
181 | * |
182 | * 0 Status Cause EPC PRId |
183 | * 1 IntCtl EBase |
184 | * 2 SRSCtl NestedEPC CDMMBase |
185 | * 3 SRSMap CMGCRBase |
186 | * 4 View_IPL View_RIPL BEVVA |
187 | * 5 SRSMap2 NestedExc |
188 | * 6 GuestCtl0 |
189 | * 7 GTOffset |
190 | * |
191 | * |
192 | * Register 16 Register 17 Register 18 Register 19 |
193 | * ----------- ----------- ----------- ----------- |
194 | * |
195 | * 0 Config LLAddr WatchLo0 WatchHi |
196 | * 1 Config1 MAAR WatchLo1 WatchHi |
197 | * 2 Config2 MAARI WatchLo2 WatchHi |
198 | * 3 Config3 WatchLo3 WatchHi |
199 | * 4 Config4 WatchLo4 WatchHi |
200 | * 5 Config5 WatchLo5 WatchHi |
201 | * 6 WatchLo6 WatchHi |
202 | * 7 WatchLo7 WatchHi |
203 | * |
204 | * |
205 | * Register 20 Register 21 Register 22 Register 23 |
206 | * ----------- ----------- ----------- ----------- |
207 | * |
208 | * 0 XContext Debug |
209 | * 1 TraceControl |
210 | * 2 TraceControl2 |
211 | * 3 UserTraceData1 |
212 | * 4 TraceIBPC |
213 | * 5 TraceDBPC |
214 | * 6 Debug2 |
215 | * 7 |
216 | * |
217 | * |
218 | * Register 24 Register 25 Register 26 Register 27 |
219 | * ----------- ----------- ----------- ----------- |
220 | * |
221 | * 0 DEPC PerfCnt ErrCtl CacheErr |
222 | * 1 PerfCnt |
223 | * 2 TraceControl3 PerfCnt |
224 | * 3 UserTraceData2 PerfCnt |
225 | * 4 PerfCnt |
226 | * 5 PerfCnt |
227 | * 6 PerfCnt |
228 | * 7 PerfCnt |
229 | * |
230 | * |
231 | * Register 28 Register 29 Register 30 Register 31 |
232 | * ----------- ----------- ----------- ----------- |
233 | * |
234 | * 0 DataLo DataHi ErrorEPC DESAVE |
235 | * 1 TagLo TagHi |
236 | * 2 DataLo1 DataHi1 KScratch<n> |
237 | * 3 TagLo1 TagHi1 KScratch<n> |
238 | * 4 DataLo2 DataHi2 KScratch<n> |
239 | * 5 TagLo2 TagHi2 KScratch<n> |
240 | * 6 DataLo3 DataHi3 KScratch<n> |
241 | * 7 TagLo3 TagHi3 KScratch<n> |
242 | * |
243 | */ |
244 | #define CP0_REGISTER_00 0 |
245 | #define CP0_REGISTER_01 1 |
246 | #define CP0_REGISTER_02 2 |
247 | #define CP0_REGISTER_03 3 |
248 | #define CP0_REGISTER_04 4 |
249 | #define CP0_REGISTER_05 5 |
250 | #define CP0_REGISTER_06 6 |
251 | #define CP0_REGISTER_07 7 |
252 | #define CP0_REGISTER_08 8 |
253 | #define CP0_REGISTER_09 9 |
254 | #define CP0_REGISTER_10 10 |
255 | #define CP0_REGISTER_11 11 |
256 | #define CP0_REGISTER_12 12 |
257 | #define CP0_REGISTER_13 13 |
258 | #define CP0_REGISTER_14 14 |
259 | #define CP0_REGISTER_15 15 |
260 | #define CP0_REGISTER_16 16 |
261 | #define CP0_REGISTER_17 17 |
262 | #define CP0_REGISTER_18 18 |
263 | #define CP0_REGISTER_19 19 |
264 | #define CP0_REGISTER_20 20 |
265 | #define CP0_REGISTER_21 21 |
266 | #define CP0_REGISTER_22 22 |
267 | #define CP0_REGISTER_23 23 |
268 | #define CP0_REGISTER_24 24 |
269 | #define CP0_REGISTER_25 25 |
270 | #define CP0_REGISTER_26 26 |
271 | #define CP0_REGISTER_27 27 |
272 | #define CP0_REGISTER_28 28 |
273 | #define CP0_REGISTER_29 29 |
274 | #define CP0_REGISTER_30 30 |
275 | #define CP0_REGISTER_31 31 |
276 | |
277 | |
278 | /* CP0 Register 00 */ |
279 | #define CP0_REG00__INDEX 0 |
280 | #define CP0_REG00__MVPCONTROL 1 |
281 | #define CP0_REG00__MVPCONF0 2 |
282 | #define CP0_REG00__MVPCONF1 3 |
283 | #define CP0_REG00__VPCONTROL 4 |
284 | /* CP0 Register 01 */ |
285 | #define CP0_REG01__RANDOM 0 |
286 | #define CP0_REG01__VPECONTROL 1 |
287 | #define CP0_REG01__VPECONF0 2 |
288 | #define CP0_REG01__VPECONF1 3 |
289 | #define CP0_REG01__YQMASK 4 |
290 | #define CP0_REG01__VPESCHEDULE 5 |
291 | #define CP0_REG01__VPESCHEFBACK 6 |
292 | #define CP0_REG01__VPEOPT 7 |
293 | /* CP0 Register 02 */ |
294 | #define CP0_REG02__ENTRYLO0 0 |
295 | #define CP0_REG02__TCSTATUS 1 |
296 | #define CP0_REG02__TCBIND 2 |
297 | #define CP0_REG02__TCRESTART 3 |
298 | #define CP0_REG02__TCHALT 4 |
299 | #define CP0_REG02__TCCONTEXT 5 |
300 | #define CP0_REG02__TCSCHEDULE 6 |
301 | #define CP0_REG02__TCSCHEFBACK 7 |
302 | /* CP0 Register 03 */ |
303 | #define CP0_REG03__ENTRYLO1 0 |
304 | #define CP0_REG03__GLOBALNUM 1 |
305 | #define CP0_REG03__TCOPT 7 |
306 | /* CP0 Register 04 */ |
307 | #define CP0_REG04__CONTEXT 0 |
308 | #define CP0_REG04__CONTEXTCONFIG 1 |
309 | #define CP0_REG04__USERLOCAL 2 |
310 | #define CP0_REG04__XCONTEXTCONFIG 3 |
311 | #define CP0_REG04__DBGCONTEXTID 4 |
312 | #define CP0_REG00__MMID 5 |
313 | /* CP0 Register 05 */ |
314 | #define CP0_REG05__PAGEMASK 0 |
315 | #define CP0_REG05__PAGEGRAIN 1 |
316 | #define CP0_REG05__SEGCTL0 2 |
317 | #define CP0_REG05__SEGCTL1 3 |
318 | #define CP0_REG05__SEGCTL2 4 |
319 | #define CP0_REG05__PWBASE 5 |
320 | #define CP0_REG05__PWFIELD 6 |
321 | #define CP0_REG05__PWSIZE 7 |
322 | /* CP0 Register 06 */ |
323 | #define CP0_REG06__WIRED 0 |
324 | #define CP0_REG06__SRSCONF0 1 |
325 | #define CP0_REG06__SRSCONF1 2 |
326 | #define CP0_REG06__SRSCONF2 3 |
327 | #define CP0_REG06__SRSCONF3 4 |
328 | #define CP0_REG06__SRSCONF4 5 |
329 | #define CP0_REG06__PWCTL 6 |
330 | /* CP0 Register 07 */ |
331 | #define CP0_REG07__HWRENA 0 |
332 | /* CP0 Register 08 */ |
333 | #define CP0_REG08__BADVADDR 0 |
334 | #define CP0_REG08__BADINSTR 1 |
335 | #define CP0_REG08__BADINSTRP 2 |
336 | #define CP0_REG08__BADINSTRX 3 |
337 | /* CP0 Register 09 */ |
338 | #define CP0_REG09__COUNT 0 |
339 | #define CP0_REG09__SAARI 6 |
340 | #define CP0_REG09__SAAR 7 |
341 | /* CP0 Register 10 */ |
342 | #define CP0_REG10__ENTRYHI 0 |
343 | #define CP0_REG10__GUESTCTL1 4 |
344 | #define CP0_REG10__GUESTCTL2 5 |
345 | #define CP0_REG10__GUESTCTL3 6 |
346 | /* CP0 Register 11 */ |
347 | #define CP0_REG11__COMPARE 0 |
348 | #define CP0_REG11__GUESTCTL0EXT 4 |
349 | /* CP0 Register 12 */ |
350 | #define CP0_REG12__STATUS 0 |
351 | #define CP0_REG12__INTCTL 1 |
352 | #define CP0_REG12__SRSCTL 2 |
353 | #define CP0_REG12__SRSMAP 3 |
354 | #define CP0_REG12__VIEW_IPL 4 |
355 | #define CP0_REG12__SRSMAP2 5 |
356 | #define CP0_REG12__GUESTCTL0 6 |
357 | #define CP0_REG12__GTOFFSET 7 |
358 | /* CP0 Register 13 */ |
359 | #define CP0_REG13__CAUSE 0 |
360 | #define CP0_REG13__VIEW_RIPL 4 |
361 | #define CP0_REG13__NESTEDEXC 5 |
362 | /* CP0 Register 14 */ |
363 | #define CP0_REG14__EPC 0 |
364 | #define CP0_REG14__NESTEDEPC 2 |
365 | /* CP0 Register 15 */ |
366 | #define CP0_REG15__PRID 0 |
367 | #define CP0_REG15__EBASE 1 |
368 | #define CP0_REG15__CDMMBASE 2 |
369 | #define CP0_REG15__CMGCRBASE 3 |
370 | #define CP0_REG15__BEVVA 4 |
371 | /* CP0 Register 16 */ |
372 | #define CP0_REG16__CONFIG 0 |
373 | #define CP0_REG16__CONFIG1 1 |
374 | #define CP0_REG16__CONFIG2 2 |
375 | #define CP0_REG16__CONFIG3 3 |
376 | #define CP0_REG16__CONFIG4 4 |
377 | #define CP0_REG16__CONFIG5 5 |
378 | #define CP0_REG16__CONFIG6 6 |
379 | #define CP0_REG16__CONFIG7 7 |
380 | /* CP0 Register 17 */ |
381 | #define CP0_REG17__LLADDR 0 |
382 | #define CP0_REG17__MAAR 1 |
383 | #define CP0_REG17__MAARI 2 |
384 | /* CP0 Register 18 */ |
385 | #define CP0_REG18__WATCHLO0 0 |
386 | #define CP0_REG18__WATCHLO1 1 |
387 | #define CP0_REG18__WATCHLO2 2 |
388 | #define CP0_REG18__WATCHLO3 3 |
389 | #define CP0_REG18__WATCHLO4 4 |
390 | #define CP0_REG18__WATCHLO5 5 |
391 | #define CP0_REG18__WATCHLO6 6 |
392 | #define CP0_REG18__WATCHLO7 7 |
393 | /* CP0 Register 19 */ |
394 | #define CP0_REG19__WATCHHI0 0 |
395 | #define CP0_REG19__WATCHHI1 1 |
396 | #define CP0_REG19__WATCHHI2 2 |
397 | #define CP0_REG19__WATCHHI3 3 |
398 | #define CP0_REG19__WATCHHI4 4 |
399 | #define CP0_REG19__WATCHHI5 5 |
400 | #define CP0_REG19__WATCHHI6 6 |
401 | #define CP0_REG19__WATCHHI7 7 |
402 | /* CP0 Register 20 */ |
403 | #define CP0_REG20__XCONTEXT 0 |
404 | /* CP0 Register 21 */ |
405 | /* CP0 Register 22 */ |
406 | /* CP0 Register 23 */ |
407 | #define CP0_REG23__DEBUG 0 |
408 | #define CP0_REG23__TRACECONTROL 1 |
409 | #define CP0_REG23__TRACECONTROL2 2 |
410 | #define CP0_REG23__USERTRACEDATA1 3 |
411 | #define CP0_REG23__TRACEIBPC 4 |
412 | #define CP0_REG23__TRACEDBPC 5 |
413 | #define CP0_REG23__DEBUG2 6 |
414 | /* CP0 Register 24 */ |
415 | #define CP0_REG24__DEPC 0 |
416 | /* CP0 Register 25 */ |
417 | #define CP0_REG25__PERFCTL0 0 |
418 | #define CP0_REG25__PERFCNT0 1 |
419 | #define CP0_REG25__PERFCTL1 2 |
420 | #define CP0_REG25__PERFCNT1 3 |
421 | #define CP0_REG25__PERFCTL2 4 |
422 | #define CP0_REG25__PERFCNT2 5 |
423 | #define CP0_REG25__PERFCTL3 6 |
424 | #define CP0_REG25__PERFCNT3 7 |
425 | /* CP0 Register 26 */ |
426 | #define CP0_REG26__ERRCTL 0 |
427 | /* CP0 Register 27 */ |
428 | #define CP0_REG27__CACHERR 0 |
429 | /* CP0 Register 28 */ |
430 | #define CP0_REG28__TAGLO 0 |
431 | #define CP0_REG28__DATALO 1 |
432 | #define CP0_REG28__TAGLO1 2 |
433 | #define CP0_REG28__DATALO1 3 |
434 | #define CP0_REG28__TAGLO2 4 |
435 | #define CP0_REG28__DATALO2 5 |
436 | #define CP0_REG28__TAGLO3 6 |
437 | #define CP0_REG28__DATALO3 7 |
438 | /* CP0 Register 29 */ |
439 | #define CP0_REG29__TAGHI 0 |
440 | #define CP0_REG29__DATAHI 1 |
441 | #define CP0_REG29__TAGHI1 2 |
442 | #define CP0_REG29__DATAHI1 3 |
443 | #define CP0_REG29__TAGHI2 4 |
444 | #define CP0_REG29__DATAHI2 5 |
445 | #define CP0_REG29__TAGHI3 6 |
446 | #define CP0_REG29__DATAHI3 7 |
447 | /* CP0 Register 30 */ |
448 | #define CP0_REG30__ERROREPC 0 |
449 | /* CP0 Register 31 */ |
450 | #define CP0_REG31__DESAVE 0 |
451 | #define CP0_REG31__KSCRATCH1 2 |
452 | #define CP0_REG31__KSCRATCH2 3 |
453 | #define CP0_REG31__KSCRATCH3 4 |
454 | #define CP0_REG31__KSCRATCH4 5 |
455 | #define CP0_REG31__KSCRATCH5 6 |
456 | #define CP0_REG31__KSCRATCH6 7 |
457 | |
458 | |
459 | typedef struct TCState TCState; |
460 | struct TCState { |
461 | target_ulong gpr[32]; |
462 | target_ulong PC; |
463 | target_ulong HI[MIPS_DSP_ACC]; |
464 | target_ulong LO[MIPS_DSP_ACC]; |
465 | target_ulong ACX[MIPS_DSP_ACC]; |
466 | target_ulong DSPControl; |
467 | int32_t CP0_TCStatus; |
468 | #define CP0TCSt_TCU3 31 |
469 | #define CP0TCSt_TCU2 30 |
470 | #define CP0TCSt_TCU1 29 |
471 | #define CP0TCSt_TCU0 28 |
472 | #define CP0TCSt_TMX 27 |
473 | #define CP0TCSt_RNST 23 |
474 | #define CP0TCSt_TDS 21 |
475 | #define CP0TCSt_DT 20 |
476 | #define CP0TCSt_DA 15 |
477 | #define CP0TCSt_A 13 |
478 | #define CP0TCSt_TKSU 11 |
479 | #define CP0TCSt_IXMT 10 |
480 | #define CP0TCSt_TASID 0 |
481 | int32_t CP0_TCBind; |
482 | #define CP0TCBd_CurTC 21 |
483 | #define CP0TCBd_TBE 17 |
484 | #define CP0TCBd_CurVPE 0 |
485 | target_ulong CP0_TCHalt; |
486 | target_ulong CP0_TCContext; |
487 | target_ulong CP0_TCSchedule; |
488 | target_ulong CP0_TCScheFBack; |
489 | int32_t CP0_Debug_tcstatus; |
490 | target_ulong CP0_UserLocal; |
491 | |
492 | int32_t msacsr; |
493 | |
494 | #define MSACSR_FS 24 |
495 | #define MSACSR_FS_MASK (1 << MSACSR_FS) |
496 | #define MSACSR_NX 18 |
497 | #define MSACSR_NX_MASK (1 << MSACSR_NX) |
498 | #define MSACSR_CEF 2 |
499 | #define MSACSR_CEF_MASK (0xffff << MSACSR_CEF) |
500 | #define MSACSR_RM 0 |
501 | #define MSACSR_RM_MASK (0x3 << MSACSR_RM) |
502 | #define MSACSR_MASK (MSACSR_RM_MASK | MSACSR_CEF_MASK | MSACSR_NX_MASK | \ |
503 | MSACSR_FS_MASK) |
504 | |
505 | float_status msa_fp_status; |
506 | |
507 | /* Upper 64-bit MMRs (multimedia registers); the lower 64-bit are GPRs */ |
508 | uint64_t mmr[32]; |
509 | |
510 | #define NUMBER_OF_MXU_REGISTERS 16 |
511 | target_ulong mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1]; |
512 | target_ulong mxu_cr; |
513 | #define MXU_CR_LC 31 |
514 | #define MXU_CR_RC 30 |
515 | #define MXU_CR_BIAS 2 |
516 | #define MXU_CR_RD_EN 1 |
517 | #define MXU_CR_MXU_EN 0 |
518 | |
519 | }; |
520 | |
521 | struct MIPSITUState; |
522 | typedef struct CPUMIPSState CPUMIPSState; |
523 | struct CPUMIPSState { |
524 | TCState active_tc; |
525 | CPUMIPSFPUContext active_fpu; |
526 | |
527 | uint32_t current_tc; |
528 | uint32_t current_fpu; |
529 | |
530 | uint32_t SEGBITS; |
531 | uint32_t PABITS; |
532 | #if defined(TARGET_MIPS64) |
533 | # define PABITS_BASE 36 |
534 | #else |
535 | # define PABITS_BASE 32 |
536 | #endif |
537 | target_ulong SEGMask; |
538 | uint64_t PAMask; |
539 | #define PAMASK_BASE ((1ULL << PABITS_BASE) - 1) |
540 | |
541 | int32_t msair; |
542 | #define MSAIR_ProcID 8 |
543 | #define MSAIR_Rev 0 |
544 | |
545 | /* |
546 | * CP0 Register 0 |
547 | */ |
548 | int32_t CP0_Index; |
549 | /* CP0_MVP* are per MVP registers. */ |
550 | int32_t CP0_VPControl; |
551 | #define CP0VPCtl_DIS 0 |
552 | /* |
553 | * CP0 Register 1 |
554 | */ |
555 | int32_t CP0_Random; |
556 | int32_t CP0_VPEControl; |
557 | #define CP0VPECo_YSI 21 |
558 | #define CP0VPECo_GSI 20 |
559 | #define CP0VPECo_EXCPT 16 |
560 | #define CP0VPECo_TE 15 |
561 | #define CP0VPECo_TargTC 0 |
562 | int32_t CP0_VPEConf0; |
563 | #define CP0VPEC0_M 31 |
564 | #define CP0VPEC0_XTC 21 |
565 | #define CP0VPEC0_TCS 19 |
566 | #define CP0VPEC0_SCS 18 |
567 | #define CP0VPEC0_DSC 17 |
568 | #define CP0VPEC0_ICS 16 |
569 | #define CP0VPEC0_MVP 1 |
570 | #define CP0VPEC0_VPA 0 |
571 | int32_t CP0_VPEConf1; |
572 | #define CP0VPEC1_NCX 20 |
573 | #define CP0VPEC1_NCP2 10 |
574 | #define CP0VPEC1_NCP1 0 |
575 | target_ulong CP0_YQMask; |
576 | target_ulong CP0_VPESchedule; |
577 | target_ulong CP0_VPEScheFBack; |
578 | int32_t CP0_VPEOpt; |
579 | #define CP0VPEOpt_IWX7 15 |
580 | #define CP0VPEOpt_IWX6 14 |
581 | #define CP0VPEOpt_IWX5 13 |
582 | #define CP0VPEOpt_IWX4 12 |
583 | #define CP0VPEOpt_IWX3 11 |
584 | #define CP0VPEOpt_IWX2 10 |
585 | #define CP0VPEOpt_IWX1 9 |
586 | #define CP0VPEOpt_IWX0 8 |
587 | #define CP0VPEOpt_DWX7 7 |
588 | #define CP0VPEOpt_DWX6 6 |
589 | #define CP0VPEOpt_DWX5 5 |
590 | #define CP0VPEOpt_DWX4 4 |
591 | #define CP0VPEOpt_DWX3 3 |
592 | #define CP0VPEOpt_DWX2 2 |
593 | #define CP0VPEOpt_DWX1 1 |
594 | #define CP0VPEOpt_DWX0 0 |
595 | /* |
596 | * CP0 Register 2 |
597 | */ |
598 | uint64_t CP0_EntryLo0; |
599 | /* |
600 | * CP0 Register 3 |
601 | */ |
602 | uint64_t CP0_EntryLo1; |
603 | #if defined(TARGET_MIPS64) |
604 | # define CP0EnLo_RI 63 |
605 | # define CP0EnLo_XI 62 |
606 | #else |
607 | # define CP0EnLo_RI 31 |
608 | # define CP0EnLo_XI 30 |
609 | #endif |
610 | int32_t CP0_GlobalNumber; |
611 | #define CP0GN_VPId 0 |
612 | /* |
613 | * CP0 Register 4 |
614 | */ |
615 | target_ulong CP0_Context; |
616 | int32_t CP0_MemoryMapID; |
617 | /* |
618 | * CP0 Register 5 |
619 | */ |
620 | int32_t CP0_PageMask; |
621 | int32_t CP0_PageGrain_rw_bitmask; |
622 | int32_t CP0_PageGrain; |
623 | #define CP0PG_RIE 31 |
624 | #define CP0PG_XIE 30 |
625 | #define CP0PG_ELPA 29 |
626 | #define CP0PG_IEC 27 |
627 | target_ulong CP0_SegCtl0; |
628 | target_ulong CP0_SegCtl1; |
629 | target_ulong CP0_SegCtl2; |
630 | #define CP0SC_PA 9 |
631 | #define CP0SC_PA_MASK (0x7FULL << CP0SC_PA) |
632 | #define CP0SC_PA_1GMASK (0x7EULL << CP0SC_PA) |
633 | #define CP0SC_AM 4 |
634 | #define CP0SC_AM_MASK (0x7ULL << CP0SC_AM) |
635 | #define CP0SC_AM_UK 0ULL |
636 | #define CP0SC_AM_MK 1ULL |
637 | #define CP0SC_AM_MSK 2ULL |
638 | #define CP0SC_AM_MUSK 3ULL |
639 | #define CP0SC_AM_MUSUK 4ULL |
640 | #define CP0SC_AM_USK 5ULL |
641 | #define CP0SC_AM_UUSK 7ULL |
642 | #define CP0SC_EU 3 |
643 | #define CP0SC_EU_MASK (1ULL << CP0SC_EU) |
644 | #define CP0SC_C 0 |
645 | #define CP0SC_C_MASK (0x7ULL << CP0SC_C) |
646 | #define CP0SC_MASK (CP0SC_C_MASK | CP0SC_EU_MASK | CP0SC_AM_MASK | \ |
647 | CP0SC_PA_MASK) |
648 | #define CP0SC_1GMASK (CP0SC_C_MASK | CP0SC_EU_MASK | CP0SC_AM_MASK | \ |
649 | CP0SC_PA_1GMASK) |
650 | #define CP0SC0_MASK (CP0SC_MASK | (CP0SC_MASK << 16)) |
651 | #define CP0SC1_XAM 59 |
652 | #define CP0SC1_XAM_MASK (0x7ULL << CP0SC1_XAM) |
653 | #define CP0SC1_MASK (CP0SC_MASK | (CP0SC_MASK << 16) | CP0SC1_XAM_MASK) |
654 | #define CP0SC2_XR 56 |
655 | #define CP0SC2_XR_MASK (0xFFULL << CP0SC2_XR) |
656 | #define CP0SC2_MASK (CP0SC_1GMASK | (CP0SC_1GMASK << 16) | CP0SC2_XR_MASK) |
657 | target_ulong CP0_PWBase; |
658 | target_ulong CP0_PWField; |
659 | #if defined(TARGET_MIPS64) |
660 | #define CP0PF_BDI 32 /* 37..32 */ |
661 | #define CP0PF_GDI 24 /* 29..24 */ |
662 | #define CP0PF_UDI 18 /* 23..18 */ |
663 | #define CP0PF_MDI 12 /* 17..12 */ |
664 | #define CP0PF_PTI 6 /* 11..6 */ |
665 | #define CP0PF_PTEI 0 /* 5..0 */ |
666 | #else |
667 | #define CP0PF_GDW 24 /* 29..24 */ |
668 | #define CP0PF_UDW 18 /* 23..18 */ |
669 | #define CP0PF_MDW 12 /* 17..12 */ |
670 | #define CP0PF_PTW 6 /* 11..6 */ |
671 | #define CP0PF_PTEW 0 /* 5..0 */ |
672 | #endif |
673 | target_ulong CP0_PWSize; |
674 | #if defined(TARGET_MIPS64) |
675 | #define CP0PS_BDW 32 /* 37..32 */ |
676 | #endif |
677 | #define CP0PS_PS 30 |
678 | #define CP0PS_GDW 24 /* 29..24 */ |
679 | #define CP0PS_UDW 18 /* 23..18 */ |
680 | #define CP0PS_MDW 12 /* 17..12 */ |
681 | #define CP0PS_PTW 6 /* 11..6 */ |
682 | #define CP0PS_PTEW 0 /* 5..0 */ |
683 | /* |
684 | * CP0 Register 6 |
685 | */ |
686 | int32_t CP0_Wired; |
687 | int32_t CP0_PWCtl; |
688 | #define CP0PC_PWEN 31 |
689 | #if defined(TARGET_MIPS64) |
690 | #define CP0PC_PWDIREXT 30 |
691 | #define CP0PC_XK 28 |
692 | #define CP0PC_XS 27 |
693 | #define CP0PC_XU 26 |
694 | #endif |
695 | #define CP0PC_DPH 7 |
696 | #define CP0PC_HUGEPG 6 |
697 | #define CP0PC_PSN 0 /* 5..0 */ |
698 | int32_t CP0_SRSConf0_rw_bitmask; |
699 | int32_t CP0_SRSConf0; |
700 | #define CP0SRSC0_M 31 |
701 | #define CP0SRSC0_SRS3 20 |
702 | #define CP0SRSC0_SRS2 10 |
703 | #define CP0SRSC0_SRS1 0 |
704 | int32_t CP0_SRSConf1_rw_bitmask; |
705 | int32_t CP0_SRSConf1; |
706 | #define CP0SRSC1_M 31 |
707 | #define CP0SRSC1_SRS6 20 |
708 | #define CP0SRSC1_SRS5 10 |
709 | #define CP0SRSC1_SRS4 0 |
710 | int32_t CP0_SRSConf2_rw_bitmask; |
711 | int32_t CP0_SRSConf2; |
712 | #define CP0SRSC2_M 31 |
713 | #define CP0SRSC2_SRS9 20 |
714 | #define CP0SRSC2_SRS8 10 |
715 | #define CP0SRSC2_SRS7 0 |
716 | int32_t CP0_SRSConf3_rw_bitmask; |
717 | int32_t CP0_SRSConf3; |
718 | #define CP0SRSC3_M 31 |
719 | #define CP0SRSC3_SRS12 20 |
720 | #define CP0SRSC3_SRS11 10 |
721 | #define CP0SRSC3_SRS10 0 |
722 | int32_t CP0_SRSConf4_rw_bitmask; |
723 | int32_t CP0_SRSConf4; |
724 | #define CP0SRSC4_SRS15 20 |
725 | #define CP0SRSC4_SRS14 10 |
726 | #define CP0SRSC4_SRS13 0 |
727 | /* |
728 | * CP0 Register 7 |
729 | */ |
730 | int32_t CP0_HWREna; |
731 | /* |
732 | * CP0 Register 8 |
733 | */ |
734 | target_ulong CP0_BadVAddr; |
735 | uint32_t CP0_BadInstr; |
736 | uint32_t CP0_BadInstrP; |
737 | uint32_t CP0_BadInstrX; |
738 | /* |
739 | * CP0 Register 9 |
740 | */ |
741 | int32_t CP0_Count; |
742 | uint32_t CP0_SAARI; |
743 | #define CP0SAARI_TARGET 0 /* 5..0 */ |
744 | uint64_t CP0_SAAR[2]; |
745 | #define CP0SAAR_BASE 12 /* 43..12 */ |
746 | #define CP0SAAR_SIZE 1 /* 5..1 */ |
747 | #define CP0SAAR_EN 0 |
748 | /* |
749 | * CP0 Register 10 |
750 | */ |
751 | target_ulong CP0_EntryHi; |
752 | #define CP0EnHi_EHINV 10 |
753 | target_ulong CP0_EntryHi_ASID_mask; |
754 | /* |
755 | * CP0 Register 11 |
756 | */ |
757 | int32_t CP0_Compare; |
758 | /* |
759 | * CP0 Register 12 |
760 | */ |
761 | int32_t CP0_Status; |
762 | #define CP0St_CU3 31 |
763 | #define CP0St_CU2 30 |
764 | #define CP0St_CU1 29 |
765 | #define CP0St_CU0 28 |
766 | #define CP0St_RP 27 |
767 | #define CP0St_FR 26 |
768 | #define CP0St_RE 25 |
769 | #define CP0St_MX 24 |
770 | #define CP0St_PX 23 |
771 | #define CP0St_BEV 22 |
772 | #define CP0St_TS 21 |
773 | #define CP0St_SR 20 |
774 | #define CP0St_NMI 19 |
775 | #define CP0St_IM 8 |
776 | #define CP0St_KX 7 |
777 | #define CP0St_SX 6 |
778 | #define CP0St_UX 5 |
779 | #define CP0St_KSU 3 |
780 | #define CP0St_ERL 2 |
781 | #define CP0St_EXL 1 |
782 | #define CP0St_IE 0 |
783 | int32_t CP0_IntCtl; |
784 | #define CP0IntCtl_IPTI 29 |
785 | #define CP0IntCtl_IPPCI 26 |
786 | #define CP0IntCtl_VS 5 |
787 | int32_t CP0_SRSCtl; |
788 | #define CP0SRSCtl_HSS 26 |
789 | #define CP0SRSCtl_EICSS 18 |
790 | #define CP0SRSCtl_ESS 12 |
791 | #define CP0SRSCtl_PSS 6 |
792 | #define CP0SRSCtl_CSS 0 |
793 | int32_t CP0_SRSMap; |
794 | #define CP0SRSMap_SSV7 28 |
795 | #define CP0SRSMap_SSV6 24 |
796 | #define CP0SRSMap_SSV5 20 |
797 | #define CP0SRSMap_SSV4 16 |
798 | #define CP0SRSMap_SSV3 12 |
799 | #define CP0SRSMap_SSV2 8 |
800 | #define CP0SRSMap_SSV1 4 |
801 | #define CP0SRSMap_SSV0 0 |
802 | /* |
803 | * CP0 Register 13 |
804 | */ |
805 | int32_t CP0_Cause; |
806 | #define CP0Ca_BD 31 |
807 | #define CP0Ca_TI 30 |
808 | #define CP0Ca_CE 28 |
809 | #define CP0Ca_DC 27 |
810 | #define CP0Ca_PCI 26 |
811 | #define CP0Ca_IV 23 |
812 | #define CP0Ca_WP 22 |
813 | #define CP0Ca_IP 8 |
814 | #define CP0Ca_IP_mask 0x0000FF00 |
815 | #define CP0Ca_EC 2 |
816 | /* |
817 | * CP0 Register 14 |
818 | */ |
819 | target_ulong CP0_EPC; |
820 | /* |
821 | * CP0 Register 15 |
822 | */ |
823 | int32_t CP0_PRid; |
824 | target_ulong CP0_EBase; |
825 | target_ulong CP0_EBaseWG_rw_bitmask; |
826 | #define CP0EBase_WG 11 |
827 | target_ulong CP0_CMGCRBase; |
828 | /* |
829 | * CP0 Register 16 |
830 | */ |
831 | int32_t CP0_Config0; |
832 | #define CP0C0_M 31 |
833 | #define CP0C0_K23 28 /* 30..28 */ |
834 | #define CP0C0_KU 25 /* 27..25 */ |
835 | #define CP0C0_MDU 20 |
836 | #define CP0C0_MM 18 |
837 | #define CP0C0_BM 16 |
838 | #define CP0C0_Impl 16 /* 24..16 */ |
839 | #define CP0C0_BE 15 |
840 | #define CP0C0_AT 13 /* 14..13 */ |
841 | #define CP0C0_AR 10 /* 12..10 */ |
842 | #define CP0C0_MT 7 /* 9..7 */ |
843 | #define CP0C0_VI 3 |
844 | #define CP0C0_K0 0 /* 2..0 */ |
845 | int32_t CP0_Config1; |
846 | #define CP0C1_M 31 |
847 | #define CP0C1_MMU 25 /* 30..25 */ |
848 | #define CP0C1_IS 22 /* 24..22 */ |
849 | #define CP0C1_IL 19 /* 21..19 */ |
850 | #define CP0C1_IA 16 /* 18..16 */ |
851 | #define CP0C1_DS 13 /* 15..13 */ |
852 | #define CP0C1_DL 10 /* 12..10 */ |
853 | #define CP0C1_DA 7 /* 9..7 */ |
854 | #define CP0C1_C2 6 |
855 | #define CP0C1_MD 5 |
856 | #define CP0C1_PC 4 |
857 | #define CP0C1_WR 3 |
858 | #define CP0C1_CA 2 |
859 | #define CP0C1_EP 1 |
860 | #define CP0C1_FP 0 |
861 | int32_t CP0_Config2; |
862 | #define CP0C2_M 31 |
863 | #define CP0C2_TU 28 /* 30..28 */ |
864 | #define CP0C2_TS 24 /* 27..24 */ |
865 | #define CP0C2_TL 20 /* 23..20 */ |
866 | #define CP0C2_TA 16 /* 19..16 */ |
867 | #define CP0C2_SU 12 /* 15..12 */ |
868 | #define CP0C2_SS 8 /* 11..8 */ |
869 | #define CP0C2_SL 4 /* 7..4 */ |
870 | #define CP0C2_SA 0 /* 3..0 */ |
871 | int32_t CP0_Config3; |
872 | #define CP0C3_M 31 |
873 | #define CP0C3_BPG 30 |
874 | #define CP0C3_CMGCR 29 |
875 | #define CP0C3_MSAP 28 |
876 | #define CP0C3_BP 27 |
877 | #define CP0C3_BI 26 |
878 | #define CP0C3_SC 25 |
879 | #define CP0C3_PW 24 |
880 | #define CP0C3_VZ 23 |
881 | #define CP0C3_IPLV 21 /* 22..21 */ |
882 | #define CP0C3_MMAR 18 /* 20..18 */ |
883 | #define CP0C3_MCU 17 |
884 | #define CP0C3_ISA_ON_EXC 16 |
885 | #define CP0C3_ISA 14 /* 15..14 */ |
886 | #define CP0C3_ULRI 13 |
887 | #define CP0C3_RXI 12 |
888 | #define CP0C3_DSP2P 11 |
889 | #define CP0C3_DSPP 10 |
890 | #define CP0C3_CTXTC 9 |
891 | #define CP0C3_ITL 8 |
892 | #define CP0C3_LPA 7 |
893 | #define CP0C3_VEIC 6 |
894 | #define CP0C3_VInt 5 |
895 | #define CP0C3_SP 4 |
896 | #define CP0C3_CDMM 3 |
897 | #define CP0C3_MT 2 |
898 | #define CP0C3_SM 1 |
899 | #define CP0C3_TL 0 |
900 | int32_t CP0_Config4; |
901 | int32_t CP0_Config4_rw_bitmask; |
902 | #define CP0C4_M 31 |
903 | #define CP0C4_IE 29 /* 30..29 */ |
904 | #define CP0C4_AE 28 |
905 | #define CP0C4_VTLBSizeExt 24 /* 27..24 */ |
906 | #define CP0C4_KScrExist 16 |
907 | #define CP0C4_MMUExtDef 14 |
908 | #define CP0C4_FTLBPageSize 8 /* 12..8 */ |
909 | /* bit layout if MMUExtDef=1 */ |
910 | #define CP0C4_MMUSizeExt 0 /* 7..0 */ |
911 | /* bit layout if MMUExtDef=2 */ |
912 | #define CP0C4_FTLBWays 4 /* 7..4 */ |
913 | #define CP0C4_FTLBSets 0 /* 3..0 */ |
914 | int32_t CP0_Config5; |
915 | int32_t CP0_Config5_rw_bitmask; |
916 | #define CP0C5_M 31 |
917 | #define CP0C5_K 30 |
918 | #define CP0C5_CV 29 |
919 | #define CP0C5_EVA 28 |
920 | #define CP0C5_MSAEn 27 |
921 | #define CP0C5_PMJ 23 /* 25..23 */ |
922 | #define CP0C5_WR2 22 |
923 | #define CP0C5_NMS 21 |
924 | #define CP0C5_ULS 20 |
925 | #define CP0C5_XPA 19 |
926 | #define CP0C5_CRCP 18 |
927 | #define CP0C5_MI 17 |
928 | #define CP0C5_GI 15 /* 16..15 */ |
929 | #define CP0C5_CA2 14 |
930 | #define CP0C5_XNP 13 |
931 | #define CP0C5_DEC 11 |
932 | #define CP0C5_L2C 10 |
933 | #define CP0C5_UFE 9 |
934 | #define CP0C5_FRE 8 |
935 | #define CP0C5_VP 7 |
936 | #define CP0C5_SBRI 6 |
937 | #define CP0C5_MVH 5 |
938 | #define CP0C5_LLB 4 |
939 | #define CP0C5_MRP 3 |
940 | #define CP0C5_UFR 2 |
941 | #define CP0C5_NFExists 0 |
942 | int32_t CP0_Config6; |
943 | int32_t CP0_Config7; |
944 | uint64_t CP0_LLAddr; |
945 | uint64_t CP0_MAAR[MIPS_MAAR_MAX]; |
946 | int32_t CP0_MAARI; |
947 | /* XXX: Maybe make LLAddr per-TC? */ |
948 | /* |
949 | * CP0 Register 17 |
950 | */ |
951 | target_ulong lladdr; /* LL virtual address compared against SC */ |
952 | target_ulong llval; |
953 | uint64_t llval_wp; |
954 | uint32_t llnewval_wp; |
955 | uint64_t CP0_LLAddr_rw_bitmask; |
956 | int CP0_LLAddr_shift; |
957 | /* |
958 | * CP0 Register 18 |
959 | */ |
960 | target_ulong CP0_WatchLo[8]; |
961 | /* |
962 | * CP0 Register 19 |
963 | */ |
964 | int32_t CP0_WatchHi[8]; |
965 | #define CP0WH_ASID 16 |
966 | /* |
967 | * CP0 Register 20 |
968 | */ |
969 | target_ulong CP0_XContext; |
970 | int32_t CP0_Framemask; |
971 | /* |
972 | * CP0 Register 23 |
973 | */ |
974 | int32_t CP0_Debug; |
975 | #define CP0DB_DBD 31 |
976 | #define CP0DB_DM 30 |
977 | #define CP0DB_LSNM 28 |
978 | #define CP0DB_Doze 27 |
979 | #define CP0DB_Halt 26 |
980 | #define CP0DB_CNT 25 |
981 | #define CP0DB_IBEP 24 |
982 | #define CP0DB_DBEP 21 |
983 | #define CP0DB_IEXI 20 |
984 | #define CP0DB_VER 15 |
985 | #define CP0DB_DEC 10 |
986 | #define CP0DB_SSt 8 |
987 | #define CP0DB_DINT 5 |
988 | #define CP0DB_DIB 4 |
989 | #define CP0DB_DDBS 3 |
990 | #define CP0DB_DDBL 2 |
991 | #define CP0DB_DBp 1 |
992 | #define CP0DB_DSS 0 |
993 | /* |
994 | * CP0 Register 24 |
995 | */ |
996 | target_ulong CP0_DEPC; |
997 | /* |
998 | * CP0 Register 25 |
999 | */ |
1000 | int32_t CP0_Performance0; |
1001 | /* |
1002 | * CP0 Register 26 |
1003 | */ |
1004 | int32_t CP0_ErrCtl; |
1005 | #define CP0EC_WST 29 |
1006 | #define CP0EC_SPR 28 |
1007 | #define CP0EC_ITC 26 |
1008 | /* |
1009 | * CP0 Register 28 |
1010 | */ |
1011 | uint64_t CP0_TagLo; |
1012 | int32_t CP0_DataLo; |
1013 | /* |
1014 | * CP0 Register 29 |
1015 | */ |
1016 | int32_t CP0_TagHi; |
1017 | int32_t CP0_DataHi; |
1018 | /* |
1019 | * CP0 Register 30 |
1020 | */ |
1021 | target_ulong CP0_ErrorEPC; |
1022 | /* |
1023 | * CP0 Register 31 |
1024 | */ |
1025 | int32_t CP0_DESAVE; |
1026 | target_ulong CP0_KScratch[MIPS_KSCRATCH_NUM]; |
1027 | |
1028 | /* We waste some space so we can handle shadow registers like TCs. */ |
1029 | TCState tcs[MIPS_SHADOW_SET_MAX]; |
1030 | CPUMIPSFPUContext fpus[MIPS_FPU_MAX]; |
1031 | /* QEMU */ |
1032 | int error_code; |
1033 | #define EXCP_TLB_NOMATCH 0x1 |
1034 | #define EXCP_INST_NOTAVAIL 0x2 /* No valid instruction word for BadInstr */ |
1035 | uint32_t hflags; /* CPU State */ |
1036 | /* TMASK defines different execution modes */ |
1037 | #define MIPS_HFLAG_TMASK 0x1F5807FF |
1038 | #define MIPS_HFLAG_MODE 0x00007 /* execution modes */ |
1039 | /* |
1040 | * The KSU flags must be the lowest bits in hflags. The flag order |
1041 | * must be the same as defined for CP0 Status. This allows to use |
1042 | * the bits as the value of mmu_idx. |
1043 | */ |
1044 | #define MIPS_HFLAG_KSU 0x00003 /* kernel/supervisor/user mode mask */ |
1045 | #define MIPS_HFLAG_UM 0x00002 /* user mode flag */ |
1046 | #define MIPS_HFLAG_SM 0x00001 /* supervisor mode flag */ |
1047 | #define MIPS_HFLAG_KM 0x00000 /* kernel mode flag */ |
1048 | #define MIPS_HFLAG_DM 0x00004 /* Debug mode */ |
1049 | #define MIPS_HFLAG_64 0x00008 /* 64-bit instructions enabled */ |
1050 | #define MIPS_HFLAG_CP0 0x00010 /* CP0 enabled */ |
1051 | #define MIPS_HFLAG_FPU 0x00020 /* FPU enabled */ |
1052 | #define MIPS_HFLAG_F64 0x00040 /* 64-bit FPU enabled */ |
1053 | /* |
1054 | * True if the MIPS IV COP1X instructions can be used. This also |
1055 | * controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S |
1056 | * and RSQRT.D. |
1057 | */ |
1058 | #define MIPS_HFLAG_COP1X 0x00080 /* COP1X instructions enabled */ |
1059 | #define MIPS_HFLAG_RE 0x00100 /* Reversed endianness */ |
1060 | #define MIPS_HFLAG_AWRAP 0x00200 /* 32-bit compatibility address wrapping */ |
1061 | #define MIPS_HFLAG_M16 0x00400 /* MIPS16 mode flag */ |
1062 | #define MIPS_HFLAG_M16_SHIFT 10 |
1063 | /* |
1064 | * If translation is interrupted between the branch instruction and |
1065 | * the delay slot, record what type of branch it is so that we can |
1066 | * resume translation properly. It might be possible to reduce |
1067 | * this from three bits to two. |
1068 | */ |
1069 | #define MIPS_HFLAG_BMASK_BASE 0x803800 |
1070 | #define MIPS_HFLAG_B 0x00800 /* Unconditional branch */ |
1071 | #define MIPS_HFLAG_BC 0x01000 /* Conditional branch */ |
1072 | #define MIPS_HFLAG_BL 0x01800 /* Likely branch */ |
1073 | #define MIPS_HFLAG_BR 0x02000 /* branch to register (can't link TB) */ |
1074 | /* Extra flags about the current pending branch. */ |
1075 | #define MIPS_HFLAG_BMASK_EXT 0x7C000 |
1076 | #define MIPS_HFLAG_B16 0x04000 /* branch instruction was 16 bits */ |
1077 | #define MIPS_HFLAG_BDS16 0x08000 /* branch requires 16-bit delay slot */ |
1078 | #define MIPS_HFLAG_BDS32 0x10000 /* branch requires 32-bit delay slot */ |
1079 | #define MIPS_HFLAG_BDS_STRICT 0x20000 /* Strict delay slot size */ |
1080 | #define MIPS_HFLAG_BX 0x40000 /* branch exchanges execution mode */ |
1081 | #define MIPS_HFLAG_BMASK (MIPS_HFLAG_BMASK_BASE | MIPS_HFLAG_BMASK_EXT) |
1082 | /* MIPS DSP resources access. */ |
1083 | #define MIPS_HFLAG_DSP 0x080000 /* Enable access to DSP resources. */ |
1084 | #define MIPS_HFLAG_DSP_R2 0x100000 /* Enable access to DSP R2 resources. */ |
1085 | #define MIPS_HFLAG_DSP_R3 0x20000000 /* Enable access to DSP R3 resources. */ |
1086 | /* Extra flag about HWREna register. */ |
1087 | #define MIPS_HFLAG_HWRENA_ULR 0x200000 /* ULR bit from HWREna is set. */ |
1088 | #define MIPS_HFLAG_SBRI 0x400000 /* R6 SDBBP causes RI excpt. in user mode */ |
1089 | #define MIPS_HFLAG_FBNSLOT 0x800000 /* Forbidden slot */ |
1090 | #define MIPS_HFLAG_MSA 0x1000000 |
1091 | #define MIPS_HFLAG_FRE 0x2000000 /* FRE enabled */ |
1092 | #define MIPS_HFLAG_ELPA 0x4000000 |
1093 | #define MIPS_HFLAG_ITC_CACHE 0x8000000 /* CACHE instr. operates on ITC tag */ |
1094 | #define MIPS_HFLAG_ERL 0x10000000 /* error level flag */ |
1095 | target_ulong btarget; /* Jump / branch target */ |
1096 | target_ulong bcond; /* Branch condition (if needed) */ |
1097 | |
1098 | int SYNCI_Step; /* Address step size for SYNCI */ |
1099 | int CCRes; /* Cycle count resolution/divisor */ |
1100 | uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */ |
1101 | uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */ |
1102 | uint64_t insn_flags; /* Supported instruction set */ |
1103 | int saarp; |
1104 | |
1105 | /* Fields up to this point are cleared by a CPU reset */ |
1106 | struct {} end_reset_fields; |
1107 | |
1108 | /* Fields from here on are preserved across CPU reset. */ |
1109 | CPUMIPSMVPContext *mvp; |
1110 | #if !defined(CONFIG_USER_ONLY) |
1111 | CPUMIPSTLBContext *tlb; |
1112 | #endif |
1113 | |
1114 | const mips_def_t *cpu_model; |
1115 | void *irq[8]; |
1116 | QEMUTimer *timer; /* Internal timer */ |
1117 | struct MIPSITUState *itu; |
1118 | MemoryRegion *itc_tag; /* ITC Configuration Tags */ |
1119 | target_ulong exception_base; /* ExceptionBase input to the core */ |
1120 | }; |
1121 | |
1122 | /** |
1123 | * MIPSCPU: |
1124 | * @env: #CPUMIPSState |
1125 | * |
1126 | * A MIPS CPU. |
1127 | */ |
1128 | struct MIPSCPU { |
1129 | /*< private >*/ |
1130 | CPUState parent_obj; |
1131 | /*< public >*/ |
1132 | |
1133 | CPUNegativeOffsetState neg; |
1134 | CPUMIPSState env; |
1135 | }; |
1136 | |
1137 | |
1138 | void mips_cpu_list(void); |
1139 | |
1140 | #define cpu_signal_handler cpu_mips_signal_handler |
1141 | #define cpu_list mips_cpu_list |
1142 | |
1143 | extern void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env); |
1144 | extern uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env); |
1145 | |
1146 | /* |
1147 | * MMU modes definitions. We carefully match the indices with our |
1148 | * hflags layout. |
1149 | */ |
1150 | #define MMU_MODE0_SUFFIX _kernel |
1151 | #define MMU_MODE1_SUFFIX _super |
1152 | #define MMU_MODE2_SUFFIX _user |
1153 | #define MMU_MODE3_SUFFIX _error |
1154 | #define MMU_USER_IDX 2 |
1155 | |
1156 | static inline int hflags_mmu_index(uint32_t hflags) |
1157 | { |
1158 | if (hflags & MIPS_HFLAG_ERL) { |
1159 | return 3; /* ERL */ |
1160 | } else { |
1161 | return hflags & MIPS_HFLAG_KSU; |
1162 | } |
1163 | } |
1164 | |
1165 | static inline int cpu_mmu_index(CPUMIPSState *env, bool ifetch) |
1166 | { |
1167 | return hflags_mmu_index(env->hflags); |
1168 | } |
1169 | |
1170 | typedef CPUMIPSState CPUArchState; |
1171 | typedef MIPSCPU ArchCPU; |
1172 | |
1173 | #include "exec/cpu-all.h" |
1174 | |
1175 | /* |
1176 | * Memory access type : |
1177 | * may be needed for precise access rights control and precise exceptions. |
1178 | */ |
1179 | enum { |
1180 | /* 1 bit to define user level / supervisor access */ |
1181 | ACCESS_USER = 0x00, |
1182 | ACCESS_SUPER = 0x01, |
1183 | /* 1 bit to indicate direction */ |
1184 | ACCESS_STORE = 0x02, |
1185 | /* Type of instruction that generated the access */ |
1186 | ACCESS_CODE = 0x10, /* Code fetch access */ |
1187 | ACCESS_INT = 0x20, /* Integer load/store access */ |
1188 | ACCESS_FLOAT = 0x30, /* floating point load/store access */ |
1189 | }; |
1190 | |
1191 | /* Exceptions */ |
1192 | enum { |
1193 | EXCP_NONE = -1, |
1194 | EXCP_RESET = 0, |
1195 | EXCP_SRESET, |
1196 | EXCP_DSS, |
1197 | EXCP_DINT, |
1198 | EXCP_DDBL, |
1199 | EXCP_DDBS, |
1200 | EXCP_NMI, |
1201 | EXCP_MCHECK, |
1202 | EXCP_EXT_INTERRUPT, /* 8 */ |
1203 | EXCP_DFWATCH, |
1204 | EXCP_DIB, |
1205 | EXCP_IWATCH, |
1206 | EXCP_AdEL, |
1207 | EXCP_AdES, |
1208 | EXCP_TLBF, |
1209 | EXCP_IBE, |
1210 | EXCP_DBp, /* 16 */ |
1211 | EXCP_SYSCALL, |
1212 | EXCP_BREAK, |
1213 | EXCP_CpU, |
1214 | EXCP_RI, |
1215 | EXCP_OVERFLOW, |
1216 | EXCP_TRAP, |
1217 | EXCP_FPE, |
1218 | EXCP_DWATCH, /* 24 */ |
1219 | EXCP_LTLBL, |
1220 | EXCP_TLBL, |
1221 | EXCP_TLBS, |
1222 | EXCP_DBE, |
1223 | EXCP_THREAD, |
1224 | EXCP_MDMX, |
1225 | EXCP_C2E, |
1226 | EXCP_CACHE, /* 32 */ |
1227 | EXCP_DSPDIS, |
1228 | EXCP_MSADIS, |
1229 | EXCP_MSAFPE, |
1230 | EXCP_TLBXI, |
1231 | EXCP_TLBRI, |
1232 | |
1233 | EXCP_LAST = EXCP_TLBRI, |
1234 | }; |
1235 | |
1236 | /* |
1237 | * This is an internally generated WAKE request line. |
1238 | * It is driven by the CPU itself. Raised when the MT |
1239 | * block wants to wake a VPE from an inactive state and |
1240 | * cleared when VPE goes from active to inactive. |
1241 | */ |
1242 | #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0 |
1243 | |
1244 | int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc); |
1245 | |
1246 | #define MIPS_CPU_TYPE_SUFFIX "-" TYPE_MIPS_CPU |
1247 | #define MIPS_CPU_TYPE_NAME(model) model MIPS_CPU_TYPE_SUFFIX |
1248 | #define CPU_RESOLVING_TYPE TYPE_MIPS_CPU |
1249 | |
1250 | bool cpu_supports_cps_smp(const char *cpu_type); |
1251 | bool cpu_supports_isa(const char *cpu_type, uint64_t isa); |
1252 | void cpu_set_exception_base(int vp_index, target_ulong address); |
1253 | |
1254 | /* mips_int.c */ |
1255 | void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level); |
1256 | |
1257 | /* mips_itu.c */ |
1258 | void itc_reconfigure(struct MIPSITUState *tag); |
1259 | |
1260 | /* helper.c */ |
1261 | target_ulong exception_resume_pc(CPUMIPSState *env); |
1262 | |
1263 | static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, target_ulong *pc, |
1264 | target_ulong *cs_base, uint32_t *flags) |
1265 | { |
1266 | *pc = env->active_tc.PC; |
1267 | *cs_base = 0; |
1268 | *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK | |
1269 | MIPS_HFLAG_HWRENA_ULR); |
1270 | } |
1271 | |
1272 | #endif /* MIPS_CPU_H */ |
1273 | |