1 | /* |
2 | * Altera Nios II virtual CPU header |
3 | * |
4 | * Copyright (c) 2012 Chris Wulff <crwulff@gmail.com> |
5 | * |
6 | * This library is free software; you can redistribute it and/or |
7 | * modify it under the terms of the GNU Lesser General Public |
8 | * License as published by the Free Software Foundation; either |
9 | * version 2.1 of the License, or (at your option) any later version. |
10 | * |
11 | * This library is distributed in the hope that it will be useful, |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
14 | * Lesser General Public License for more details. |
15 | * |
16 | * You should have received a copy of the GNU Lesser General Public |
17 | * License along with this library; if not, see |
18 | * <http://www.gnu.org/licenses/lgpl-2.1.html> |
19 | */ |
20 | |
21 | #ifndef NIOS2_CPU_H |
22 | #define NIOS2_CPU_H |
23 | |
24 | #include "exec/cpu-defs.h" |
25 | #include "hw/core/cpu.h" |
26 | |
27 | typedef struct CPUNios2State CPUNios2State; |
28 | #if !defined(CONFIG_USER_ONLY) |
29 | #include "mmu.h" |
30 | #endif |
31 | |
32 | #define TYPE_NIOS2_CPU "nios2-cpu" |
33 | |
34 | #define NIOS2_CPU_CLASS(klass) \ |
35 | OBJECT_CLASS_CHECK(Nios2CPUClass, (klass), TYPE_NIOS2_CPU) |
36 | #define NIOS2_CPU(obj) \ |
37 | OBJECT_CHECK(Nios2CPU, (obj), TYPE_NIOS2_CPU) |
38 | #define NIOS2_CPU_GET_CLASS(obj) \ |
39 | OBJECT_GET_CLASS(Nios2CPUClass, (obj), TYPE_NIOS2_CPU) |
40 | |
41 | /** |
42 | * Nios2CPUClass: |
43 | * @parent_reset: The parent class' reset handler. |
44 | * |
45 | * A Nios2 CPU model. |
46 | */ |
47 | typedef struct Nios2CPUClass { |
48 | /*< private >*/ |
49 | CPUClass parent_class; |
50 | /*< public >*/ |
51 | |
52 | DeviceRealize parent_realize; |
53 | void (*parent_reset)(CPUState *cpu); |
54 | } Nios2CPUClass; |
55 | |
56 | #define TARGET_HAS_ICE 1 |
57 | |
58 | /* Configuration options for Nios II */ |
59 | #define RESET_ADDRESS 0x00000000 |
60 | #define EXCEPTION_ADDRESS 0x00000004 |
61 | #define FAST_TLB_MISS_ADDRESS 0x00000008 |
62 | |
63 | |
64 | /* GP regs + CR regs + PC */ |
65 | #define NUM_CORE_REGS (32 + 32 + 1) |
66 | |
67 | /* General purpose register aliases */ |
68 | #define R_ZERO 0 |
69 | #define R_AT 1 |
70 | #define R_RET0 2 |
71 | #define R_RET1 3 |
72 | #define R_ARG0 4 |
73 | #define R_ARG1 5 |
74 | #define R_ARG2 6 |
75 | #define R_ARG3 7 |
76 | #define R_ET 24 |
77 | #define R_BT 25 |
78 | #define R_GP 26 |
79 | #define R_SP 27 |
80 | #define R_FP 28 |
81 | #define R_EA 29 |
82 | #define R_BA 30 |
83 | #define R_RA 31 |
84 | |
85 | /* Control register aliases */ |
86 | #define CR_BASE 32 |
87 | #define CR_STATUS (CR_BASE + 0) |
88 | #define CR_STATUS_PIE (1 << 0) |
89 | #define CR_STATUS_U (1 << 1) |
90 | #define CR_STATUS_EH (1 << 2) |
91 | #define CR_STATUS_IH (1 << 3) |
92 | #define CR_STATUS_IL (63 << 4) |
93 | #define CR_STATUS_CRS (63 << 10) |
94 | #define CR_STATUS_PRS (63 << 16) |
95 | #define CR_STATUS_NMI (1 << 22) |
96 | #define CR_STATUS_RSIE (1 << 23) |
97 | #define CR_ESTATUS (CR_BASE + 1) |
98 | #define CR_BSTATUS (CR_BASE + 2) |
99 | #define CR_IENABLE (CR_BASE + 3) |
100 | #define CR_IPENDING (CR_BASE + 4) |
101 | #define CR_CPUID (CR_BASE + 5) |
102 | #define CR_CTL6 (CR_BASE + 6) |
103 | #define CR_EXCEPTION (CR_BASE + 7) |
104 | #define CR_PTEADDR (CR_BASE + 8) |
105 | #define CR_PTEADDR_PTBASE_SHIFT 22 |
106 | #define CR_PTEADDR_PTBASE_MASK (0x3FF << CR_PTEADDR_PTBASE_SHIFT) |
107 | #define CR_PTEADDR_VPN_SHIFT 2 |
108 | #define CR_PTEADDR_VPN_MASK (0xFFFFF << CR_PTEADDR_VPN_SHIFT) |
109 | #define CR_TLBACC (CR_BASE + 9) |
110 | #define CR_TLBACC_IGN_SHIFT 25 |
111 | #define CR_TLBACC_IGN_MASK (0x7F << CR_TLBACC_IGN_SHIFT) |
112 | #define CR_TLBACC_C (1 << 24) |
113 | #define CR_TLBACC_R (1 << 23) |
114 | #define CR_TLBACC_W (1 << 22) |
115 | #define CR_TLBACC_X (1 << 21) |
116 | #define CR_TLBACC_G (1 << 20) |
117 | #define CR_TLBACC_PFN_MASK 0x000FFFFF |
118 | #define CR_TLBMISC (CR_BASE + 10) |
119 | #define CR_TLBMISC_WAY_SHIFT 20 |
120 | #define CR_TLBMISC_WAY_MASK (0xF << CR_TLBMISC_WAY_SHIFT) |
121 | #define CR_TLBMISC_RD (1 << 19) |
122 | #define CR_TLBMISC_WR (1 << 18) |
123 | #define CR_TLBMISC_PID_SHIFT 4 |
124 | #define CR_TLBMISC_PID_MASK (0x3FFF << CR_TLBMISC_PID_SHIFT) |
125 | #define CR_TLBMISC_DBL (1 << 3) |
126 | #define CR_TLBMISC_BAD (1 << 2) |
127 | #define CR_TLBMISC_PERM (1 << 1) |
128 | #define CR_TLBMISC_D (1 << 0) |
129 | #define CR_ENCINJ (CR_BASE + 11) |
130 | #define CR_BADADDR (CR_BASE + 12) |
131 | #define CR_CONFIG (CR_BASE + 13) |
132 | #define CR_MPUBASE (CR_BASE + 14) |
133 | #define CR_MPUACC (CR_BASE + 15) |
134 | |
135 | /* Other registers */ |
136 | #define R_PC 64 |
137 | |
138 | /* Exceptions */ |
139 | #define EXCP_BREAK 0x1000 |
140 | #define EXCP_RESET 0 |
141 | #define EXCP_PRESET 1 |
142 | #define EXCP_IRQ 2 |
143 | #define EXCP_TRAP 3 |
144 | #define EXCP_UNIMPL 4 |
145 | #define EXCP_ILLEGAL 5 |
146 | #define EXCP_UNALIGN 6 |
147 | #define EXCP_UNALIGND 7 |
148 | #define EXCP_DIV 8 |
149 | #define EXCP_SUPERA 9 |
150 | #define EXCP_SUPERI 10 |
151 | #define EXCP_SUPERD 11 |
152 | #define EXCP_TLBD 12 |
153 | #define EXCP_TLBX 13 |
154 | #define EXCP_TLBR 14 |
155 | #define EXCP_TLBW 15 |
156 | #define EXCP_MPUI 16 |
157 | #define EXCP_MPUD 17 |
158 | |
159 | #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 |
160 | |
161 | struct CPUNios2State { |
162 | uint32_t regs[NUM_CORE_REGS]; |
163 | |
164 | #if !defined(CONFIG_USER_ONLY) |
165 | Nios2MMU mmu; |
166 | |
167 | uint32_t irq_pending; |
168 | #endif |
169 | }; |
170 | |
171 | /** |
172 | * Nios2CPU: |
173 | * @env: #CPUNios2State |
174 | * |
175 | * A Nios2 CPU. |
176 | */ |
177 | typedef struct Nios2CPU { |
178 | /*< private >*/ |
179 | CPUState parent_obj; |
180 | /*< public >*/ |
181 | |
182 | CPUNegativeOffsetState neg; |
183 | CPUNios2State env; |
184 | |
185 | bool mmu_present; |
186 | uint32_t pid_num_bits; |
187 | uint32_t tlb_num_ways; |
188 | uint32_t tlb_num_entries; |
189 | |
190 | /* Addresses that are hard-coded in the FPGA build settings */ |
191 | uint32_t reset_addr; |
192 | uint32_t exception_addr; |
193 | uint32_t fast_tlb_miss_addr; |
194 | } Nios2CPU; |
195 | |
196 | |
197 | void nios2_tcg_init(void); |
198 | void nios2_cpu_do_interrupt(CPUState *cs); |
199 | int cpu_nios2_signal_handler(int host_signum, void *pinfo, void *puc); |
200 | void dump_mmu(CPUNios2State *env); |
201 | void nios2_cpu_dump_state(CPUState *cpu, FILE *f, int flags); |
202 | hwaddr nios2_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); |
203 | void nios2_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, |
204 | MMUAccessType access_type, |
205 | int mmu_idx, uintptr_t retaddr); |
206 | |
207 | qemu_irq *nios2_cpu_pic_init(Nios2CPU *cpu); |
208 | void nios2_check_interrupts(CPUNios2State *env); |
209 | |
210 | void do_nios2_semihosting(CPUNios2State *env); |
211 | |
212 | #define CPU_RESOLVING_TYPE TYPE_NIOS2_CPU |
213 | |
214 | #define cpu_gen_code cpu_nios2_gen_code |
215 | #define cpu_signal_handler cpu_nios2_signal_handler |
216 | |
217 | #define CPU_SAVE_VERSION 1 |
218 | |
219 | /* MMU modes definitions */ |
220 | #define MMU_MODE0_SUFFIX _kernel |
221 | #define MMU_MODE1_SUFFIX _user |
222 | #define MMU_SUPERVISOR_IDX 0 |
223 | #define MMU_USER_IDX 1 |
224 | |
225 | static inline int cpu_mmu_index(CPUNios2State *env, bool ifetch) |
226 | { |
227 | return (env->regs[CR_STATUS] & CR_STATUS_U) ? MMU_USER_IDX : |
228 | MMU_SUPERVISOR_IDX; |
229 | } |
230 | |
231 | bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size, |
232 | MMUAccessType access_type, int mmu_idx, |
233 | bool probe, uintptr_t retaddr); |
234 | |
235 | static inline int cpu_interrupts_enabled(CPUNios2State *env) |
236 | { |
237 | return env->regs[CR_STATUS] & CR_STATUS_PIE; |
238 | } |
239 | |
240 | typedef CPUNios2State CPUArchState; |
241 | typedef Nios2CPU ArchCPU; |
242 | |
243 | #include "exec/cpu-all.h" |
244 | |
245 | static inline void cpu_get_tb_cpu_state(CPUNios2State *env, target_ulong *pc, |
246 | target_ulong *cs_base, uint32_t *flags) |
247 | { |
248 | *pc = env->regs[R_PC]; |
249 | *cs_base = 0; |
250 | *flags = (env->regs[CR_STATUS] & (CR_STATUS_EH | CR_STATUS_U)); |
251 | } |
252 | |
253 | #endif /* NIOS2_CPU_H */ |
254 | |